April 2009 - U-Boot

[U-Boot] [PATCH v2] OMAP3: Remove legacy NAND defines
by Dirk Behme 27 Apr '09

27 Apr '09

Remove remaining legacy NAND defines for Beagle, EVM, Overo and Pandora. Signed-off-by: Dirk Behme <dirk.behme(a)googlemail.com> --- For Zoom1 it was already removed by http://lists.denx.de/pipermail/u-boot/2009-April/050150.html http://lists.denx.de/pipermail/u-boot/2009-April/050871.html Changes in v2: - Remove even more legacy NAND defines. Thanks to Tom Rix for the hint. This version v2 makes all previous versions of this patch obsolete. include/configs/omap3_beagle.h | 29 ----------------------------- include/configs/omap3_evm.h | 29 ----------------------------- include/configs/omap3_overo.h | 30 ------------------------------ include/configs/omap3_pandora.h | 29 ----------------------------- 4 files changed, 117 deletions(-) Index: u-boot-main/include/configs/omap3_beagle.h =================================================================== --- u-boot-main.orig/include/configs/omap3_beagle.h +++ u-boot-main/include/configs/omap3_beagle.h @@ -135,18 +135,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define SECTORSIZE 512 - -#define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 -#define CONFIG_SYS_NAND_WP #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ @@ -306,21 +294,4 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif - -#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, &nand_cs_base->nand_cmd) -#define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, &nand_cs_base->nand_adr) -#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) -#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) - -/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ - while (0) -#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ - while (0) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) udelay(10) - #endif /* __CONFIG_H */ Index: u-boot-main/include/configs/omap3_evm.h =================================================================== --- u-boot-main.orig/include/configs/omap3_evm.h +++ u-boot-main/include/configs/omap3_evm.h @@ -133,18 +133,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ -#define SECTORSIZE 512 - -#define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 -#define CONFIG_SYS_NAND_WP #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ @@ -299,23 +287,6 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif - -#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, &nand_cs_base->nand_cmd) -#define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, &nand_cs_base->nand_adr) -#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) -#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) - -/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ - while (0) -#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ - while (0) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) udelay(10) - /*---------------------------------------------------------------------------- * SMSC9115 Ethernet from SMSC9118 family *---------------------------------------------------------------------------- Index: u-boot-main/include/configs/omap3_overo.h =================================================================== --- u-boot-main.orig/include/configs/omap3_overo.h +++ u-boot-main/include/configs/omap3_overo.h @@ -122,19 +122,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define SECTORSIZE 512 - -#define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 -#define CONFIG_SYS_NAND_WP - #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" @@ -293,21 +280,4 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif - -#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, &nand_cs_base->nand_cmd) -#define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, &nand_cs_base->nand_adr) -#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) -#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) - -/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ - while (0) -#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ - while (0) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) udelay(10) - #endif /* __CONFIG_H */ Index: u-boot-main/include/configs/omap3_pandora.h =================================================================== --- u-boot-main.orig/include/configs/omap3_pandora.h +++ u-boot-main/include/configs/omap3_pandora.h @@ -125,18 +125,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define SECTORSIZE 512 - -#define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 -#define CONFIG_SYS_NAND_WP #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ @@ -295,21 +283,4 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif - -#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, &nand_cs_base->nand_cmd) -#define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, &nand_cs_base->nand_adr) -#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) -#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) - -/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ - while (0) -#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ - while (0) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) udelay(10) - #endif /* __CONFIG_H */

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[U-Boot] OMAP3 ARCH STATUS
by Jean-Christophe PLAGNIOL-VILLARD 26 Apr '09

26 Apr '09

Hi all, The current implementation of the omap3 needs cleanup in the following area gpio API (done by Tom Rix) mux API device init implementation (as done for the at91) interrupt duplicated code Best Regards, J.

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[U-Boot] [PATCH] OMAP3: Fix changed mmc init command
by Dirk Behme 26 Apr '09

26 Apr '09

In recent U-Boot mmcinit changed to mmc init. Signed-off-by: Steve Sakoman <steve(a)sakoman.com> Signed-off-by: Dirk Behme <dirk.behme(a)googlemail.com> --- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_overo.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_zoom1.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) Index: u-boot-main/include/configs/omap3_beagle.h =================================================================== --- u-boot-main.orig/include/configs/omap3_beagle.h +++ u-boot-main/include/configs/omap3_beagle.h @@ -185,7 +185,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmcinit; then " \ + "if mmc init; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ Index: u-boot-main/include/configs/omap3_evm.h =================================================================== --- u-boot-main.orig/include/configs/omap3_evm.h +++ u-boot-main/include/configs/omap3_evm.h @@ -178,7 +178,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmcinit; then " \ + "if mmc init; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ Index: u-boot-main/include/configs/omap3_overo.h =================================================================== --- u-boot-main.orig/include/configs/omap3_overo.h +++ u-boot-main/include/configs/omap3_overo.h @@ -172,7 +172,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmcinit; then " \ + "if mmc init; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ Index: u-boot-main/include/configs/omap3_pandora.h =================================================================== --- u-boot-main.orig/include/configs/omap3_pandora.h +++ u-boot-main/include/configs/omap3_pandora.h @@ -174,7 +174,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmcinit; then " \ + "if mmc init; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ Index: u-boot-main/include/configs/omap3_zoom1.h =================================================================== --- u-boot-main.orig/include/configs/omap3_zoom1.h +++ u-boot-main/include/configs/omap3_zoom1.h @@ -182,7 +182,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmcinit; then " \ + "if mmc init; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \

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[U-Boot] Medical Doctor Listing
by Carlo ] Cardenas 26 Apr '09

26 Apr '09

Essential tool for marketing to heathcare professionals Current Doctors in the USA 788,748 in total * 17,500 emails Featuring the most accurate contact information in many different areas of medicine you can sort by many different fields like city, state or zip Pharmaceutical Companies in the United States Personal email addresses (47,000 in total) and names for top level executives Complete Directory of Hospitals in the US Full data for all the major positions in more than 7k facilities Dentists in the United States 597,000 dentists and dental services ( a $350 value!) Chiropractors in the USA Complete data for all chiropractors in the US (a $250 value) This week only you pay only: $390 for everything Email us at: Masters(a)medexecdata.com only during this week to adjust your subscription status email to delrem(a)medexecdata.com

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[U-Boot] [PATCH 1/2] OMAP3: Remove unused board-types
by Sanjeev Premi 26 Apr '09

26 Apr '09

The board-types defined in struct omap3_sysinfo seem to be unused. The function display_board_info() is passed board type as an argument; which is ignored. This patch removes all uses of board-type, related definitions and functions. Signed-off-by: Sanjeev Premi <premi(a)ti.com> --- board/omap3/beagle/beagle.h | 2 -- board/omap3/evm/evm.h | 2 -- board/omap3/overo/overo.h | 2 -- board/omap3/pandora/pandora.h | 2 -- board/omap3/zoom1/zoom1.h | 2 -- cpu/arm_cortexa8/omap3/board.c | 5 +---- cpu/arm_cortexa8/omap3/sys_info.c | 19 +------------------ include/asm-arm/arch-omap3/omap3.h | 8 -------- include/asm-arm/arch-omap3/sys_proto.h | 5 +---- 9 files changed, 3 insertions(+), 44 deletions(-) diff --git a/board/omap3/beagle/beagle.h b/board/omap3/beagle/beagle.h index d66f159..5d45f01 100644 --- a/board/omap3/beagle/beagle.h +++ b/board/omap3/beagle/beagle.h @@ -24,8 +24,6 @@ #define _BEAGLE_H_ const omap3_sysinfo sysinfo = { - SDP_3430_V1, - SDP_3430_V2, DDR_STACKED, "OMAP3 Beagle board", #if defined(CONFIG_ENV_IS_IN_ONENAND) diff --git a/board/omap3/evm/evm.h b/board/omap3/evm/evm.h index 199824f..4a82a7f 100644 --- a/board/omap3/evm/evm.h +++ b/board/omap3/evm/evm.h @@ -24,8 +24,6 @@ #define _EVM_H_ const omap3_sysinfo sysinfo = { - OMAP3EVM_V1, - OMAP3EVM_V2, DDR_DISCRETE, "OMAP3 EVM board", #if defined(CONFIG_ENV_IS_IN_ONENAND) diff --git a/board/omap3/overo/overo.h b/board/omap3/overo/overo.h index e8ccc1d..b595f6a 100644 --- a/board/omap3/overo/overo.h +++ b/board/omap3/overo/overo.h @@ -24,8 +24,6 @@ #define _OVERO_H_ const omap3_sysinfo sysinfo = { - SDP_3430_V1, - SDP_3430_V2, DDR_STACKED, "Gumstix Overo board", #if defined(CONFIG_ENV_IS_IN_ONENAND) diff --git a/board/omap3/pandora/pandora.h b/board/omap3/pandora/pandora.h index dd09f12..8f0838c 100644 --- a/board/omap3/pandora/pandora.h +++ b/board/omap3/pandora/pandora.h @@ -24,8 +24,6 @@ #define _PANDORA_H_ const omap3_sysinfo sysinfo = { - SDP_3430_V1, - SDP_3430_V2, DDR_STACKED, "OMAP3 Pandora", "NAND", diff --git a/board/omap3/zoom1/zoom1.h b/board/omap3/zoom1/zoom1.h index bc8fba8..4f49a41 100644 --- a/board/omap3/zoom1/zoom1.h +++ b/board/omap3/zoom1/zoom1.h @@ -28,8 +28,6 @@ #define _BOARD_ZOOM1_H_ const omap3_sysinfo sysinfo = { - SDP_3430_V1, - SDP_3430_V2, DDR_STACKED, "OMAP3 Zoom MDK Rev 1", "NAND", diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 15ea936..9318e22 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -272,11 +272,8 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; unsigned int size0 = 0, size1 = 0; - u32 btype; - btype = get_board_type(); - - display_board_info(btype); + display_board_info(); /* * If a second bank of DDR is attached to CS1 this is diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index b385b91..80f6e5e 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -130,23 +130,6 @@ u32 get_sdr_cs_offset(u32 cs) return offset; } -/*********************************************************************** - * get_board_type() - get board type based on current production stats. - * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. - * when they are available we can get info from there. This should - * be correct of all known boards up until today. - * - NOTE-2- EEPROMs are populated but they are updated very slowly. To - * avoid waiting on them we will use ES version of the chip to get info. - * A later version of the FPGA migth solve their speed issue. - ************************************************************************/ -u32 get_board_type(void) -{ - if (get_cpu_rev() == CPU_3430_ES2) - return sysinfo.board_type_v2; - else - return sysinfo.board_type_v1; -} - /*************************************************************************** * get_gpmc0_base() - Return current address hardware will be * fetching from. The below effectively gives what is correct, its a bit @@ -188,7 +171,7 @@ u32 get_board_rev(void) /********************************************************************* * display_board_info() - print banner with board info. *********************************************************************/ -void display_board_info(u32 btype) +void display_board_info(void) { char *cpu_s, *mem_s, *sec_s; diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h index 8c9656f..d0d2737 100644 --- a/include/asm-arm/arch-omap3/omap3.h +++ b/include/asm-arm/arch-omap3/omap3.h @@ -177,14 +177,6 @@ typedef struct gpio { #define WIDTH_8BIT 0x0000 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ -/* SDP definitions according to FPGA Rev. Is this OK?? */ -#define SDP_3430_V1 0x1 -#define SDP_3430_V2 0x2 - -/* EVM definitions */ -#define OMAP3EVM_V1 0x1 -#define OMAP3EVM_V2 0x2 - /* I2C power management companion definitions */ #define PWRMGT_ADDR_ID1 0x48 #define PWRMGT_ADDR_ID2 0x49 diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index 8b554bb..1bcec04 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -22,8 +22,6 @@ #define _SYS_PROTO_H_ typedef struct { - u32 board_type_v1; - u32 board_type_v2; u32 mtype; char *board_string; char *nand_string; @@ -46,8 +44,7 @@ u32 get_sysboot_value(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void); u32 get_gpmc0_width(void); -u32 get_board_type(void); -void display_board_info(u32); +void display_board_info(void); u32 get_sdr_cs_size(u32); u32 get_sdr_cs_offset(u32); u32 is_running_in_sdram(void); -- 1.6.2.1

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[U-Boot] [PATCH] lib_arm/board.c: remove misleading "test-only" comment.
by Wolfgang Denk 26 Apr '09

26 Apr '09

For a long time, the print_cpuinfo() declaration in lib_arm/board.c had been marked as "test-only", which is plain wrong considering current usage. Delete this misleading comment. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- lib_arm/board.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/lib_arm/board.c b/lib_arm/board.c index 6847ea8..5d05d9b 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -258,7 +258,7 @@ static int arm_pci_init(void) */ typedef int (init_fnc_t) (void); -int print_cpuinfo (void); /* test-only */ +int print_cpuinfo (void); init_fnc_t *init_sequence[] = { cpu_init, /* basic cpu dependent setup */ -- 1.6.0.6

1 1

[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision
by Sanjeev Premi 26 Apr '09

26 Apr '09

The function display_board_info() displays incorrect silicon revision - based on the return value from function get_cpu_rev(). This patch fixes the problem. Signed-off-by: Sanjeev Premi <premi(a)ti.com> --- cpu/arm_cortexa8/cpu.c | 4 ++-- cpu/arm_cortexa8/omap3/clock.c | 5 +++-- cpu/arm_cortexa8/omap3/sys_info.c | 30 ++++++++++++++++++++++-------- include/asm-arm/arch-omap3/omap3.h | 10 ++++++++-- 4 files changed, 35 insertions(+), 14 deletions(-) diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 5e7b935..3e1780b 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -101,7 +101,7 @@ void l2cache_enable() volatile unsigned int j; /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() == CPU_3430_ES2) { + if (get_cpu_rev() >= CPU_3XX_ES20) { __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); @@ -131,7 +131,7 @@ void l2cache_disable() volatile unsigned int j; /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() == CPU_3430_ES2) { + if (get_cpu_rev() >= CPU_3XX_ES20) { __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c index 8ac31be..d035677 100644 --- a/cpu/arm_cortexa8/omap3/clock.c +++ b/cpu/arm_cortexa8/omap3/clock.c @@ -132,7 +132,7 @@ void prcm_init(void) void (*f_lock_pll) (u32, u32, u32, u32); int xip_safe, p0, p1, p2, p3; u32 osc_clk = 0, sys_clkin_sel; - u32 clk_index, sil_index; + u32 clk_index, sil_index = 0; prm_t *prm_base = (prm_t *)PRM_BASE; prcm_t *prcm_base = (prcm_t *)PRCM_BASE; dpll_param *dpll_param_p; @@ -170,7 +170,8 @@ void prcm_init(void) * and sil_index will get the values for that SysClk for the * appropriate silicon rev. */ - sil_index = get_cpu_rev() - 1; + if (get_cpu_rev()) + sil_index = 1; /* Unlock MPU DPLL (slows things down, and needed later) */ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index 80f6e5e..9246790 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -35,6 +35,12 @@ extern omap3_sysinfo sysinfo; static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE; static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; +static char *rev_s[CPU_3XX_MAX_REV] = { + "1.0", + "2.0", + "2.1", + "3.0", + "3.1"}; /***************************************************************** * dieid_num_r(void) - read and set die ID @@ -76,18 +82,27 @@ u32 get_cpu_type(void) u32 get_cpu_rev(void) { u32 cpuid = 0; + ctrl_id_t *id_base; /* * On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. + * so using CPU ID to differentiate between ES1.0 and > ES1.0. */ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); if ((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; + return CPU_3XX_ES10; + else { + /* Decode the IDs on > ES1.0 */ + id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE; + + cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xff; + + /* Some early ES2.0 seem to report ID 0, fix this */ + if(cpuid == 0) + cpuid = CPU_3XX_ES20; + return cpuid; + } } /**************************************************** @@ -215,9 +230,8 @@ void display_board_info(void) sec_s = "?"; } - - printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", cpu_s, - sec_s, get_cpu_rev()); + printf("OMAP%s-%s [ES%s], CPU-OPP2 L3-165MHz\n", cpu_s, + sec_s, rev_s[get_cpu_rev()]); printf("%s + %s/%s\n", sysinfo.board_string, mem_s, sysinfo.nand_string); diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h index d0d2737..8cce18b 100644 --- a/include/asm-arm/arch-omap3/omap3.h +++ b/include/asm-arm/arch-omap3/omap3.h @@ -171,8 +171,14 @@ typedef struct gpio { * ES1 = 0+1 = 1 * ES1 = 1+1 = 1 */ -#define CPU_3430_ES1 1 -#define CPU_3430_ES2 2 +#define CPU_3XX_ES10 0 +#define CPU_3XX_ES20 1 +#define CPU_3XX_ES21 2 +#define CPU_3XX_ES30 3 +#define CPU_3XX_ES31 4 +#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1) + +#define CPU_3XX_ID_SHIFT 28 #define WIDTH_8BIT 0x0000 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ -- 1.6.2.1

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Re: [U-Boot] Problems with ext2ls & SD
by Wolfgang Denk 25 Apr '09

25 Apr '09

Dear Karl, In message <669754ad0903281214x77796b95x76062f1c428ecda8(a)mail.gmail.com> you wrote: > > I am simply using fdisk under Ubuntu 8.04 and a 2GB SD card, I create a > primary partition of type 0x83. When I run dumpe2fs it shows an inode size > of 256 bytes. I confirm the problem. I finally found some time to run some tests, and was able to reproduce the problem. I even re-tested the old patch that Ryan Chen posted long ago (in July 2008), but as my earlier tests indicated, this patch is seriously broken and does not work at all. So we have to state that ext2 file system support in U-Boot is broken for recent ext2 versions which use bigger inode sizes. Best regards, Viele Grüße, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de The most difficult thing in the world is to know how to do a thing and to watch someone else doing it wrong, without commenting. -- T.H. White

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[U-Boot] U-boot memory dump
by alfred steele 25 Apr '09

25 Apr '09

Hi, I am using uboot on the MX31 PDk board. I am trying to dump the contents of a status register found at location 50004004. This status register shows the status of the SDHC( SD card host controller) like interrupt , card insertion, card removal etc. According to the MX31 manual, the status register i.e the contents at the corresponding memory location should change on events like card insertion and removal. But the contents aren't changing as expected. I have verified this with Linux and it works. i) Before card insertion => md.l 50004004 50004004: 30004000 00000008 00000000 00000040 ii)After card insertion => md.l 50004004 50004004: 30004000 00000008 00000000 00000040 Could anything be wrong with my u-boot image or the memory initialization(although anything going wrong with the init dosent make sense). Thanks in advance! Thanks, Alfred

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[U-Boot] [PATCH v8] Marvell MV88E61XX Switch Driver support
by Prafulla Wadaskar 25 Apr '09

25 Apr '09

Chips supported:- 1. 88E6161 6 port gbe swtich with 5 integrated PHYs 2. 88E6165 6 port gbe swtich with 5 integrated PHYs 2. 88E6132 3 port gbe swtich with 2 integrated PHYs Platform specific configuration supported default and router port vlan config supported Note: This driver is supported and tested against kirkwood egiga interface Contributors: Yotam Admon <yotam(a)marvell.com> Michael Blostein <michaelbl(a)marvell.com Reviewed by: Ronen Shitrit <rshitrit(a)marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Change log:- v2: updated as per review comments for v1 removed other two drivers form earlier patch debug_prints removed driver moved to drivers/net/ v3: updated as per review comments for v2 miiphy interface used, platform specific dependency resolved Chip id detection and printing added common code forked out some cosmetic and magic number fixes v4: updated as per review comments for v3 mv88e61xx.h added platform specific configuration support added some more documentation references provided cleaned rgmii delay enable related code v5: updated as per review comments for v3 code moved to drivers/net/phy/ vlan_init changed to vlan_config and platform specific v6: mutichip related alias moved to header file vlan_config functions renamed as port_vlan_config mv_switch_88f61xx_init renamed as mv88f61xx_switch_initialization the function prototype for same is added in netdev.h v7: minor updates as per v6 review feedback RD_PHY/WR_PHY macros defined and used in the code v8: BITxx macros replaced by 1<<xx drivers/net/phy/Makefile | 1 + drivers/net/phy/mv88e61xx.c | 298 +++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/mv88e61xx.h | 86 +++++++++++++ include/netdev.h | 1 + 4 files changed, 386 insertions(+), 0 deletions(-) create mode 100644 drivers/net/phy/mv88e61xx.c create mode 100644 drivers/net/phy/mv88e61xx.h diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 4fe3b05..3b92614 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libphy.a COBJS-$(CONFIG_BITBANGMII) += miiphybb.o +COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c new file mode 100644 index 0000000..100934f --- /dev/null +++ b/drivers/net/phy/mv88e61xx.c @@ -0,0 +1,298 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include "mv88e61xx.h" + +#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +static int mv88e61xx_busychk_multic(u32 devaddr) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, &reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & 1<<15); + return 0; +} + +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { + printf("Error..could not read PHY dev address\n"); + return; + } + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | 1<<10 | 1<<12 | 1<<15); +} + +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { + printf("Error..could not read PHY dev address\n"); + return; + } + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | 1<<10 | 1<<12 | 1<<15); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig, + u32 max_prtnum, u32 ports_ofs) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 cpu_port = swconfig->cpuport; + u32 port_mask = swconfig->ports_enabled; + enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg; + + /* be sure all ports are disabled */ + for (prt = 0; prt < max_prtnum; prt++) { + RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg); + } + /* Set CPU port VID to 0x1 */ + RD_PHY(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0xfff; + reg |= 0x1; + WR_PHY(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, reg); + + /* Setting Port default priority for all ports to zero */ + for (prt = 0; prt < max_prtnum; prt++) { + RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0xc000; + WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg); + } + /* Setting VID and VID map for all ports except CPU port */ + for (prt = 0; prt < max_prtnum; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* skip CPU port */ + if (prt == cpu_port) + continue; + + /* + * set Ports VLAN Mapping. + * port prt <--> cpu_port VLAN #prt+1. + */ + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0x0fff; + reg |= (prt + 1); + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, reg); + + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, &reg); + if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) { + /* + * all any port can send frames to all other ports + * ref: sec 3.2.1.1 of datasheet + */ + reg |= 0x03f; + reg &= ~(1 << prt); + } else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) { + /* + * all other ports can send frames to CPU port only + * ref: sec 3.2.1.2 of datasheet + */ + reg &= ~((1 << max_prtnum) - 1); + reg |= (1 << cpu_port); + } + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } + /* Set Vlan map table for cpu_port to see all ports */ + RD_PHY(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= port_mask & ~(1 << cpu_port); + WR_PHY(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, reg); + + /* + * enable only appropriate ports to forwarding mode + * and disable the others + */ + for (prt = 0; prt < max_prtnum; prt++) { + if ((1 << prt) & port_mask) { + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg |= 0x3; + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } else { + /* Disable port */ + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } + } +} + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88e61xx_busychk(char *name) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + RD_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (u16 *) & reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & 1<<28); /* busy mask */ + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->cpuport < 4) { + swconfig->cpuport = 5; + printf("Invalid cpu port config, using default port5\n"); + } + + RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg); + reg &= 0xfff0; + if (reg == 0x1610) + idstr = "88E6161"; + if (reg == 0x1650) + idstr = "88E6165"; + if (reg == 0x1210) { + idstr = "88E6123"; + /* ports 2,3,4 not available */ + swconfig->ports_enabled &= 0x023; + } + + /* Port based VLANs configuration */ + if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT) + || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER)) + mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM, + MV88E61XX_PRT_OFST); + else { + printf("Unsupported mode %s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + WR_PHY(name, MV88E61XX_PRT_OFST + 5, + MV88E61XX_RGMII_TIMECTRL_REG, 0x18); + WR_PHY(name, MV88E61XX_PRT_OFST + 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + if (prt != swconfig->cpuport) { + /* Write Copper Specific control reg1 (0x14) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x3360); + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (0x9410 | (prt << 5))); + + if (mv88e61xx_busychk(name)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (set bit 15 low) + * reset other default values + */ + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x1140); + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (0x9400 | (prt << 5))); + + if (mv88e61xx_busychk(name)) + return -1; + } + + /*Program port state */ + RD_PHY(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + WR_PHY(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h new file mode 100644 index 0000000..8cc4798 --- /dev/null +++ b/drivers/net/phy/mv88e61xx.h @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#include <miiphy.h> + +#define PORT(_x) (1 << _x) +#define MV88E61XX_CPU_PORT 0x5 +#define MV88E61XX_MAX_PORTS_NUM 0x6 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +#define MV88E61XX_PRT_STS_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 + +#define MV88E61XX_PRT_OFST 0x10 +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A +#define MV88E61XX_GLB2REG_DEVADR 0x1C + +/* constants for switch configuration */ +enum mv88e61xx_cfg_vlan { + MV88E61XX_VLANCFG_DEFAULT, + MV88E61XX_VLANCFG_ROUTER +}; + +enum mv88e61xx_cfg_rgmiid { + MV88E61XX_RGMII_DELAY_DIS, + MV88E61XX_RGMII_DELAY_EN +}; + +enum mv88e61xx_cfg_prtstt { + MV88E61XX_PORTSTT_DISABLED, + MV88E61XX_PORTSTT_BLOCKING, + MV88E61XX_PORTSTT_LEARNING, + MV88E61XX_PORTSTT_FORWARDING +}; + +/* switch configuration structure */ +struct mv88e61xx_config { + char *name; + enum mv88e61xx_cfg_vlan vlancfg; + enum mv88e61xx_cfg_rgmiid rgmii_delay; + enum mv88e61xx_cfg_prtstt portstate; + u32 ports_enabled; + u8 cpuport; +}; + +#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +static int mv88e61xx_busychk_multic(u32 devaddr); +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data); +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data); +#define WR_PHY mv88e61xx_wr_phy +#define RD_PHY mv88e61xx_rd_phy +#else +#define WR_PHY miiphy_write +#define RD_PHY miiphy_read +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +#endif /* _MV88E61XX_H */ diff --git a/include/netdev.h b/include/netdev.h index 2794ddd..f7a7db1 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -59,6 +59,7 @@ int mpc512x_fec_initialize(bd_t *bis); int mpc5xxx_fec_initialize(bd_t *bis); int mpc8220_fec_initialize(bd_t *bis); int mpc82xx_scc_enet_initialize(bd_t *bis); +int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); int natsemi_initialize(bd_t *bis); int npe_initialize(bd_t *bis); int ns8382x_initialize(bd_t *bis); -- 1.5.3.4

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