December 2009 - U-Boot

[U-Boot] [PATCH] imx27lite: Reenable MTD support on NOR flash.
by Detlev Zundel 14 Dec '09

14 Dec '09

The support for this was silently dropped by a configuration split during the merge of the imx27lite board support in commit 864aa034f3a0e10ce710e8bbda171df3cab59414 (cmd_mtdparts: Move to common handling of FLASH devices via MTD layer). Signed-off-by: Detlev Zundel <dzu(a)denx.de> --- include/configs/imx27lite.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h index 8ebb0bb..c639e5b 100644 --- a/include/configs/imx27lite.h +++ b/include/configs/imx27lite.h @@ -145,6 +145,7 @@ /* * MTD */ +#define CONFIG_FLASH_CFI_MTD #define CONFIG_MTD_DEVICE /* -- 1.6.2.5

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[U-Boot] Pull request: nand flash
by Scott Wood 14 Dec '09

14 Dec '09

The following changes since commit 3b887ca8ce72cc12129183538f6e828db13f4867: Peter Korsgaard (1): mpc83xx: boot time regression, move LCRR setup back to cpu_init_f are available in the git repository at: git://git.denx.de/u-boot-nand-flash.git master Stefan Roese (1): nand: Fix access to last block in NAND devices drivers/mtd/nand/nand_util.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)

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[U-Boot] Adding a new board to the configuration
by Dunda, Matthias 14 Dec '09

14 Dec '09

Hi all- I'd like to add a new custom board configuration to the u-boot build. Which files have to be created and/or patched to add a new board to build system? Our design uses the MPC8568E CPU, so I suppose, I can use a lot of present code coming from parameters like "ppc" and "mpc85xx". Of course I am taking a look at other configurations, but I'd like to know how to set it up from scratch, especially to getting to know the essentials. So, what is needed for that later I can give it a "make MYCOOLBOARD_config" followed by "make all"? Cheers Matthias

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[U-Boot] GPIO - MPC8315
by Marcos Cunha 14 Dec '09

14 Dec '09

I want to configure GPIOs on MPC8315, but I can't set the gpio. Below the configuration code and the output. What is wrong? #define SPI_CS_IO 0x20000000 int board_mmc_init(bd_t *bd) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&immr->gpio[0]; printf("INIT MMC\n"); //tmpval = inbe32( out_be32(&gpio->dir, SPI_CS_IO); // Set IO as output out_be32(&gpio->odr, 0 /*~SPI_CS_IO*/); // Set pulled up out_be32(&gpio->ier, SPI_CS_IO); // Disable interrupt out_be32(&gpio->imr, 0 /*~SPI_CS_IO*/); // Disable interrupt mask out_be32(&gpio->icr, 0 /*~SPI_CS_IO*/); // Disable interrupt level/edge udelay(2000); out_be32(&gpio->dat, SPI_CS_IO); // Set the output pin /*DEBUG*/ printf("SPI - CHIP SELECT CONFIGURATION\n"); printf("$gpio = %x\n", gpio); printf("gpio->dir = %x \n", gpio->dir ); printf("gpio->odr = %x \n", gpio->odr ); printf("gpio->ier = %x \n", gpio->ier ); printf("gpio->imr = %x \n", gpio->imr ); printf("gpio->icr = %x \n", gpio->icr ); printf("gpio->dat = %x \n", gpio->dat ); } This is the output. MMC: INIT MMC SPI - CHIP SELECT CONFIGURATION $gpio = e0000c00 gpio->dir = 3f000000 gpio->odr = 0 gpio->ier = c00dff00 gpio->imr = 0 gpio->icr = 0 gpio->dat = 0 FINISH MMC Thanks in advance, Marcos Cunha Electrical Engineer

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[U-Boot] [PATCH 0/3] enable CONFIG_NET_MULTI for LAN91C96
by Nishanth Menon 14 Dec '09

14 Dec '09

Based on the discussion[1] here is the patchset Patchset is based on [2], and tested on SDP3430. Other platforms would be prefered to be build/tested/fixed as required Nishanth Menon (3): NET: LAN91C96 CONFIG_NET_MULTIify TI OMAP3: SDP3430 FIX NET_MULTI Warning LAN91C96: Enable NET_MULTI LAN driver board/apollon/apollon.c | 12 +- board/ti/sdp3430/sdp.c | 12 +- drivers/net/Makefile | 2 +- drivers/net/lan91c96.c | 452 ++++++++++++++++----------------------- drivers/net/lan91c96.h | 110 +++++----- include/configs/B2.h | 2 +- include/configs/apollon.h | 3 +- include/configs/assabet.h | 3 +- include/configs/gcplus.h | 3 +- include/configs/lubbock.h | 3 +- include/configs/omap1510inn.h | 3 +- include/configs/omap1610h2.h | 3 +- include/configs/omap1610inn.h | 3 +- include/configs/omap2420h4.h | 3 +- include/configs/omap3_sdp3430.h | 3 +- include/configs/omap5912osk.h | 3 +- include/configs/omap730p2.h | 3 +- include/configs/pleb2.h | 6 +- include/netdev.h | 1 + 19 files changed, 277 insertions(+), 353 deletions(-) Regards, Nishanth Menon Ref: [1] http://www.nabble.com/-U-Boot--NET%3A-SDP3430%3A-trouble-with-shifting-from… [2] http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-ti.git

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[U-Boot] error executing fw_printenv
by twebb 14 Dec '09

14 Dec '09

I've cross-compiled and am running fw_printenv on an ARM system using linux-2.6.28. The u-boot environment is kept in SPI-based NOR flash. The configuration within fw_env.h is... //#define CONFIG_FILE "/etc/fw_env.config" //#define HAVE_REDUND /* For systems with 2 env sectors */ #define DEVICE1_NAME "/dev/mtd7" #define DEVICE1_OFFSET 0x00080000 #define ENV1_SIZE 0x00020000 #define DEVICE1_ESIZE 0x00010000 #define DEVICE1_ENVSECTORS 0 /* should be ignored for NOR */ I get the following error when executing fw_printenv... Read error on /dev/mtd7: Success Adding some debug, I've determined that the error results from the read of mtd7 returning 0 bytes read. *** mtdinfo.type = NOR *** Read 0 bytes, readlen = 131072, seek = 524288 Read error on /dev/mtd7: Success However, using the command... dd if=/dev/mtd7 of=/tmp/dummy bs=512 count=1 skip=1024 dummy contains the u-boot environment area as I would expect. Any ideas why the read is returning 0? Thanks, twebb

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[U-Boot] [PATCH v2] net: dm9000x: fix debug output
by Thomas Weber 14 Dec '09

14 Dec '09

commit 60f61e6d7655400bb785a2ef637581679941f6d1 breaks compile with gcc by introducing __func__ instead of constant string "func" in the macro call but missed to change the macro. Signed-off-by: Thomas Weber <weber(a)corscience.de> --- drivers/net/dm9000x.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 73dd335..a7fef56 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -75,7 +75,7 @@ TODO: external MII is not functional, only internal at the moment. #define DM9000_DMP_PACKET(func,packet,length) \ do { \ int i; \ - printf(func ": length: %d\n", length); \ + printf("%s: length: %d\n", func, length); \ for (i = 0; i < length; i++) { \ if (i % 8 == 0) \ printf("\n%s: %02x: ", func, i); \ -- 1.6.4.4

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[U-Boot] [PATCH] fec_mxc: incomplete error handling
by John Ogness 14 Dec '09

14 Dec '09

fec_init() will only allocate fec->base_ptr if it is non-NULL. But the cleanup routine on error will free the pointer without setting it to NULL. This means that a later call to fec_init() would result in using an invalid pointer. The following patch to fix this is against u-boot-2009.11-rc2. Signed-off-by: John Ogness <john.ogness(a)linutronix.de> --- drivers/net/fec_mxc.c | 1 + 1 file changed, 1 insertion(+) --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -450,6 +450,7 @@ static int fec_init(struct eth_device *d */ if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { free(fec->base_ptr); + fec->base_ptr = NULL; return -ENOMEM; } fec_tbd_init(fec);

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[U-Boot] [PATCH] net: e1000: Add support for the Intel 82546GB controller
by Stefan Roese 14 Dec '09

14 Dec '09

From: Reinhard Arlt <reinhard.arlt(a)esd.eu> This chip is equipped for example on the esd PMC-ETH2-GB board. So let's add it to the list of supported chips to the e1000 driver. Signed-off-by: Reinhard Arlt <reinhard.arlt(a)esd.eu> Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Ben Warren <biggerbadderben(a)gmail.com> --- drivers/net/e1000.c | 1 + include/pci_ids.h | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 7f9f783..2825342 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -79,6 +79,7 @@ static struct pci_device_id supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, diff --git a/include/pci_ids.h b/include/pci_ids.h index d783c5b..edfdc1e 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1828,6 +1828,7 @@ #define PCI_DEVICE_ID_INTEL_82546EB_COPPER 0x1010 #define PCI_DEVICE_ID_INTEL_82545EM_FIBER 0x1011 #define PCI_DEVICE_ID_INTEL_82546EB_FIBER 0x1012 +#define PCI_DEVICE_ID_INTEL_82546GB_COPPER 0x1079 #define PCI_DEVICE_ID_INTEL_82540EM_LOM 0x1015 #define PCI_DEVICE_ID_INTEL_82545GM_COPPER 0x1026 #define PCI_DEVICE_ID_INTEL_82559 0x1030 -- 1.6.6.rc1

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[U-Boot] MPC8567 - TEXT BASE boot rom question... Half the message was missing.. trying again..
by Bob Winslow 14 Dec '09

14 Dec '09

last try, sorry about the multiple posts. I must be doing something stupid, or I just don't understand how the 8567 boots from rom..., law entries, tables, etc... Our board is using a MPC8567 with a 4 MEGByte boot rom flash (16 bit).... It has just 512MB of DDR2 memory(no ram on the local bus). I can get u-boot to come up to the prompt ok but only with a rom image(u-boot.bin) of 4MEG BYTE size and the settings in the files, see below. I am using the BDI to write the 4meg image to the rom. I guess I don't understand TEXT_BASE very well.. and how it relates to the boot location. What do I need to change to get a uboot image for the rom of reasonable size(say 512k instead of the 4meg)??? I have tried to change the value of TEXT_BASE to (xFFF8_0000) in the config.mk file(and other entries) but I must not be doing something else right.. Any suggestions/help would be greatly appreciated!! Am I writng the u-boot.bin to the wrong location in the flash when it is 512k? Below is the relevant info from the files I think: Thanks for your help in advance! Bob *********** config.mk file TEXT_BASE = 0xffc00000 ********** from the include/configs/sevis8567.h file /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 8M */ #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH_BASE /*Chip select 0 - Flash*/ #define CONFIG_SYS_BR0_PRELIM 0xfe001001 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ I have OR's and BR's for the others also, but should not be relevant to the question so I didnt include. #define CONFIG_SYS_LBC_LCRR 0x00030002 /* LB clock ratio reg */ #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_CPLD_BASE 0xD0000000 #define CONFIG_SYS_E1_IF_BASE 0xD1000000 #define CONFIG_SYS_DSP_BASE 0xD2000000 #define CONFIG_SYS_FPGA_BASE 0xD3000000 #define CONFIG_SYS_LBC_CPLD_BASE CONFIG_SYS_CPLD_BASE #define CONFIG_SYS_LBC_E1_IF_BASE CONFIG_SYS_E1_IF_BASE #define CONFIG_SYS_LBC_DSP_BASE CONFIG_SYS_DSP_BASE #define CONFIG_SYS_LBC_FPGA_BASE CONFIG_SYS_FPGA_BASE #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */ #define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */ /* * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 256K(one sector) for env */ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xD0000) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OVERWRITE /* allow user to overwrite serial and ethaddr */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ **************** from board/sevis/law.c struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), /* LBC window */ SET_LAW(CONFIG_SYS_LBC_CPLD_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_LBC_E1_IF_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_LBC_DSP_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_LBC_FPGA_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); ****************** from board/sevis/tlb.c (the flash table entries I know must be wrong but the uboot comes up when these are set this way) struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 Initializations */ /* * TLBe 0: 16M Non-cacheable, guarded * 0xff000000 16M FLASH (upper half) * Out of reset this entry is only 4K. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), /* * TLBe 1: 16M Non-cacheable, guarded * 0xfe000000 16M FLASH (lower half) */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* * TLBe 2: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 8M PCI1 IO * 0xe280_0000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_64M, 1), /* * TLB 3+4: 512M DDR, cache disabled (needed for memory test) * 0x00000000 512M DDR System memory * Without SPD EEPROM configured DDR, this must be setup manually. */ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_16M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_E1_IF_BASE, CONFIG_SYS_E1_IF_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_DSP_BASE, CONFIG_SYS_DSP_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), }; int num_tlb_entries = ARRAY_SIZE(tlb_table);

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