October 2009 - U-Boot

Re: [U-Boot] [PATCH 1/3] memcpy: use 32-bit copies if possible
by Chris Moore 08 Oct '09

08 Oct '09

Alessandro Rubini a écrit : > From: Alessandro Rubini <rubini(a)unipv.it> > > Signed-off-by: Alessandro Rubini <rubini(a)unipv.it> > Acked-by: Andrea Gallo <andrea.gallo(a)stericsson.com> > --- > lib_generic/string.c | 11 ++++++++++- > 1 files changed, 10 insertions(+), 1 deletions(-) > > diff --git a/lib_generic/string.c b/lib_generic/string.c > index 181eda6..fdccab6 100644 > --- a/lib_generic/string.c > +++ b/lib_generic/string.c > @@ -449,7 +449,16 @@ char * bcopy(const char * src, char * dest, int count) > void * memcpy(void * dest,const void *src,size_t count) > { > char *tmp = (char *) dest, *s = (char *) src; > + u32 *d32 = (u32 *)dest, *s32 = (u32 *) src; > > + /* if both are aligned, use 32-bit copy */ > + if ( (((int)dest & 3) | ((int)src & 3) | (count & 3)) == 0 ) { > This can be factorized as (a & 3) | (b & 3) | (c & 3) is equivalent to (a | b | c) & 3. GCC is pretty smart but I doubt that it will pick this up :( > + count /= 4; > + while (count--) > + *d32++ = *s32++; > + return dest; > + } > + /* else, use 1-byte copy */ > while (count--) > *tmp++ = *s++; > > Cheers, Chris

2 1

[U-Boot] [PATCH v2] 85xx: Ensure BSS segment isn't linked at address 0
by Peter Tyser 08 Oct '09

08 Oct '09

When U-Boot is relocated from flash to RAM pointers are modified accordingly. However, pointers initialzed with NULL values should not be modified so that they maintain their intended NULL value. If the BSS segment is linked at address 0 its address will not be updated as necessary during relocation. This is a temporary workaround. The end goal is to add support to U-Boot to dynamically locate the BSS at an arbitrary address at runtime. When the ability to fixup the BSS inteligently is added, this workaround can be removed and the 85xx link script can put the BSS at a fixed address at link time. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- Changes since v1: - Updated commit title and description - Cleaned up logic to determine if we need to fixup bss address cpu/mpc85xx/u-boot.lds | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/cpu/mpc85xx/u-boot.lds b/cpu/mpc85xx/u-boot.lds index a347cd1..183dce9 100644 --- a/cpu/mpc85xx/u-boot.lds +++ b/cpu/mpc85xx/u-boot.lds @@ -131,6 +131,17 @@ SECTIONS . = RESET_VECTOR_ADDRESS + 0x4; + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. Note that + * this is a temporary fix. Code to dynamically the fixup the bss + * location will be added in the future. When the bss relocation + * fixup code is present this workaround should be removed. + */ +#if (RESET_VECTOR_ADDRESS == 0xfffffffc) + . |= 0x10; +#endif + __bss_start = .; .bss (NOLOAD) : { -- 1.6.2.1

4 4

[U-Boot] [PATCH] mpc8xxx: improve LAW error messages when setting up DDR
by Paul Gortmaker 08 Oct '09

08 Oct '09

When setting up the LAWs for the DDR, if there was an error, you got the not-so-helpful error text "ERROR" and nothing else. Not only is it non-informative, but it is also pretty frustrating trying to grep for "ERROR" in the source. Signed-off-by: Paul Gortmaker <paul.gortmaker(a)windriver.com> --- cpu/mpc8xxx/ddr/util.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu/mpc8xxx/ddr/util.c b/cpu/mpc8xxx/ddr/util.c index 4451989..d0f61a8 100644 --- a/cpu/mpc8xxx/ddr/util.c +++ b/cpu/mpc8xxx/ddr/util.c @@ -89,16 +89,16 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, ? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1; if (set_ddr_laws(base, size, lawbar1_target_id) < 0) { - printf("ERROR\n"); + printf("set_lawbar: ERROR (%d)\n", memctl_interleaved); return ; } } else if (ctrl_num == 1) { if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) { - printf("ERROR\n"); + printf("set_lawbar: ERROR (ctrl #2)\n"); return ; } } else { - printf("unexpected controller number %u in %s\n", + printf("set_lawbar: unexpected controller number %u in %s\n", ctrl_num, __FUNCTION__); } } -- 1.6.5.rc1

3 4

[U-Boot] [PATCH v1] ppc/P1_P2_RDB: NAND Boot Support
by Dipen Dudhat 08 Oct '09

08 Oct '09

NAND Boot support for P1 and P2 series RDB platforms. This patch is derived from latest NAND Boot support on MPC8536DS by Mingkai Hu. Signed-off-by: Dipen Dudhat <dipen.dudhat(a)freescale.com> --- - Applies to http://git.denx.de/u-boot.git MAKEALL | 1 + Makefile | 1 + board/freescale/p1_p2_rdb/config.mk | 7 ++ board/freescale/p1_p2_rdb/tlb.c | 10 ++ include/configs/P1_P2_RDB.h | 72 +++++++++++++-- nand_spl/board/freescale/p1_p2_rdb/Makefile | 123 ++++++++++++++++++++++++ nand_spl/board/freescale/p1_p2_rdb/nand_boot.c | 97 +++++++++++++++++++ 7 files changed, 304 insertions(+), 7 deletions(-) create mode 100644 nand_spl/board/freescale/p1_p2_rdb/Makefile create mode 100644 nand_spl/board/freescale/p1_p2_rdb/nand_boot.c diff --git a/MAKEALL b/MAKEALL index 0a54d75..de81c93 100755 --- a/MAKEALL +++ b/MAKEALL @@ -398,6 +398,7 @@ LIST_85xx=" \ P1020RDB \ P2010RDB \ P2020RDB \ + P2020RDB_NAND \ PM854 \ PM856 \ sbc8540 \ diff --git a/Makefile b/Makefile index c8a883c..652d930 100644 --- a/Makefile +++ b/Makefile @@ -2526,6 +2526,7 @@ P2020DS_config: unconfig P1011RDB_config \ P1020RDB_config \ P2010RDB_config \ +P2020RDB_NAND_config \ P2020RDB_config: unconfig @$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk index a56b536..17abcf8 100644 --- a/board/freescale/p1_p2_rdb/config.mk +++ b/board/freescale/p1_p2_rdb/config.mk @@ -24,6 +24,13 @@ # p1_p2rdb board # +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds +endif +endif + ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index cf9bffe..0009913 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -78,6 +78,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 8e97ad0..aacd4ca 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -43,6 +43,12 @@ #define CONFIG_P2020 #endif +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_NAND 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -82,16 +88,34 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ + /* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */ /* CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ /* CONFIG_SYS_IMMR */ + +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) @@ -158,6 +182,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO @@ -177,7 +207,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#endif #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -187,6 +221,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ @@ -202,10 +245,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); | OR_FCM_TRLX \ | OR_FCM_EHTR) +#ifdef CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#endif #define CONFIG_SYS_VSC7385_BASE 0xffb00000 @@ -371,14 +421,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * Environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_IS_IN_FLASH 1 + #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 + #define CONFIG_ENV_ADDR 0xfff80000 + #else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #endif + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile new file mode 100644 index 0000000..77a5137 --- /dev/null +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -0,0 +1,123 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 +PAD_TO := 0xfff01000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S + +$(obj)start.S: + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c new file mode 100644 index 0000000..fd24452 --- /dev/null +++ b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c @@ -0,0 +1,97 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <mpc85xx.h> +#include <asm-ppc/io.h> +#include <ns16550.h> +#include <nand.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_law.h> + +#define SYSCLK_MASK 0x00200000 +#define BOARDREV_MASK 0x10100000 +#define BOARDREV_B 0x10100000 +#define BOARDREV_C 0x00100000 + +#define SYSCLK_66 66666666 +#define SYSCLK_50 50000000 +#define SYSCLK_100 100000000 + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong bootflag) +{ + uint plat_ratio, bus_clk, sys_clk; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + uint val, temp, sysclk_mask; + + val = pgpio->gpdat; + sysclk_mask = val & SYSCLK_MASK; + temp = val & BOARDREV_MASK; + if (temp == BOARDREV_C) { + if(sysclk_mask == 0) + sys_clk = SYSCLK_66; + else + sys_clk = SYSCLK_100; + } else if (temp == BOARDREV_B) { + if(sysclk_mask == 0) + sys_clk = SYSCLK_66; + else + sys_clk = SYSCLK_50; + } + + plat_ratio = gur->porpllsr & 0x0000003e; + plat_ratio >>= 1; + bus_clk = plat_ratio * sys_clk; + NS16550_init((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* copy code to DDR and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} -- 1.5.6.3

2 2

[U-Boot] [PATCH] sbc8641d: fix LAW so board doesn't hang on DDR init
by Paul Gortmaker 08 Oct '09

08 Oct '09

All versions between now and since this commit: commit bd76729bcbfd64b5d016a9b936f058931fc06eaf MPC86xx: set CONFIG_MAX_MEM_MAPPED to 2G by default will fail to allow the SBC8641D to get past DDR init, because the LAW config was overlapping. Eventually this board will do SPD EEPROM config, but for now this gets the board working again. Signed-off-by: Paul Gortmaker <paul.gortmaker(a)windriver.com> --- board/sbc8641d/law.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index 760c693..d20fa51 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -44,14 +44,17 @@ struct law_entry law_table[] = { +#if !defined(CONFIG_SPD_EEPROM) SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), +#endif SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; -- 1.6.5.rc1

2 1

[U-Boot] [PATCH] relocation: Do not relocate NULL pointers.
by Joakim Tjernlund 08 Oct '09

08 Oct '09

NULL is an absolute value and should not be relocated. After this correction code like: void weak_fun(void) __attribute__((weak)); printf("weak_fun:%p\n", weak_fun); will still print null after relocation. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund(a)transmode.se> --- So here is the latest version of the patch. v2: included ppc4xx too. cpu/mpc512x/start.S | 6 ++++-- cpu/mpc5xx/start.S | 6 ++++-- cpu/mpc5xxx/start.S | 6 ++++-- cpu/mpc8220/start.S | 6 ++++-- cpu/mpc824x/start.S | 6 ++++-- cpu/mpc8260/start.S | 6 ++++-- cpu/mpc83xx/start.S | 6 ++++-- cpu/mpc85xx/start.S | 6 ++++-- cpu/mpc86xx/start.S | 6 ++++-- cpu/mpc8xx/start.S | 6 ++++-- cpu/ppc4xx/start.S | 6 ++++-- 11 files changed, 44 insertions(+), 22 deletions(-) diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 360682d..a00e045 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -609,15 +609,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 106935c..85ea7a8 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -458,15 +458,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 6b1162a..eb42939 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -684,15 +684,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index 3abc619..af9472d 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -649,15 +649,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index 39325cd..750457b 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -589,15 +589,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index 379f2fb..edb95e6 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -909,15 +909,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 26e3106..ee4b862 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -957,16 +957,18 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b #ifndef CONFIG_NAND_SPL /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 4f7236f..d56003b 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -932,15 +932,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 63cc8db..e65f1c0 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -733,15 +733,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index 8864c37..e84326e 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -589,15 +589,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index f2b8908..c3cf2ba 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1568,15 +1568,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 -- 1.6.4.4

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[U-Boot] [PATCH] mpc512x: fix fixed_sdram() init code.
by Wolfgang Denk 08 Oct '09

08 Oct '09

Commit 054197ba and later fixes used an array to initialize some of the MDDRC parameters; however, the use of an array turned out to be a bad idea as it was not possible to correlate structure entries to array indices in readable and reliable way. Now we use a struct instead, which makes this self-explanatory. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- board/freescale/mpc5121ads/mpc5121ads.c | 12 +++++----- cpu/mpc512x/fixed_sdram.c | 33 +++++++++++++++++------------- include/asm-ppc/immap_512x.h | 10 +++++++++ include/asm-ppc/mpc512x.h | 3 +- 4 files changed, 37 insertions(+), 21 deletions(-) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 13bd73c..2fa3650 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -169,11 +169,11 @@ phys_size_t initdram(int board_type) * Elpida MDDRC and initialization settings are an alternative * to the Default Micron ones for all but the earliest Rev 4 boards */ - u32 elpida_mddrc_config[4] = { - CONFIG_SYS_MDDRC_TIME_CFG0, - CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, - CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, - CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, + ddr512x_config_t elpida_mddrc_config = { + .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, + .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0, + .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, + .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, }; u32 elpida_init_sequence[] = { @@ -229,7 +229,7 @@ phys_size_t initdram(int board_type) if (is_micron()) { msize = fixed_sdram(NULL, NULL, 0); } else { - msize = fixed_sdram(elpida_mddrc_config, + msize = fixed_sdram(&elpida_mddrc_config, elpida_init_sequence, sizeof(elpida_init_sequence)/sizeof(u32)); } diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index 673d61e..442b5fc 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -26,13 +26,13 @@ #include <asm/mpc512x.h> /* - * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers + * MDDRC Config Runtime Settings */ -u32 default_mddrc_config[4] = { - CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */ - CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */ - CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */ - CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ +ddr512x_config_t default_mddrc_config = { + .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG, + .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0, + .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1, + .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2, }; u32 default_init_seq[] = { @@ -74,7 +74,8 @@ u32 default_init_seq[] = { * The board doesn't use memory modules that have serial presence * detect or similar mechanism for discovery of the DRAM settings */ -long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) +long int fixed_sdram(ddr512x_config_t *mddrc_config, + u32 *dram_init_seq, int seq_sz) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; @@ -83,7 +84,7 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) /* take default settings and init sequence if necessary */ if (mddrc_config == NULL) - mddrc_config = default_mddrc_config; + mddrc_config = &default_mddrc_config; if (dram_init_seq == NULL) { dram_init_seq = default_init_seq; seq_sz = sizeof(default_init_seq)/sizeof(u32); @@ -130,18 +131,22 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) * put MDDRC in CMD mode and * set the max time between refreshes to 0 during init process */ - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK); - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK); - out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]); - out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]); + out_be32(&im->mddrc.ddr_sys_config, + mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK); + out_be32(&im->mddrc.ddr_time_config0, + mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK); + out_be32(&im->mddrc.ddr_time_config1, + mddrc_config->ddr_time_config1); + out_be32(&im->mddrc.ddr_time_config2, + mddrc_config->ddr_time_config2); /* Initialize DDR with either default or supplied init sequence */ for (i = 0; i < seq_sz; i++) out_be32(&im->mddrc.ddr_command, dram_init_seq[i]); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]); - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]); + out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0); + out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config); return msize; } diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 79cdd80..bdc6ff2 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -347,6 +347,16 @@ typedef struct ddr512x { #define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF /* + * DDR Memory Controller Configuration settings + */ +typedef struct ddr512x_config { + u32 ddr_sys_config; /* System Configuration Register */ + u32 ddr_time_config0; /* Timing Configuration Register */ + u32 ddr_time_config1; /* Timing Configuration Register */ + u32 ddr_time_config2; /* Timing Configuration Register */ +} ddr512x_config_t; + +/* * DMA/Messaging Unit */ typedef struct dma512x { diff --git a/include/asm-ppc/mpc512x.h b/include/asm-ppc/mpc512x.h index 8ef0d9c..960e229 100644 --- a/include/asm-ppc/mpc512x.h +++ b/include/asm-ppc/mpc512x.h @@ -50,7 +50,8 @@ static inline void sync_law(volatile void *addr) /* * Prototypes */ -extern long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz); +extern long int fixed_sdram(ddr512x_config_t *mddrc_config, + u32 *dram_init_seq, int seq_sz); extern int mpc5121_diu_init(void); extern void ide_set_reset(int idereset); -- 1.6.0.6

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[U-Boot] Please pull u-boot-ppc4xx/master
by Stefan Roese 08 Oct '09

08 Oct '09

Hi Wolfgang, please pull those fixes and updates (initial version was posted before the merge window was closed). Thanks. The following changes since commit 99dbd4efd6d5ecc37d7e8f28b20d9be8c83055c7: Ben Warren (1): Add information about return values of xxx_eth_register() in documentation are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Mike Nuss (1): PPC4xx: Denali core: Fix incorrect DDR row bits Niklaus Giger (4): ppc4xx: Cleanup some HW register names ppc_4xx: Apply new HW register names ppc4xx: Rework cmd reginfo ppc4xx: respect 80-chars per line in ppc*.h files Stefan Roese (2): ppc4xx: Fix msg "initialization as root-complex failed" upon PCIe scan ppc4xx: Add PPC405EX(r) Rev D support board/amcc/bamboo/bamboo.c | 32 +- board/amcc/canyonlands/canyonlands.c | 25 +- board/amcc/ebony/ebony.c | 22 +- board/amcc/katmai/katmai.c | 25 +- board/amcc/kilauea/kilauea.c | 3 + board/amcc/luan/epld.h | 22 +- board/amcc/luan/luan.c | 22 +- board/amcc/makalu/makalu.c | 3 + board/amcc/ocotea/ocotea.c | 22 +- board/amcc/sequoia/sequoia.c | 28 +- board/amcc/taishan/showinfo.c | 112 ++-- board/amcc/taishan/taishan.c | 22 +- board/amcc/yosemite/yosemite.c | 32 +- board/amcc/yucca/yucca.c | 25 +- board/esd/common/cmd_loadpci.c | 2 +- board/esd/du440/du440.c | 28 +- board/esd/pmc440/cmd_pmc440.c | 10 +- board/esd/pmc440/pmc440.c | 32 +- board/exbitgen/init.S | 4 +- board/gdsys/gdppc440etx/gdppc440etx.c | 32 +- board/gdsys/intip/intip.c | 22 +- board/korat/korat.c | 28 +- board/lwmon5/lwmon5.c | 32 +- board/netstal/hcu5/hcu5.c | 28 +- board/pcs440ep/pcs440ep.c | 32 +- board/prodrive/alpr/alpr.c | 52 +- board/prodrive/p3p440/p3p440.c | 22 +- board/sandburst/common/ppc440gx_i2c.h | 2 +- board/sandburst/common/sb_common.c | 22 +- board/xes/xpedite1000/xpedite1000.c | 24 +- common/cmd_reginfo.c | 158 +---- cpu/ppc4xx/4xx_pci.c | 48 +- cpu/ppc4xx/4xx_pcie.c | 3 +- cpu/ppc4xx/Makefile | 4 + cpu/ppc4xx/cpu.c | 30 +- cpu/ppc4xx/cpu_init.c | 4 +- cpu/ppc4xx/denali_spd_ddr2.c | 2 +- cpu/ppc4xx/miiphy.c | 24 +- cpu/ppc4xx/reginfo.c | 370 +++++++++ cpu/ppc4xx/speed.c | 6 +- drivers/net/4xx_enet.c | 100 ++-- include/4xx_i2c.h | 2 +- include/asm-ppc/processor.h | 6 +- include/ppc405.h | 530 +++++++------- include/ppc440.h | 1401 +++++++++++++++++++-------------- include/ppc4xx.h | 36 +- include/ppc4xx_enet.h | 314 ++++---- post/cpu/ppc4xx/ether.c | 50 +- 48 files changed, 2151 insertions(+), 1704 deletions(-) create mode 100644 cpu/ppc4xx/reginfo.c

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Re: [U-Boot] [PATCH 1/3] memcpy: use 32-bit copies if possible
by Peter Tyser 07 Oct '09

07 Oct '09

Hi Alessandro, > --- a/lib_generic/string.c > +++ b/lib_generic/string.c > @@ -449,7 +449,16 @@ char * bcopy(const char * src, char * dest, int count) > void * memcpy(void * dest,const void *src,size_t count) > { > char *tmp = (char *) dest, *s = (char *) src; > + u32 *d32 = (u32 *)dest, *s32 = (u32 *) src; > > + /* if both are aligned, use 32-bit copy */ > + if ( (((int)dest & 3) | ((int)src & 3) | (count & 3)) == 0 ) { > + count /= 4; > + while (count--) > + *d32++ = *s32++; > + return dest; > + } > + /* else, use 1-byte copy */ > while (count--) > *tmp++ = *s++; If we're adding this logic, what about adding it such that: if (src/dest are 32-bit aligned and count > 3) { perform 32-bit copies till count <= 3 } perform remaining 8-bit copies till count == 0 You'd still get the performance boost but not have the requirement that count is evenly divisible by 4. You could do byte copies before the 32-bit copies to align the src/dest in some cases, but that might be overkill... Same comment goes for the memset implementation. Best, Peter

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[U-Boot] Xilinx LL temac update
by monstr＠monstr.eu 07 Oct '09

07 Oct '09

Hi Ben, I updated LL-temac driver - all fixes are there. Ad to your point Microblaze uses only one ethernet core. It is possible to use a lot of IPs but I don't have board like this to test it that's why I don't want change it. If you find any other problem please let me know. If is OK - I'll create net branch with these changes (LL_TEMAC/Emaclite + removing old Emac driver) Thanks, Michal

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