October 2009 - U-Boot

[U-Boot] [PATCH] TI DaVinci DVEVM: Add Config option for 64 bit Support
by s-paulraj＠ti.com 11 Oct '09

11 Oct '09

From: Sandeep Paulraj <s-paulraj(a)ti.com> Adding the CONFIG_SYS_64BIT_VSPRINTF in the DVEVM config. Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- include/configs/davinci_dvevm.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index f7d2399..b045e80 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -138,6 +138,7 @@ #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) #ifdef CONFIG_NOR_UART_BOOT -- 1.6.0.4

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[U-Boot] [PATCH] TI DaVinci Sonata: Add Config option for 64 bit Support
by s-paulraj＠ti.com 11 Oct '09

11 Oct '09

From: Sandeep Paulraj <s-paulraj(a)ti.com> Adding the CONFIG_SYS_64BIT_VSPRINTF fot the DM644x based Sonata Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- Previous patch incorrectly said that it was meant for the DM355 EVM include/configs/davinci_sonata.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 5a55c56..9138b2b 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -125,6 +125,7 @@ #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) #ifdef CONFIG_NOR_UART_BOOT -- 1.6.0.4

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[U-Boot] [PATCH] TI DaVinci Sonata: Add Config option for 64 bit Support
by s-paulraj＠ti.com 11 Oct '09

11 Oct '09

From: Sandeep Paulraj <s-paulraj(a)ti.com> Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM355 EVM config. Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- include/configs/davinci_sonata.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 5a55c56..9138b2b 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -125,6 +125,7 @@ #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) #ifdef CONFIG_NOR_UART_BOOT -- 1.6.0.4

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[U-Boot] Relocation size penalty calculation
by Graeme Russ 11 Oct '09

11 Oct '09

Out of curiosity, I wanted to see just how much of a size penalty I am incurring by using gcc -fpic / ld -pic on my x86 u-boot build. Here are the results (fixed width font will help - its space, not tab, formatted): Section non-reloc reloc --------------------------------------- .text 000118c4 000137fc <- 0x1f38 bytes (~8kB) bigger .rodata 00005bad 000059d0 .interp n/a 00000013 .dynstr n/a 00000648 .hash n/a 00000428 .eh_frame 00003268 000034fc .data 00000a6c 000001dc .data.rel n/a 00000098 .data.rel.ro.local n/a 00000178 .data.rel.local n/a 000007e4 .got 00000000 000001f0 .got.plt n/a 0000000c .rel.got n/a 000003e0 .rel.dyn n/a 00001228 .dynsym n/a 00000850 .dynamic n/a 00000080 .u_boot_cmd 000003c0 000003c0 .bss 00001a34 00001a34 .realmode 00000166 00000166 .bios 0000053e 0000053e ======================================= Total 0001d5dd 00022287 <- 0x4caa bytes (~19kB) bigger Its more than a 16% increase in size!!! .text accounts for a little under half of the total bloat, and of that, the crude dynamic loader accounts for only 341 bytes Have any metrics been done for PPC? Regards, Graeme

6 27

[U-Boot] [PATCH 5/5 v3] ARM:OMAP3:SDP3430: initial support
by Nishanth Menon 11 Oct '09

11 Oct '09

From: David Brownell <david-b(a)pacbell.net> ---- Sandeep pointed me to: http://lists.denx.de/pipermail/u-boot/2009-October/062086.html so the v3 of patch with size fixes ---- Start of support of Texas Instruments Software Development Platform(SDP) for OMAP3430 - SDP3430 Highlights of this platform are: Flash Memory devices: Sibley NOR, Micron 8bit NAND and OneNAND Connectivity: 3 UARTs and expanded 4 UART ports + IrDA Ethernet, USB Other peripherals: TWL5030 PMIC+Audio+Keypad VGA display Expansion ports: Memory devices plugin boards (PISMO) Connectivity board for GPS,WLAN etc.. Completely configurable boot sequence and device mapping etc.. For more details, please refer: http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&na… Support default jumpering and: - UART1/ttyS0 console(legacy sdp3430 u-boot) - UART3/ttyS2 console (matching other boards, and SDP HW docs) - Ethernet - mmc0 - NOR boot TODO: - mmc1 - NAND (boot or 128M storage) - OneNAND (boot or 256M storage) - Fix NOR env variable load - Review SDRC timing configuration/DPLL configuration - Dynamically read FPGA dip switch settings and map NOR/NAND/ONENAND devices to right chipselects Currently the UART1 is enabled by default. for compatibility with other OMAP3 u-boot platforms, enable the #define of CONSOLE_J9. Signed-off-by: David Brownell <david-b(a)pacbell.net> Signed-off-by: Nishanth Menon <nm(a)ti.com> Cc: Vikram Pandita <vikram.pandita(a)ti.com> Cc: Richard Woodruff <r-woodruff2(a)ti.com> Cc: Sandeep Paulraj <s-paulraj(a)ti.com> Cc: Tom Rix <tom.rix(a)windriver.com> Cc: Dirk Behme <dirk.behme(a)googlemail.com> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/ti/sdp3430/Makefile | 49 +++++ board/ti/sdp3430/config.mk | 33 +++ board/ti/sdp3430/sdp.c | 204 +++++++++++++++++++ board/ti/sdp3430/sdp.h | 417 +++++++++++++++++++++++++++++++++++++++ include/configs/omap3_sdp3430.h | 369 ++++++++++++++++++++++++++++++++++ 8 files changed, 1077 insertions(+), 0 deletions(-) create mode 100644 board/ti/sdp3430/Makefile create mode 100644 board/ti/sdp3430/config.mk create mode 100644 board/ti/sdp3430/sdp.c create mode 100644 board/ti/sdp3430/sdp.h create mode 100644 include/configs/omap3_sdp3430.h diff --git a/MAINTAINERS b/MAINTAINERS index 2297651..5742782 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -628,6 +628,7 @@ Guennadi Liakhovetski <g.liakhovetski(a)gmx.de> Nishanth Menon <nm(a)ti.com> + omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC) omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC) David Müller <d.mueller(a)elsoft.ch> diff --git a/MAKEALL b/MAKEALL index 38cd076..9bf75e8 100755 --- a/MAKEALL +++ b/MAKEALL @@ -603,6 +603,7 @@ LIST_ARM_CORTEX_A8=" \ omap3_overo \ omap3_evm \ omap3_pandora \ + omap3_sdp3430 \ omap3_zoom1 \ omap3_zoom2 \ " diff --git a/Makefile b/Makefile index 9637643..8dbe552 100644 --- a/Makefile +++ b/Makefile @@ -3144,6 +3144,9 @@ omap3_zoom1_config : unconfig omap3_zoom2_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3 +omap3_sdp3430_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3 + ######################################################################### ## XScale Systems ######################################################################### diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile new file mode 100644 index 0000000..2554c7b --- /dev/null +++ b/board/ti/sdp3430/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := sdp.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/sdp3430/config.mk b/board/ti/sdp3430/config.mk new file mode 100644 index 0000000..18e4761 --- /dev/null +++ b/board/ti/sdp3430/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2006-2009 +# Texas Instruments Incorporated, <www.ti.com> +# +# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c new file mode 100644 index 0000000..40cf26f --- /dev/null +++ b/board/ti/sdp3430/sdp.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated, <www.ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include "sdp.h" + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "OMAP3 SDP3430 board", +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "OneNAND", +#elif defined(CONFIG_ENV_IS_IN_NAND) + "NAND", +#else + "NOR", +#endif +}; + +/* Timing definitions for GPMC controller for Sibley NOR */ +static const u32 gpmc_sdp_nor[] = { + SDP3430_NOR_GPMC_CONF1, + SDP3430_NOR_GPMC_CONF2, + SDP3430_NOR_GPMC_CONF3, + SDP3430_NOR_GPMC_CONF4, + SDP3430_NOR_GPMC_CONF5, + SDP3430_NOR_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* + * Timing definitions for GPMC controller for Debug Board + * Debug board contains access to ethernet and DIP Switch setting + * information etc. + */ +static const u32 gpmc_sdp_debug[] = { + SDP3430_DEBUG_GPMC_CONF1, + SDP3430_DEBUG_GPMC_CONF2, + SDP3430_DEBUG_GPMC_CONF3, + SDP3430_DEBUG_GPMC_CONF4, + SDP3430_DEBUG_GPMC_CONF5, + SDP3430_DEBUG_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* Timing defintions for GPMC OneNAND */ +static const u32 gpmc_sdp_onenand[] = { + SDP3430_ONENAND_GPMC_CONF1, + SDP3430_ONENAND_GPMC_CONF2, + SDP3430_ONENAND_GPMC_CONF3, + SDP3430_ONENAND_GPMC_CONF4, + SDP3430_ONENAND_GPMC_CONF5, + SDP3430_ONENAND_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* GPMC definitions for GPMC NAND */ +static const u32 gpmc_sdp_nand[] = { + SDP3430_NAND_GPMC_CONF1, + SDP3430_NAND_GPMC_CONF2, + SDP3430_NAND_GPMC_CONF3, + SDP3430_NAND_GPMC_CONF4, + SDP3430_NAND_GPMC_CONF5, + SDP3430_NAND_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* gpmc_cfg is initialized by gpmc_init and we use it here */ +extern struct gpmc *gpmc_cfg; + +/** + * @brief board_init - gpmc and basic setup as phase1 of boot sequence + * + * @return 0 + */ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* TODO: Dynamically pop out CS mapping and program accordingly */ + /* Configure devices for default ON ON ON settings */ + enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0], + CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M); + enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000, + GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000, + GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE, + GPMC_SIZE_16M); + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c) +#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b) + +/** + * @brief ether_init Take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + */ +static void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + writew(0x0, LAN_RESET_REGISTER); + do { + writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto reset_err_out; + --cnt; + } while (readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto reset_err_out; + --cnt; + } while (readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG); + udelay(1000); +reset_err_out: + return; + +#endif +} + +/** + * @brief misc_init_r - Configure SDP board specific configurations + * such as power configurations, ethernet initialization as phase2 of + * boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ + /* Partial setup: + * VAUX3 - 2.8V for DVI + * VPLL1 - 1.8V + * VDAC - 1.8V + * and turns on LEDA/LEDB (not needed ... NOP?) + */ + twl4030_power_init(); + + /* FIXME finish setup: + * VAUX1 - 2.8V for mainboard I/O + * VAUX2 - 2.8V for camera + * VAUX4 - 1.8V for OMAP3 CSI + * VMMC1 - 3.15V (init, variable) for MMC1 + * VMMC2 - 1.85V for MMC2 + * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM + * VPLL2 - 1.8V + */ + ether_init(); + + return 0; +} + +/** + * @brief set_muxconf_regs Setting up the configuration Mux registers + * specific to the hardware. Many pins need to be moved from protect + * to primary mode. + */ +void set_muxconf_regs(void) +{ + /* platform specific muxes */ + MUX_SDP3430(); +} diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h new file mode 100644 index 0000000..3526e94 --- /dev/null +++ b/board/ti/sdp3430/sdp.h @@ -0,0 +1,417 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated + * Richard Woodruff <r-woodruff2(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _BOARD_SDP_H_ +#define _BOARD_SDP_H_ + +#define OFF_IN_PD 0 +#define OFF_OUT_PD 0 + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_SDP3430()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\ + MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\ + MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\ + MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\ + MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\ + MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\ + MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + /*Audio InterfACe */\ + MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + /*Expansion Card */\ + MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\ + MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\ + MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\ + MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\ + MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\ + MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\ + MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\ + MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\ + MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\ + MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\ + MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\ + MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\ + MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\ + MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\ + MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\ + MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\ + MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\ + MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\ + MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\ + MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\ + MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + /*Die to Die */\ + MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/ + +/* + * GPMC Timing definitions for SDP3430 + * at L3 = 166Mhz + */ + +/* Timing definitions for GPMC controller for Sibley NOR */ +#define SDP3430_NOR_GPMC_CONF1 0x00001200 +#define SDP3430_NOR_GPMC_CONF2 0x001F1F00 +#define SDP3430_NOR_GPMC_CONF3 0x00080802 +#define SDP3430_NOR_GPMC_CONF4 0x1C091C09 +#define SDP3430_NOR_GPMC_CONF5 0x01131F1F +#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2 + +/* + * Timing definitions for GPMC controller for Debug Board + * Debug board contains access to ethernet and DIP Switch setting + * information etc. + */ +#define SDP3430_DEBUG_GPMC_CONF1 0x00611200 +#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01 +#define SDP3430_DEBUG_GPMC_CONF3 0x00080803 +#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09 +#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F +#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4 + +/* Timing defintions for GPMC OneNAND */ +#define SDP3430_ONENAND_GPMC_CONF1 0x00001200 +#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01 +#define SDP3430_ONENAND_GPMC_CONF3 0x00030301 +#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04 +#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010 +#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000 + +/* GPMC definitions for GPMC NAND */ +#define SDP3430_NAND_GPMC_CONF1 0x00000800 +#define SDP3430_NAND_GPMC_CONF2 0x00141400 +#define SDP3430_NAND_GPMC_CONF3 0x00141400 +#define SDP3430_NAND_GPMC_CONF4 0x0F010F01 +#define SDP3430_NAND_GPMC_CONF5 0x010C1414 +#define SDP3430_NAND_GPMC_CONF6 0x1F040A80 + +#endif /* _BOARD_SDP_H_ */ diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h new file mode 100644 index 0000000..229dc5e --- /dev/null +++ b/include/configs/omap3_sdp3430.h @@ -0,0 +1,369 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments Incorporated. + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <x0khasim(a)ti.com> + * Nishanth Menon <nm(a)ti.com> + * + * Configuration settings for the 3430 TI SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* TODO: REMOVE THE FOLLOWING + * Retained the following till size.h is removed in u-boot + */ +#include <asm/sizes.h> +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * NOTE: these #defines presume standard SDP jumper settings. + * In particular: + * - 26 MHz clock (not 19.2 or 38.4 MHz) + * - Boot from 128MB NOR, not NAND or OneNAND + * + * At this writing, OMAP3 U-Boot support doesn't permit concurrent + * support for all the flash types the board supports. + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + * Total Size Environment - 256k + * Malloc - add 256k + */ +#define CONFIG_ENV_SIZE (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/*--------------------------------------------------------------------------*/ + +/* + * Hardware drivers + */ + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER 1 + +/* + * serial port - NS16550 compatible + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be + * swapped with UART2 via jumpering. Downsides of using J8: it doesn't + * support UART boot (that's only for UART3); it prevents sharing a Linux + * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards. + * + * UART boot uses UART3 on J9, and the SDP user's guide says to use + * that for console. Downsides of using J9: you can't use IRDA too; + * since UART3 isn't in the CORE power domain, it may be a bit less + * usable in certain PM-sensitive debug scenarios. + */ +#undef CONSOLE_J9 /* else J8/UART1 (innermost) */ + +#ifdef CONSOLE_J9 +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ +#else +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 */ +#endif + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +/* + * I2C for power management setup + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* OMITTED: single 1 Gbit MT29F1G NAND flash */ + +/* + * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash + */ +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */ +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ + +#define CONFIG_SYS_FLASH_CFI_WIDTH 2 +#define PHYS_FLASH_SIZE (128 << 20) +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */ + +/* timeout values are in milliseconds */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */ + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10) +#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE) +/*--------------------------------------------------------------------------*/ + +/* commands to include */ +#include <config_cmd_default.h> + +/* Enabled commands */ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NET + +/* Disabled commands */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +/*--------------------------------------------------------------------------*/ +/* + * MMC boot support + */ + +#if defined(CONFIG_CMD_MMC) +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 +#endif + +/*---------------------------------------------------------------------------- + * SMSC9115 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- + */ +#if defined(CONFIG_CMD_NET) + +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE DEBUG_BASE +#define CONFIG_LAN91C96_EXT_PHY + +#define CONFIG_BOOTP_SEND_HOSTNAME +/* + * BOOTP fields + */ +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 +#endif /* (CONFIG_CMD_NET) */ + +/* + * Environment setup + * + * Default boot order: mmc bootscript, MMC uImage, NOR image. + * Network booting environment must be configured at site. + */ + +/* allow overwriting serial config and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS0,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "norargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock3 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from MMC/SD ...; " \ + "autoscr ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from MMC/SD ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "norboot=echo Booting from NOR ...; " \ + "run norargs; " \ + "bootm 0x80000\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmcinit; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run norboot; " \ + "fi; " \ + "fi; " \ + "else run norboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 + +/*--------------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP34XX SDP # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg - + * a basic sanity check ONLY + * IF you would like to increase coverage, increase the end address + * or run the test with custom options + */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20)) + +/* Default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) + +/*--------------------------------------------------------------------------*/ + +/* + * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */ +#endif + +/* + * SDRAM Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*--------------------------------------------------------------------------*/ + +/* + * NOR FLASH usage ... default nCS0: + * - one 256KB sector for U-Boot + * - one 256KB sector for its parameters (not all used) + * - eight sectors (2 MB) for kernel + * - rest for JFFS2 + */ + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +/* + * NAND FLASH usage ... default nCS1: + * - four 128KB sectors for X-Loader + * - four 128KB sectors for U-Boot + * - two 128KB sector for its parameters + * - 32 sectors (4 MB) for kernel + * - rest for filesystem + */ + +/* + * OneNAND FLASH usage ... default nCS2: + * - four 128KB sectors for X-Loader + * - two 128KB sectors for U-Boot + * - one 128KB sector for its parameters + * - sixteen sectors (2 MB) for kernel + * - rest for filesystem + */ + +/*--------------------------------------------------------------------------*/ + +#ifndef __ASSEMBLY__ +extern struct gpmc *gpmc_cfg; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#endif /* __CONFIG_H */ -- 1.6.0.4

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Re: [U-Boot] [PATCH V2 1/3] memcpy: copy one word at a time if possible
by Wolfgang Denk 11 Oct '09

11 Oct '09

Dear Alessandro Rubini, In message <45d5e3a574bf4844f46f50b2c88054a5b28f973b.1255000877.git.rubini@ unipv.it> you wrote: > From: Alessandro Rubini <rubini(a)unipv.it> > > Signed-off-by: Alessandro Rubini <rubini(a)unipv.it> > Acked-by: Andrea Gallo <andrea.gallo(a)stericsson.com> > --- > lib_generic/string.c | 17 +++++++++++++---- > 1 files changed, 13 insertions(+), 4 deletions(-) > > diff --git a/lib_generic/string.c b/lib_generic/string.c > index 181eda6..9911941 100644 > --- a/lib_generic/string.c > +++ b/lib_generic/string.c > @@ -446,12 +446,21 @@ char * bcopy(const char * src, char * dest, int count) > * You should not use this function to access IO space, use memcpy_toio() > * or memcpy_fromio() instead. > */ > -void * memcpy(void * dest,const void *src,size_t count) > +void * memcpy(void *dest, const void *src, size_t count) > { > - char *tmp = (char *) dest, *s = (char *) src; > + char *d8 = (char *)dest, *s8 = (char *)src; > + unsigned long *dl = (unsigned long *)dest, *sl = (unsigned long *)src; > > + /* if all data is aligned (common case), copy a word at a time */ > + if ( (((int)dest | (int)src | count) & (sizeof(long) - 1)) == 0) { > + count /= sizeof(unsigned long); > + while (count--) > + *dl++ = *sl++; > + return dest; > + } > + /* else, use 1-byte copy */ > while (count--) > - *tmp++ = *s++; > + *d8++ = *s8++; > > return dest; I think we should change this if-else into a plain if, something like that: void * memcpy(void *dest, const void *src, size_t count) { char *tmp = (char *) dest, *s = (char *) src; char *d8 = (char *)dest, *s8 = (char *)src; unsigned long *dl = (unsigned long *)dest, *sl = (unsigned long *)src; /* while all data is aligned (common case), copy a word at a time */ if ( (((int)dest | (int)src | count) & (sizeof(long) - 1)) == 0) { while (count) { *dl++ = *sl++; count -= sizeof(unsigned long); } } while (count--) *d8++ = *s8++; return dest; } This way we can have both - the "long" copy of a potential aligne dfirst part, and the byte copy of any trailing (or unaligned) part. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Computers make excellent and efficient servants, but I have no wish to serve under them. Captain, a starship also runs on loyalty to one man. And nothing can replace it or him. -- Spock, "The Ultimate Computer", stardate 4729.4

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Re: [U-Boot] Relocation size penalty calculation
by Graeme Russ 11 Oct '09

11 Oct '09

On Sun, Oct 11, 2009 at 3:18 AM, J. William Campbell <jwilliamcampbell(a)comcast.net> wrote: > Graeme Russ wrote: >> >> On Sat, Oct 10, 2009 at 9:47 PM, Joakim Tjernlund >> <joakim.tjernlund(a)transmode.se> wrote: >> >>> >>> Graeme Russ <graeme.russ(a)gmail.com> wrote on 10/10/2009 12:38:19: >>> >>>> >>>> On Sat, Oct 10, 2009 at 8:27 PM, Joakim Tjernlund >>>> <joakim.tjernlund(a)transmode.se> wrote: >>>> >>>>> >>>>> Graeme Russ <graeme.russ(a)gmail.com> wrote on 10/10/2009 10:46:52: >>>>> >>>>>> >>>>>> On Sat, Oct 10, 2009 at 7:07 PM, Joakim Tjernlund >>>>>> <joakim.tjernlund(a)transmode.se> wrote: >>>>>> >>>>>>> >>>>>>> Graeme Russ <graeme.russ(a)gmail.com> wrote on 10/10/2009 06:43:52: >>>>>>> >>>>>>>> >>>>>>>> On Fri, Oct 9, 2009 at 10:12 AM, Joakim Tjernlund >>>>>>>> <joakim.tjernlund(a)transmode.se> wrote: >>>>>>>> >>>>>>>>>> >>>>>>>>>> On Fri, Oct 9, 2009 at 9:27 AM, J. William Campbell >>>>>>>>>> <jwilliamcampbell(a)comcast.net> wrote: >>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> Graeme Russ wrote: >>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> On Fri, Oct 9, 2009 at 2:58 AM, J. William Campbell >>>>>>>>>>>> <jwilliamcampbell(a)comcast.net> wrote: >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>> Graeme Russ wrote: >>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>> Out of curiosity, I wanted to see just how much of a size >>>>>>>>>>>>>> penalty I am >>>>>>>>>>>>>> incurring by using gcc -fpic / ld -pic on my x86 u-boot build. >>>>>>>>>>>>>> Here are >>>>>>>>>>>>>> the results (fixed width font will help - its space, not tab, >>>>>>>>>>>>>> formatted): >>>>>>>>>>>>>> >>>>>>>>>>>>>> Section non-reloc reloc >>>>>>>>>>>>>> --------------------------------------- >>>>>>>>>>>>>> .text 000118c4 000137fc <- 0x1f38 bytes (~8kB) >>>>>>>>>>>>>> bigger >>>>>>>>>>>>>> .rodata 00005bad 000059d0 >>>>>>>>>>>>>> .interp n/a 00000013 >>>>>>>>>>>>>> .dynstr n/a 00000648 >>>>>>>>>>>>>> .hash n/a 00000428 >>>>>>>>>>>>>> .eh_frame 00003268 000034fc >>>>>>>>>>>>>> .data 00000a6c 000001dc >>>>>>>>>>>>>> .data.rel n/a 00000098 >>>>>>>>>>>>>> .data.rel.ro.local n/a 00000178 >>>>>>>>>>>>>> .data.rel.local n/a 000007e4 >>>>>>>>>>>>>> .got 00000000 000001f0 >>>>>>>>>>>>>> .got.plt n/a 0000000c >>>>>>>>>>>>>> .rel.got n/a 000003e0 >>>>>>>>>>>>>> .rel.dyn n/a 00001228 >>>>>>>>>>>>>> .dynsym n/a 00000850 >>>>>>>>>>>>>> .dynamic n/a 00000080 >>>>>>>>>>>>>> .u_boot_cmd 000003c0 000003c0 >>>>>>>>>>>>>> .bss 00001a34 00001a34 >>>>>>>>>>>>>> .realmode 00000166 00000166 >>>>>>>>>>>>>> .bios 0000053e 0000053e >>>>>>>>>>>>>> ======================================= >>>>>>>>>>>>>> Total 0001d5dd 00022287 <- 0x4caa bytes >>>>>>>>>>>>>> (~19kB) bigger >>>>>>>>>>>>>> >>>>>>>>>>>>>> Its more than a 16% increase in size!!! >>>>>>>>>>>>>> >>>>>>>>>>>>>> .text accounts for a little under half of the total bloat, and >>>>>>>>>>>>>> of that, >>>>>>>>>>>>>> the crude dynamic loader accounts for only 341 bytes >>>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>> Hi Graeme, >>>>>>>>>>>>> I would be interested in a third option (column), the x86 >>>>>>>>>>>>> build with >>>>>>>>>>>>> just -mrelocateable but NOT -fpic. It will not be definitive >>>>>>>>>>>>> because >>>>>>>>>>>>> there >>>>>>>>>>>>> will be extra code that references the GOT and missing code to >>>>>>>>>>>>> do some of >>>>>>>>>>>>> the relocation, but it would still be interesting. >>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> x86 does not have -mrelocatable. This is a PPC only option :( >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> Hi Graeme, >>>>>>>>>>> You are unfortunately correct. However, I wonder if we >>>>>>>>>>> can get >>>>>>>>>>> essentially the same result by executing the final ld step with >>>>>>>>>>> the >>>>>>>>>>> --emit-relocs switch included. This may also include some "extra" >>>>>>>>>>> sections >>>>>>>>>>> that we would want to strip out, but if it works, it could give >>>>>>>>>>> all >>>>>>>>>>> ELF-based systems a way to a relocatable u-boot. >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>> >>>>>>>>>> I don't think --emit-relocs is necessary with -pic. I haven't gone >>>>>>>>>> through >>>>>>>>>> all the permutations to see if there is a smaller option, but gcc >>>>>>>>>> -fpic and >>>>>>>>>> ld -pie creates enough information to perform relocation on the >>>>>>>>>> x86 >>>>>>>>>> platform >>>>>>>>>> >>>>>>>>> >>>>>>>>> Try -fvisibility=hidden >>>>>>>>> >>>>>>>> >>>>>>>> Thanks - Shaved another 2539 bytes off the binary >>>>>>>> >>>>>>>> Also found out how to get rid of .eh_frame (crept in when I upgraded >>>>>>>> to >>>>>>>> gcc 4.4.1) with -fno-dwarf2-cfi-asm, so that shaves another 13452 >>>>>>>> bytes >>>>>>>> >>>>>>>> Total saving of 15.6k >>>>>>>> >>>>>>> >>>>>>> Great, so now you are back at just a few percent added I guess? >>>>>>> >>>>>>> >>>>>>> >>>>>> >>>>>> Not really - The .eh_frame saving applies to both relocated and non >>>>>> relocated builds >>>>>> >>>>> >>>>> OK, so you didn't use PIC before at all? >>>>> >>>>> Anyway I think you can do more. Using -Bsymbolic you should get >>>>> away with RELATIVE relocs only and be able to skip a lot of segments >>>>> above. >>>>> Have a look at uClibc ldso/ldso/dl-startup.c >>>>> >>>>> >>>>> >>>> >>>> My build options thus far are: >>>> >>>> PLATFORM_RELFLAGS += -fpie -fvisibility=hidden >>>> PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm >>>> PLATFORM_LDFLAGS += -pie >>>> >>>> -fpic / -pic make no difference >>>> >>> >>> not on x86, on ppc it is a big difference. >>> >>> >>>> >>>> Interestingly, -Bsymbolic adds exactly 8 bytes to .dynamic, but doesn't >>>> change the size of any other section >>>> >>>> Pulling apart the relocation sections, it seems that all relocations are >>>> already RELATIVE even without -Bsymbolic >>>> >>> >>> Ah, that is because you built an exe with -pie >>> Then you should be able to drop everything but the RELATIVE >>> from the linking, or almost in any case. >>> >>> Jocke >>> >>> >>> >> >> Hmm, so its seems I may have hit the limit. I tried: >> >> PLATFORM_LDFLAGS += -r --emit-relocs >> >> but there is not enough information left to complete the relocation. > > Hi Graeme, > I am glad you tried this. It should work, -fpie should not be necessary. > Did you also change PLATFORM_RELFLAGS to omit the -fpie? Without pie, and > with no libraries linked in that are pie, there should BE no .got, AFIK. I > wonder if absolutely everything is getting re-built, like maybe there is a > library routine that is being linked in? What exactly was missing when you > compiled and linked without pie? I just tried with: PLATFORM_RELFLAGS += -fvisibility=hidden PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm PLATFORM_LDFLAGS += -Bsymbolic --emit-relocs There is relocation information in the linker output, however it is not marked for allocation so it gets stripped out when creating u-boot.bin > > Best Regards, > Bill Campbell >> >> It >> seems as though I need .rel.got, .got.plt, .dynsym and .rel.dyn in order >> to find the actual bytes that need modifying (it also seems to mess with >> the size of the stripped binary for some reason) >> >> Looks like I'll have to proceed with my original plan - a bit bloated, >> but it works >> >> Graeme >> >> >> > >

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Re: [U-Boot] [PATCH V4 2/3] lib_generic memset: fill one word at a time if possible
by Alessandro Rubini 10 Oct '09

10 Oct '09

> The above while can be slow if not the complier manages to turn into: But the compiler is able, and Wolfgang already told that in another thread. Yes, I checked my assembly. No, not all platforms and all versions. like Wolfgang. I think you may have a point, but unless you have a measured misworking case to show, we'd better stop here. /alessandro, who'll lift linux/arch/arm/lib/memcpy.S next time

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[U-Boot] [PATCH] OMAP3: Update Overo and Beagle environment
by Dirk Behme 10 Oct '09

10 Oct '09

From: Steve Sakoman <sakoman(a)gmail.com> Update default environment to support new kernel DSS2 subsystem and simplify rootfs type and location changes. Signed-off-by: Steve Sakoman <sakoman(a)gmail.com> Signed-off-by: Dirk Behme <dirk.behme(a)googlemail.com> --- include/configs/omap3_beagle.h | 27 +++++++++++++++++++-------- include/configs/omap3_overo.h | 27 +++++++++++++++++++-------- 2 files changed, 38 insertions(+), 16 deletions(-) Index: u-boot-ti/include/configs/omap3_overo.h =================================================================== --- u-boot-ti.orig/include/configs/omap3_overo.h +++ u-boot-ti/include/configs/omap3_overo.h @@ -155,16 +155,27 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ - "videomode=1024x768@60,vxres=1024,vyres=768\0" \ - "videospec=omapfb:vram:2M,vram:4M\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ "mmcargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ Index: u-boot-ti/include/configs/omap3_beagle.h =================================================================== --- u-boot-ti.orig/include/configs/omap3_beagle.h +++ u-boot-ti/include/configs/omap3_beagle.h @@ -164,16 +164,27 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ - "videomode=1024x768@60,vxres=1024,vyres=768\0" \ - "videospec=omapfb:vram:2M,vram:4M\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ "mmcargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \

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[U-Boot] [PATCH] TI: OMAP3: Overo Tobi ethernet support
by Olof Johansson 10 Oct '09

10 Oct '09

Add setup for ethernet on Tobi, allowing kernel/ramdisk to be loaded over tftp. Based on the omap3 evm code. I added a new highlevel define for Tobi to avoid having it dependent on CMD_NET (which would seem backward in this case). Signed-off-by: Olof Johansson <olof(a)lixom.net> diff --git a/board/overo/overo.c b/board/overo/overo.c index dd6d286..4a67360 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -32,6 +32,7 @@ #include <twl4030.h> #include <asm/io.h> #include <asm/arch/mux.h> +#include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> #include <asm/mach-types.h> #include "overo.h" @@ -62,6 +63,10 @@ int misc_init_r(void) twl4030_power_init(); twl4030_led_init(); +#if defined(CONFIG_OMAP3_OVERO_TOBI) + setup_net_chip(); +#endif + dieid_num_r(); return 0; @@ -76,4 +81,59 @@ int misc_init_r(void) void set_muxconf_regs(void) { MUX_OVERO(); +#if defined(CONFIG_OMAP3_OVERO_TOBI) + MUX_OVERO_TOBI(); +#endif +} + +#if defined(CONFIG_OMAP3_OVERO_TOBI) +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE; + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + /* Configure GPMC registers */ + writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); + writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); + writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); + writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); + writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); + writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); + writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); + + /* Make GPIO 64 as output pin */ + writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe); + + /* Now send a pulse on the GPIO pin */ + writel(GPIO0, &gpio3_base->setdataout); + udelay(1); + writel(GPIO0, &gpio3_base->cleardataout); + udelay(1); + writel(GPIO0, &gpio3_base->setdataout); +} +#endif + + + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; } + diff --git a/board/overo/overo.h b/board/overo/overo.h index 0b59120..f0ec18a 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -33,6 +33,8 @@ const omap3_sysinfo sysinfo = { #endif }; +static void setup_net_chip(void); + /* * IEN - Input Enable * IDIS - Input Disable @@ -378,4 +380,42 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ +#if defined(CONFIG_OMAP3_OVERO_TOBI) +#define MUX_OVERO_TOBI() \ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + /* - SMSC911X_NRES*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\ + /* - LAN_INTR */\ + + +#endif + #endif diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 07a031b..6616b55 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -28,7 +28,8 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_OMAP3_OVERO 1 /* working with overo */ +#define CONFIG_OMAP3_OVERO 1 /* working with overo */ +//#define CONFIG_OMAP3_OVERO_TOBI 1 /* overo mounted on tobi */ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> @@ -105,9 +106,13 @@ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ #undef CONFIG_CMD_IMLS /* List all found images */ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ +#if !defined(CONFIG_OMAP3_OVERO_TOBI) +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#endif + + #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 @@ -293,4 +298,18 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif +#if defined(CONFIG_OMAP3_OVERO_TOBI) +/*---------------------------------------------------------------------------- + * SMSC9115 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- + */ + +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 + +#endif /* (CONFIG_CMD_NET) */ + + #endif /* __CONFIG_H */

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