October 2009 - U-Boot

Re: [U-Boot] MIPS cpu has problem detecting CFI
by Andrew Dyer 13 Oct '09

13 Oct '09

On Sat, Oct 10, 2009 at 12:27 PM, <myuboot(a)fastmail.fm> wrote: > On Fri, 09 Oct 2009 12:16 -0500, "Andrew Dyer" <amdyer(a)gmail.com> wrote: >> On Fri, Oct 9, 2009 at 11:21 AM, <myuboot(a)fastmail.fm> wrote: >> > I think I found a problem in cpu/mips/start.S. >> > >> > gp register is used to point to the SDRAM. But after gp is adjusted to >> > proper location, a C function flush_cache is called. But this function >> > actually changes gp register before gp is used to jump to SDRAM. That >> > makes the u-boot run from flash and fails to detect CFI. >> > >> > Here is the assembler code for flush_cache.c >> > (gdb) disassem 0xb0000798 >> > Dump of assembler code for function flush_cache: >> > 0xb000078c <flush_cache+0>: lui gp,0x3 >> > 0xb0000790 <flush_cache+4>: addiu gp,gp,-32300 >> > 0xb0000794 <flush_cache+8>: addu gp,gp,t9 >> > >> > And here is how I fixed the issue - >> > >> > >> > diff --git a/u-boot-2009.08/cpu/mips/start.S >> > b/u-boot-2009.08/cpu/mips/start.S >> > index 57db589..0e8f8ed 100644 >> > --- a/u-boot-2009.08/cpu/mips/start.S >> > +++ b/u-boot-2009.08/cpu/mips/start.S >> > @@ -321,6 +321,7 @@ relocate_code: >> > move t6, gp >> > sub gp, CONFIG_SYS_MONITOR_BASE >> > add gp, a2 /* gp now adjusted */ >> > + move t8, gp >> > sub s1, gp, t6 /* s1 <-- relocation offset */ >> > >> > /* >> > @@ -358,6 +359,7 @@ relocate_code: >> > >> > /* Jump to where we've relocated ourselves. >> > */ >> > + move gp, t8 >> > addi t0, s2, in_ram - _start >> > jr t0 >> > nop >> >> Something seems weird here - IIRC, $gp is supposed to be saved in the >> stack frame during the function prologue and restored from the frame >> on exit. Also I think relying on $t8 is risky, as I don't believe it >> is guaranteed by the ABI to be preserved across function calls. >> >> What compiler are you using? Can you post the whole flush_cache() >> disassembly? > > You may be right. The c function should get the input arguments through > stack. I just use the same toolchain(with -S option) to generate the > assembler code and the assembler code does not show the modification on > the gp register. I am attaching the whole assembler code file here too. > But the assembler code I sent in my previous mail did show the gp > pointer is changed. In that email, I got that assembler using gdb > through a BDI debugger. I don't have BDI with me today so I cann't give > you the whole assembler code using BDI. > > Could it be the gcc toolchain generates the wrong code when it is > creating object file, but generates correct assembler code? Or the BDI > is changing the assembler code at run time such that I see the wrong > assembler code? But if that is the case, I don't know how to explain > with my workaround/fix the board did come up even without bdi and it > seems to work every time. I am so confused now. Any suggestion on > anything I can try? 1) please don't top post, put replies on the bottom, I fixed this in this post. 2) reply to the list, there are a lot of smart people (better versed in toolchains than I) who read it. I've cc'd the list on this one. 3) the assembler looks fine, but it doesn't have the function prologue that the gdb dump shows. I doubt the bdi is modifying the asm. I /think/ the linker might be the part that inserts that or maybe the compile after it generates the asm. Try looking at the output of '${CROSS_COMPILE}objdump --source cpu.o' and then '${CROSS_COMPILE}objdump --source u-boot'. 4) where did the toolchain come from, what version, etc.? Maybe run gcc with the -v option to see the subprograms and options it sets. 5) try downloading the mips ELDK and build u-boot with that.

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[U-Boot] Pull request - net
by Ben Warren 12 Oct '09

12 Oct '09

Wolfgang, With this pull, I believe all net-related changes for 2009.11 are in. The following changes since commit cd77dd109c4a439519a78c32eddc42bdebc7a61f: Wolfgang Denk (1): Merge branch 'reloc' are available in the git repository at: git://git.denx.de/u-boot-net.git master Luigi 'Comio' Mantellini (3): Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an arbitrary number of mii buses. Add bb_miiphy_init call before any ethernet bring-up code. Update all board to support new bbmiiphy driver (with multibus support) doc/README.bitbangMII | 56 +++++++ drivers/net/phy/miiphybb.c | 346 +++++++++++++++++++++++++++++------------- include/configs/ISPAN.h | 4 + include/configs/MPC8260ADS.h | 3 + include/configs/MPC8266ADS.h | 4 + include/configs/MPC8560ADS.h | 4 + include/configs/Rattler.h | 4 + include/configs/SBC8540.h | 4 + include/configs/TQM8272.h | 3 + include/configs/VoVPN-GW.h | 5 + include/configs/ZPC1900.h | 4 + include/configs/ep8248.h | 1 + include/configs/ep82xxm.h | 1 + include/configs/gw8260.h | 5 + include/configs/hymod.h | 12 ++ include/configs/muas3001.h | 4 + include/configs/ppmc8260.h | 4 + include/configs/sacsng.h | 4 + include/configs/sbc8260.h | 4 + include/configs/sbc8560.h | 4 + include/miiphy.h | 25 +++- lib_arm/board.c | 7 + lib_avr32/board.c | 7 + lib_blackfin/board.c | 7 + lib_i386/board.c | 9 +- lib_m68k/board.c | 7 + lib_mips/board.c | 7 + lib_ppc/board.c | 7 + lib_sh/board.c | 7 + lib_sparc/board.c | 7 + 30 files changed, 460 insertions(+), 106 deletions(-) create mode 100644 doc/README.bitbangMII

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[U-Boot] [PATCH 00/13] ppc: Fix relocation
by Peter Tyser 12 Oct '09

12 Oct '09

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[U-Boot] [PATCH 2/7] mpc85xx: Add eSDHC support for MPC8569E-MDS boards
by Anton Vorontsov 12 Oct '09

12 Oct '09

eSDHC is mutually exlusive with UART0* and I2C2. When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. * Actually, according to User's Guide we can use eSDHC in serial (1-bit) mode without disabling UART0, but for me it doesn't work on prototype boards. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- board/freescale/mpc8569mds/mpc8569mds.c | 85 +++++++++++++++++++++++++++++++ cpu/mpc85xx/speed.c | 2 + include/asm-ppc/global_data.h | 3 +- include/configs/MPC8569MDS.h | 16 ++++++ 4 files changed, 105 insertions(+), 1 deletions(-) diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 1e7526a..7c1aaa5 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <hwconfig.h> #include <pci.h> #include <asm/processor.h> #include <asm/mmu.h> @@ -35,6 +36,7 @@ #include <ioports.h> #include <libfdt.h> #include <fdt_support.h> +#include <fsl_esdhc.h> #include "bcsr.h" @@ -303,6 +305,87 @@ local_bus_init(void) out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); } +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bd) +{ + struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; + + if (!hwconfig("esdhc")) + return 0; + + printf("Enabling eSDHC...\n" + " For eSDHC to function, UART0 and I2C2 should be disabled.\n" + " Redirecting stderr, stdout and stdin to UART1...\n"); + console_assign(stderr, "eserial1"); + console_assign(stdout, "eserial1"); + console_assign(stdin, "eserial1"); + printf("Switched to UART1 (initial log has been printed to UART0).\n"); + + /* Assign I2C2 signals to eSDHC. */ + clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK, + PLPPAR1_ESDHC_VAL); + clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK, + PLPDIR1_ESDHC_VAL); + + /* Mux UART0 & I2C2 signals to eSDHC. */ + setbits_8(&bcsr[6], BCSR6_SD_ENABLE); + + return fsl_esdhc_mmc_init(bd); +} + +static void fdt_board_fixup_esdhc(void *blob, bd_t *bd) +{ + const char *status = "disabled"; + int off; + int err; + + /* + * In case of enabled eSDHC, we should disable UART0 and I2C2 + * in the device tree, otherwise nothing to do. + */ + if (!hwconfig("esdhc")) + return; + + off = fdt_path_offset(blob, "serial0"); + if (off < 0) { + printf("WARNING: could not find serial0 alias: %s.\n", + fdt_strerror(off)); + goto disable_i2c2; + } + + err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); + if (err) { + printf("WARNING: could not set status for serial0: %s.\n", + fdt_strerror(err)); + return; + } + +disable_i2c2: + off = -1; + while (1) { + const u32 *idx; + int len; + + off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c"); + if (off < 0) + break; + + idx = fdt_getprop(blob, off, "cell-index", &len); + if (!idx || len != sizeof(*idx)) + continue; + + if (*idx == 1) { + fdt_setprop(blob, off, "status", status, + strlen(status) + 1); + break; + } + } +} +#else +static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {} +#endif + #ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ @@ -449,5 +532,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif + fdt_fixup_esdhc(blob, bd); + fdt_board_fixup_esdhc(blob, bd); } #endif diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 286b6b2..73ecb76 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -155,6 +155,8 @@ int get_clocks (void) #if defined(CONFIG_MPC8536) gd->sdhc_clk = gd->bus_clk / 2; +#elif defined(CONFIG_MPC8569) + gd->sdhc_clk = gd->bus_clk; #endif #if defined(CONFIG_CPM2) diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 244c161..7cbcdb7 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -86,7 +86,8 @@ typedef struct global_data { u32 mem_sec_clk; #endif /* CONFIG_MPC8360 */ #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8536) +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536) || \ + defined(CONFIG_MPC8569) u32 sdhc_clk; #endif #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 32e747e..3d07a5b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -70,6 +70,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_HWCONFIG #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 @@ -206,6 +207,7 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 +#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -258,8 +260,10 @@ extern unsigned long get_clock_freq(void); #define PLPPAR1_I2C_BIT_MASK 0x0000000F #define PLPPAR1_I2C2_VAL 0x00000000 +#define PLPPAR1_ESDHC_VAL 0x0000000A #define PLPDIR1_I2C_BIT_MASK 0x0000000F #define PLPDIR1_I2C2_VAL 0x0000000F +#define PLPDIR1_ESDHC_VAL 0x00000006 /* * General PCI @@ -450,6 +454,18 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * Miscellaneous configurable options */ -- 1.6.3.3

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[U-Boot] [PATCH 4/7] mpc85xx: Setup SRIO memory region LAW for MPC8569E-MDS boards
by Anton Vorontsov 12 Oct '09

12 Oct '09

This patch sets memory window for Serial RapidIO on MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- board/freescale/mpc8569mds/law.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c index e7381aa..60eea45 100644 --- a/board/freescale/mpc8569mds/law.c +++ b/board/freescale/mpc8569mds/law.c @@ -54,6 +54,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); -- 1.6.3.3

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[U-Boot] [PATCH 3/7] mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards
by Anton Vorontsov 12 Oct '09

12 Oct '09

Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- board/freescale/mpc8569mds/tlb.c | 30 +++++++++++------------------- include/configs/MPC8569MDS.h | 23 +++++++++++++++++++++++ 2 files changed, 34 insertions(+), 19 deletions(-) diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c index d3b251e..3b8ee05 100644 --- a/board/freescale/mpc8569mds/tlb.c +++ b/board/freescale/mpc8569mds/tlb.c @@ -46,22 +46,24 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 Initializations */ /* - * TLBe 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH (upper half) + * TLBe 0: 64M Non-cacheable, guarded * Out of reset this entry is only 4K. + * 0xfc000000 256K NAND FLASH (CS3) + * 0xfe000000 32M NOR FLASH (CS0) */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), + 0, 0, BOOKE_PAGESZ_64M, 1), /* - * TLBe 1: 16M Non-cacheable, guarded - * 0xfe000000 16M FLASH (lower half) + * TLBe 1: 256KB Non-cacheable, guarded + * 0xf8000000 32K BCSR + * 0xf8008000 32K PIB (CS4) + * 0xf8010000 32K PIB (CS5) */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), + 0, 1, BOOKE_PAGESZ_256K, 1), /* * TLBe 2: 256M Non-cacheable, guarded @@ -88,16 +90,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), - - /* - * TLBe 5: 256K Non-cacheable, guarded - * 0xf8000000 32K BCSR - * 0xf8008000 32K PIB (CS4) - * 0xf8010000 32K PIB (CS5) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 3d07a5b..17ea3bb 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -181,6 +181,29 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO +/* Chip select 3 - NAND */ +#define CONFIG_SYS_NAND_BASE 0xFC000000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) +#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ /* * SDRAM on the LocalBus -- 1.6.3.3

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[U-Boot] u-boot-ti next updated
by Paulraj, Sandeep 12 Oct '09

12 Oct '09

All, I've updated the u-boot-ti next tree with quite a few patches. There are instances were multiple patches modify the same file. Can the OMAP 3 boards be tested to see if things are ok? It will be nice to have this info before I send Tom a pull request some time next week. This pull request will have some DaVinci fixes and updates which I can test by myself :-) Thanks, Sandeep

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[U-Boot] Zoom2 Fix serial setup
by Tom Rix 12 Oct '09

12 Oct '09

This patch is against u-boot-ti/master I run tested this on Zoom2. Tom

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Re: [U-Boot] [PATCH] * mpc8313erdb.dts: Fixed eTSEC interrupt assignment.
by Kim Phillips 12 Oct '09

12 Oct '09

On Wed, 9 Sep 2009 15:28:01 -0500 Kumar Gala <galak(a)kernel.crashing.org> wrote: > > On Sep 9, 2009, at 1:22 PM, Scott Wood wrote: > > > On Fri, Sep 04, 2009 at 12:31:25PM +0200, Roland Lezuo wrote: > >> The following patch is needed to correctly assign the IRQs for the > >> gianfar driver on the MPC8313ERDB-revc boards. ERR and TX are swapped > >> as well as the interrupt lines for the two devices. > > > > And it will incorrectly assign them on older revisions of the chip. > > > > We really should have a u-boot fixup based on SVR. Roland, is it possible for you to test this u-boot patch?: >From 44c73137acf20626e930e3f4142e60054d8bd46f Mon Sep 17 00:00:00 2001 From: Kim Phillips <kim.phillips(a)freescale.com> Date: Mon, 12 Oct 2009 10:51:20 -0500 Subject: [PATCH] mpc83xx: mpc8313 - handle erratum IPIC1 (TSEC IRQ number swappage) mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 h/w (see AN3545). The base device tree in use has rev. 1 ID numbers, so if on Rev. 2 (and higher) h/w, we fix them up here. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- cpu/mpc83xx/fdt.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 39 insertions(+), 0 deletions(-) diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index 13443cb..daf73a6 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -69,6 +69,45 @@ void ft_cpu_setup(void *blob, bd_t *bd) defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) fdt_fixup_ethernet(blob); +#ifdef CONFIG_MPC8313 + /* + * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 + * h/w (see AN3545). The base device tree in use has rev. 1 ID numbers, + * so if on Rev. 2 (and higher) h/w, we fix them up here + */ + if (REVID_MAJOR(immr->sysconf.spridr) >= 2) { + int nodeoffset, path; + const char *prop; + + nodeoffset = fdt_path_offset(blob, "/aliases"); + if (nodeoffset >= 0) { +#if defined(CONFIG_HAS_ETH0) + prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL); + if (prop) { + u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 }; + + path = fdt_path_offset(blob, prop); + prop = fdt_getprop(blob, path, "interrupts", 0); + if (prop) + fdt_setprop(blob, path, "interrupts", + &tmp, sizeof(tmp)); + } +#endif +#if defined(CONFIG_HAS_ETH1) + prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL); + if (prop) { + u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 }; + + path = fdt_path_offset(blob, prop); + prop = fdt_getprop(blob, path, "interrupts", 0); + if (prop) + fdt_setprop(blob, path, "interrupts", + &tmp, sizeof(tmp)); + } +#endif + } + } +#endif #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, -- 1.6.4.4

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[U-Boot] [PATCH V3 1/3] lib_generic memcpy: copy one word at a time if possible
by Alessandro Rubini 12 Oct '09

12 Oct '09

From: Alessandro Rubini <rubini(a)unipv.it> If source and destination are aligned, this copies ulong values until possible, trailing part is copied by byte. Thanks for the details to Wolfgang Denk, Mike Frysinger, Peter Tyser, Chris Moore. Signed-off-by: Alessandro Rubini <rubini(a)unipv.it> Acked-by: Andrea Gallo <andrea.gallo(a)stericsson.com> --- lib_generic/string.c | 19 +++++++++++++++---- 1 files changed, 15 insertions(+), 4 deletions(-) diff --git a/lib_generic/string.c b/lib_generic/string.c index 181eda6..9bee79b 100644 --- a/lib_generic/string.c +++ b/lib_generic/string.c @@ -446,12 +446,23 @@ char * bcopy(const char * src, char * dest, int count) * You should not use this function to access IO space, use memcpy_toio() * or memcpy_fromio() instead. */ -void * memcpy(void * dest,const void *src,size_t count) +void * memcpy(void *dest, const void *src, size_t count) { - char *tmp = (char *) dest, *s = (char *) src; - + unsigned long *dl = (unsigned long *)dest, *sl = (unsigned long *)src; + char *d8, *s8; + + /* while all data is aligned (common case), copy a word at a time */ + if ( (((ulong)dest | (ulong)src | count) & (sizeof(*dl) - 1)) == 0) { + while (count >= sizeof(*dl)) { + *dl++ = *sl++; + count -= sizeof(*dl); + } + } + /* copy the reset one byte at a time */ + d8 = (char *)dl; + s8 = (char *)sl; while (count--) - *tmp++ = *s++; + *d8++ = *s8++; return dest; } -- 1.5.6.5

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