October 2009 - U-Boot

[U-Boot] V2 of OMAP3 USB device Support
by Tom Rix 14 Oct '09

14 Oct '09

The technical change is better handling of address setting on the usb handshaking setup phase. Other changes from Jean's comments 2/8 USB add macros for debugging usb device setup. static inline function replacing debug macros 3/8 TWL4030 Add usb PHY support add empty lines between variables and statements other empty lines added for readablity 4/8 OMAP3 Add usb device support 80+ char lines reduced Used MUSB_FLAGS_PRINT macro suggestion lowercased function names multi-lined ep0_state_enum Used suggestion on udelay to 1000 * 1000 add empty lines between variables and statements inverted check of ep0_urb->device_request.wLength other empty lines added for readablity 5/8 OMAP3 zoom1 Add usbtty configuration This was ack-ed by Jean 6/8 OMAP3 beagle Add usbtty configuration This was ack-ed by Jean 8/8 OMAP3 zoom2 Use usbtty if the debug board cleanup using usbtty_* functions or their stubs without #define's

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[U-Boot] UBIFS LZO decompression failure
by Simon Kagstrom 14 Oct '09

14 Oct '09

Hi List! I have a slight problem with UBIFS on the OpenRD base board (an ARM board very similar to sheevaplug). Loading files which have been compressed with LZO by ubifs fails: OpenRD>> ubi part root; ubifsmount rootfs Creating 1 MTD partitions on "nand0": 0x0000001e0000-0x000020000000 : "mtd=1" UBI: attaching mtd1 to ubi0 UBI: physical eraseblock size: 131072 bytes (128 KiB) UBI: logical eraseblock size: 129024 bytes UBI: smallest flash I/O unit: 2048 UBI: sub-page size: 512 UBI: VID header offset: 512 (aligned 512) UBI: data offset: 2048 UBI: attached mtd1 to ubi0 UBI: MTD device name: "mtd=1" UBI: MTD device size: 510 MiB UBI: number of good PEBs: 4081 UBI: number of bad PEBs: 0 UBI: max. allowed volumes: 128 UBI: wear-leveling threshold: 4096 UBI: number of internal volumes: 1 UBI: number of user volumes: 1 UBI: available PEBs: 54 UBI: total number of reserved PEBs: 4027 UBI: number of PEBs reserved for bad PEB handling: 40 UBI: max/mean erase counter: 6/4 UBIFS: mounted UBI device 0, volume 0, name "rootfs" UBIFS: mounted read-only UBIFS: file system size: 511967232 bytes (499968 KiB, 488 MiB, 3968 LEBs) UBIFS: journal size: 25675776 bytes (25074 KiB, 24 MiB, 199 LEBs) UBIFS: media format: w4/r0 (latest is w4/r0) UBIFS: default compressor: LZO UBIFS: reserved for root: 5182151 bytes (5060 KiB) OpenRD>> ubifsload 0x8000000 /boot/primary/uImage Loading file '/boot/primary/uImage' to addr 0x08000000 with size 7196920 (0x006dd0f8)... UBIFS error (pid 0): ubifs_decompress: cannot decompress 3204 bytes, compressor LZO, error -6 UBIFS error (pid 0): read_block: bad data node (block 0, inode 88) UBIFS error (pid 0): do_readpage: cannot read page 0 of inode 88, error -22 Error reading file '/boot/primary/uImage' I've created the filesystem in Linux on the target (v2.6.31). The compression error -6 is LZO_E_LOOKBEHIND_OVERRUN, and it fails because of this test in lzo1x_decompress.c: if (HAVE_LB(m_pos, out, op)) goto lookbehind_overrun; where HAVE_LB is defined as (m_pos < out || m_pos >= op) and the m_pos, out and op values are 0x07ffde77, 0x08000000, 0x08000083 (i.e., the first test fails). The lzo1x_decompress.c file is identical to that in Linux, so something is fishy here. Does it work for the rest of you? In our case it doesn't matter very much since the file (an uImage) is compressed anyway and we therefore save work anyway by marking it as using no compression, but it would be nice if this would work anyhow. // Simon

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[U-Boot] Running u-boot without relocation to RAM?
by Kraitschy, Tobias 14 Oct '09

14 Oct '09

Hi, I´m working on running U-Boot from a Leon3-System on an evaluation board from Actel. Some GPIO and "Hello World" programs are already running. Now I created the necessary files for my board/sytem and compiling of U-Boot goes well, but starting this application nothing is happening on the serial terminal. After checking my U-Boot and system configuration again, I think that my very small RAM area of only 16 kB might be the problem while U-Boot relocates itself to RAM at startup. So is it possible to completly disable the relocation process at startup and run U-Boot with having opcode in PROM and data in RAM? If yes, how could I achieve this? I already tried to remove the corresponding code in the start.S and searched the README for switches, but without success. Best regards, Tobias Kraitschy

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[U-Boot] [PATCH] TI DaVinci: Fix DM6467 EVM Compilation Warning
by s-paulraj＠ti.com 14 Oct '09

14 Oct '09

From: Sandeep Paulraj <s-paulraj(a)ti.com> Due to new TI boards being added to U-Boot, the hardware.h is getting very messy. The warning being fixed is due to the EMIF addresses being redefined. The long term solution(after 2009.11) to this is to have SOC specific header files. Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- include/asm-arm/arch-davinci/hardware.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index ac32510..acf12ea 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -71,10 +71,12 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_SPI_BASE (0x01c66800) #define DAVINCI_GPIO_BASE (0x01c67000) #define DAVINCI_VPSS_REGS_BASE (0x01c70000) +#if !defined(CONFIG_SOC_DM646X) #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#endif #define DAVINCI_DDR_BASE (0x80000000) #ifdef CONFIG_SOC_DM644X -- 1.6.0.4

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[U-Boot] [PATCH] Blackfin: drop MAC display at boot
by Mike Frysinger 14 Oct '09

14 Oct '09

The default Blackfin boot would display the MAC address for the first NIC, but this relies on the environment. The current net multi stack no longer writes the default hardware settings to the environment, so most of the time the display shows all zeros. This can be pretty confusing and really doesn't add anything useful, so just drop it. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- lib_blackfin/board.c | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index bf943ea..6cade7d 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -278,7 +278,6 @@ static void board_net_init_r(bd_t *bd) bb_miiphy_init(); #endif #ifdef CONFIG_CMD_NET - uchar enetaddr[6]; char *s; if ((s = getenv("bootfile")) != NULL) @@ -288,9 +287,6 @@ static void board_net_init_r(bd_t *bd) printf("Net: "); eth_initialize(gd->bd); - - eth_getenv_enetaddr("ethaddr", enetaddr); - printf("MAC: %pM\n", enetaddr); #endif } -- 1.6.5

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[U-Boot] [PATCH] TI DaVinci: Adding Copyright for DM365 EVM
by s-paulraj＠ti.com 14 Oct '09

14 Oct '09

From: Sandeep Paulraj <s-paulraj(a)ti.com> Forgot to add Copyright while submitting the patch. This patch adds the copyright. Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- board/davinci/dm365evm/dm365evm.c | 1 + include/configs/davinci_dm365evm.h | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index 1e3a14f..290eb99 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -1,4 +1,5 @@ /* + * Copyright (C) 2009 Texas Instruments Incorporated * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index f715da3..53a105b 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -1,4 +1,5 @@ /* + * Copyright (C) 2009 Texas Instruments Incorporated * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as -- 1.6.0.4

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[U-Boot] Running concurrent applications
by Salvatore Campagna 14 Oct '09

14 Oct '09

I'd like to know whether it is possible to run two or more concurrent executables from the u-boot command prompt. There is no operating systems running on the machine and I just need to run two applications concurrently. Thanks a lot.

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[U-Boot] [RFC] [mpc8xxx_spi] enabling driver to support MPC8360e SPI in cpu-mode
by Richard Retanubun 14 Oct '09

14 Oct '09

Hi, I am working on getting u-boot (circa 2009.08) to program an SPI flash (STMicro M25P40) that contains the equations for our board's fpga. While looking at mpc8xxx_spi I realized it is coded for a non-QUICC-Engine based SPI flavor of 8xxx. I worked up this patch that compiles for mpc8360e. I'd like to share to get some sanity check if this is a good approach that have a hope of being mainlined. The idea is to use the MPC8360e SPI controller in cpu-mode, in which case SOME bits are different, but none are being used at the moment. Another approach I looked at is the /cpu/mpc8260/spi.c but I think this will eventually be superseded by mpc_8xxx.spi, no? Right now I'm stuck in the transfer timing out. With a slight head-scratching at this comment: /* * Wait for SPI transmit to get out * or time out (1 second = 1000 ms) * The NE event must be read and cleared first */ Yet in the loop I don't see any udelay(1000) to get us to 1second (based on SPI_TIMEOUT = 1000) am I missing something here? This is what I've done so far to compile with mpc8360 ----------------------------------------------------- diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index c4b36f0..ff4b44e 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -27,14 +27,27 @@ #include <spi.h> #include <asm/mpc8xxx_spi.h> +#if defined (CONFIG_MPC8360) +#include <asm/immap_qe.h> +#endif + +#if defined (CONFIG_MPC8360) +#define SPI_EV_NE (0x80 >> 6) /* Receiver Not Empty */ +#define SPI_EV_NF (0x80 >> 7) /* Transmitter Not Full */ +#else #define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */ #define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */ +#endif #define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */ #define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */ #define SPI_MODE_MS (0x80000000 >> 6) /* Always master */ #define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */ +#if defined (CONFIG_MPC8360) +#define SPI_MODE_OP (0x80000000 >> 17) /* CPU mode */ +#endif + #define SPI_TIMEOUT 1000 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, @@ -67,6 +80,22 @@ void spi_free_slave(struct spi_slave *slave) void spi_init(void) { +#if defined (CONFIG_MPC8360) + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile qe_map_t *qe = (volatile qe_map_t *)&im->qe; + volatile spi_t *spi = (volatile spi_t *)&qe->spi; + + /* + * SPI pins on the MPC83xx are not muxed, so all we do is initialize + * some registers (mode must be CPU mode to use this driver) + */ + spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN | SPI_MODE_OP; + spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use QE_CLK / 16 + (12.5 MHz typ.) */ + spi->event = 0xff; /* Clear all SPI events */ + spi->mask = 0x00; /* Mask all SPI interrupts */ + spi->com = 0; /* LST bit doesn't do anything, so disregard */ +#else volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi; /* @@ -79,6 +108,8 @@ void spi_init(void) spi->event = 0xffffffff; /* Clear all SPI events */ spi->mask = 0x00000000; /* Mask all SPI interrupts */ spi->com = 0; /* LST bit doesn't do anything, so disregard */ +#endif + } int spi_claim_bus(struct spi_slave *slave) @@ -94,19 +125,32 @@ void spi_release_bus(struct spi_slave *slave) int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { +#if defined (CONFIG_MPC8360) + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile qe_map_t *qe = (volatile qe_map_t *)&im->qe; + volatile spi_t *spi = (volatile spi_t *)&qe->spi; + unsigned short event; +#else volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi; - unsigned int tmpdout, tmpdin, event; + unsigned int event; +#endif + + unsigned int tmpdout, tmpdin; int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0); int tm, isRead = 0; unsigned char charSize = 32; - debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", + printf("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen); if (flags & SPI_XFER_BEGIN) spi_cs_activate(slave); +#if defined (CONFIG_MPC8360) + spi->event = 0xff; /* Clear all SPI events */ +#else spi->event = 0xffffffff; /* Clear all SPI events */ +#endif /* handle data in 32-bit chunks */ while (numBlks--) { @@ -139,7 +183,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } spi->tx = tmpdout; /* Write the data out */ - debug("*** spi_xfer: ... %08x written\n", tmpdout); + printf("*** spi_xfer: ... %08x written\n", tmpdout); /* * Wait for SPI transmit to get out diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index 531cfc8..4f11e04 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -159,18 +159,18 @@ typedef struct qe_brg { */ typedef struct spi { u8 res0[0x20]; - u32 spmode; /* SPI mode register */ + u32 mode; /* SPI mode register */ u8 res1[0x2]; - u8 spie; /* SPI event register */ + u8 event; /* SPI event register */ u8 res2[0x1]; u8 res3[0x2]; - u8 spim; /* SPI mask register */ + u8 mask; /* SPI mask register */ u8 res4[0x1]; u8 res5[0x1]; - u8 spcom; /* SPI command register */ + u8 com; /* SPI command register */ u8 res6[0x2]; - u32 spitd; /* SPI transmit data register (cpu mode) */ - u32 spird; /* SPI receive data register (cpu mode) */ + u32 tx; /* SPI transmit data register (cpu mode) */ + u32 rx; /* SPI receive data register (cpu mode) */ u8 res7[0x8]; } __attribute__ ((packed)) spi_t;

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[U-Boot] [PATCH] TI DaVinci: DM355 Leopard: Fix compilation warning
by s-paulraj＠ti.com 13 Oct '09

13 Oct '09

From: Sandeep Paulraj <s-paulraj(a)ti.com> We get a compliation warning when we enable the NAND driver for DM355 leopard. The waring we get is that we have an implicit declaration of davinci_nand_init. It is fixed by including the asm/arch/nand_defs.h header file Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- board/davinci/dm355leopard/dm355leopard.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c index 7350e8d..e89786e 100644 --- a/board/davinci/dm355leopard/dm355leopard.c +++ b/board/davinci/dm355leopard/dm355leopard.c @@ -21,6 +21,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/gpio_defs.h> +#include <asm/arch/nand_defs.h> #include "../common/misc.h" #include <net.h> #include <netdev.h> -- 1.6.0.4

2 1

[U-Boot] [PATCH v3 3/3] ppc/p1_p2_RDB: DDR Relocation support for NAND/SD/eSPI Boot
by Dipen Dudhat 13 Oct '09

13 Oct '09

DDR support to boot from NAND/eSDHC/eSPI on P1 & P2 RDB platforms. Specifically this support needed when L2 Cache size is less than 512K. Signed-off-by: Dipen Dudhat <dipen.dudhat(a)freescale.com> --- - Applies to http://git.denx.de/u-boot.git - Changes from v2: integrated kumar's comments. board/freescale/p1_p2_rdb/config.mk | 8 +++ board/freescale/p1_p2_rdb/ddr.c | 3 + board/freescale/p1_p2_rdb/tlb.c | 9 +++- include/configs/P1_P2_RDB.h | 31 ++++++++++++ nand_spl/board/freescale/p1_p2_rdb/nand_boot.c | 59 ++++++++++++++++++++++++ 5 files changed, 109 insertions(+), 1 deletions(-) diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk index 0f7a048..e782928 100644 --- a/board/freescale/p1_p2_rdb/config.mk +++ b/board/freescale/p1_p2_rdb/config.mk @@ -33,13 +33,21 @@ endif ifeq ($(CONFIG_MK_SDCARD), y) TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +ifdef CONFIG_SYS_FSL_BOOT_DDR +RESET_VECTOR_ADDRESS = 0x1107fffc +else RESET_VECTOR_ADDRESS = 0xf8fffffc endif +endif ifeq ($(CONFIG_MK_SPIFLASH), y) TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +ifdef CONFIG_SYS_FSL_BOOT_DDR +RESET_VECTOR_ADDRESS = 0x1107fffc +else RESET_VECTOR_ADDRESS = 0xf8fffffc endif +endif ifndef TEXT_BASE TEXT_BASE = 0xeff80000 diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 37c4b0a..dc967de 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -246,6 +246,9 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_FSL_BOOT_DDR) + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +#endif dram_size = fixed_sdram(); set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1); diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 0009913..c250e3e 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -78,7 +78,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_INIT_L2_ADDR) /* *I*G - L2SRAM */ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -87,6 +88,12 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_256K, 1), +#else + /* *I*G - DDR */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1G, 1) +#endif #endif }; diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 310242e..dae2e8d 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -43,21 +43,40 @@ #define CONFIG_P2020 #endif +/* Boot using DDR for eSDHC/eSPI/NAND boot because L2 Cache size + * on these platforms is 256K. + */ +#if defined(CONFIG_P1011) || defined(CONFIG_P1020) +#define CONFIG_SYS_FSL_BOOT_DDR +#endif + #ifdef CONFIG_MK_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND 1 +#ifdef CONFIG_SYS_FSL_BOOT_DDR +#define CONFIG_RAMBOOT_TEXT_BASE 0x01001000 +#else #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 #endif +#endif #ifdef CONFIG_MK_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 +#ifdef CONFIG_SYS_FSL_BOOT_DDR +#define CONFIG_RAMBOOT_TEXT_BASE 0x11000000 +#else #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 #endif +#endif #ifdef CONFIG_MK_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 +#ifdef CONFIG_SYS_FSL_BOOT_DDR +#define CONFIG_RAMBOOT_TEXT_BASE 0x11000000 +#else #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 #endif +#endif /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ @@ -101,6 +120,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * Config the L2 Cache as L2 SRAM */ +#ifndef CONFIG_SYS_FSL_BOOT_DDR #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull @@ -109,6 +129,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#endif /* * Base addresses -- Note these are effective addresses where the @@ -233,6 +254,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) /* NAND boot: 4K NAND loader config */ +#ifdef CONFIG_SYS_FSL_BOOT_DDR +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x01000000 - CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x01000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) +#else #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) @@ -240,6 +270,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ diff --git a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c index bd513b8..2512f15 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c @@ -39,6 +39,60 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_SYS_FSL_BOOT_DDR) +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/ +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 + +#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000 +#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802 +#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543 +#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1 +#define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_667 0x00040852 +#define CONFIG_SYS_DDR_MODE_2_667 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 + +#define udelay(x) {int i, j; for (i = 0; i < x; i++) for (j = 0; j < 10000; j++); } + +void initsdram(void) +{ + + volatile ccsr_ddr_t *ddr= (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + int d_init, dbw; + volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + unsigned int ddr_size; + sys_info_t sysinfo; + phys_size_t dram_size = 0; + + set_next_law(0,LAW_SIZE_1G , LAW_TRGT_IF_DDR_1); + + out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&ddr->cs0_config_2, CONFIG_SYS_DDR_CS0_CONFIG_2); + + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667); + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667); + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667); + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667); + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667); + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); + + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg |= 0x80000000; + +} +#endif + void board_init_f(ulong bootflag) { uint plat_ratio, bus_clk, sys_clk; @@ -69,6 +123,11 @@ void board_init_f(ulong bootflag) puts("\nNAND boot... "); +#ifdef CONFIG_SYS_FSL_BOOT_DDR + /* board specific DDR initialization */ + initsdram(); +#endif + /* copy code to DDR and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. -- 1.5.6.3

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