January 2009 - U-Boot

[U-Boot] [ANNOUNCE] DATAFLASH DRIVER
by Jean-Christophe PLAGNIOL-VILLARD 08 Jan '09

08 Jan '09

Hi, The AT91 arch use a at45 driver design to be show as a parallel flash but it's a spi flash. Haavard add a new spi flash framework which support the dataflash so the current driver is mark as *depracated* and plan to be remove New board and cpu must use the new framework Only justify exception will be ack The actual only exception will the at91rm9200ek and bug fix Best Regards, J.

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[U-Boot] MPC8548 not able to detect Marvell 88E1145 PHY
by Ajeesh Kumar 08 Jan '09

08 Jan '09

Hi Sir/Madam, We were working on EP8548A board (MPC8548E silicon revision 2.0) which had a u-boot 1.2.0. Also, MPC8548 eTSECn was connected to a Marvell PHY(D0 version) chip 88E1145(4 ports) and 2 ethernet ports are working fine. Now we have a custom board which is similar to EP8548A. But with MPC8548E silicon revision 2.1 and Marvell PHY with E0 version. The eTSECn is conntected to Marvell PHY(4 ports) chip. I'm able to boot our custom board using the same u-boot 1.2.0 which was used for EP8548 board. But I'm not able to detect and configure my PHY chip. I have a board configuration file with TSEC related macros as below #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" #define CONFIG_MPC85XX_TSEC2 1 #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" #define CONFIG_MPC85XX_TSEC4 1 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 #define TSEC4_PHY_ADDR 3 #define TSEC1_FLAGS TSEC_GIGABIT | TSEC_REDUCED #define TSEC2_FLAGS TSEC_GIGABIT | TSEC_REDUCED #define TSEC3_FLAGS TSEC_GIGABIT | TSEC_REDUCED #define TSEC4_FLAGS TSEC_GIGABIT | TSEC_REDUCED #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" When the U-boot comes up i get the below display: U-Boot 1.2.0 (Jan 5 2009 - 10:18:30) CPU: 8548_E, Version: 2.1, (0x80390021) Core: E500, Version: 2.2, (0x80210022) Clock Configuration: CPU: 666 MHz, CCB: 266 MHz, DDR: 133 MHz, LBC: 33 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Board: .......... I2C: ready DRAM: Initializing DDR: 512 MB SRIO: disabled FLASH: 128 MB L2 cache 512KB: enabled *** Warning - bad CRC, using default environment PCIe: disabled In: serial Out: serial Err: serial Net: eTSEC0: PHY id ffffffff is not supported! eTSEC0: No PHY found eTSEC1: PHY id ffffffff is not supported! eTSEC1: No PHY found eTSEC2: PHY id ffffffff is not supported! eTSEC2: No PHY found eTSEC3: PHY id ffffffff is not supported! eTSEC3: No PHY found eTSEC0, eTSEC1, eTSEC2, eTSEC3 Hit any key to stop autoboot: 0 ## Booting image at fc000000 ... Bad Magic Number <board>=> Later we scanned through all the PHY address(0 to 31) and only ONE port's PHY address(0x12) was successfully read. Our queries are as follows 1. Why were we not able to detect and configure the PHY in the first attempt??? 2. Why other PHY address are not set. We checked the Hardware its correct. >From MARVEL the PHY address is 0,1,2,3 - but MPC is reading PHY address as 0x12 but not others. 2. We connected LAN cable to the PORT 0x12, still its not getting pinged. We have connected in RGMII mode (TSEC0) During POR the POR register are getting configured for default (GMII) mode, how can we change the PORT to RGMII, after Boot. 1. in Marvel - MDIO is selected in Configuration, and also in Four Independented Serial Management Mode. Please help me in this regard. Thanks, Ajeesh Kumar The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments contained in it.

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[U-Boot] Help!I cannot open the virtual com port
by kennywin 08 Jan '09

08 Jan '09

I am making usb driver for omap1510 on uboot. When I pluged in the USB port to PC. It found COM6 (a virtual com port). But When I open the COM6 on hyper-terminal, it says "Cannot open" The following traces are from the Bus Hound Device Phase Data Description Cmd.Phase.Ofs(rep) ------ ----- -------------------------------------------------- ---------------- ------------------ 26.0 CTL a1 21 00 00 00 00 07 00 GET LINE CODING 1.1.0(4) 26.0 DI 00 c2 01 00 00 00 08 ....... 1.2.0 26.0 URB 50 00 08 00 00 00 00 00 40 3a 3a 85 22 00 00 00 CONTROL TRANSFER 1.3.0 58 3a 3a 85 0b 00 00 00 07 00 00 00 f0 ab f5 b9 1.3.16 26.0 CTL 21 20 00 00 00 00 07 00 SET LINE CODING 5.1.0 26.0 DO 00 c2 01 00 00 00 08 ....... 5.2.0 26.0 USTS 04 00 00 c0 stall pid 5.3.0 26.0 URB 50 00 08 00 04 00 00 c0 40 3a 3a 85 22 00 00 00 CONTROL TRANSFER 5.4.0 58 3a 3a 85 0a 00 00 00 07 00 00 00 ec ab f5 b9 5.4.16 26.0 CTL a1 21 00 00 00 00 07 00 GET LINE CODING 6.1.0 26.0 DI 00 c2 01 00 00 00 08 ....... 6.2.0 26.0 URB 50 00 08 00 00 00 00 00 40 3a 3a 85 22 00 00 00 CONTROL TRANSFER 6.3.0 58 3a 3a 85 0b 00 00 00 07 00 00 00 c8 ab f5 b9 6.3.16 26.0 CTL a1 21 00 00 00 00 07 00 GET LINE CODING 7.1.0(2) 26.0 DI 00 c2 01 00 00 00 08 ....... 7.2.0 26.0 URB 50 00 08 00 00 00 00 00 40 3a 3a 85 22 00 00 00 CONTROL TRANSFER 7.3.0 58 3a 3a 85 0b 00 00 00 07 00 00 00 f0 ab f5 b9 7.3.16 26.0 CTL 21 20 00 00 00 00 07 00 SET LINE CODING 9.1.0 26.0 DO b0 04 00 00 00 00 08 ....... 9.2.0 26.0 USTS 04 00 00 c0 stall pid 9.3.0 26.0 URB 50 00 08 00 04 00 00 c0 40 3a 3a 85 22 00 00 00 CONTROL TRANSFER 9.4.0 58 3a 3a 85 0a 00 00 00 07 00 00 00 ec ab f5 b9 9.4.16 26.0 CTL a1 21 00 00 00 00 07 00 GET LINE CODING 10.1.0 26.0 DI 00 c2 01 00 00 00 08 ....... 10.2.0 26.0 URB 50 00 08 00 00 00 00 00 40 3a 3a 85 22 00 00 00 CONTROL TRANSFER 10.3.0 58 3a 3a 85 0b 00 00 00 07 00 00 00 c8 ab f5 b9 10.3.16 26.0 CTL 21 22 00 00 00 00 00 00 SET CTRL LINE ST 11.1.0 26.0 URB 50 00 08 00 00 00 00 00 40 3a 3a 85 20 00 00 00 CONTROL TRANSFER 11.2.0 58 3a 3a 85 0a 00 00 00 00 00 00 00 00 00 00 00 11.2.16 How can I solve this problem? -- View this message in context: http://www.nabble.com/Help%21I-cannot-open-the-virtual-com-port-tp21348997p… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] u-boot for marvell littleton debug board (PXA310)?
by Ricky Xian 08 Jan '09

08 Jan '09

Dear All, Are there anyone or projects for u-boot on marvell littleton debug board? it's based PXA310, the same as zylonite. Thanks! Ricky

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[U-Boot] ads5121 cygwin build
by Jeff Smith 08 Jan '09

08 Jan '09

I have built u-boot-2008.10 for the ads5121 (from the latest LTIB sources) under WindowsXP in cygwin. If anyone is interested I have a set of patches and some instructions.

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[U-Boot] [RFC/PATCH 4/4] Add multi-chip NAND support for the TQM8548 modules
by Wolfgang Grandegger 07 Jan '09

07 Jan '09

This patches configures the NAND UPM-FSL driver with multi-chip support for the Micro MT29F8G08FAB on the TQM8548 modules. Signed-off-by: Wolfgang Grandegger <wg(a)grandegger.com> --- board/tqc/tqm85xx/nand.c | 2 ++ include/configs/TQM85xx.h | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) Index: u-boot/board/tqc/tqm85xx/nand.c =================================================================== --- u-boot.orig/board/tqc/tqm85xx/nand.c +++ u-boot/board/tqc/tqm85xx/nand.c @@ -446,6 +446,8 @@ static struct fsl_upm_nand fun = { .width = 8, .upm_cmd_offset = 0x08, .upm_addr_offset = 0x10, + .upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST, + .chip_offset = CONFIG_SYS_NAND_CS_DIST, .chip_delay = NAND_BIG_DELAY_US, }; Index: u-boot/include/configs/TQM85xx.h =================================================================== --- u-boot.orig/include/configs/TQM85xx.h +++ u-boot/include/configs/TQM85xx.h @@ -362,8 +362,8 @@ #define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST) #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 2 #if (CONFIG_SYS_MAX_NAND_DEVICE == 1) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }

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[U-Boot] [RFC/PATCH 3/4] Add support for TQM-specific chip select logic to UPM-FSL
by Wolfgang Grandegger 07 Jan '09

07 Jan '09

For the NAND chips on the TQM8548 modules, a special chip-select logic is used. It uses dedicated address lines to be controlled via UPM machine address register (mar). This patch adds corresponding support to the FSL-UPM driver. Signed-off-by: Wolfgang Grandegger <wg(a)grandegger.com> --- drivers/mtd/nand/fsl_upm.c | 5 ++++- include/linux/mtd/fsl_upm.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) Index: u-boot/drivers/mtd/nand/fsl_upm.c =================================================================== --- u-boot.orig/drivers/mtd/nand/fsl_upm.c +++ u-boot/drivers/mtd/nand/fsl_upm.c @@ -90,8 +90,11 @@ static void fun_cmd_ctrl(struct mtd_info mar = cmd << (32 - fun->width); io_addr = fun->upm.io_addr; #if NAND_MAX_CHIPS > 1 - if (fun->chip_nr > 0) + if (fun->chip_nr > 0) { io_addr += fun->chip_offset * fun->chip_nr; + if (fun->upm_mar_chip_offset) + mar |= fun->upm_mar_chip_offset * fun->chip_nr; + } #endif fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar); Index: u-boot/include/linux/mtd/fsl_upm.h =================================================================== --- u-boot.orig/include/linux/mtd/fsl_upm.h +++ u-boot/include/linux/mtd/fsl_upm.h @@ -28,6 +28,7 @@ struct fsl_upm_nand { int width; int upm_cmd_offset; int upm_addr_offset; + int upm_mar_chip_offset; int wait_pattern; int (*dev_ready)(int chip_nr); int chip_delay;

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[U-Boot] [RFC/PATCH 2/4] Add multi chip support to the UPM-FSL driver
by Wolfgang Grandegger 07 Jan '09

07 Jan '09

This patch adds support for multi-chip NAND devices to the FSL-UPM driver. The "dev_ready" callback of the "struct fsl_upm_nand" is now called with the argument "chip_nr" to allow testing the proper chip select line. This requires various BSPs to be updated appropriately and I will provide proper patches in the next version of this patch (it's still an RFC). Signed-off-by: Wolfgang Grandegger <wg(a)grandegger.com> --- drivers/mtd/nand/fsl_upm.c | 44 ++++++++++++++++++++++++++++++++++++-------- include/linux/mtd/fsl_upm.h | 4 +++- 2 files changed, 39 insertions(+), 9 deletions(-) Index: u-boot/drivers/mtd/nand/fsl_upm.c =================================================================== --- u-boot.orig/drivers/mtd/nand/fsl_upm.c +++ u-boot/drivers/mtd/nand/fsl_upm.c @@ -31,26 +31,45 @@ static void fsl_upm_end_pattern(struct f eieio(); } -static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd) +static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, + void __iomem *io_addr, u32 mar) { - out_be32(upm->mar, cmd << (32 - width)); + out_be32(upm->mar, mar); switch (width) { case 8: - out_8(upm->io_addr, 0x0); + out_8(io_addr, 0x0); break; case 16: - out_be16(upm->io_addr, 0x0); + out_be16(io_addr, 0x0); break; case 32: - out_be32(upm->io_addr, 0x0); + out_be32(io_addr, 0x0); break; } } +#if NAND_MAX_CHIPS > 1 +static void fun_select_chip(struct mtd_info *mtd, int chip_nr) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_upm_nand *fun = chip->priv; + + if (chip_nr >= 0) { + fun->chip_nr = chip_nr; + chip->IO_ADDR_R = chip->IO_ADDR_W = + fun->upm.io_addr + fun->chip_offset * chip_nr; + } else if (chip_nr == -1) { + chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); + } +} +#endif + static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; struct fsl_upm_nand *fun = chip->priv; + void __iomem *io_addr; + u32 mar; if (!(ctrl & fun->last_ctrl)) { fsl_upm_end_pattern(&fun->upm); @@ -68,7 +87,13 @@ static void fun_cmd_ctrl(struct mtd_info fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); } - fsl_upm_run_pattern(&fun->upm, fun->width, cmd); + mar = cmd << (32 - fun->width); + io_addr = fun->upm.io_addr; +#if NAND_MAX_CHIPS > 1 + if (fun->chip_nr > 0) + io_addr += fun->chip_offset * fun->chip_nr; +#endif + fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar); /* * Some boards/chips needs this. At least on MPC8360E-RDK we @@ -77,7 +102,7 @@ static void fun_cmd_ctrl(struct mtd_info * 0-2 unexpected busy states per block read. */ if (fun->wait_pattern) { - while (!fun->dev_ready()) + while (!fun->dev_ready(fun->chip_nr)) debug("unexpected busy state\n"); } } @@ -125,7 +150,7 @@ static int nand_dev_ready(struct mtd_inf struct nand_chip *chip = mtd->priv; struct fsl_upm_nand *fun = chip->priv; - return fun->dev_ready(); + return fun->dev_ready(fun->chip_nr); } int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) @@ -139,6 +164,9 @@ int fsl_upm_nand_init(struct nand_chip * chip->chip_delay = fun->chip_delay; chip->ecc.mode = NAND_ECC_SOFT; chip->cmd_ctrl = fun_cmd_ctrl; +#if NAND_MAX_CHIPS > 1 + chip->select_chip = fun_select_chip; +#endif chip->read_byte = nand_read_byte; chip->read_buf = nand_read_buf; chip->write_buf = nand_write_buf; Index: u-boot/include/linux/mtd/fsl_upm.h =================================================================== --- u-boot.orig/include/linux/mtd/fsl_upm.h +++ u-boot/include/linux/mtd/fsl_upm.h @@ -29,8 +29,10 @@ struct fsl_upm_nand { int upm_cmd_offset; int upm_addr_offset; int wait_pattern; - int (*dev_ready)(void); + int (*dev_ready)(int chip_nr); int chip_delay; + int chip_offset; + int chip_nr; /* no need to fill */ int last_ctrl;

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[U-Boot] [RFC/PATCH 0/4] Add multi-chips support for NAND, FSL-UPM and TQM8548
by Wolfgang Grandegger 07 Jan '09

07 Jan '09

The following patch series intends to support the Micron multi-chip NAND device MT29F8G08FAB on the TQM8548 modules from TQ-Components. It makes sense to offer such a multi-chip device as one single device to the user. Multi-chip devices seem already be supported by the NAND layer, but U-Boot does not use it yet: [RFC/PATCH 1/4] Enable multi-chip support in the NAND layer [RFC/PATCH 2/4] Add multi-chip support to the UPM-FSL driver [RFC/PATCH 3/4] Add support for TQM-specific chip select logic to UPM-FSL [RFC/PATCH 4/4] Add multi-chip support for the TQM8548 modules Please comment. Thanks. Wolfgang.

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[U-Boot] RV: Question about U-Boot for MPC5121
by Marco Donadio 07 Jan '09

07 Jan '09

Good morning, our team is working on a new telematic platform using MPC5121 device. Our Boar has some features of ADS512101 evaluacion board. We are not familiar with boot loader system because it's the first time that we develop a board based on operating system. We need some basic help to put boot loader in our architecture; we start with files in the directory "u-boot-2008.10": - please can you tell us wich files we need to change (in order to adapt them to our architecture)?? - Whic files we need to compile in order to have a u-boot image??? We read all the documentation on the DENX website but without success... Thanks a lot for your help Best regards Marco Donadio GMV-FICOSA mdonadio(a)gmv.com <mailto:vijimenez@gmv.com> _____________________________ MASISCONVI, S.A. C/ Mas Dorca, 13, nave 5 Polígono Industrial L'Ametlla Park 08480 L'Ametlla del Vallès (Barcelona) Tel.: +34 93 845 79 00 - +34 93 845 79 10 Fax.: +34 93 845 79 05 P Save a tree...please don't print this e-mail unless you really need to ______________________ Este mensaje, y en su caso, cualquier fichero anexo al mismo, puede contener informacion clasificada por su emisor como confidencial en el marco de su Sistema de Gestion de Seguridad de la Informacion siendo para uso exclusivo del destinatario, quedando prohibida su divulgacion copia o distribucion a terceros sin la autorizacion expresa del remitente. Si Vd. ha recibido este mensaje erroneamente, se ruega lo notifique al remitente y proceda a su borrado. Gracias por su colaboracion. ______________________ This message including any attachments may contain confidential information, according to our Information Security Management System, and intended solely for a specific individual to whom they are addressed. Any unauthorised copy, disclosure or distribution of this message is strictly forbidden. If you have received this transmission in error, please notify the sender immediately and delete it. ______________________

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