January 2009 - U-Boot

[U-Boot] [PATCH 2/5] ARM: Add/Improve support for Atmel AT91RM9200DK/E
by Ulf Samuelsson 10 Jan '09

10 Jan '09

This patchset updates the at91rm9200dk board support to look similar to the rest of the at91 boards, using more modern access functions for I/O instead of direct pointer accesses. A derivative of the board is added, ---- at91rm9200dk_df - at91rm9200dk with environment in dataflash Support for the AT91RM9200EK is added ---- at91rm9200ek - at91rm9200ek with environment in nor flash Support for a generic AT91RM9200 board with dataflash is added ---- at91rm9200df - at91rm9200 with environment in dataflash and no norflash drivers. ------------------------------------------------------------------------------- Patch [1/5] Updates to include/asm-arm/arch.at91rm9200 Patch [2/5] Updates to Makefile and include/configs for at91rm9200dk/dk_df Patch [3/5] Updates to board/atmel/at91rm9200dk Patch [4/5] Updates to Makefile and include/configs for at91rm9200df/ek Patch [5/5] Updates to MAKEALL [2/5] AFFECTS include/configs/at91rm9200dk_df.h include/configs/at91rm9200dk.h Makefile Signed-off-by: Ulf Samuelsson <ulf.samuelsson(a)atmel.com> --- diff -urN u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk_df.h u-boot-2009.01/include/configs/at91rm9200dk_df.h --- u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk_df.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2009.01/include/configs/at91rm9200dk_df.h 2009-01-01 21:19:30.000000000 +0100 @@ -0,0 +1,251 @@ +/* + * Rick Bronson <rick(a)efn.org> + * + * Configuration settings for the AT91RM9200DK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#define AT91RM9200_BOARD MACH_TYPE_AT91RM9200DK +#define CONFIG_HOSTNAME at91rm9200dk + +/* ARM asynchronous clock */ +#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ +#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ +/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91 1 /* THis is an ARM from the AT91 family */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define USE_920T_MMU 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT /* Already done by dataflashboot */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ + +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000080 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#else +#define CONFIG_SKIP_RELOCATE_UBOOT +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 115200 + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_DBGU +#undef CONFIG_USART0 +#undef CONFIG_USART1 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_BOOTDELAY 3 +/* #define CONFIG_ENV_OVERWRITE 1 */ + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_AT91_SPIMUX + +#define CONFIG_NAND_LEGACY + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ +#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ + +#include <asm/arch/AT91RM9200.h> /* needed for port definitions */ +#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) +#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) + +#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 + +#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_AT91C_USE_RMII + +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 +#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ +#define CONFIG__SUPPORT_BLOCK_ERASE 1 + + +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_NEW_PARTITION 1 + +#ifdef CONFIG_ENV_IS_IN_DATAFLASH +#ifdef CONFIG_NEW_PARTITION +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 /* 8 * 1056 really , but start.s is not OK with this*/ +#else +#define CONFIG_ENV_OFFSET 0x20000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ +#endif +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ +#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ +#else +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ +#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_ENV_IS_IN_DATAFLASH */ + +#if defined(CONFIG_AT91RM9200DK) +#define DATAFLASH_MMC_SELECT AT91_PIN_PB7 +#else +#define DATAFLASH_MMC_SELECT AT91_PIN_PB22 +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */ +#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) +#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */ +#else +#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ +#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1 +#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff -urN u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk.h u-boot-2009.01/include/configs/at91rm9200dk.h --- u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk.h 2009-01-01 13:09:35.000000000 +0100 +++ u-boot-2009.01/include/configs/at91rm9200dk.h 2009-01-01 17:06:32.000000000 +0100 @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define AT91RM9200_BOARD MACH_TYPE_AT91RM9200DK +#define CONFIG_HOSTNAME at91rm9200dk /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ @@ -33,6 +35,7 @@ #define AT91_SLOW_CLOCK 32768 /* slow clock */ #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91 1 /* THis is an ARM from the AT91 family */ #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -117,6 +120,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII #define CONFIG_CMD_NAND +#define CONFIG_CMD_AT91_SPIMUX #define CONFIG_NAND_LEGACY @@ -198,6 +202,11 @@ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ #endif /* CONFIG_ENV_IS_IN_DATAFLASH */ +#if defined(CONFIG_AT91RM9200DK) +#define DATAFLASH_MMC_SELECT AT91_PIN_PB7 +#else +#define DATAFLASH_MMC_SELECT AT91_PIN_PB22 +#endif #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ diff -urN u-boot-2009.01-rc1-0rig//Makefile u-boot-2009.01/Makefile --- u-boot-2009.01-rc1-0rig//Makefile 2009-01-01 13:09:30.000000000 +0100 +++ u-boot-2009.01/Makefile 2009-01-01 21:35:24.000000000 +0100 @@ -2562,6 +2562,9 @@ ## Atmel AT91RM9200 Systems ######################################################################### +at91rm9200dk_df_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200 + at91rm9200dk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200 Best Regards Ulf Samuelsson

4 11

[U-Boot] [PATCH 1/5] ARM: Add/Improve support for Atmel AT91RM9200DK/EK
by Ulf Samuelsson 10 Jan '09

10 Jan '09

[PATCH 1/5] ARM: Add/Improve support for Atmel AT91RM9200DK/EK This patchset updates the at91rm9200dk board support to look similar to the rest of the at91 boards, using more modern access functions for I/O instead of direct pointer accesses. A derivative of the board is added, ---- at91rm9200dk_df - at91rm9200dk with environment in dataflash Support for the AT91RM9200EK is added ---- at91rm9200ek - at91rm9200ek with environment in nor flash Support for a generic AT91RM9200 board with dataflash ---- at91rm9200df - at91rm9200 with environment in dataflash and no norflash drivers. ------------------------------------------------------------------------------- Patch [1/5] Updates to include/asm-arm/arch.at91rm9200 Patch [2/5] Updates to Makefile and include/configs for at91rm9200dk/dk_df Patch [3/5] Updates to board/atmel/at91rm9200dk Patch [4/5] Updates to Makefile and include/configs Patch [5/5] Updates to MAKEALL [1/5] AFFECTS include/asm-arm/arch-at91rm9200/at91_pio.h include/asm-arm/arch-at91rm9200/at91_pmc.h include/asm-arm/arch-at91rm9200/AT91RM9200.h include/asm-arm/arch-at91rm9200/gpio.h include/asm-arm/arch-at91rm9200/io.h Signed-off-by: Ulf Samuelsson <ulf.samuelsson(a)atmel.com> --- diff -urN u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/at91_pio.h u-boot-2009.01/include/asm-arm/arch-at91rm9200/at91_pio.h --- u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/at91_pio.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2009.01/include/asm-arm/arch-at91rm9200/at91_pio.h 2009-01-01 14:02:28.000000000 +0100 @@ -0,0 +1,49 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Parallel I/O Controller (PIO) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_PIO_H +#define AT91_PIO_H + +#define PIO_PER 0x00 /* Enable Register */ +#define PIO_PDR 0x04 /* Disable Register */ +#define PIO_PSR 0x08 /* Status Register */ +#define PIO_OER 0x10 /* Output Enable Register */ +#define PIO_ODR 0x14 /* Output Disable Register */ +#define PIO_OSR 0x18 /* Output Status Register */ +#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ +#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ +#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ +#define PIO_SODR 0x30 /* Set Output Data Register */ +#define PIO_CODR 0x34 /* Clear Output Data Register */ +#define PIO_ODSR 0x38 /* Output Data Status Register */ +#define PIO_PDSR 0x3c /* Pin Data Status Register */ +#define PIO_IER 0x40 /* Interrupt Enable Register */ +#define PIO_IDR 0x44 /* Interrupt Disable Register */ +#define PIO_IMR 0x48 /* Interrupt Mask Register */ +#define PIO_ISR 0x4c /* Interrupt Status Register */ +#define PIO_MDER 0x50 /* Multi-driver Enable Register */ +#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ +#define PIO_MDSR 0x58 /* Multi-driver Status Register */ +#define PIO_PUDR 0x60 /* Pull-up Disable Register */ +#define PIO_PUER 0x64 /* Pull-up Enable Register */ +#define PIO_PUSR 0x68 /* Pull-up Status Register */ +#define PIO_ASR 0x70 /* Peripheral A Select Register */ +#define PIO_BSR 0x74 /* Peripheral B Select Register */ +#define PIO_ABSR 0x78 /* AB Status Register */ +#define PIO_OWER 0xa0 /* Output Write Enable Register */ +#define PIO_OWDR 0xa4 /* Output Write Disable Register */ +#define PIO_OWSR 0xa8 /* Output Write Status Register */ + +#endif diff -urN u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/at91_pmc.h u-boot-2009.01/include/asm-arm/arch-at91rm9200/at91_pmc.h --- u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/at91_pmc.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2009.01/include/asm-arm/arch-at91rm9200/at91_pmc.h 2009-01-01 15:51:28.000000000 +0100 @@ -0,0 +1,116 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91_pmc.h] + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Copyright (C) 2008 Ulf Samuelsson + * + * Power Management Controller (PMC) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_PMC_H +#define AT91_PMC_H + +#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ +#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ + +#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ +#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ +#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ +#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ +#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ +#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ +#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ +#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ +#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ +#define AT91_PMC_RES_0C (AT91_PMC + 0x0c) /* Reserved */ + +#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ +#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ +#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ +#define AT91_PMC_RES_1C (AT91_PMC + 0x1c) /* Reserved */ + + +#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ +#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ +#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ + +#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ +#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ +#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ + +#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ +#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ +#define AT91_PMC_DIV (0xff << 0) /* Divider */ +#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ +#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ +#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ +#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ +#define AT91_PMC_USBDIV_1 (0 << 28) +#define AT91_PMC_USBDIV_2 (1 << 28) +#define AT91_PMC_USBDIV_4 (2 << 28) +#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ + +#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ +#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ +#define AT91_PMC_CSS_SLOW (0 << 0) +#define AT91_PMC_CSS_MAIN (1 << 0) +#define AT91_PMC_CSS_PLLA (2 << 0) +#define AT91_PMC_CSS_PLLB (3 << 0) +#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ +#define AT91_PMC_PRES_1 (0 << 2) +#define AT91_PMC_PRES_2 (1 << 2) +#define AT91_PMC_PRES_4 (2 << 2) +#define AT91_PMC_PRES_8 (3 << 2) +#define AT91_PMC_PRES_16 (4 << 2) +#define AT91_PMC_PRES_32 (5 << 2) +#define AT91_PMC_PRES_64 (6 << 2) +#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ +#define AT91_PMC_MDIV_1 (0 << 8) +#define AT91_PMC_MDIV_2 (1 << 8) +#define AT91_PMC_MDIV_3 (2 << 8) +#define AT91_PMC_MDIV_4 (3 << 8) + +#define AT91_PMC_RES_34 (AT91_PMC + 0x34) /* Reserved */ +#define AT91_PMC_RES_38 (AT91_PMC + 0x38) /* Reserved */ +#define AT91_PMC_RES_3C (AT91_PMC + 0x3c) /* Reserved */ + +#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ + +#define AT91_PMC_RES_50 (AT91_PMC + 0x50) /* Reserved */ +#define AT91_PMC_RES_54 (AT91_PMC + 0x54) /* Reserved */ +#define AT91_PMC_RES_58 (AT91_PMC + 0x58) /* Reserved */ +#define AT91_PMC_RES_5C (AT91_PMC + 0x5c) /* Reserved */ + +#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ +#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ +#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ +#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ +#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ +#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ +#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ + +#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ + +#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ + +#endif diff -urN u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/AT91RM9200.h u-boot-2009.01/include/asm-arm/arch-at91rm9200/AT91RM9200.h --- u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/AT91RM9200.h 2009-01-01 13:09:34.000000000 +0100 +++ u-boot-2009.01/include/asm-arm/arch-at91rm9200/AT91RM9200.h 2009-01-01 15:52:00.000000000 +0100 @@ -28,6 +28,114 @@ #ifndef __ASSEMBLY__ typedef volatile unsigned int AT91_REG; /* Hardware register definition */ +/* + * Peripheral identifiers/interrupts. + */ +#define AT91RM9200_ID_AIC 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91RM9200_ID_SYSIRQ 1 /* System Peripherals */ +#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ +#define AT91RM9200_ID_US0 6 /* USART 0 */ +#define AT91RM9200_ID_US1 7 /* USART 1 */ +#define AT91RM9200_ID_US2 8 /* USART 2 */ +#define AT91RM9200_ID_US3 9 /* USART 2 */ +#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ +#define AT91RM9200_ID_UDP 11 /* USB Device Port */ +#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ +#define AT91RM9200_ID_SPI0 13 /* Serial Peripheral Interface 0 */ +#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller */ +#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller */ +#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller */ +#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ +#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ +#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ +#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ +#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ +#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ +#define AT91RM9200_ID_UHP 23 /* USB Host port */ +#define AT91RM9200_ID_EMAC 24 /* Ethernet */ +#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ +#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ +#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ +#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ +#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ +/* + * User Peripheral physical base addresses. + */ + + + +#define AT91RM9200_BASE_TC0 0xFFFA0000 /* (TC0) Base Address */ +#define AT91RM9200_BASE_TC1 0xFFFA4000 /* (TC0) Base Address */ +#define AT91RM9200_BASE_UDP 0xFFFB0000 /* (TC0) Base Address */ +#define AT91RM9200_BASE_MCI 0xFFFB4000 /* (TC0) Base Address */ +#define AT91RM9200_BASE_TWI 0xFFFB8000 /* (TC0) Base Address */ +#define AT91RM9200_BASE_EMAC 0xFFFBC000 /* (EMAC) Base Address */ +#define AT91RM9200_BASE_US0 0xFFFC0000 /* (US0) Base Address */ +#define AT91RM9200_BASE_US1 0xFFFC4000 /* (US1) Base Address */ +#define AT91RM9200_BASE_US2 0xFFFC8000 /* (US1) Base Address */ +#define AT91RM9200_BASE_US3 0xFFFCC000 /* (US1) Base Address */ +#define AT91RM9200_BASE_SPI 0xFFFE0000 /* (SPI) Base Address */ + +#define AT91RM9200_BASE_AIC 0xFFFFF000 /* (AIC) Base Address */ +#define AT91RM9200_BASE_DBGU 0xFFFFF200 /* (DBGU) Base Address */ +#define AT91RM9200_BASE_PIOA 0xFFFFF400 /* (PIOA) Base Address */ +#define AT91RM9200_BASE_PIOB 0xFFFFF600 /* (PIOB) Base Address */ +#define AT91RM9200_BASE_PIOC 0xFFFFF800 /* (PIOC) Base Address */ +#define AT91RM9200_BASE_PIOD 0xFFFFFA00 /* (PIOC) Base Address */ +#define AT91RM9200_BASE_PMC 0xFFFFFC00 /* (PMC) Base Address */ +#define AT91RM9200_BASE_CKGR 0xFFFFFC20 /* (CKGR) Base Address */ +#define AT91RM9200_BASE_ST 0xFFFFFD00 /* (PMC) Base Address */ +#define AT91RM9200_BASE_RTC 0xFFFFFE00 /* (PMC) Base Address */ +#define AT91RM9200_BASE_MC 0xFFFFFF00 /* (PMC) Base Address */ +#define AT91RM9200_BASE_EBI 0xFFFFFF60 /* (PMC) Base Address */ +#define AT91RM9200_BASE_SMC2 0xFFFFFF70 /* (SMC2) Base Address */ +#define AT91RM9200_BASE_SDRAMC 0xFFFFFF90 /* (SMC2) Base Address */ +#define AT91RM9200_BASE_BFC 0xFFFFFFC0 /* (SMC2) Base Address */ + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_BASE_SYS AT91RM9200_BASE_AIC + +#define AT91_AIC (AT91RM9200_BASE_AIC - AT91_BASE_SYS) +#define AT91_DBGU (AT91RM9200_BASE_DBGU - AT91_BASE_SYS) +#define AT91_PIOA (AT91RM9200_BASE_PIOA - AT91_BASE_SYS) +#define AT91_PIOB (AT91RM9200_BASE_PIOB - AT91_BASE_SYS) +#define AT91_PIOC (AT91RM9200_BASE_PIOC - AT91_BASE_SYS) +#define AT91_PIOD (AT91RM9200_BASE_PIOD - AT91_BASE_SYS) +#define AT91_PMC (AT91RM9200_BASE_PMC - AT91_BASE_SYS) +#define AT91_PMC (AT91RM9200_BASE_PMC - AT91_BASE_SYS) +#define AT91_PMC (AT91RM9200_BASE_PMC - AT91_BASE_SYS) +#define AT91_PMC (AT91RM9200_BASE_PMC - AT91_BASE_SYS) +#define AT91_PMC (AT91RM9200_BASE_PMC - AT91_BASE_SYS) + +#define AT91_CKGR (AT91RM9200_BASE_CKGR - AT91_BASE_SYS) +#define AT91_ST (AT91RM9200_BASE_ST - AT91_BASE_SYS) +#define AT91_RTC (AT91RM9200_BASE_RTC - AT91_BASE_SYS) +#define AT91_MC (AT91RM9200_BASE_MC - AT91_BASE_SYS) +#define AT91_EBI (AT91RM9200_BASE_EBI - AT91_BASE_SYS) +#define AT91_EBI_CSA ((AT91RM9200_BASE_EBI +0x00) - AT91_BASE_SYS) +#define AT91_SMC2 (AT91RM9200_BASE_SMC2 - AT91_BASE_SYS) +#define AT91_SMC2_CSR0 ((AT91RM9200_BASE_SMC2+0x00) - AT91_BASE_SYS) +#define AT91_SMC2_CSR1 ((AT91RM9200_BASE_SMC2+0x04) - AT91_BASE_SYS) +#define AT91_SMC2_CSR2 ((AT91RM9200_BASE_SMC2+0x08) - AT91_BASE_SYS) +#define AT91_SMC2_CSR3 ((AT91RM9200_BASE_SMC2+0x0c) - AT91_BASE_SYS) +#define AT91_SMC2_CSR4 ((AT91RM9200_BASE_SMC2+0x10) - AT91_BASE_SYS) +#define AT91_SMC2_CSR5 ((AT91RM9200_BASE_SMC2+0x14) - AT91_BASE_SYS) +#define AT91_SMC2_CSR6 ((AT91RM9200_BASE_SMC2+0x18) - AT91_BASE_SYS) +#define AT91_SMC2_CSR7 ((AT91RM9200_BASE_SMC2+0x1c) - AT91_BASE_SYS) + + +#define AT91_USART0 AT91RM9200_BASE_US0 +#define AT91_USART1 AT91RM9200_BASE_US1 +#define AT91_USART2 AT91RM9200_BASE_US2 +#define AT91_USART3 AT91RM9200_BASE_US3 + /*****************************************************************************/ /* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ /*****************************************************************************/ diff -urN u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/gpio.h u-boot-2009.01/include/asm-arm/arch-at91rm9200/gpio.h --- u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/gpio.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2009.01/include/asm-arm/arch-at91rm9200/gpio.h 2009-01-01 14:02:11.000000000 +0100 @@ -0,0 +1,367 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h] + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_AT91_GPIO_H +#define __ASM_ARCH_AT91_GPIO_H + +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/hardware.h> + +#define PIN_BASE 32 + +#define MAX_GPIO_BANKS 5 + +/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ + +#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) +#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) +#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) +#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) +#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) +#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) +#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) +#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) +#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) +#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) +#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) +#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) +#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) +#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) +#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) +#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) +#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) +#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) +#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) +#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) +#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) +#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) +#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) +#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) +#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) +#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) +#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) +#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) +#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) +#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) +#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) +#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) + +#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) +#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) +#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) +#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) +#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) +#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) +#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) +#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) +#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) +#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) +#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) +#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) +#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) +#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) +#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) +#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) +#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) +#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) +#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) +#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) +#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) +#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) +#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) +#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) +#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) +#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) +#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) +#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) +#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) +#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) +#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) +#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) + +#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) +#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) +#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) +#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) +#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) +#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) +#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) +#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) +#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) +#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) +#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) +#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) +#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) +#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) +#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) +#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) +#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) +#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) +#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) +#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) +#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) +#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) +#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) +#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) +#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) +#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) +#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) +#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) +#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) +#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) +#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) +#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) + +#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) +#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) +#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) +#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) +#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) +#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) +#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) +#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) +#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) +#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) +#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) +#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) +#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) +#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) +#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) +#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) +#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) +#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) +#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) +#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) +#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) +#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) +#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) +#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) +#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) +#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) +#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) +#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) +#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) +#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) +#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) +#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) + +#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) +#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) +#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) +#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) +#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) +#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) +#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) +#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) +#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) +#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) +#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) +#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) +#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) +#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) +#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) +#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) +#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) +#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) +#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) +#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) +#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) +#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) +#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) +#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) +#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) +#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) +#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) +#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) +#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) +#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) +#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) +#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) + +static unsigned long at91_pios[] = { + AT91_PIOA, + AT91_PIOB, + AT91_PIOC, +#ifdef AT91_PIOD + AT91_PIOD, +#ifdef AT91_PIOE + AT91_PIOE +#endif +#endif +}; + +static inline void *pin_to_controller(unsigned pin) +{ + pin -= PIN_BASE; + pin /= 32; + return (void *)(AT91_BASE_SYS + at91_pios[pin]); +} + +static inline unsigned pin_to_mask(unsigned pin) +{ + pin -= PIN_BASE; + return 1 << (pin % 32); +} + +/* + * mux the pin to the "GPIO" peripheral role. + */ +static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + __raw_writel(mask, pio + PIO_IDR); + __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); + __raw_writel(mask, pio + PIO_PER); + return 0; +} + +/* + * mux the pin to the "A" internal peripheral role. + */ +static inline int at91_set_A_periph(unsigned pin, int use_pullup) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + __raw_writel(mask, pio + PIO_IDR); + __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); + __raw_writel(mask, pio + PIO_ASR); + __raw_writel(mask, pio + PIO_PDR); + return 0; +} + +/* + * mux the pin to the "B" internal peripheral role. + */ +static inline int at91_set_B_periph(unsigned pin, int use_pullup) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + __raw_writel(mask, pio + PIO_IDR); + __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); + __raw_writel(mask, pio + PIO_BSR); + __raw_writel(mask, pio + PIO_PDR); + return 0; +} + +/* + * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and + * configure it for an input. + */ +static inline int at91_set_gpio_input(unsigned pin, int use_pullup) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + __raw_writel(mask, pio + PIO_IDR); + __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); + __raw_writel(mask, pio + PIO_ODR); + __raw_writel(mask, pio + PIO_PER); + return 0; +} + +/* + * mux the pin to the gpio controller (instead of "A" or "B" peripheral), + * and configure it for an output. + */ +static inline int at91_set_gpio_output(unsigned pin, int value) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + __raw_writel(mask, pio + PIO_IDR); + __raw_writel(mask, pio + PIO_PUDR); + __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); + __raw_writel(mask, pio + PIO_OER); + __raw_writel(mask, pio + PIO_PER); + return 0; +} + +/* + * enable/disable the glitch filter; mostly used with IRQ handling. + */ +static inline int at91_set_deglitch(unsigned pin, int is_on) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); + return 0; +} + +/* + * enable/disable the multi-driver; This is only valid for output and + * allows the output pin to run as an open collector output. + */ +static inline int at91_set_multi_drive(unsigned pin, int is_on) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); + return 0; +} + +static inline int gpio_direction_input(unsigned pin) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (!(__raw_readl(pio + PIO_PSR) & mask)) + return -EINVAL; + __raw_writel(mask, pio + PIO_ODR); + return 0; +} + +static inline int gpio_direction_output(unsigned pin, int value) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + if (!(__raw_readl(pio + PIO_PSR) & mask)) + return -EINVAL; + __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); + __raw_writel(mask, pio + PIO_OER); + return 0; +} + +/* + * assuming the pin is muxed as a gpio output, set its value. + */ +static inline int at91_set_gpio_value(unsigned pin, int value) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + + __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); + return 0; +} + +/* + * read the pin's value (works even if it's not muxed as a gpio). + */ +static inline int at91_get_gpio_value(unsigned pin) +{ + void *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); + u32 pdsr; + + pdsr = __raw_readl(pio + PIO_PDSR); + return (pdsr & mask) != 0; +} + +#endif diff -urN u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/io.h u-boot-2009.01/include/asm-arm/arch-at91rm9200/io.h --- u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/io.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2009.01/include/asm-arm/arch-at91rm9200/io.h 2009-01-01 15:59:51.000000000 +0100 @@ -0,0 +1,56 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/io.h] + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include <asm/io.h> + +static inline unsigned int at91_sys_read(unsigned int reg_offset) +{ + void *addr = (void *)AT91_BASE_SYS; + + return __raw_readl(addr + reg_offset); +} + +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) +{ + void *addr = (void *)AT91_BASE_SYS; + + __raw_writel(value, addr + reg_offset); +} + +static inline void at91_sys_setbit(unsigned long value, unsigned int reg_offset) +{ + void *addr = (void *)(AT91_BASE_SYS + reg_offset); + value |= __raw_readl(addr); + __raw_writel(value, addr); +} + +static inline void at91_sys_clrbit(unsigned long value, unsigned int reg_offset) +{ + void *addr = (void *)(AT91_BASE_SYS + reg_offset); + unsigned long data; + data = __raw_readl(addr); + data &= ~value; + __raw_writel(data, addr); +} + +#endif Best Regards Ulf Samuelsson

2 1

[U-Boot] AT91 Pull request
by Jean-Christophe PLAGNIOL-VILLARD 10 Jan '09

10 Jan '09

Hi Wolfgang, Please pulli The following changes since commit f85cd46918241842546e5021d0b88db2be50a048: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx are available in the git repository at: git://git.denx.de/u-boot-at91.git master Jean-Christophe PLAGNIOL-VILLARD (5): at91: Fix Atmel's at91sam9 boards out of tree build fix bmp_logo.h make dependencies to allow parallel build at91rm9200: rename lowlevel init value to CONFIG_SYS_ m501sk: move to the common memory setup at91rm9200: move define from lowlevel_init to header Nicolas Ferre (1): at91: add at91sam9xeek board support Makefile | 23 +++- board/m501sk/Makefile | 2 - board/m501sk/memsetup.S | 200 -------------------------- cpu/arm920t/at91rm9200/lowlevel_init.S | 158 +++++++++------------ doc/README.at91 | 2 +- include/asm-arm/arch-at91rm9200/AT91RM9200.h | 27 ++++ include/configs/at91rm9200dk.h | 46 +++--- include/configs/cmc_pu2.h | 46 +++--- include/configs/csb637.h | 46 +++--- include/configs/m501sk.h | 33 +++++ include/configs/mp2usb.h | 46 +++--- 11 files changed, 241 insertions(+), 388 deletions(-) delete mode 100644 board/m501sk/memsetup.S Best Regards, J.

2 1

[U-Boot] [PATCH] [update] Fix up rsk7203 target for out of tree build
by Kieran Bingham 10 Jan '09

10 Jan '09

Patch updated to correct changes made during debug Signed-off-by: Kieran Bingham <kbingham(a)mpc-data.co.uk> --- Makefile | 4 ++-- board/renesas/rsk7203/Makefile | 4 ++++ cpu/sh2/Makefile | 21 +++++++++++++-------- 3 files changed, 19 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index d6cd91a..552ef85 100644 --- a/Makefile +++ b/Makefile @@ -3200,8 +3200,8 @@ mimc200_config : unconfig ## sh2 (Renesas SuperH) ######################################################################### rsk7203_config: unconfig - @ >include/config.h - @echo "#define CONFIG_RSK7203 1" >> include/config.h + @mkdir -p $(obj)include + @echo "#define CONFIG_RSK7203 1" > $(obj)/include/config.h @$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas ######################################################################### diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile index 7365d19..5412010 100644 --- a/board/renesas/rsk7203/Makefile +++ b/board/renesas/rsk7203/Makefile @@ -26,6 +26,10 @@ LIB = lib$(BOARD).a OBJS := rsk7203.o SOBJS := lowlevel_init.o +LIB := $(addprefix $(obj),$(LIB)) +OBJS := $(addprefix $(obj),$(OBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/cpu/sh2/Makefile b/cpu/sh2/Makefile index e33ba0f..346d328 100644 --- a/cpu/sh2/Makefile +++ b/cpu/sh2/Makefile @@ -28,18 +28,23 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o -OBJS = cpu.o interrupts.o watchdog.o +SOBJS = start.o +COBJS = cpu.o interrupts.o watchdog.o -all: .depend $(START) $(LIB) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -######################################################################### +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ +######################################################################### # defines $(obj).depend target include $(SRCTREE)/rules.mk -- 1.6.1

2 1

[U-Boot] [PATCH 1/2] sh: lowlevel_init coding style cleanup
by Jean-Christophe PLAGNIOL-VILLARD 10 Jan '09

10 Jan '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- board/mpr2/lowlevel_init.S | 44 +- board/ms7722se/lowlevel_init.S | 34 +- board/ms7750se/lowlevel_init.S | 150 +++--- board/renesas/MigoR/lowlevel_init.S | 10 +- board/renesas/ap325rxa/lowlevel_init.S | 86 ++-- board/renesas/r2dplus/lowlevel_init.S | 126 +++--- board/renesas/r7780mp/lowlevel_init.S | 858 +++++++++++++++--------------- board/renesas/rsk7203/lowlevel_init.S | 214 ++++---- board/renesas/sh7763rdp/lowlevel_init.S | 162 +++--- board/renesas/sh7785lcr/lowlevel_init.S | 2 +- 10 files changed, 846 insertions(+), 840 deletions(-) rewrite board/renesas/r7780mp/lowlevel_init.S (68%) diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S index 060957a..187b5bb 100644 --- a/board/mpr2/lowlevel_init.S +++ b/board/mpr2/lowlevel_init.S @@ -33,17 +33,17 @@ lowlevel_init: /* * Set frequency multipliers and dividers in FRQCR. */ - mov.l WTCSR_A,r1 - mov.l WTCSR_D,r0 - mov.w r0,@r1 + mov.l WTCSR_A, r1 + mov.l WTCSR_D, r0 + mov.w r0, @r1 - mov.l WTCNT_A,r1 - mov.l WTCNT_D,r0 - mov.w r0,@r1 + mov.l WTCNT_A, r1 + mov.l WTCNT_D, r0 + mov.w r0, @r1 - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.w r0,@r1 + mov.l FRQCR_A, r1 + mov.l FRQCR_D, r0 + mov.w r0, @r1 /* * Setup CS0 (Flash). @@ -112,21 +112,27 @@ WTCSR_D: .long 0xA507 /* divide by 4096 */ /* * Spansion S29GL256N11 @ 48 MHz */ -CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */ -CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ +/* 1 idle cycle inserted, normal space, 16 bit */ +CS0BCR_D: .long 0x12490400 +/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ +CS0WCR_D: .long 0x00000340 /* * Samsung K4S511632B-UL75 @ 48 MHz * Micron MT48LC32M16A2-75 @ 48 MHz */ -CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ -CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ -SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */ -SDCR_D2: .long 0x00000812 /* refresh */ -RTCSR_D: .long 0xA55A0008 /* 1/4, once */ -RTCNT_D: .long 0xA55A005D /* count 93 */ -RTCOR_D: .long 0xa55a005d /* count 93 */ -SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */ +/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ +CS3BCR_D: .long 0x10004400 +/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ +CS3WCR_D: .long 0x00000091 +/* no refresh, 13 rows, 10 cols, NO bank active mode */ +SDCR_D1: .long 0x00000012 +SDCR_D2: .long 0x00000812 /* refresh */ +RTCSR_D: .long 0xA55A0008 /* 1/4, once */ +RTCNT_D: .long 0xA55A005D /* count 93 */ +RTCOR_D: .long 0xa55a005d /* count 93 */ +/* mode register CL2, burst read and SINGLE WRITE */ +SDMR3_D: .long 0x440 /* * Registers diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S index 8b46595..3e887cf 100644 --- a/board/ms7722se/lowlevel_init.S +++ b/board/ms7722se/lowlevel_init.S @@ -29,11 +29,11 @@ #include <asm/processor.h> /* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. * - * (Note: As no stack is available, no subroutines can be called...). + * (Note: As no stack is available, no subroutines can be called...). */ .global lowlevel_init @@ -203,7 +203,7 @@ bsc_init: mov #0x00, r0 ! SDMR3 data -> R0 mov.b r0, @r1 ! SDMR3 set - ! BL bit off (init = ON) (?!?) + ! BL bit off (init = ON) (?!?) stc sr, r0 ! BL bit off(init=ON) mov.l SR_MASK_D, r1 @@ -232,28 +232,28 @@ MSTPCR0_D: .long 0x00001001 MSTPCR2_D: .long 0xffffffff FRQCR_D: .long 0x07022538 -PSELA_A: .long 0xa405014E -PSELA_D: .word 0x0A10 +PSELA_A: .long 0xa405014E +PSELA_D: .word 0x0A10 .align 2 -DRVCR_A: .long 0xa405018A -DRVCR_D: .word 0x0554 +DRVCR_A: .long 0xa405018A +DRVCR_D: .word 0x0554 .align 2 -PCCR_A: .long 0xa4050104 -PCCR_D: .word 0x8800 +PCCR_A: .long 0xa4050104 +PCCR_D: .word 0x8800 .align 2 -PECR_A: .long 0xa4050108 -PECR_D: .word 0x0000 +PECR_A: .long 0xa4050108 +PECR_D: .word 0x0000 .align 2 -PJCR_A: .long 0xa4050110 -PJCR_D: .word 0x1000 +PJCR_A: .long 0xa4050110 +PJCR_D: .word 0x1000 .align 2 -PXCR_A: .long 0xa4050148 -PXCR_D: .word 0x0AAA +PXCR_A: .long 0xa4050148 +PXCR_D: .word 0x0AAA .align 2 CMNCR_A: .long CMNCR diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index d3e3cd5..de05dd9 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -31,118 +31,118 @@ #include <asm/processor.h> #ifdef CONFIG_CPU_SH7751 -#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ -#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ +#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ +#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ #ifdef CONFIG_MARUBUN_PCCARD -#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:6 A0B:7 */ +#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:6 A0B:7 */ #else /* CONFIG_MARUBUN_PCCARD */ -#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:6 A0B:7 */ +#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:6 A0B:7 */ #endif /* CONFIG_MARUBUN_PCCARD */ -#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 - A2: 1-3 A1: 1-3 A0: 0-1 */ -#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ -#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ -#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */ -#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ +#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ +#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ +#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ +#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ #else /* CONFIG_CPU_SH7751 */ -#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ -#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ -#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:15 A0B:7 */ -#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 - A2: 1-3 A1: 1-3 A0: 0-1 */ -#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ -#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ -#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */ -#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ +#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ +#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ +#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:15 A0B:7 */ +#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ +#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ +#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ +#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ #endif /* CONFIG_CPU_SH7751 */ .global lowlevel_init .text - .align 2 + .align 2 lowlevel_init: - mov.l CCR_A, r1 ! CCR Address - mov.l CCR_D_DISABLE, r0 ! CCR Data - mov.l r0, @r1 + mov.l CCR_A, r1 ! CCR Address + mov.l CCR_D_DISABLE, r0 ! CCR Data + mov.l r0, @r1 init_bsc: - mov.l FRQCR_A,r1 /* FRQCR Address */ - mov.l FRQCR_D,r0 /* FRQCR Data */ - mov.w r0,@r1 + mov.l FRQCR_A, r1 /* FRQCR Address */ + mov.l FRQCR_D, r0 /* FRQCR Data */ + mov.w r0, @r1 - mov.l BCR1_A,r1 /* BCR1 Address */ - mov.l BCR1_D,r0 /* BCR1 Data */ - mov.l r0,@r1 + mov.l BCR1_A, r1 /* BCR1 Address */ + mov.l BCR1_D, r0 /* BCR1 Data */ + mov.l r0, @r1 - mov.l BCR2_A,r1 /* BCR2 Address */ - mov.l BCR2_D,r0 /* BCR2 Data */ - mov.w r0,@r1 + mov.l BCR2_A, r1 /* BCR2 Address */ + mov.l BCR2_D, r0 /* BCR2 Data */ + mov.w r0, @r1 - mov.l WCR1_A,r1 /* WCR1 Address */ - mov.l WCR1_D,r0 /* WCR1 Data */ - mov.l r0,@r1 + mov.l WCR1_A, r1 /* WCR1 Address */ + mov.l WCR1_D, r0 /* WCR1 Data */ + mov.l r0, @r1 - mov.l WCR2_A,r1 /* WCR2 Address */ - mov.l WCR2_D,r0 /* WCR2 Data */ - mov.l r0,@r1 + mov.l WCR2_A, r1 /* WCR2 Address */ + mov.l WCR2_D, r0 /* WCR2 Data */ + mov.l r0, @r1 - mov.l WCR3_A,r1 /* WCR3 Address */ - mov.l WCR3_D,r0 /* WCR3 Data */ - mov.l r0,@r1 + mov.l WCR3_A, r1 /* WCR3 Address */ + mov.l WCR3_D, r0 /* WCR3 Data */ + mov.l r0, @r1 - mov.l MCR_A,r1 /* MCR Address */ - mov.l MCR_D1,r0 /* MCR Data1 */ - mov.l r0,@r1 + mov.l MCR_A, r1 /* MCR Address */ + mov.l MCR_D1, r0 /* MCR Data1 */ + mov.l r0, @r1 - mov.l SDMR3_A,r1 /* Set SDRAM mode */ - mov #0,r0 - mov.b r0,@r1 + mov.l SDMR3_A, r1 /* Set SDRAM mode */ + mov #0, r0 + mov.b r0, @r1 ! Do you need PCMCIA setting? ! If so, please add the lines here... - mov.l RTCNT_A,r1 /* RTCNT Address */ - mov.l RTCNT_D,r0 /* RTCNT Data */ - mov.w r0,@r1 + mov.l RTCNT_A, r1 /* RTCNT Address */ + mov.l RTCNT_D, r0 /* RTCNT Data */ + mov.w r0, @r1 - mov.l RTCOR_A,r1 /* RTCOR Address */ - mov.l RTCOR_D,r0 /* RTCOR Data */ - mov.w r0,@r1 + mov.l RTCOR_A, r1 /* RTCOR Address */ + mov.l RTCOR_D, r0 /* RTCOR Data */ + mov.w r0, @r1 - mov.l RTCSR_A,r1 /* RTCSR Address */ - mov.l RTCSR_D,r0 /* RTCSR Data */ - mov.w r0,@r1 + mov.l RTCSR_A, r1 /* RTCSR Address */ + mov.l RTCSR_D, r0 /* RTCSR Data */ + mov.w r0, @r1 - mov.l RFCR_A,r1 /* RFCR Address */ - mov.l RFCR_D,r0 /* RFCR Data */ - mov.w r0,@r1 /* Clear reflesh counter */ + mov.l RFCR_A, r1 /* RFCR Address */ + mov.l RFCR_D, r0 /* RFCR Data */ + mov.w r0, @r1 /* Clear reflesh counter */ /* Wait DRAM refresh 30 times */ - mov #30,r3 + mov #30, r3 1: - mov.w @r1,r0 - extu.w r0,r2 - cmp/hi r3,r2 + mov.w @r1, r0 + extu.w r0, r2 + cmp/hi r3, r2 bf 1b - mov.l MCR_A,r1 /* MCR Address */ - mov.l MCR_D2,r0 /* MCR Data2 */ - mov.l r0,@r1 + mov.l MCR_A, r1 /* MCR Address */ + mov.l MCR_D2, r0 /* MCR Data2 */ + mov.l r0, @r1 - mov.l SDMR3_A,r1 /* Set SDRAM mode */ - mov #0,r0 - mov.b r0,@r1 + mov.l SDMR3_A, r1 /* Set SDRAM mode */ + mov #0, r0 + mov.b r0, @r1 rts - nop + nop .align 2 -CCR_A: .long CCR -CCR_D_DISABLE: .long 0x0808 +CCR_A: .long CCR +CCR_D_DISABLE: .long 0x0808 FRQCR_A: .long FRQCR FRQCR_D: #ifdef CONFIG_CPU_TYPE_R diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S index 4c1900e..13c83bf 100644 --- a/board/renesas/MigoR/lowlevel_init.S +++ b/board/renesas/MigoR/lowlevel_init.S @@ -29,11 +29,11 @@ #include <asm/processor.h> /* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. * - * (Note: As no stack is available, no subroutines can be called...). + * (Note: As no stack is available, no subroutines can be called...). */ .global lowlevel_init @@ -176,7 +176,7 @@ bsc_init: mov #0x00, r0 ! SDMR3 data -> R0 mov.b r0, @r1 ! SDMR3 set - ! BL bit off (init = ON) (?!?) + ! BL bit off (init = ON) (?!?) stc sr, r0 ! BL bit off(init=ON) mov.l SR_MASK_D, r1 diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index 4f66588..558e779 100644 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -39,111 +39,111 @@ lowlevel_init: mov.l DRVCRA_A, r1 - mov.l DRVCRA_D, r0 + mov.l DRVCRA_D, r0 mov.w r0, @r1 mov.l DRVCRB_A, r1 - mov.l DRVCRB_D, r0 + mov.l DRVCRB_D, r0 mov.w r0, @r1 mov.l RWTCSR_A, r1 - mov.l RWTCSR_D1, r0 + mov.l RWTCSR_D1, r0 mov.w r0, @r1 mov.l RWTCNT_A, r1 - mov.l RWTCNT_D, r0 + mov.l RWTCNT_D, r0 mov.w r0, @r1 mov.l RWTCSR_A, r1 - mov.l RWTCSR_D2, r0 + mov.l RWTCSR_D2, r0 mov.w r0, @r1 mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 + mov.l FRQCR_D, r0 mov.l r0, @r1 mov.l CMNCR_A, r1 mov.l CMNCR_D, r0 mov.l r0, @r1 - mov.l CS0BCR_A ,r1 - mov.l CS0BCR_D ,r0 + mov.l CS0BCR_A, r1 + mov.l CS0BCR_D, r0 mov.l r0, @r1 - mov.l CS4BCR_A ,r1 - mov.l CS4BCR_D ,r0 + mov.l CS4BCR_A, r1 + mov.l CS4BCR_D, r0 mov.l r0, @r1 - mov.l CS5ABCR_A ,r1 - mov.l CS5ABCR_D ,r0 + mov.l CS5ABCR_A, r1 + mov.l CS5ABCR_D, r0 mov.l r0, @r1 - mov.l CS5BBCR_A ,r1 - mov.l CS5BBCR_D ,r0 + mov.l CS5BBCR_A, r1 + mov.l CS5BBCR_D, r0 mov.l r0, @r1 - mov.l CS6ABCR_A ,r1 - mov.l CS6ABCR_D ,r0 + mov.l CS6ABCR_A, r1 + mov.l CS6ABCR_D, r0 mov.l r0, @r1 - mov.l CS6BBCR_A ,r1 - mov.l CS6BBCR_D ,r0 + mov.l CS6BBCR_A, r1 + mov.l CS6BBCR_D, r0 mov.l r0, @r1 - mov.l CS0WCR_A ,r1 - mov.l CS0WCR_D ,r0 + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 mov.l r0, @r1 - mov.l CS4WCR_A ,r1 - mov.l CS4WCR_D ,r0 + mov.l CS4WCR_A, r1 + mov.l CS4WCR_D, r0 mov.l r0, @r1 - mov.l CS5AWCR_A ,r1 - mov.l CS5AWCR_D ,r0 + mov.l CS5AWCR_A, r1 + mov.l CS5AWCR_D, r0 mov.l r0, @r1 - mov.l CS5BWCR_A ,r1 - mov.l CS5BWCR_D ,r0 + mov.l CS5BWCR_A, r1 + mov.l CS5BWCR_D, r0 mov.l r0, @r1 - mov.l CS6AWCR_A ,r1 - mov.l CS6AWCR_D ,r0 + mov.l CS6AWCR_A, r1 + mov.l CS6AWCR_D, r0 mov.l r0, @r1 - mov.l CS6BWCR_A ,r1 - mov.l CS6BWCR_D ,r0 + mov.l CS6BWCR_A, r1 + mov.l CS6BWCR_D, r0 mov.l r0, @r1 mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D1, r0 + mov.l SBSC_SDCR_D1, r0 mov.l r0, @r1 mov.l SBSC_SDWCR_A, r1 - mov.l SBSC_SDWCR_D, r0 + mov.l SBSC_SDWCR_D, r0 mov.l r0, @r1 mov.l SBSC_SDPCR_A, r1 - mov.l SBSC_SDPCR_D, r0 + mov.l SBSC_SDPCR_D, r0 mov.l r0, @r1 mov.l SBSC_RTCSR_A, r1 - mov.l SBSC_RTCSR_D, r0 + mov.l SBSC_RTCSR_D, r0 mov.l r0, @r1 mov.l SBSC_RTCNT_A, r1 - mov.l SBSC_RTCNT_D, r0 + mov.l SBSC_RTCNT_D, r0 mov.l r0, @r1 mov.l SBSC_RTCOR_A, r1 - mov.l SBSC_RTCOR_D, r0 + mov.l SBSC_RTCOR_D, r0 mov.l r0, @r1 mov.l SBSC_SDMR3_A1, r1 - mov.l SBSC_SDMR3_D, r0 + mov.l SBSC_SDMR3_D, r0 mov.b r0, @r1 mov.l SBSC_SDMR3_A2, r1 - mov.l SBSC_SDMR3_D, r0 + mov.l SBSC_SDMR3_D, r0 mov.b r0, @r1 mov.l SLEEP_CNT, r1 @@ -153,18 +153,18 @@ lowlevel_init: dt r1 mov.l SBSC_SDMR3_A3, r1 - mov.l SBSC_SDMR3_D, r0 + mov.l SBSC_SDMR3_D, r0 mov.b r0, @r1 mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D2, r0 + mov.l SBSC_SDCR_D2, r0 mov.l r0, @r1 mov.l CCR_A, r1 - mov.l CCR_D, r0 + mov.l CCR_D, r0 mov.l r0, @r1 - ! BL bit off (init = ON) (?!?) + ! BL bit off (init = ON) (?!?) stc sr, r0 ! BL bit off(init=ON) mov.l SR_MASK_D, r1 @@ -211,7 +211,7 @@ SBSC_SDMR3_D: .long 0x00 CMNCR_A: .long CMNCR CS0BCR_A: .long CS0BCR CS4BCR_A: .long CS4BCR -CS5ABCR_A: .long CS5ABCR +CS5ABCR_A: .long CS5ABCR CS5BBCR_A: .long CS5BBCR CS6ABCR_A: .long CS6ABCR CS6BBCR_A: .long CS6BBCR diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 28d2b37..a057370 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -17,92 +17,92 @@ lowlevel_init: mov.l CCR_A, r1 mov.l CCR_D_D, r0 - mov.l r0,@r1 + mov.l r0, @r1 - mov.l MMUCR_A,r1 - mov.l MMUCR_D,r0 - mov.l r0,@r1 + mov.l MMUCR_A, r1 + mov.l MMUCR_D, r0 + mov.l r0, @r1 - mov.l BCR1_A,r1 - mov.l BCR1_D,r0 - mov.l r0,@r1 + mov.l BCR1_A, r1 + mov.l BCR1_D, r0 + mov.l r0, @r1 - mov.l BCR2_A,r1 - mov.l BCR2_D,r0 - mov.w r0,@r1 + mov.l BCR2_A, r1 + mov.l BCR2_D, r0 + mov.w r0, @r1 - mov.l BCR3_A,r1 - mov.l BCR3_D,r0 - mov.w r0,@r1 + mov.l BCR3_A, r1 + mov.l BCR3_D, r0 + mov.w r0, @r1 - mov.l BCR4_A,r1 - mov.l BCR4_D,r0 - mov.l r0,@r1 + mov.l BCR4_A, r1 + mov.l BCR4_D, r0 + mov.l r0, @r1 - mov.l WCR1_A,r1 - mov.l WCR1_D,r0 - mov.l r0,@r1 + mov.l WCR1_A, r1 + mov.l WCR1_D, r0 + mov.l r0, @r1 - mov.l WCR2_A,r1 - mov.l WCR2_D,r0 - mov.l r0,@r1 + mov.l WCR2_A, r1 + mov.l WCR2_D, r0 + mov.l r0, @r1 - mov.l WCR3_A,r1 - mov.l WCR3_D,r0 - mov.l r0,@r1 + mov.l WCR3_A, r1 + mov.l WCR3_D, r0 + mov.l r0, @r1 - mov.l PCR_A,r1 - mov.l PCR_D,r0 - mov.w r0,@r1 + mov.l PCR_A, r1 + mov.l PCR_D, r0 + mov.w r0, @r1 - mov.l LED_A,r1 - mov #0xff,r0 - mov.w r0,@r1 + mov.l LED_A, r1 + mov #0xff, r0 + mov.w r0, @r1 - mov.l MCR_A,r1 - mov.l MCR_D1,r0 - mov.l r0,@r1 + mov.l MCR_A, r1 + mov.l MCR_D1, r0 + mov.l r0, @r1 - mov.l RTCNT_A,r1 - mov.l RTCNT_D,r0 - mov.w r0,@r1 + mov.l RTCNT_A, r1 + mov.l RTCNT_D, r0 + mov.w r0, @r1 - mov.l RTCOR_A,r1 - mov.l RTCOR_D,r0 - mov.w r0,@r1 + mov.l RTCOR_A, r1 + mov.l RTCOR_D, r0 + mov.w r0, @r1 - mov.l RFCR_A,r1 - mov.l RFCR_D,r0 - mov.w r0,@r1 + mov.l RFCR_A, r1 + mov.l RFCR_D, r0 + mov.w r0, @r1 - mov.l RTCSR_A,r1 - mov.l RTCSR_D,r0 - mov.w r0,@r1 + mov.l RTCSR_A, r1 + mov.l RTCSR_D, r0 + mov.w r0, @r1 - mov.l SDMR3_A,r1 - mov #0x55,r0 - mov.b r0,@r1 + mov.l SDMR3_A, r1 + mov #0x55, r0 + mov.b r0, @r1 /* Wait DRAM refresh 30 times */ - mov.l RFCR_A,r1 - mov #30,r3 + mov.l RFCR_A, r1 + mov #30, r3 1: - mov.w @r1,r0 - extu.w r0,r2 - cmp/hi r3,r2 + mov.w @r1, r0 + extu.w r0, r2 + cmp/hi r3, r2 bf 1b - mov.l MCR_A,r1 - mov.l MCR_D2,r0 - mov.l r0,@r1 + mov.l MCR_A, r1 + mov.l MCR_D2, r0 + mov.l r0, @r1 - mov.l SDMR3_A,r1 - mov #0,r0 - mov.b r0,@r1 + mov.l SDMR3_A, r1 + mov #0, r0 + mov.b r0, @r1 - mov.l IRLMASK_A,r1 - mov.l IRLMASK_D,r0 - mov.l r0,@r1 + mov.l IRLMASK_A, r1 + mov.l IRLMASK_D, r0 + mov.l r0, @r1 mov.l CCR_A, r1 mov.l CCR_D_E, r0 diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S dissimilarity index 68% index ab0499a..0df8c84 100644 --- a/board/renesas/r7780mp/lowlevel_init.S +++ b/board/renesas/r7780mp/lowlevel_init.S @@ -1,429 +1,429 @@ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu - * - * u-boot/board/r7780mp/lowlevel_init.S - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/processor.h> - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_D, r0 /* Instruction Cache Invalidate */ - mov.l r0, @r1 - - mov.l FRQCR_A, r1 /* Frequency control register */ - mov.l FRQCR_D, r0 - mov.l r0, @r1 - - /* pin_multi_setting */ - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR1,r0 - mov.l r0,@r1 - - mov.l BBG_PMSR1_A,r1 - mov.l BBG_PMSR1_D,r0 - mov.l r0,@r1 - - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR2,r0 - mov.l r0,@r1 - - mov.l BBG_PMSR2_A,r1 - mov.l BBG_PMSR2_D,r0 - mov.l r0,@r1 - - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR3,r0 - mov.l r0,@r1 - - mov.l BBG_PMSR3_A,r1 - mov.l BBG_PMSR3_D,r0 - mov.l r0,@r1 - - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR4,r0 - mov.l r0,@r1 - - mov.l BBG_PMSR4_A,r1 - mov.l BBG_PMSR4_D,r0 - mov.l r0,@r1 - - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSRG,r0 - mov.l r0,@r1 - - mov.l BBG_PMSRG_A,r1 - mov.l BBG_PMSRG_D,r0 - mov.l r0,@r1 - - /* cpg_setting */ - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.l r0,@r1 - - mov.l DLLCSR_A,r1 - mov.l DLLCSR_D,r0 - mov.l r0,@r1 - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* wait 200us */ - mov.l REPEAT0_R3,r3 - mov #0,r2 -repeat0: - add #1,r2 - cmp/hs r3,r2 - bf repeat0 - nop - - /* bsc_setting */ - mov.l MMSELR_A,r1 - mov.l MMSELR_D,r0 - mov.l r0,@r1 - - mov.l BCR_A,r1 - mov.l BCR_D,r0 - mov.l r0,@r1 - - mov.l CS0BCR_A,r1 - mov.l CS0BCR_D,r0 - mov.l r0,@r1 - - mov.l CS1BCR_A,r1 - mov.l CS1BCR_D,r0 - mov.l r0,@r1 - - mov.l CS2BCR_A,r1 - mov.l CS2BCR_D,r0 - mov.l r0,@r1 - - mov.l CS4BCR_A,r1 - mov.l CS4BCR_D,r0 - mov.l r0,@r1 - - mov.l CS5BCR_A,r1 - mov.l CS5BCR_D,r0 - mov.l r0,@r1 - - mov.l CS6BCR_A,r1 - mov.l CS6BCR_D,r0 - mov.l r0,@r1 - - mov.l CS0WCR_A,r1 - mov.l CS0WCR_D,r0 - mov.l r0,@r1 - - mov.l CS1WCR_A,r1 - mov.l CS1WCR_D,r0 - mov.l r0,@r1 - - mov.l CS2WCR_A,r1 - mov.l CS2WCR_D,r0 - mov.l r0,@r1 - - mov.l CS4WCR_A,r1 - mov.l CS4WCR_D,r0 - mov.l r0,@r1 - - mov.l CS5WCR_A,r1 - mov.l CS5WCR_D,r0 - mov.l r0,@r1 - - mov.l CS6WCR_A,r1 - mov.l CS6WCR_D,r0 - mov.l r0,@r1 - - mov.l CS5PCR_A,r1 - mov.l CS5PCR_D,r0 - mov.l r0,@r1 - - mov.l CS6PCR_A,r1 - mov.l CS6PCR_D,r0 - mov.l r0,@r1 - - /* ddr_setting */ - /* wait 200us */ - mov.l REPEAT0_R3,r3 - mov #0,r2 -repeat1: - add #1,r2 - cmp/hs r3,r2 - bf repeat1 - nop - - mov.l MIM_U_A,r0 - mov.l MIM_U_D,r1 - synco - mov.l r1,@r0 - synco - - mov.l MIM_L_A,r0 - mov.l MIM_L_D0,r1 - synco - mov.l r1,@r0 - synco - - mov.l STR_L_A,r0 - mov.l STR_L_D,r1 - synco - mov.l r1,@r0 - synco - - mov.l SDR_L_A,r0 - mov.l SDR_L_D,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - nop - - mov.l SCR_L_A,r0 - mov.l SCR_L_D0,r1 - synco - mov.l r1,@r0 - synco - - mov.l SCR_L_A,r0 - mov.l SCR_L_D1,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l EMRS_A,r0 - mov.l EMRS_D,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l MRS1_A,r0 - mov.l MRS1_D,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l SCR_L_A,r0 - mov.l SCR_L_D2,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l SCR_L_A,r0 - mov.l SCR_L_D3,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l SCR_L_A,r0 - mov.l SCR_L_D4,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l MRS2_A,r0 - mov.l MRS2_D,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l SCR_L_A,r0 - mov.l SCR_L_D5,r1 - synco - mov.l r1,@r0 - synco - - /* wait 200us */ - mov.l REPEAT0_R1,r3 - mov #0,r2 -repeat2: - add #1,r2 - cmp/hs r3,r2 - bf repeat2 - - synco - - mov.l MIM_L_A,r0 - mov.l MIM_L_D1,r1 - synco - mov.l r1,@r0 - synco - - rts - nop - .align 4 - -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA507 -RWTCNT_D: .word 0x5A00 - .align 2 - -BBG_PMMR_A: .long 0xFF800010 -BBG_PMSR1_A: .long 0xFF800014 -BBG_PMSR2_A: .long 0xFF800018 -BBG_PMSR3_A: .long 0xFF80001C -BBG_PMSR4_A: .long 0xFF800020 -BBG_PMSRG_A: .long 0xFF800024 - -BBG_PMMR_D_PMSR1: .long 0xffffbffd -BBG_PMSR1_D: .long 0x00004002 -BBG_PMMR_D_PMSR2: .long 0xfc21a7ff -BBG_PMSR2_D: .long 0x03de5800 -BBG_PMMR_D_PMSR3: .long 0xfffffff8 -BBG_PMSR3_D: .long 0x00000007 -BBG_PMMR_D_PMSR4: .long 0xdffdfff9 -BBG_PMSR4_D: .long 0x20020006 -BBG_PMMR_D_PMSRG: .long 0xffffffff -BBG_PMSRG_D: .long 0x00000000 - -FRQCR_A: .long FRQCR -DLLCSR_A: .long 0xffc40010 -FRQCR_D: .long 0x40233035 -DLLCSR_D: .long 0x00000000 - -/* for DDR-SDRAM */ -MIM_U_A: .long MIM_1 -MIM_L_A: .long MIM_2 -SCR_U_A: .long SCR_1 -SCR_L_A: .long SCR_2 -STR_U_A: .long STR_1 -STR_L_A: .long STR_2 -SDR_U_A: .long SDR_1 -SDR_L_A: .long SDR_2 - -EMRS_A: .long 0xFEC02000 -MRS1_A: .long 0xFEC00B08 -MRS2_A: .long 0xFEC00308 - -MIM_U_D: .long 0x00004000 -MIM_L_D0: .long 0x03e80009 -MIM_L_D1: .long 0x03e80209 -SCR_L_D0: .long 0x3 -SCR_L_D1: .long 0x2 -SCR_L_D2: .long 0x2 -SCR_L_D3: .long 0x4 -SCR_L_D4: .long 0x4 -SCR_L_D5: .long 0x0 -STR_L_D: .long 0x000f0000 -SDR_L_D: .long 0x00000400 -EMRS_D: .long 0x0 -MRS1_D: .long 0x0 -MRS2_D: .long 0x0 - -/* Cache Controller */ -CCR_A: .long CCR -MMUCR_A: .long MMUCR -RWTCNT_A: .long WTCNT - -CCR_D: .long 0x0000090b -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff - -/* local Bus State Controller */ -MMSELR_A: .long MMSELR -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS1BCR_A: .long CS1BCR -CS2BCR_A: .long CS2BCR -CS4BCR_A: .long CS4BCR -CS5BCR_A: .long CS5BCR -CS6BCR_A: .long CS6BCR -CS0WCR_A: .long CS0WCR -CS1WCR_A: .long CS1WCR -CS2WCR_A: .long CS2WCR -CS4WCR_A: .long CS4WCR -CS5WCR_A: .long CS5WCR -CS6WCR_A: .long CS6WCR -CS5PCR_A: .long CS5PCR -CS6PCR_A: .long CS6PCR - -MMSELR_D: .long 0xA5A50003 -BCR_D: .long 0x00000000 -CS0BCR_D: .long 0x77777770 -CS1BCR_D: .long 0x77777670 -CS2BCR_D: .long 0x77777770 -CS4BCR_D: .long 0x77777770 -CS5BCR_D: .long 0x77777670 -CS6BCR_D: .long 0x77777770 -CS0WCR_D: .long 0x00020006 -CS1WCR_D: .long 0x00232304 -CS2WCR_D: .long 0x7777770F -CS4WCR_D: .long 0x7777770F -CS5WCR_D: .long 0x00101006 -CS6WCR_D: .long 0x77777703 -CS5PCR_D: .long 0x77000000 -CS6PCR_D: .long 0x77000000 - -REPEAT0_R3: .long 0x00002000 -REPEAT0_R1: .long 0x0000200 +/* + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu + * + * u-boot/board/r7780mp/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + mov.l CCR_A, r1 /* Address of Cache Control Register */ + mov.l CCR_D, r0 /* Instruction Cache Invalidate */ + mov.l r0, @r1 + + mov.l FRQCR_A, r1 /* Frequency control register */ + mov.l FRQCR_D, r0 + mov.l r0, @r1 + + /* pin_multi_setting */ + mov.l BBG_PMMR_A, r1 + mov.l BBG_PMMR_D_PMSR1, r0 + mov.l r0, @r1 + + mov.l BBG_PMSR1_A, r1 + mov.l BBG_PMSR1_D, r0 + mov.l r0, @r1 + + mov.l BBG_PMMR_A, r1 + mov.l BBG_PMMR_D_PMSR2, r0 + mov.l r0, @r1 + + mov.l BBG_PMSR2_A, r1 + mov.l BBG_PMSR2_D, r0 + mov.l r0, @r1 + + mov.l BBG_PMMR_A, r1 + mov.l BBG_PMMR_D_PMSR3, r0 + mov.l r0, @r1 + + mov.l BBG_PMSR3_A, r1 + mov.l BBG_PMSR3_D, r0 + mov.l r0, @r1 + + mov.l BBG_PMMR_A, r1 + mov.l BBG_PMMR_D_PMSR4, r0 + mov.l r0, @r1 + + mov.l BBG_PMSR4_A, r1 + mov.l BBG_PMSR4_D, r0 + mov.l r0, @r1 + + mov.l BBG_PMMR_A, r1 + mov.l BBG_PMMR_D_PMSRG, r0 + mov.l r0, @r1 + + mov.l BBG_PMSRG_A, r1 + mov.l BBG_PMSRG_D, r0 + mov.l r0, @r1 + + /* cpg_setting */ + mov.l FRQCR_A, r1 + mov.l FRQCR_D, r0 + mov.l r0, @r1 + + mov.l DLLCSR_A, r1 + mov.l DLLCSR_D, r0 + mov.l r0, @r1 + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* wait 200us */ + mov.l REPEAT0_R3, r3 + mov #0, r2 +repeat0: + add #1, r2 + cmp/hs r3, r2 + bf repeat0 + nop + + /* bsc_setting */ + mov.l MMSELR_A, r1 + mov.l MMSELR_D, r0 + mov.l r0, @r1 + + mov.l BCR_A, r1 + mov.l BCR_D, r0 + mov.l r0, @r1 + + mov.l CS0BCR_A, r1 + mov.l CS0BCR_D, r0 + mov.l r0, @r1 + + mov.l CS1BCR_A, r1 + mov.l CS1BCR_D, r0 + mov.l r0, @r1 + + mov.l CS2BCR_A, r1 + mov.l CS2BCR_D, r0 + mov.l r0, @r1 + + mov.l CS4BCR_A, r1 + mov.l CS4BCR_D, r0 + mov.l r0, @r1 + + mov.l CS5BCR_A, r1 + mov.l CS5BCR_D, r0 + mov.l r0, @r1 + + mov.l CS6BCR_A, r1 + mov.l CS6BCR_D, r0 + mov.l r0, @r1 + + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 + mov.l r0, @r1 + + mov.l CS1WCR_A, r1 + mov.l CS1WCR_D, r0 + mov.l r0, @r1 + + mov.l CS2WCR_A, r1 + mov.l CS2WCR_D, r0 + mov.l r0, @r1 + + mov.l CS4WCR_A, r1 + mov.l CS4WCR_D, r0 + mov.l r0, @r1 + + mov.l CS5WCR_A, r1 + mov.l CS5WCR_D, r0 + mov.l r0, @r1 + + mov.l CS6WCR_A, r1 + mov.l CS6WCR_D, r0 + mov.l r0, @r1 + + mov.l CS5PCR_A, r1 + mov.l CS5PCR_D, r0 + mov.l r0, @r1 + + mov.l CS6PCR_A, r1 + mov.l CS6PCR_D, r0 + mov.l r0, @r1 + + /* ddr_setting */ + /* wait 200us */ + mov.l REPEAT0_R3, r3 + mov #0, r2 +repeat1: + add #1, r2 + cmp/hs r3, r2 + bf repeat1 + nop + + mov.l MIM_U_A, r0 + mov.l MIM_U_D, r1 + synco + mov.l r1, @r0 + synco + + mov.l MIM_L_A, r0 + mov.l MIM_L_D0, r1 + synco + mov.l r1, @r0 + synco + + mov.l STR_L_A, r0 + mov.l STR_L_D, r1 + synco + mov.l r1, @r0 + synco + + mov.l SDR_L_A, r0 + mov.l SDR_L_D, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + nop + + mov.l SCR_L_A, r0 + mov.l SCR_L_D0, r1 + synco + mov.l r1, @r0 + synco + + mov.l SCR_L_A, r0 + mov.l SCR_L_D1, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l EMRS_A, r0 + mov.l EMRS_D, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l MRS1_A, r0 + mov.l MRS1_D, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l SCR_L_A, r0 + mov.l SCR_L_D2, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l SCR_L_A, r0 + mov.l SCR_L_D3, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l SCR_L_A, r0 + mov.l SCR_L_D4, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l MRS2_A, r0 + mov.l MRS2_D, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l SCR_L_A, r0 + mov.l SCR_L_D5, r1 + synco + mov.l r1, @r0 + synco + + /* wait 200us */ + mov.l REPEAT0_R1, r3 + mov #0, r2 +repeat2: + add #1, r2 + cmp/hs r3, r2 + bf repeat2 + + synco + + mov.l MIM_L_A, r0 + mov.l MIM_L_D1, r1 + synco + mov.l r1, @r0 + synco + + rts + nop + .align 4 + +RWTCSR_D_1: .word 0xA507 +RWTCSR_D_2: .word 0xA507 +RWTCNT_D: .word 0x5A00 + .align 2 + +BBG_PMMR_A: .long 0xFF800010 +BBG_PMSR1_A: .long 0xFF800014 +BBG_PMSR2_A: .long 0xFF800018 +BBG_PMSR3_A: .long 0xFF80001C +BBG_PMSR4_A: .long 0xFF800020 +BBG_PMSRG_A: .long 0xFF800024 + +BBG_PMMR_D_PMSR1: .long 0xffffbffd +BBG_PMSR1_D: .long 0x00004002 +BBG_PMMR_D_PMSR2: .long 0xfc21a7ff +BBG_PMSR2_D: .long 0x03de5800 +BBG_PMMR_D_PMSR3: .long 0xfffffff8 +BBG_PMSR3_D: .long 0x00000007 +BBG_PMMR_D_PMSR4: .long 0xdffdfff9 +BBG_PMSR4_D: .long 0x20020006 +BBG_PMMR_D_PMSRG: .long 0xffffffff +BBG_PMSRG_D: .long 0x00000000 + +FRQCR_A: .long FRQCR +DLLCSR_A: .long 0xffc40010 +FRQCR_D: .long 0x40233035 +DLLCSR_D: .long 0x00000000 + +/* for DDR-SDRAM */ +MIM_U_A: .long MIM_1 +MIM_L_A: .long MIM_2 +SCR_U_A: .long SCR_1 +SCR_L_A: .long SCR_2 +STR_U_A: .long STR_1 +STR_L_A: .long STR_2 +SDR_U_A: .long SDR_1 +SDR_L_A: .long SDR_2 + +EMRS_A: .long 0xFEC02000 +MRS1_A: .long 0xFEC00B08 +MRS2_A: .long 0xFEC00308 + +MIM_U_D: .long 0x00004000 +MIM_L_D0: .long 0x03e80009 +MIM_L_D1: .long 0x03e80209 +SCR_L_D0: .long 0x3 +SCR_L_D1: .long 0x2 +SCR_L_D2: .long 0x2 +SCR_L_D3: .long 0x4 +SCR_L_D4: .long 0x4 +SCR_L_D5: .long 0x0 +STR_L_D: .long 0x000f0000 +SDR_L_D: .long 0x00000400 +EMRS_D: .long 0x0 +MRS1_D: .long 0x0 +MRS2_D: .long 0x0 + +/* Cache Controller */ +CCR_A: .long CCR +MMUCR_A: .long MMUCR +RWTCNT_A: .long WTCNT + +CCR_D: .long 0x0000090b +CCR_D_2: .long 0x00000103 +MMUCR_D: .long 0x00000004 +MSTPCR0_D: .long 0x00001001 +MSTPCR2_D: .long 0xffffffff + +/* local Bus State Controller */ +MMSELR_A: .long MMSELR +BCR_A: .long BCR +CS0BCR_A: .long CS0BCR +CS1BCR_A: .long CS1BCR +CS2BCR_A: .long CS2BCR +CS4BCR_A: .long CS4BCR +CS5BCR_A: .long CS5BCR +CS6BCR_A: .long CS6BCR +CS0WCR_A: .long CS0WCR +CS1WCR_A: .long CS1WCR +CS2WCR_A: .long CS2WCR +CS4WCR_A: .long CS4WCR +CS5WCR_A: .long CS5WCR +CS6WCR_A: .long CS6WCR +CS5PCR_A: .long CS5PCR +CS6PCR_A: .long CS6PCR + +MMSELR_D: .long 0xA5A50003 +BCR_D: .long 0x00000000 +CS0BCR_D: .long 0x77777770 +CS1BCR_D: .long 0x77777670 +CS2BCR_D: .long 0x77777770 +CS4BCR_D: .long 0x77777770 +CS5BCR_D: .long 0x77777670 +CS6BCR_D: .long 0x77777770 +CS0WCR_D: .long 0x00020006 +CS1WCR_D: .long 0x00232304 +CS2WCR_D: .long 0x7777770F +CS4WCR_D: .long 0x7777770F +CS5WCR_D: .long 0x00101006 +CS6WCR_D: .long 0x77777703 +CS5PCR_D: .long 0x77000000 +CS6PCR_D: .long 0x77000000 + +REPEAT0_R3: .long 0x00002000 +REPEAT0_R1: .long 0x0000200 diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index e4d6f9e..f6a6231 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -29,153 +29,153 @@ lowlevel_init: /* Cache setting */ - mov.l CCR1_A ,r1 - mov.l CCR1_D ,r0 - mov.l r0,@r1 + mov.l CCR1_A, r1 + mov.l CCR1_D, r0 + mov.l r0, @r1 /* ConfigurePortPins */ - mov.l PECRL3_A, r1 - mov.l PECRL3_D, r0 - mov.w r0,@r1 + mov.l PECRL3_A, r1 + mov.l PECRL3_D, r0 + mov.w r0, @r1 - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D0, r0 - mov.w r0,@r1 + mov.l PCCRL4_A, r1 + mov.l PCCRL4_D0, r0 + mov.w r0, @r1 - mov.l PECRL4_A, r1 - mov.l PECRL4_D0, r0 - mov.w r0,@r1 + mov.l PECRL4_A, r1 + mov.l PECRL4_D0, r0 + mov.w r0, @r1 - mov.l PEIORL_A, r1 - mov.l PEIORL_D0, r0 - mov.w r0,@r1 + mov.l PEIORL_A, r1 + mov.l PEIORL_D0, r0 + mov.w r0, @r1 - mov.l PCIORL_A, r1 - mov.l PCIORL_D, r0 - mov.w r0,@r1 + mov.l PCIORL_A, r1 + mov.l PCIORL_D, r0 + mov.w r0, @r1 - mov.l PFCRH2_A, r1 - mov.l PFCRH2_D, r0 - mov.w r0,@r1 + mov.l PFCRH2_A, r1 + mov.l PFCRH2_D, r0 + mov.w r0, @r1 - mov.l PFCRH3_A, r1 - mov.l PFCRH3_D, r0 - mov.w r0,@r1 + mov.l PFCRH3_A, r1 + mov.l PFCRH3_D, r0 + mov.w r0, @r1 - mov.l PFCRH1_A, r1 - mov.l PFCRH1_D, r0 - mov.w r0,@r1 + mov.l PFCRH1_A, r1 + mov.l PFCRH1_D, r0 + mov.w r0, @r1 - mov.l PFIORH_A, r1 - mov.l PFIORH_D, r0 - mov.w r0,@r1 + mov.l PFIORH_A, r1 + mov.l PFIORH_D, r0 + mov.w r0, @r1 - mov.l PECRL1_A, r1 - mov.l PECRL1_D0, r0 - mov.w r0,@r1 + mov.l PECRL1_A, r1 + mov.l PECRL1_D0, r0 + mov.w r0, @r1 - mov.l PEIORL_A, r1 - mov.l PEIORL_D1, r0 - mov.w r0,@r1 + mov.l PEIORL_A, r1 + mov.l PEIORL_D1, r0 + mov.w r0, @r1 /* Configure Operating Frequency */ - mov.l WTCSR_A ,r1 - mov.l WTCSR_D0 ,r0 - mov.w r0,@r1 + mov.l WTCSR_A, r1 + mov.l WTCSR_D0, r0 + mov.w r0, @r1 - mov.l WTCSR_A ,r1 - mov.l WTCSR_D1 ,r0 - mov.w r0,@r1 + mov.l WTCSR_A, r1 + mov.l WTCSR_D1, r0 + mov.w r0, @r1 - mov.l WTCNT_A ,r1 - mov.l WTCNT_D ,r0 - mov.w r0,@r1 + mov.l WTCNT_A, r1 + mov.l WTCNT_D, r0 + mov.w r0, @r1 /* Set clock mode*/ - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.w r0,@r1 + mov.l FRQCR_A, r1 + mov.l FRQCR_D, r0 + mov.w r0, @r1 /* Configure Bus And Memory */ init_bsc_cs0: - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D1,r0 - mov.w r0,@r1 + mov.l PCCRL4_A, r1 + mov.l PCCRL4_D1, r0 + mov.w r0, @r1 - mov.l PECRL1_A,r1 - mov.l PECRL1_D1,r0 - mov.w r0,@r1 + mov.l PECRL1_A, r1 + mov.l PECRL1_D1, r0 + mov.w r0, @r1 - mov.l CMNCR_A,r1 - mov.l CMNCR_D,r0 - mov.l r0,@r1 + mov.l CMNCR_A, r1 + mov.l CMNCR_D, r0 + mov.l r0, @r1 - mov.l SC0BCR_A,r1 - mov.l SC0BCR_D,r0 - mov.l r0,@r1 + mov.l SC0BCR_A, r1 + mov.l SC0BCR_D, r0 + mov.l r0, @r1 - mov.l CS0WCR_A,r1 - mov.l CS0WCR_D,r0 - mov.l r0,@r1 + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 + mov.l r0, @r1 init_bsc_cs1: - mov.l PECRL4_A,r1 - mov.l PECRL4_D1,r0 - mov.w r0,@r1 + mov.l PECRL4_A, r1 + mov.l PECRL4_D1, r0 + mov.w r0, @r1 - mov.l CS1WCR_A,r1 - mov.l CS1WCR_D,r0 - mov.l r0,@r1 + mov.l CS1WCR_A, r1 + mov.l CS1WCR_D, r0 + mov.l r0, @r1 init_sdram: - mov.l PCCRL2_A,r1 - mov.l PCCRL2_D,r0 - mov.w r0,@r1 + mov.l PCCRL2_A, r1 + mov.l PCCRL2_D, r0 + mov.w r0, @r1 - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D2,r0 - mov.w r0,@r1 + mov.l PCCRL4_A, r1 + mov.l PCCRL4_D2, r0 + mov.w r0, @r1 - mov.l PCCRL1_A,r1 - mov.l PCCRL1_D,r0 - mov.w r0,@r1 + mov.l PCCRL1_A, r1 + mov.l PCCRL1_D, r0 + mov.w r0, @r1 - mov.l PCCRL3_A,r1 - mov.l PCCRL3_D,r0 - mov.w r0,@r1 + mov.l PCCRL3_A, r1 + mov.l PCCRL3_D, r0 + mov.w r0, @r1 - mov.l CS3BCR_A,r1 - mov.l CS3BCR_D,r0 - mov.l r0,@r1 + mov.l CS3BCR_A, r1 + mov.l CS3BCR_D, r0 + mov.l r0, @r1 - mov.l CS3WCR_A,r1 - mov.l CS3WCR_D,r0 - mov.l r0,@r1 + mov.l CS3WCR_A, r1 + mov.l CS3WCR_D, r0 + mov.l r0, @r1 - mov.l SDCR_A,r1 - mov.l SDCR_D,r0 - mov.l r0,@r1 + mov.l SDCR_A, r1 + mov.l SDCR_D, r0 + mov.l r0, @r1 - mov.l RTCOR_A,r1 - mov.l RTCOR_D,r0 - mov.l r0,@r1 + mov.l RTCOR_A, r1 + mov.l RTCOR_D, r0 + mov.l r0, @r1 - mov.l RTCSR_A,r1 - mov.l RTCSR_D,r0 - mov.l r0,@r1 + mov.l RTCSR_A, r1 + mov.l RTCSR_D, r0 + mov.l r0, @r1 /* wait 200us */ - mov.l REPEAT_D,r3 - mov #0,r2 + mov.l REPEAT_D, r3 + mov #0, r2 repeat0: - add #1,r2 - cmp/hs r3,r2 - bf repeat0 + add #1, r2 + cmp/hs r3, r2 + bf repeat0 nop - mov.l SDRAM_MODE, r1 - mov #0,r0 - mov.l r0, @r1 + mov.l SDRAM_MODE, r1 + mov #0, r0 + mov.l r0, @r1 nop rts @@ -208,8 +208,8 @@ PECRL1_D0: .long 0x00000033 WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D +WTCSR_D0: .long 0x0000A518 +WTCSR_D1: .long 0x0000A51D WTCNT_A: .long 0xFFFE0002 WTCNT_D: .long 0x00005A84 FRQCR_A: .long 0xFFFE0010 @@ -259,7 +259,7 @@ STBCR4_A: .long 0xFFFE040C STBCR4_D: .long 0x00000008 STBCR5_A: .long 0xFFFE0410 STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 +STBCR6_A: .long 0xFFFE0414 STBCR6_D: .long 0x00000002 SDRAM_MODE: .long 0xFFFC5040 REPEAT_D: .long 0x00009C40 diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 2a44eee..715e75f 100644 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -33,17 +33,17 @@ lowlevel_init: - mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ - mov.l WDTCSR_D, r0 - mov.l r0, @r1 + mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ + mov.l WDTCSR_D, r0 + mov.l r0, @r1 - mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ - mov.l WDTST_D, r0 - mov.l r0, @r1 + mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ + mov.l WDTST_D, r0 + mov.l r0, @r1 - mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ - mov.l WDTBST_D, r0 - mov.l r0, @r1 + mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ + mov.l WDTBST_D, r0 + mov.l r0, @r1 mov.l CCR_A, r1 /* Address of Cache Control Register */ mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */ @@ -61,107 +61,107 @@ lowlevel_init: mov.l MSTPCR1_D, r0 mov.l r0, @r1 - mov.l RAMCR_A,r1 - mov.l RAMCR_D,r0 + mov.l RAMCR_A, r1 + mov.l RAMCR_D, r0 mov.l r0, @r1 - mov.l MMSELR_A,r1 - mov.l MMSELR_D,r0 + mov.l MMSELR_A, r1 + mov.l MMSELR_D, r0 synco mov.l r0, @r1 - mov.l @r1,r2 /* execute two reads after setting MMSELR*/ - mov.l @r1,r2 + mov.l @r1, r2 /* execute two reads after setting MMSELR*/ + mov.l @r1, r2 synco /* issue memory read */ - mov.l DDRSD_START_A,r1 /* memory address to read*/ - mov.l @r1,r0 + mov.l DDRSD_START_A, r1 /* memory address to read*/ + mov.l @r1, r0 synco - mov.l MIM8_A,r1 - mov.l MIM8_D,r0 - mov.l r0,@r1 + mov.l MIM8_A, r1 + mov.l MIM8_D, r0 + mov.l r0, @r1 - mov.l MIMC_A,r1 - mov.l MIMC_D1,r0 - mov.l r0,@r1 + mov.l MIMC_A, r1 + mov.l MIMC_D1, r0 + mov.l r0, @r1 - mov.l STRC_A,r1 - mov.l STRC_D,r0 - mov.l r0,@r1 + mov.l STRC_A, r1 + mov.l STRC_D, r0 + mov.l r0, @r1 - mov.l SDR4_A,r1 - mov.l SDR4_D,r0 - mov.l r0,@r1 + mov.l SDR4_A, r1 + mov.l SDR4_D, r0 + mov.l r0, @r1 - mov.l MIMC_A,r1 - mov.l MIMC_D2,r0 - mov.l r0,@r1 + mov.l MIMC_A, r1 + mov.l MIMC_D2, r0 + mov.l r0, @r1 nop nop nop - mov.l SCR4_A,r1 - mov.l SCR4_D3,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D3, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D2,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D2, r0 + mov.l r0, @r1 - mov.l SDMR02000_A,r1 - mov.l SDMR02000_D,r0 - mov.l r0,@r1 + mov.l SDMR02000_A, r1 + mov.l SDMR02000_D, r0 + mov.l r0, @r1 - mov.l SDMR00B08_A,r1 - mov.l SDMR00B08_D,r0 - mov.l r0,@r1 + mov.l SDMR00B08_A, r1 + mov.l SDMR00B08_D, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D2,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D2, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D4,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D4, r0 + mov.l r0, @r1 nop nop nop nop - mov.l SCR4_A,r1 - mov.l SCR4_D4,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D4, r0 + mov.l r0, @r1 nop nop nop nop - mov.l SDMR00308_A,r1 - mov.l SDMR00308_D,r0 - mov.l r0,@r1 + mov.l SDMR00308_A, r1 + mov.l SDMR00308_D, r0 + mov.l r0, @r1 - mov.l MIMC_A,r1 - mov.l MIMC_D3,r0 - mov.l r0,@r1 + mov.l MIMC_A, r1 + mov.l MIMC_D3, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D1,r0 - mov.l DELAY60_D,r3 + mov.l SCR4_A, r1 + mov.l SCR4_D1, r0 + mov.l DELAY60_D, r3 delay_loop_60: - mov.l r0,@r1 + mov.l r0, @r1 dt r3 bf delay_loop_60 nop - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_CACHE_D_2, r0 - mov.l r0, @r1 + mov.l CCR_A, r1 /* Address of Cache Control Register */ + mov.l CCR_CACHE_D_2, r0 + mov.l r0, @r1 bsc_init: mov.l BCR_A, r1 @@ -172,9 +172,9 @@ bsc_init: mov.l CS0BCR_D, r0 mov.l r0, @r1 - mov.l CS1BCR_A,r1 - mov.l CS1BCR_D,r0 - mov.l r0,@r1 + mov.l CS1BCR_A, r1 + mov.l CS1BCR_D, r0 + mov.l r0, @r1 mov.l CS2BCR_A, r1 mov.l CS2BCR_D, r0 @@ -224,27 +224,27 @@ bsc_init: mov.l CS6PCR_D, r0 mov.l r0, @r1 - mov.l DELAY200_D,r3 + mov.l DELAY200_D, r3 delay_loop_200: dt r3 bf delay_loop_200 nop - mov.l PSEL0_A,r1 - mov.l PSEL0_D,r0 - mov.w r0,@r1 + mov.l PSEL0_A, r1 + mov.l PSEL0_D, r0 + mov.w r0, @r1 - mov.l PSEL1_A,r1 - mov.l PSEL1_D,r0 - mov.w r0,@r1 + mov.l PSEL1_A, r1 + mov.l PSEL1_D, r0 + mov.w r0, @r1 - mov.l ICR0_A,r1 - mov.l ICR0_D,r0 - mov.l r0,@r1 + mov.l ICR0_A, r1 + mov.l ICR0_D, r0 + mov.l r0, @r1 stc sr, r0 /* BL bit off(init=ON) */ - mov.l SR_MASK_D, r1 + mov.l SR_MASK_D, r1 and r1, r0 ldc r0, sr @@ -321,7 +321,7 @@ CS4BCR_D: .long 0x77777670 CS5BCR_D: .long 0x77777670 CS6BCR_D: .long 0x77777670 CS0WCR_D: .long 0x7777770F -CS1WCR_D: .long 0x22000002 +CS1WCR_D: .long 0x22000002 CS2WCR_D: .long 0x7777770F CS4WCR_D: .long 0x7777770F CS5WCR_D: .long 0x7777770F diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 50e1789..4cb1d9d 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -305,7 +305,7 @@ CS4WCR_D: .long 0x00101012 CS_USB_BCR_D: .long 0x11111200 CS_USB_WCR_D: .long 0x00020004 -/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ +/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ CS_SD_BCR_D: .long 0x00000300 CS_SD_WCR_D: .long 0x00030108 -- 1.5.6.5

2 2

[U-Boot] [PATCH] sh: update sh2/sh2a timer coding style
by Jean-Christophe PLAGNIOL-VILLARD 10 Jan '09

10 Jan '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- lib_sh/time_sh2.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lib_sh/time_sh2.c b/lib_sh/time_sh2.c index 4f893c8..5c6c9d4 100644 --- a/lib_sh/time_sh2.c +++ b/lib_sh/time_sh2.c @@ -28,7 +28,7 @@ #include <asm/io.h> #include <asm/processor.h> -#define CMT_CMCSR_INIT 0x0001 /* PCLK/32 */ +#define CMT_CMCSR_INIT 0x0001 /* PCLK/32 */ #define CMT_CMCSR_CALIB 0x0000 #define CMT_MAX_COUNTER (0xFFFFFFFF) #define CMT_TIMER_RESET (0xFFFF) @@ -87,7 +87,7 @@ static unsigned long get_usec (void) /* return msec */ ulong get_timer(ulong base) { - return (get_usec()/1000) - base; + return (get_usec() / 1000) - base; } void set_timer(ulong t) -- 1.5.6.5

2 1

[U-Boot] [PATCH] sh: update sh timer coding style
by Jean-Christophe PLAGNIOL-VILLARD 10 Jan '09

10 Jan '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- lib_sh/time.c | 26 +++++++++++++------------- 1 files changed, 13 insertions(+), 13 deletions(-) diff --git a/lib_sh/time.c b/lib_sh/time.c index 2bd7715..8fccce3 100644 --- a/lib_sh/time.c +++ b/lib_sh/time.c @@ -49,21 +49,21 @@ int timer_init (void) { /* Divide clock by TMU_CLK_DIVIDER */ u16 bit = 0; - switch( TMU_CLK_DIVIDER ){ - case 4: - bit = 0; - break; - case 16: - bit = 1; - break; - case 64: bit = 2; + + switch (TMU_CLK_DIVIDER) { + case 1024: + bit = 4; break; case 256: bit = 3; break; - case 1024: - bit = 4; + case 64: + bit = 2; break; + case 16: + bit = 1; + break; + case 4: default: bit = 0; break; @@ -71,7 +71,7 @@ int timer_init (void) writew(readw(TCR0) | bit, TCR0); /* Clock adjustment calc */ - clk_adj = (int)(1.0/((1.0/CONFIG_SYS_HZ)*1000000)); + clk_adj = (int)(1.0 / ((1.0 / CONFIG_SYS_HZ) * 1000000)); if (clk_adj < 1) clk_adj = 1; @@ -102,8 +102,8 @@ void udelay (unsigned long usec) unsigned long get_timer (unsigned long base) { - /* return msec */ - return ((get_usec()/clk_adj)/1000) - base; + /* return msec */ + return ((get_usec() / clk_adj) / 1000) - base; } void set_timer (unsigned long t) -- 1.5.6.5

2 1

[U-Boot] 税--票/代开
by 李先生 10 Jan '09

10 Jan '09

您好：我公司有地税--票/代开；如: （1）普通商品销售税--票；（2）广告业、各类服务业税--票；（3）运输、建筑安装、工程----票（4）普通增值税发票/等等。如有需要，欢迎您与我联系：负责人：李先生（0）13689556043

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[U-Boot] Setting usbact=dev causes startup hang
by Dave Cogley 09 Jan '09

09 Jan '09

Hello, We are using a Sequoia 440 EPX running u-boot 1.3.1 and are encountering an inconsistent startup problem when setting usbact=dev. We are using the USB DMA channel for our own DMA functionality and do not require a USB host interface. The problem is when we enable this field to 'dev' the board will take a significantly longer amount of time to boot or will hang indefinitely sometimes. It appears to always hang during network adapter initializations. After issuing a soft reset the board will boot up immediately. Dave Cogley Software Engineer Ultra Stereo Labs, Inc. (805) 549-0161 mailto:dcogley@uslinc.com

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[U-Boot] [PATCH 3/3] Change PCIE1&2 deciide logic on MPC8544DS board more readable
by Roy Zang 09 Jan '09

09 Jan '09

From: Roy Zang <tie-fei.zang(a)freescale.com> The IO port selection for MPC8544DS board: Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 This patch changes the PCIE12 and PCIE2 logic more readable. Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- board/freescale/mpc8544ds/mpc8544ds.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index a02a932..7ff5a9b 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -188,7 +188,7 @@ pci_init_board(void) volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 5); - int pcie_configured = io_sel & 6; + int pcie_configured = io_sel >= 2; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -251,7 +251,7 @@ pci_init_board(void) volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; int pcie_ep = (host_agent == 3); - int pcie_configured = io_sel & 4; + int pcie_configured = io_sel >= 4; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){

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