January 2009 - U-Boot

[U-Boot] [GIT PULL] MIPS updates
by Shinya Kuribayashi 27 Jan '09

27 Jan '09

Hi Wolfgang, please pull U-Boot/MIPS repository to pick up the following changes. Thanks in advance, Shinya --- The following changes since commit 8f86a3636ef88427f880610638e80991adc41896: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx are available in the git repository at: git://git.denx.de/u-boot-mips.git master Stefan Roese (4): MIPS: Add flush_dcache_range() and invalidate_dcache_range() MIPS: Add VCT board series support (Part 1/3) MIPS: Add VCT board series support (Part 2/3) MIPS: Add VCT board series support (Part 3/3) MAINTAINERS | 4 + MAKEALL | 12 + Makefile | 35 ++ board/micronas/vct/Makefile | 57 +++ board/micronas/vct/bcu.h | 170 +++++++++ board/micronas/vct/config.mk | 31 ++ board/micronas/vct/dcgu.c | 258 +++++++++++++ board/micronas/vct/dcgu.h | 179 +++++++++ board/micronas/vct/ebi.c | 48 +++ board/micronas/vct/ebi.h | 95 +++++ board/micronas/vct/ebi_nor_flash.c | 131 +++++++ board/micronas/vct/ebi_onenand.c | 198 ++++++++++ board/micronas/vct/ebi_smc911x.c | 94 +++++ board/micronas/vct/ehci.c | 110 ++++++ board/micronas/vct/gpio.c | 88 +++++ board/micronas/vct/scc.c | 669 ++++++++++++++++++++++++++++++++++ board/micronas/vct/scc.h | 205 +++++++++++ board/micronas/vct/smc_eeprom.c | 394 ++++++++++++++++++++ board/micronas/vct/top.c | 289 +++++++++++++++ board/micronas/vct/u-boot.lds | 71 ++++ board/micronas/vct/vct.c | 117 ++++++ board/micronas/vct/vct.h | 104 ++++++ board/micronas/vct/vcth/reg_dcgu.h | 36 ++ board/micronas/vct/vcth/reg_ebi.h | 242 ++++++++++++ board/micronas/vct/vcth/reg_fwsram.h | 73 ++++ board/micronas/vct/vcth/reg_gpio.h | 32 ++ board/micronas/vct/vcth/reg_scc.h | 102 +++++ board/micronas/vct/vcth/reg_usbh.h | 33 ++ board/micronas/vct/vcth/reg_wdt.h | 24 ++ board/micronas/vct/vcth2/reg_ebi.h | 290 +++++++++++++++ board/micronas/vct/vctv/reg_dcgu.h | 25 ++ board/micronas/vct/vctv/reg_ebi.h | 290 +++++++++++++++ board/micronas/vct/vctv/reg_gpio.h | 32 ++ board/micronas/vct/vctv/reg_wdt.h | 24 ++ cpu/mips/cpu.c | 28 ++ include/common.h | 2 + include/configs/vct.h | 340 +++++++++++++++++ 37 files changed, 4932 insertions(+), 0 deletions(-) create mode 100644 board/micronas/vct/Makefile create mode 100644 board/micronas/vct/bcu.h create mode 100644 board/micronas/vct/config.mk create mode 100644 board/micronas/vct/dcgu.c create mode 100644 board/micronas/vct/dcgu.h create mode 100644 board/micronas/vct/ebi.c create mode 100644 board/micronas/vct/ebi.h create mode 100644 board/micronas/vct/ebi_nor_flash.c create mode 100644 board/micronas/vct/ebi_onenand.c create mode 100644 board/micronas/vct/ebi_smc911x.c create mode 100644 board/micronas/vct/ehci.c create mode 100644 board/micronas/vct/gpio.c create mode 100644 board/micronas/vct/scc.c create mode 100644 board/micronas/vct/scc.h create mode 100644 board/micronas/vct/smc_eeprom.c create mode 100644 board/micronas/vct/top.c create mode 100644 board/micronas/vct/u-boot.lds create mode 100644 board/micronas/vct/vct.c create mode 100644 board/micronas/vct/vct.h create mode 100644 board/micronas/vct/vcth/reg_dcgu.h create mode 100644 board/micronas/vct/vcth/reg_ebi.h create mode 100644 board/micronas/vct/vcth/reg_fwsram.h create mode 100644 board/micronas/vct/vcth/reg_gpio.h create mode 100644 board/micronas/vct/vcth/reg_scc.h create mode 100644 board/micronas/vct/vcth/reg_usbh.h create mode 100644 board/micronas/vct/vcth/reg_wdt.h create mode 100644 board/micronas/vct/vcth2/reg_ebi.h create mode 100644 board/micronas/vct/vctv/reg_dcgu.h create mode 100644 board/micronas/vct/vctv/reg_ebi.h create mode 100644 board/micronas/vct/vctv/reg_gpio.h create mode 100644 board/micronas/vct/vctv/reg_wdt.h create mode 100644 include/configs/vct.h

2 1

[U-Boot] [cfi-flash] Please pull git://www.denx.de/git/u-boot-cfi-flash.git
by Stefan Roese 27 Jan '09

27 Jan '09

The following changes since commit 8f86a3636ef88427f880610638e80991adc41896: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx are available in the git repository at: git://www.denx.de/git/u-boot-cfi-flash.git master Jens Gehrlein (2): CFI: avoid redundant function call in single word programming mode CFI: increase performance of function find_sector() Richard Retanubun (1): CFI: Add geometry reversal for STMicro M29W320ET drivers/mtd/cfi_flash.c | 50 +++++++++++++++++++++++++++++++++++++--------- 1 files changed, 40 insertions(+), 10 deletions(-)

2 1

[U-Boot] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git
by Stefan Roese 27 Jan '09

27 Jan '09

The following changes since commit 8f86a3636ef88427f880610638e80991adc41896: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Dirk Eibach (2): ppc4xx: Improve DDR autodetect ppc4xx: Add GDsys PowerPC 440 ETX board support. Matthias Fuchs (1): ppc4xx: Remove CONFIG_SYS_IGNORE_405_UART_ERRATA_59 from config files Stefan Roese (1): ppc4xx: Remove compilation warning in gdppc440etc.c MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/gdsys/gdppc440etx/Makefile | 51 +++++ board/gdsys/gdppc440etx/config.mk | 44 +++++ board/gdsys/gdppc440etx/gdppc440etx.c | 323 +++++++++++++++++++++++++++++++++ board/gdsys/gdppc440etx/init.S | 75 ++++++++ board/gdsys/gdppc440etx/u-boot.lds | 144 +++++++++++++++ cpu/ppc4xx/sdram.c | 55 +++++- include/configs/ASH405.h | 1 - include/configs/CATcenter.h | 1 - include/configs/CMS700.h | 1 - include/configs/CPCI2DP.h | 1 - include/configs/CPCI405.h | 1 - include/configs/CPCI4052.h | 1 - include/configs/CPCI405AB.h | 1 - include/configs/CPCI405DT.h | 1 - include/configs/DP405.h | 1 - include/configs/G2000.h | 1 - include/configs/HH405.h | 1 - include/configs/HUB405.h | 1 - include/configs/OCRTC.h | 1 - include/configs/ORSG.h | 1 - include/configs/PCI405.h | 1 - include/configs/PLU405.h | 1 - include/configs/PMC405.h | 1 - include/configs/PPChameleonEVB.h | 1 - include/configs/VOH405.h | 1 - include/configs/VOM405.h | 1 - include/configs/WUH405.h | 1 - include/configs/csb272.h | 1 - include/configs/csb472.h | 1 - include/configs/gdppc440etx.h | 194 ++++++++++++++++++++ include/configs/sbc405.h | 1 - 34 files changed, 886 insertions(+), 29 deletions(-) create mode 100644 board/gdsys/gdppc440etx/Makefile create mode 100644 board/gdsys/gdppc440etx/config.mk create mode 100644 board/gdsys/gdppc440etx/gdppc440etx.c create mode 100644 board/gdsys/gdppc440etx/init.S create mode 100644 board/gdsys/gdppc440etx/u-boot.lds create mode 100644 include/configs/gdppc440etx.h

2 1

[U-Boot] [PATCH v3 1/5] OMAP3: Add common power code, README, and BeagleBoard
by Dirk Behme 27 Jan '09

27 Jan '09

Add BeagleBoard support, common power code and README. Signed-off-by: Jason Kridner <jkridner(a)beagleboard.org> Signed-off-by: Dirk Behme <dirk.behme(a)googlemail.com> --- Changes in v3: - Fix missing entry in MAKEALL This patch replaces v2 version of this patch. All other v2 version patches are still valid. MAINTAINERS | 4 MAKEALL | 28 +-- Makefile | 7 board/omap3/beagle/Makefile | 49 +++++ board/omap3/beagle/beagle.c | 90 +++++++++ board/omap3/beagle/beagle.h | 376 +++++++++++++++++++++++++++++++++++++++++ board/omap3/beagle/config.mk | 33 +++ board/omap3/beagle/u-boot.lds | 63 ++++++ board/omap3/common/Makefile | 50 +++++ board/omap3/common/power.c | 74 ++++++++ doc/README.omap3 | 72 +++++++ include/configs/omap3_beagle.h | 325 +++++++++++++++++++++++++++++++++++ 12 files changed, 1161 insertions(+), 10 deletions(-) create mode 100644 board/omap3/beagle/Makefile create mode 100644 board/omap3/beagle/beagle.c create mode 100644 board/omap3/beagle/beagle.h create mode 100644 board/omap3/beagle/config.mk create mode 100644 board/omap3/beagle/u-boot.lds create mode 100644 board/omap3/common/Makefile create mode 100644 board/omap3/common/power.c create mode 100644 doc/README.omap3 create mode 100644 include/configs/omap3_beagle.h Index: u-boot-arm/MAINTAINERS =================================================================== --- u-boot-arm.orig/MAINTAINERS +++ u-boot-arm/MAINTAINERS @@ -486,6 +486,10 @@ Rowel Atienza <rowel(a)diwalabs.com> armadillo ARM720T +Dirk Behme <dirk.behme(a)gmail.com> + + omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC) + Rishi Bhattacharya <rishi(a)ti.com> omap5912osk ARM926EJS Index: u-boot-arm/MAKEALL =================================================================== --- u-boot-arm.orig/MAKEALL +++ u-boot-arm/MAKEALL @@ -545,6 +545,13 @@ LIST_ARM11=" \ " ######################################################################### +## ARM Cortex-A8 Systems +######################################################################### +LIST_ARM_CORTEX_A8=" \ + omap3_beagle \ +" + +######################################################################### ## AT91 Systems ######################################################################### @@ -598,15 +605,16 @@ LIST_ixp=" \ ## ARM groups ######################################################################### -LIST_arm=" \ - ${LIST_SA} \ - ${LIST_ARM7} \ - ${LIST_ARM9} \ - ${LIST_ARM10} \ - ${LIST_ARM11} \ - ${LIST_at91} \ - ${LIST_pxa} \ - ${LIST_ixp} \ +LIST_arm=" \ + ${LIST_SA} \ + ${LIST_ARM7} \ + ${LIST_ARM9} \ + ${LIST_ARM10} \ + ${LIST_ARM11} \ + ${LIST_ARM_CORTEX_A8} \ + ${LIST_at91} \ + ${LIST_pxa} \ + ${LIST_ixp} \ " ######################################################################### @@ -822,7 +830,7 @@ build_target() { for arg in $@ do case "$arg" in - arm|SA|ARM7|ARM9|ARM10|ARM11|at91|ixp|pxa \ + arm|SA|ARM7|ARM9|ARM10|ARM11|ARM_CORTEX_A8|at91|ixp|pxa \ |avr32 \ |blackfin \ |coldfire \ Index: u-boot-arm/Makefile =================================================================== --- u-boot-arm.orig/Makefile +++ u-boot-arm/Makefile @@ -2905,6 +2905,13 @@ SMN42_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292 ######################################################################### +## ARM CORTEX Systems +######################################################################### + +omap3_beagle_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle omap3 omap3 + +######################################################################### ## XScale Systems ######################################################################### Index: u-boot-arm/board/omap3/beagle/Makefile =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/beagle/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := beagle.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### Index: u-boot-arm/board/omap3/beagle/beagle.c =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/beagle/beagle.c @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include "beagle.h" + +/****************************************************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/****************************************************************************** + * Routine: misc_init_r + * Description: Configure board specific parts + *****************************************************************************/ +int misc_init_r(void) +{ + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + + power_init_r(); + + /* Configure GPIOs to output */ + writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); + writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); + + /* Set GPIOs */ + writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1, + &gpio6_base->setdataout); + writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + + return 0; +} + +/****************************************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + *****************************************************************************/ +void set_muxconf_regs(void) +{ + MUX_BEAGLE(); +} Index: u-boot-arm/board/omap3/beagle/beagle.h =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/beagle/beagle.h @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2008 + * Dirk Behme <dirk.behme(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _BEAGLE_H_ +#define _BEAGLE_H_ + +const omap3_sysinfo sysinfo = { + SDP_3430_V1, + SDP_3430_V2, + DDR_STACKED, + "3530", + "OMAP3 Beagle board", +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "OneNAND", +#else + "NAND", +#endif +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_BEAGLE() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\ + MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\ + MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ + MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ + MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\ + /* USB EHCI (port 2) */\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA2*/\ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA7*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA4*/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA5*/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA6*/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA3*/\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/ +#endif Index: u-boot-arm/board/omap3/beagle/config.mk =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/beagle/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2006 +# Texas Instruments, <www.ti.com> +# +# Beagle Board uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 Index: u-boot-arm/board/omap3/beagle/u-boot.lds =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/beagle/u-boot.lds @@ -0,0 +1,63 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm_cortexa8/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } + __exidx_start = .; + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } + __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} Index: u-boot-arm/board/omap3/common/Makefile =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/common/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS-$(CONFIG_OMAP3_BEAGLE) += power.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### Index: u-boot-arm/board/omap3/common/power.c =================================================================== --- /dev/null +++ u-boot-arm/board/omap3/common/power.c @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> + +/****************************************************************************** + * Routine: power_init_r + * Description: Configure power supply + *****************************************************************************/ +void power_init_r(void) +{ + unsigned char byte; + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + /* + * Configure OMAP3 supply voltages in power management + * companion chip. + */ + + /* set VAUX3 to 2.8V */ + byte = DEV_GRP_P1; + i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEV_GRP, 1, &byte, 1); + byte = VAUX3_VSEL_28; + i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEDICATED, 1, &byte, 1); + + /* set VPLL2 to 1.8V */ + byte = DEV_GRP_ALL; + i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEV_GRP, 1, &byte, 1); + byte = VPLL2_VSEL_18; + i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEDICATED, 1, &byte, 1); + + /* set VDAC to 1.8V */ + byte = DEV_GRP_P1; + i2c_write(PWRMGT_ADDR_ID4, VDAC_DEV_GRP, 1, &byte, 1); + byte = VDAC_VSEL_18; + i2c_write(PWRMGT_ADDR_ID4, VDAC_DEDICATED, 1, &byte, 1); + + /* enable LED */ + byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON; + i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1); +} Index: u-boot-arm/doc/README.omap3 =================================================================== --- /dev/null +++ u-boot-arm/doc/README.omap3 @@ -0,0 +1,72 @@ + +Summary +======= + +This README is about U-Boot support for TI's ARM Cortex-A8 based OMAP3 [1] +family of SoCs. TI's OMAP3 SoC family contains an ARM Cortex-A8. Additionally, +some family members contain a TMS320C64x+ DSP and/or an Imagination SGX 2D/3D +graphics processor and various other standard peripherals. + +Currently the following boards are supported: + +* OMAP3530 BeagleBoard [2] + +Toolchain +========= + +While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile +with -march=armv5 to allow more compilers to work. For U-Boot code this has +no performance impact. + +Build +===== + +* BeagleBoard: + +make omap3_beagle_config +make + +Custom commands +=============== + +To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot +for OMAP3 supports custom user command + +nandecc hw/sw + +To be compatible with NAND drivers using SW ECC (e.g. kernel code) + +nandecc sw + +enables SW ECC calculation. HW ECC enabled with + +nandecc hw + +is typically used to write 2nd stage bootloader (known as 'x-loader') which is +executed by OMAP3's boot rom and therefore has to be written with HW ECC. + +For all other commands see + +help + +Acknowledgements +================ + +OMAP3 U-Boot is based on U-Boot tar ball [3] for BeagleBoard and EVM done by +several TI employees. + +Links +===== + +[1] OMAP3: + +http://www.ti.com/omap3 (high volume) and +http://www.ti.com/omap35x (broad market) + +[2] OMAP3530 BeagleBoard: + +http://beagleboard.org/ + +[3] TI OMAP3 U-Boot: + +http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz Index: u-boot-arm/include/configs/omap3_beagle.h =================================================================== --- /dev/null +++ u-boot-arm/include/configs/omap3_beagle.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <x0khasim(a)ti.com> + * + * Configuration settings for the TI OMAP3530 Beagle board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +#define SECTORSIZE 512 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CONFIG_SYS_NAND_WP + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "videomode=1024x768@60,vxres=1024,vyres=768\0" \ + "videospec=omapfb:vram:2M,vram:4M\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "video=${videospec},mode:${videomode} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "video=${videospec},mode:${videomode} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "autoscr ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmcinit; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP3 beagleboard.org # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ + /* works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ + /* load address */ + +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#ifndef __ASSEMBLY__ +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + + +#define WRITE_NAND_COMMAND(d, adr)\ + writel(d, &nand_cs_base->nand_cmd) +#define WRITE_NAND_ADDRESS(d, adr)\ + writel(d, &nand_cs_base->nand_adr) +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ + while (0) +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ + while (0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +#endif /* __CONFIG_H */

1 0

[U-Boot] [PATCH 1/3 v3] MIPS: Add VCT board series support (Part 1/3)
by Stefan Roese 27 Jan '09

27 Jan '09

Signed-off-by: Stefan Roese <sr(a)denx.de> --- v3: - Added USB EHCI support - Added performance enhanced OneNAND read support v2: - Fixed issues in u-boot.lds mentioned by Andrew Dyer board/micronas/vct/Makefile | 57 ++++++++ board/micronas/vct/bcu.h | 170 ++++++++++++++++++++++++ board/micronas/vct/config.mk | 31 +++++ board/micronas/vct/dcgu.c | 258 ++++++++++++++++++++++++++++++++++++ board/micronas/vct/dcgu.h | 179 +++++++++++++++++++++++++ board/micronas/vct/ebi.c | 48 +++++++ board/micronas/vct/ebi.h | 95 +++++++++++++ board/micronas/vct/ebi_nor_flash.c | 131 ++++++++++++++++++ board/micronas/vct/ebi_onenand.c | 198 +++++++++++++++++++++++++++ board/micronas/vct/ebi_smc911x.c | 94 +++++++++++++ 10 files changed, 1261 insertions(+), 0 deletions(-) create mode 100644 board/micronas/vct/Makefile create mode 100644 board/micronas/vct/bcu.h create mode 100644 board/micronas/vct/config.mk create mode 100644 board/micronas/vct/dcgu.c create mode 100644 board/micronas/vct/dcgu.h create mode 100644 board/micronas/vct/ebi.c create mode 100644 board/micronas/vct/ebi.h create mode 100644 board/micronas/vct/ebi_nor_flash.c create mode 100644 board/micronas/vct/ebi_onenand.c create mode 100644 board/micronas/vct/ebi_smc911x.c diff --git a/board/micronas/vct/Makefile b/board/micronas/vct/Makefile new file mode 100644 index 0000000..2737ade --- /dev/null +++ b/board/micronas/vct/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-y += ebi.o +COBJS-$(CONFIG_VCT_NOR) += ebi_nor_flash.o +COBJS-$(CONFIG_VCT_ONENAND) += ebi_onenand.o +COBJS-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o +COBJS-y += gpio.o +COBJS-y += top.o +COBJS-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o + +COBJS := $(sort $(COBJS-y)) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/micronas/vct/bcu.h b/board/micronas/vct/bcu.h new file mode 100644 index 0000000..cac31f2 --- /dev/null +++ b/board/micronas/vct/bcu.h @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BCU_H +#define _BCU_H + +enum bcu_tags { + BCU_VBV1 = 0, + BCU_VBV2 = 1, + BCU_BSS1 = 2, + BCU_BSS2 = 3, + BCU_TSD_TXT = 4, + BCU_TSD_SUBTITLES = 5, + BCU_TSD_PES_0 = 6, + BCU_TSD_PES_1 = 7, + BCU_TSD_PES_2 = 8, + BCU_TSD_PES_3 = 9, + BCU_TSIO_RECORD_0 = 10, + BCU_TSIO_RECORD_1 = 11, + BCU_TSIO_PLAYBACK_0 = 12, + BCU_TSIO_PLAYBACK_1 = 13, + BCU_SECURE_BUFFER = 14, + BCU_PCM1 = 15, + BCU_PCM2 = 16, + BCU_BSS_COPY = 17, + BCU_BSS_EXT1 = 18, + BCU_BSS_EXT2 = 19, + BCU_PCM_JINGLE = 20, + BCU_EBI_CPU_BUFFER = 21, + BCU_PCM_DELAY = 22, + BCU_FH_BUFFER_0 = 23, + BCU_FH_BUFFER_1 = 24, + BCU_TSD_SECTION_0 = 25, + BCU_TSD_SECTION_1 = 26, + BCU_TSD_SECTION_2 = 27, + BCU_TSD_SECTION_3 = 28, + BCU_TSD_SECTION_4 = 29, + BCU_TSD_SECTION_5 = 30, + BCU_TSD_SECTION_6 = 31, + BCU_TSD_SECTION_7 = 32, + BCU_TSD_SECTION_8 = 33, + BCU_TSD_SECTION_9 = 34, + BCU_TSD_SECTION_10 = 35, + BCU_TSD_SECTION_11 = 36, + BCU_TSD_SECTION_12 = 37, + BCU_TSD_SECTION_13 = 38, + BCU_TSD_SECTION_14 = 39, + BCU_TSD_SECTION_15 = 40, + BCU_TSD_SECTION_16 = 41, + BCU_TSD_SECTION_17 = 42, + BCU_TSD_SECTION_18 = 43, + BCU_TSD_SECTION_19 = 44, + BCU_TSD_SECTION_20 = 45, + BCU_TSD_SECTION_21 = 46, + BCU_TSD_SECTION_22 = 47, + BCU_TSD_SECTION_23 = 48, + BCU_TSD_SECTION_24 = 49, + BCU_TSD_SECTION_25 = 50, + BCU_TSD_SECTION_26 = 51, + BCU_TSD_SECTION_27 = 52, + BCU_TSD_SECTION_28 = 53, + BCU_TSD_SECTION_29 = 54, + BCU_TSD_SECTION_30 = 55, + BCU_TSD_SECTION_31 = 56, + BCU_TSD_SECTION_32 = 57, + BCU_TSD_SECTION_33 = 58, + BCU_TSD_SECTION_34 = 59, + BCU_TSD_SECTION_35 = 60, + BCU_TSD_SECTION_36 = 61, + BCU_TSD_SECTION_37 = 62, + BCU_TSD_SECTION_38 = 63, + BCU_TSD_SECTION_39 = 64, + BCU_TSD_SECTION_40 = 65, + BCU_TSD_SECTION_41 = 66, + BCU_TSD_SECTION_42 = 67, + BCU_TSD_SECTION_43 = 68, + BCU_TSD_SECTION_44 = 69, + BCU_TSD_SECTION_45 = 70, + BCU_TSD_SECTION_46 = 71, + BCU_TSD_SECTION_47 = 72, + BCU_TSD_SECTION_48 = 73, + BCU_TSD_SECTION_49 = 74, + BCU_TSD_SECTION_50 = 75, + BCU_TSD_SECTION_51 = 76, + BCU_TSD_SECTION_52 = 77, + BCU_TSD_SECTION_53 = 78, + BCU_TSIO_RECORD_2 = 79, + BCU_TSIO_RECORD_3 = 80, + BCU_TSIO_RECORD_4 = 81, + BCU_TSIO_RECORD_5 = 82, + BCU_TSIO_RECORD_6 = 83, + BCU_TSIO_RECORD_7 = 84, + BCU_TSIO_RECORD_8 = 85, + BCU_TSIO_RECORD_9 = 86, + BCU_PCM_DELAY_LINEAR = 87, + BCU_VD_MASTER_USER_DATA = 88, + BCU_VD_SLAVE_USER_DATA = 89, + BCU_VD_MASTER_REF0 = 90, + BCU_VD_MASTER_REF1 = 91, + BCU_VD_SLAVE_REF0 = 92, + BCU_VD_SLAVE_REF1 = 93, + BCU_VD_MASTER_DISP0_Y = 94, + BCU_VD_MASTER_DISP1_Y = 95, + BCU_VD_MASTER_DISP2_Y = 96, + BCU_VD_MASTER_DISP0_C = 97, + BCU_VD_MASTER_DISP1_C = 98, + BCU_VD_MASTER_DISP2_C = 99, + BCU_VD_SLAVE_DISP0_Y = 100, + BCU_VD_SLAVE_DISP1_Y = 101, + BCU_VD_SLAVE_DISP2_Y = 102, + BCU_VD_SLAVE_DISP0_C = 103, + BCU_VD_SLAVE_DISP1_C = 104, + BCU_VD_SLAVE_DISP2_C = 105, + BCU_CLUT_BUFFER_0 = 106, + BCU_CLUT_BUFFER_1 = 107, + BCU_OSD_FRAME_BUFFER_0 = 108, + BCU_OSD_FRAME_BUFFER_1 = 109, + BCU_GRAPHIC_FRAME_BUFFER0 = 110, + BCU_GRAPHIC_FRAME_BUFFER1 = 111, + BCU_DVP_VBI_REINSERTION = 112, + BCU_DVP_OSD_FRAME_BUFFER0 = 113, + BCU_DVP_OSD_FRAME_BUFFER1 = 114, + BCU_GAI_BUFFER = 115, + BCU_GA_SRC_BUFFER_0 = 116, + BCU_GA_SRC_BUFFER_1 = 117, + BCU_USB_BUFFER_0 = 118, + BCU_USB_BUFFER_1 = 119, + BCU_FE_3DCOMB_0 = 120, + BCU_FE_3DCOMB_1 = 121, + BCU_FE_3DCOMB_2 = 122, + BCU_FE_3DCOMB_3 = 123, + BCU_TNR_BUFFER_0 = 124, + BCU_TNR_BUFFER_1 = 125, + BCU_TNR_BUFFER_2 = 126, + BCU_MVAL_BUFFER = 127, + BCU_RC_BUFFER_0 = 128, + BCU_RC_BUFFER_1 = 129, + BCU_RC_BUFFER_2 = 130, + BCU_RC_BUFFER_3 = 131, + BCU_PIP_BUFFER_0 = 132, + BCU_PIP_BUFFER_1 = 133, + BCU_PIP_BUFFER_2 = 134, + BCU_PIP_BUFFER_3 = 135, + BCU_EWARP_BUFFER = 136, + BCU_OSD_BUFFER_0 = 137, + BCU_OSD_BUFFER_1 = 138, + BCU_GLOBAL_BUFFER_0 = 139, + BCU_GLOBAL_BUFFER_1 = 140, + BCU_MAX = 141 +}; + +#endif /* _BCU_H */ diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk new file mode 100644 index 0000000..2a71dad --- /dev/null +++ b/board/micronas/vct/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# vct_xxx boards with MIPS 4Kc CPU core +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0x87000000 +endif diff --git a/board/micronas/vct/dcgu.c b/board/micronas/vct/dcgu.c new file mode 100644 index 0000000..b2e86b7 --- /dev/null +++ b/board/micronas/vct/dcgu.c @@ -0,0 +1,258 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * Original Author Guenter Gebhardt + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/errno.h> + +#include "vct.h" + +int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup) +{ + u32 enable; + union dcgu_clk_en1 en1; + union dcgu_clk_en2 en2; + + switch (setup) { + case DCGU_SWITCH_ON: + enable = 1; + break; + case DCGU_SWITCH_OFF: + enable = 0; + break; + default: + printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__, + setup); + return -EINVAL; + } + + if (module == DCGU_HW_MODULE_CPU) + en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); + else + en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); + + switch (module) { + case DCGU_HW_MODULE_MSMC: + en1.bits.en_clkmsmc = enable; + break; + case DCGU_HW_MODULE_SSI_S: + en1.bits.en_clkssi_s = enable; + break; + case DCGU_HW_MODULE_SSI_M: + en1.bits.en_clkssi_m = enable; + break; + case DCGU_HW_MODULE_SMC: + en1.bits.en_clksmc = enable; + break; + case DCGU_HW_MODULE_EBI: + en1.bits.en_clkebi = enable; + break; + case DCGU_HW_MODULE_USB_PLL: + en1.bits.en_usbpll = enable; + break; + case DCGU_HW_MODULE_USB_60: + en1.bits.en_clkusb60 = enable; + break; + case DCGU_HW_MODULE_USB_24: + en1.bits.en_clkusb24 = enable; + break; + case DCGU_HW_MODULE_UART_2: + en1.bits.en_clkuart2 = enable; + break; + case DCGU_HW_MODULE_UART_1: + en1.bits.en_clkuart1 = enable; + break; + case DCGU_HW_MODULE_PERI: + en1.bits.en_clkperi20 = enable; + break; + case DCGU_HW_MODULE_CPU: + en2.bits.en_clkcpu = enable; + break; + case DCGU_HW_MODULE_I2S: + en1.bits.en_clk_i2s_dly = enable; + break; + case DCGU_HW_MODULE_ABP_SCC: + en1.bits.en_clk_scc_abp = enable; + break; + case DCGU_HW_MODULE_SPDIF: + en1.bits.en_clk_dtv_spdo = enable; + break; + case DCGU_HW_MODULE_AD: + en1.bits.en_clkad = enable; + break; + case DCGU_HW_MODULE_MVD: + en1.bits.en_clkmvd = enable; + break; + case DCGU_HW_MODULE_TSD: + en1.bits.en_clktsd = enable; + break; + case DCGU_HW_MODULE_GA: + en1.bits.en_clkga = enable; + break; + case DCGU_HW_MODULE_DVP: + en1.bits.en_clkdvp = enable; + break; + case DCGU_HW_MODULE_MR2: + en1.bits.en_clkmr2 = enable; + break; + case DCGU_HW_MODULE_MR1: + en1.bits.en_clkmr1 = enable; + break; + default: + printf("%s:%i:Invalid hardware module: %i\n", __FILE__, + __LINE__, module); + return -EINVAL; + } + + /* + * The reg_read() following the reg_write() below forces the write to + * be really done on the bus. + * Otherwise the clock may not be switched on when this API function + * returns, which may cause an bus error if a registers of the hardware + * module connected to the clock is accessed. + */ + if (module == DCGU_HW_MODULE_CPU) { + reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg); + en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); + } else { + reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg); + en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); + } + + return 0; +} + +int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup) +{ + union dcgu_reset_unit1 val; + u32 enable; + + switch (setup) { + case DCGU_SWITCH_ON: + enable = 1; + break; + case DCGU_SWITCH_OFF: + enable = 0; + break; + default: + printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__, + setup); + return -EINVAL; + } + + val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE)); + switch (module) { + case DCGU_HW_MODULE_MSMC: + val.bits.swreset_clkmsmc = enable; + break; + case DCGU_HW_MODULE_SSI_S: + val.bits.swreset_clkssi_s = enable; + break; + case DCGU_HW_MODULE_SSI_M: + val.bits.swreset_clkssi_m = enable; + break; + case DCGU_HW_MODULE_SMC: + val.bits.swreset_clksmc = enable; + break; + case DCGU_HW_MODULE_EBI: + val.bits.swreset_clkebi = enable; + break; + case DCGU_HW_MODULE_USB_60: + val.bits.swreset_clkusb60 = enable; + break; + case DCGU_HW_MODULE_USB_24: + val.bits.swreset_clkusb24 = enable; + break; + case DCGU_HW_MODULE_UART_2: + val.bits.swreset_clkuart2 = enable; + break; + case DCGU_HW_MODULE_UART_1: + val.bits.swreset_clkuart1 = enable; + break; + case DCGU_HW_MODULE_PWM: + val.bits.swreset_pwm = enable; + break; + case DCGU_HW_MODULE_GPT: + val.bits.swreset_gpt = enable; + break; + case DCGU_HW_MODULE_I2C2: + val.bits.swreset_i2c2 = enable; + break; + case DCGU_HW_MODULE_I2C1: + val.bits.swreset_i2c1 = enable; + break; + case DCGU_HW_MODULE_GPIO2: + val.bits.swreset_gpio2 = enable; + break; + case DCGU_HW_MODULE_GPIO1: + val.bits.swreset_gpio1 = enable; + break; + case DCGU_HW_MODULE_CPU: + val.bits.swreset_clkcpu = enable; + break; + case DCGU_HW_MODULE_I2S: + val.bits.swreset_clk_i2s_dly = enable; + break; + case DCGU_HW_MODULE_ABP_SCC: + val.bits.swreset_clk_scc_abp = enable; + break; + case DCGU_HW_MODULE_SPDIF: + val.bits.swreset_clk_dtv_spdo = enable; + break; + case DCGU_HW_MODULE_AD: + val.bits.swreset_clkad = enable; + break; + case DCGU_HW_MODULE_MVD: + val.bits.swreset_clkmvd = enable; + break; + case DCGU_HW_MODULE_TSD: + val.bits.swreset_clktsd = enable; + break; + case DCGU_HW_MODULE_TSIO: + val.bits.swreset_clktsio = enable; + break; + case DCGU_HW_MODULE_GA: + val.bits.swreset_clkga = enable; + break; + case DCGU_HW_MODULE_MPC: + val.bits.swreset_clkmpc = enable; + break; + case DCGU_HW_MODULE_CVE: + val.bits.swreset_clkcve = enable; + break; + case DCGU_HW_MODULE_DVP: + val.bits.swreset_clkdvp = enable; + break; + case DCGU_HW_MODULE_MR2: + val.bits.swreset_clkmr2 = enable; + break; + case DCGU_HW_MODULE_MR1: + val.bits.swreset_clkmr1 = enable; + break; + default: + printf("%s:%i:Invalid hardware module: %i\n", __FILE__, + __LINE__, module); + return -EINVAL; + } + reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg); + + return 0; +} diff --git a/board/micronas/vct/dcgu.h b/board/micronas/vct/dcgu.h new file mode 100644 index 0000000..ca129c0 --- /dev/null +++ b/board/micronas/vct/dcgu.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DCGU_H +#define _DCGU_H + +enum dcgu_switch { + DCGU_SWITCH_OFF, /* Switch off */ + DCGU_SWITCH_ON /* Switch on */ +}; + +enum dcgu_hw_module { + DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */ + + DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */ + DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/ + + DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */ + DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */ + DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */ + DCGU_HW_MODULE_DVP, /* Selects dig video processing module */ + DCGU_HW_MODULE_CVE, /* Selects color video encoder module */ + DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */ + + DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */ + DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */ + + DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */ + DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */ + + DCGU_HW_MODULE_UART_1, /* Selects first UART module */ + DCGU_HW_MODULE_UART_2, /* Selects second UART module */ + + DCGU_HW_MODULE_AD, /* Selects audio decoder module */ + DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */ + DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/ + DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */ + + DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/ + DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */ + DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */ + + DCGU_HW_MODULE_USBH, /* Selects USB hub module */ + DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */ + DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */ + DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */ + + DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/ + DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/ + DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/ + DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */ + DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */ + DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */ + + DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/ + DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/ + + DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */ + DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */ + + DCGU_HW_MODULE_COM, /* Selects COM unit module */ + DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */ + DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */ + + DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/ + DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */ + DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */ + DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */ + + DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */ + DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */ + DCGU_HW_MODULE_SRAM, /* Selects SRAM module */ + DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/ + DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */ + DCGU_HW_MODULE_SCC, /* Selects SCC module */ + DCGU_HW_MODULE_MM, /* Selects Memory Manager module */ + DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */ + DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */ + DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */ + DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */ + DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/ +}; + +union dcgu_clk_en1 { + u32 reg; + struct { + u32 res1:8; /* reserved */ + u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */ + u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */ + u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */ + u32 en_clksmc:1; /* Enable bit for clksmc (#) */ + u32 en_clkebi:1; /* Enable bit for clkebi (#) */ + u32 en_usbpll:1; /* Enable bit for the USB PLL */ + u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */ + u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */ + u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */ + u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */ + u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */ + u32 res2:3; /* reserved */ + u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */ + u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */ + u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */ + u32 en_clkad:1; /* Enable bit for clkad (#) */ + u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */ + u32 en_clktsd:1; /* Enable bit for clktsd (#) */ + u32 en_clkga:1; /* Enable bit for clkga (#) */ + u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */ + u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */ + u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */ + } bits; +}; + +union dcgu_clk_en2 { + u32 reg; + struct { + u32 res1:31; /* reserved */ + u32 en_clkcpu:1; /* Enable bit for clkcpu */ + } bits; +}; + +union dcgu_reset_unit1 { + u32 reg; + struct { + u32 res1:1; + u32 swreset_clkmsmc:1; + u32 swreset_clkssi_s:1; + u32 swreset_clkssi_m:1; + u32 swreset_clksmc:1; + u32 swreset_clkebi:1; + u32 swreset_clkusb60:1; + u32 swreset_clkusb24:1; + u32 swreset_clkuart2:1; + u32 swreset_clkuart1:1; + u32 swreset_pwm:1; + u32 swreset_gpt:1; + u32 swreset_i2c2:1; + u32 swreset_i2c1:1; + u32 swreset_gpio2:1; + u32 swreset_gpio1:1; + u32 swreset_clkcpu:1; + u32 res2:2; + u32 swreset_clk_i2s_dly:1; + u32 swreset_clk_scc_abp:1; + u32 swreset_clk_dtv_spdo:1; + u32 swreset_clkad:1; + u32 swreset_clkmvd:1; + u32 swreset_clktsd:1; + u32 swreset_clktsio:1; + u32 swreset_clkga:1; + u32 swreset_clkmpc:1; + u32 swreset_clkcve:1; + u32 swreset_clkdvp:1; + u32 swreset_clkmr2:1; + u32 swreset_clkmr1:1; + } bits; +}; + +int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup); +int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup); + +#endif /* _DCGU_H */ diff --git a/board/micronas/vct/ebi.c b/board/micronas/vct/ebi.c new file mode 100644 index 0000000..8e93f69 --- /dev/null +++ b/board/micronas/vct/ebi.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +int ebi_initialize(void) +{ +#if defined(CONFIG_VCT_NOR) + if (ebi_init_nor_flash()) + return -1; +#endif + +#if defined(CONFIG_VCT_ONENAND) + if (ebi_init_onenand()) + return -1; +#endif + +#if defined(CONFIG_DRIVER_SMC911X) + if (ebi_init_smc911x()) + return -1; +#endif + + reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100); + + ebi_wait(); + + return 0; +} diff --git a/board/micronas/vct/ebi.h b/board/micronas/vct/ebi.h new file mode 100644 index 0000000..69456bd --- /dev/null +++ b/board/micronas/vct/ebi.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __EBI__ +#define __EBI__ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +#define EXT_DEVICE_CHANNEL_3 (0x30000000) +#define EXT_DEVICE_CHANNEL_2 (0x20000000) +#define EXT_DEVICE_CHANNEL_1 (0x10000000) +#define EXT_CPU_ACCESS_ACTIVE (0x00000001) +#define EXT_DMA_ACCESS_ACTIVE (1 << 14) +#define EXT_CPU_IORDY_SL (0x00000001) + +#define EBI_CPU_WRITE (1 << 31) +#define EBI_CPU_ID_SHIFT (28) +#define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT) + +/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */ +#define ADDR_LATCH_ENABLE 0 +#define ADDR_ACTIVATION 4 +#define CHIP_SELECT_START 8 +#define OUTPUT_ENABLE_START 12 +#define WAIT_TIME 28 +#define READ_DURATION 20 + +/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */ +#define OUTPUT_ENABLE_END 0 +#define CHIP_SELECT_END 4 +#define ADDR_DEACTIVATION 8 +#define RECOVER_TIME 12 +#define ACK_TIME 20 + +/* various bits in configuration register EBI_DEV[01]_CONFIG1 */ +#define EBI_EXTERNAL_DATA_8 (1 << 8) +#define EBI_EXT_ADDR_SHIFT (1 << 22) +#define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT +#define EBI_CHIP_SELECT_1 0x2 +#define EBI_CHIP_SELECT_2 0x4 +#define EBI_BUSY_EN_RD (1 << 12) +#define DIR_ACCESS_WRITE (1 << 20) +#define DIR_ACCESS_MASK (1 << 20) + +/* various bits in configuration register EBI_DEV[01]_CONFIG2 */ +#define ADDRESS_INCREMENT_ON 0x0 +#define ADDRESS_INCREMENT_OFF 0x100 +#define QUEUE_LENGTH_1 0x40 +#define QUEUE_LENGTH_2 0x80 +#define QUEUE_LENGTH_3 0xC0 +#define QUEUE_LENGTH_4 0 +#define CPU_TRANSFER_SIZE_32 0 +#define CPU_TRANSFER_SIZE_16 0x10 +#define CPU_TRANSFER_SIZE_8 0x20 +#define READ_ENDIANNESS_ABCD 0 +#define READ_ENDIANNESS_DCBA 0x4 +#define READ_ENDIANNESS_BADC 0x8 +#define READ_ENDIANNESS_CDAB 0xC +#define WRITE_ENDIANNESS_ABCD 0 +#define WRITE_ENDIANNESS_DCBA 0x1 +#define WRITE_ENDIANNESS_BADC 0x2 +#define WRITE_ENDIANNESS_CDAB 0x3 + +/* various bits in configuration register EBI_CTRL_SIG_ACTLV */ +#define IORDY_ACTIVELEVEL_HIGH (1 << 14) +#define ALE_ACTIVELEVEL_HIGH (1 << 8) + +/* bits in register EBI_SIG_LEVEL */ +#define IORDY_LEVEL_MASK 1 + +static inline void ebi_wait(void) +{ + while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE) + ; /* wait */ +} + +#endif diff --git a/board/micronas/vct/ebi_nor_flash.c b/board/micronas/vct/ebi_nor_flash.c new file mode 100644 index 0000000..ae87643 --- /dev/null +++ b/board/micronas/vct/ebi_nor_flash.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +static u32 ebi_read(u32 addr) +{ + addr &= ~0xFC000000; + + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr); + ebi_wait(); + + return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); +} + +static int ebi_write_u16(u32 addr, u32 data, int fetchIO) +{ + u32 val = (data << 16); + + addr &= ~0xFC000000; + + ebi_wait(); + + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | addr); + ebi_wait(); + + if (fetchIO) { + u32 counter = 0; + while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) { + if (counter++ > 0xFFFFFF) + return 1; + } + } + + return 0; +} + +static u16 ebi_read_u16(u32 addr) +{ + return ((ebi_read(addr) >> 16) & 0xFFFF); +} + +static u8 ebi_read_u8(u32 addr) +{ + u32 val = ebi_read(addr) >> 16; + + if (addr & 0x1) + return val & 0xff; + else + return (val >> 8) & 0xff; +} + +/* + * EBI initialization for NOR FLASH access + */ +int ebi_init_nor_flash(void) +{ + reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); + + reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002); + reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); + + reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113); + reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000); + reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113); + reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011); + reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); + + return 0; +} + +/* + * Accessor functions replacing the "weak" functions in + * drivers/mtd/cfi_flash.c + */ +void flash_write8(u8 value, void *addr) +{ + ebi_write_u16((u32)addr, value, 0); +} + +void flash_write16(u16 value, void *addr) +{ + ebi_write_u16((u32)addr, value, 0); +} + +u8 flash_read8(void *addr) +{ + return ebi_read_u8((u32)addr); +} + +u16 flash_read16(void *addr) +{ + return ebi_read_u16((u32)addr); +} + +u32 flash_read32(void *addr) +{ + return ((u32)ebi_read_u16((u32)addr) << 16) | + ebi_read_u16((u32)addr + 2); +} + +void *board_flash_read_memcpy(void *dest, const void *src, size_t count) +{ + u16 *tmp = (u16 *)dest, *s = (u16 *)src; + int i; + + for (i = 0; i < count; i += 2) + *tmp++ = flash_read16(s++); + + return dest; +} diff --git a/board/micronas/vct/ebi_onenand.c b/board/micronas/vct/ebi_onenand.c new file mode 100644 index 0000000..522b88f --- /dev/null +++ b/board/micronas/vct/ebi_onenand.c @@ -0,0 +1,198 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/onenand.h> +#include "vct.h" + +#define BURST_SIZE_WORDS 4 + +static u16 ebi_nand_read_word(void __iomem *addr) +{ + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr)); + ebi_wait(); + + return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16; +} + +static void ebi_nand_write_word(u16 data, void __iomem * addr) +{ + ebi_wait(); + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16)); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr); + ebi_wait(); +} + +/* + * EBI initialization for OneNAND FLASH access + */ +int ebi_init_onenand(void) +{ + reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); + + reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002); + reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); + + reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002); + reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */ + + reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000); + reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000); + reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223); + reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220); + reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000); + reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000); + reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000); + reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200); + + reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); + reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF); + + reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000); + reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF); + + /* prepare DMA configuration for EBI */ + reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00); + + /* READ only no byte order change, TAG 1 used */ + reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004); + + reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */ + reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1); + reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2); + reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3); + + return 0; +} + +static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len) +{ + void *ret = dst; + u16 *d = dst; + u16 *s = (u16 *)src; + + len >>= 1; + while (len-- > 0) + *d++ = ebi_nand_read_word(s++); + + return ret; +} + +static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len) +{ + void *ret = dst; + u32 *d = (u32 *)dst; + u32 s = (u32)src; + u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int); + u32 n_blocks = len / bytes_per_block; + u32 block = 0; + u32 burst_word; + + for (block = 0; block < n_blocks; block++) { + /* Trigger read channel 3 */ + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + (EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block)))); + /* Poll status to see whether read has finished */ + ebi_wait(); + + /* Squirrel the data away in a safe place */ + for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++) + *d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); + } + + return ret; +} + +static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len) +{ + void *ret = dst; + u16 *d = dst; + u16 *s = (u16 *)src; + + len >>= 1; + while (len-- > 0) + ebi_nand_write_word(*s++, d++); + + return ret; +} + +static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) +{ + struct onenand_chip *this = mtd->priv; + + if (ONENAND_CURRENT_BUFFERRAM(this)) { + if (area == ONENAND_DATARAM) + return mtd->writesize; + if (area == ONENAND_SPARERAM) + return mtd->oobsize; + } + + return 0; +} + +static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area, + unsigned char *buffer, int offset, + size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + bufferram += onenand_bufferram_offset(mtd, area); + + if (count < 4) + memcpy_16_from_onenand(buffer, bufferram + offset, count); + else + memcpy_32_from_onenand(buffer, bufferram + offset, count); + + return 0; +} + +static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, + const unsigned char *buffer, int offset, + size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + bufferram += onenand_bufferram_offset(mtd, area); + + memcpy_16_to_onenand(bufferram + offset, buffer, count); + + return 0; +} + +void onenand_board_init(struct mtd_info *mtd) +{ + struct onenand_chip *chip = mtd->priv; + + /* + * Insert board specific OneNAND access functions + */ + chip->read_word = ebi_nand_read_word; + chip->write_word = ebi_nand_write_word; + + chip->read_bufferram = ebi_read_bufferram; + chip->read_spareram = ebi_read_bufferram; + chip->write_bufferram = ebi_write_bufferram; +} diff --git a/board/micronas/vct/ebi_smc911x.c b/board/micronas/vct/ebi_smc911x.c new file mode 100644 index 0000000..e1b67a0 --- /dev/null +++ b/board/micronas/vct/ebi_smc911x.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +/* + * EBI initialization for SMC911x access + */ +int ebi_init_smc911x(void) +{ + reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020); + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); + + reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100); + reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111); + + reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000); + reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF); + + reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100); + reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110); + + return 0; +} + +/* + * Accessor functions replacing the "weak" functions in + * drivers/net/smc911x.c + */ +u32 smc911x_reg_read(u32 addr) +{ + volatile u32 data; + + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); + ebi_wait(); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); + ebi_wait(); + data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); + + return (data); +} + +void smc911x_reg_write(u32 addr, u32 data) +{ + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); + ebi_wait(); + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr); + ebi_wait(); +} + +void pkt_data_push(u32 addr, u32 data) +{ + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A); + ebi_wait(); + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr); + ebi_wait(); + + return; +} + +u32 pkt_data_pull(u32 addr) +{ + volatile u32 data; + + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A); + ebi_wait(); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); + ebi_wait(); + data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); + + return data; +} -- 1.6.1

3 4

[U-Boot] [PATCH] ne2000: take MAC address from config if available
by Daniel Mack 27 Jan '09

27 Jan '09

Hi, the board I'm currently working on has an ASIX AX88796 NE2000 clone but no EEPROM attached to it. Hence, the get_prom() routine returns zeros only so the system won't work. This patch takes the MAC address given by CONFIG_ETHADDR and translates it to numeric values. This could probably go to some other, more generic place, but I didn't find any. Best regards, Daniel diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c index f93f932..f8480a3 100644 --- a/drivers/net/ne2000_base.c +++ b/drivers/net/ne2000_base.c @@ -693,6 +693,7 @@ int eth_init(bd_t *bd) { nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE; +#ifndef CONFIG_ETHADDR r = get_prom(dev_addr, nic.base); if (!r) return -1; @@ -703,6 +704,20 @@ int eth_init(bd_t *bd) { dev_addr[4], dev_addr[5]) ; PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr); setenv ("ethaddr", ethaddr); +#else /* CONFIG_ETHADDR */ +#define STR(X) #X +#define XSTR(X) STR(X) + strncpy(ethaddr, XSTR(CONFIG_ETHADDR), sizeof(ethaddr)); + + /* replace all colons by NULL characters */ + for (r = 0; r < strlen(ethaddr); r++) + if (ethaddr[r] == ':') + ethaddr[r] = '\0'; + + /* convert the string notation */ + for (r = 0; r < 6; r++) + dev_addr[r] = simple_strtol(ethaddr + (r * 3), NULL, 16); +#endif nic.data = nic.base + DP_DATA; nic.tx_buf1 = START_PG;

3 7

[U-Boot] [PATCH v2] Remove static type from gunzip_bmp()
by Mark Jackson 27 Jan '09

27 Jan '09

The current bmp routines support gzipped files, but compilation fails (under AVR32) due to the gunzip_bmp() function being defined as static. This patch fixes this problem. Signed-off-by: Mark Jackson <mpfj(a)mimc.co.uk> --- common/cmd_bmp.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index bc08b26..084ef98 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -46,7 +46,7 @@ int gunzip(void *, int, unsigned char *, unsigned long *); * didn't contain a valid BMP signature. */ #ifdef CONFIG_VIDEO_BMP_GZIP -static bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) +bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) { void *dst; unsigned long len; @@ -85,7 +85,7 @@ static bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) return bmp; } #else -static bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) +bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) { return NULL; }

2 1

[U-Boot] [PATCH] Remove static type from gunzip_bmp()
by Mark Jackson 27 Jan '09

27 Jan '09

THe current bmp routines support gzipped files, but compilation fails due to the gunzip_bmp() function being defined as static. This patch fixes this problem. Signed-off-by: Mark Jackson <mpfj(a)mimc.co.uk> --- common/cmd_bmp.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index bc08b26..2104e59 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -46,7 +46,7 @@ int gunzip(void *, int, unsigned char *, unsigned long *); * didn't contain a valid BMP signature. */ #ifdef CONFIG_VIDEO_BMP_GZIP -static bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) +bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) { void *dst; unsigned long len;

2 1

[U-Boot] [PATCH] Add 16bpp BMP support
by Mark Jackson 27 Jan '09

27 Jan '09

This patch adds 16bpp BMP support to the common lcd code. At the moment it's only been tested on the MIMC200 AVR32 board, but the hooks are in place to extend this to other platforms. Signed-off-by: Mark Jackson <mpfj(a)mimc.co.uk> --- common/lcd.c | 54 ++++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 44 insertions(+), 10 deletions(-) diff --git a/common/lcd.c b/common/lcd.c index ae79051..93dbd3c 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -84,7 +84,7 @@ extern void lcd_enable (void); static void *lcd_logo (void); -#if LCD_BPP == LCD_COLOR8 +#if (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) extern void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); #endif @@ -656,7 +656,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) bpix = NBITS(panel_info.vl_bpix); - if ((bpix != 1) && (bpix != 8)) { + if ((bpix != 1) && (bpix != 8) && (bpix != 16)) { printf ("Error: %d bit/pixel mode not supported by U-Boot\n", bpix); return 1; @@ -738,17 +738,51 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset); fb = (uchar *) (lcd_base + (y + height - 1) * lcd_line_length + x); - for (i = 0; i < height; ++i) { - WATCHDOG_RESET(); - for (j = 0; j < width ; j++) + + switch (bpix) { + case 1: /* pass through */ + case 8: + for (i = 0; i < height; ++i) { + WATCHDOG_RESET(); + for (j = 0; j < width ; j++) #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD) - *(fb++) = *(bmap++); + *(fb++) = *(bmap++); #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200) - *(fb++)=255-*(bmap++); + *(fb++)=255-*(bmap++); #endif - bmap += (width - padded_line); - fb -= (width + lcd_line_length); - } + bmap += (width - padded_line); + fb -= (width + lcd_line_length); + } + break; + + case 16: + for (i = 0; i < height; ++i) { + WATCHDOG_RESET(); + for (j = 0; j < width; j++) { +#if defined(CONFIG_PXA250) +#error 16 bpp support not added for PXA250 +#elif defined(CONFIG_ATMEL_LCD) +#if defined(CONFIG_ATMEL_LCD_BGR555) + *(fb++) = ((bmap[0] & 0x1f) << 2) | (bmap[1] & 0x03); + *(fb++) = (bmap[0] & 0xe0) | ((bmap[1] & 0x7c) >> 2); + bmap += 2; +#else + *(fb++) = *(bmap++); + *(fb++) = *(bmap++); +#endif +#elif defined(CONFIG_MPC823) +#error 16 bpp support not added for MPC823 +#elif defined(CONFIG_MCC200) +#error 16 bpp support not added for MCC200 +#endif + } + bmap += (padded_line - width) * 2; + fb -= (width * 2 + lcd_line_length); + } + break; + default: + break; + }; return (0); }

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[U-Boot] SST39VF1601 flash driver
by Jerry Zhang 27 Jan '09

27 Jan '09

hello, all! I am porting u-boot to my board. I found it is difficult for me to write the flash driver ( flash.c) of SST39VF1601 by myself. Has anyone ever written this driver? Would you please give me a guide? Thanks in advance! Jerry.Zhang

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