January 2009 - U-Boot

[U-Boot] [PATCH] ppc4xx: Remove compilation warning in gdppc440etc.c
by Stefan Roese 26 Jan '09

26 Jan '09

Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/gdsys/gdppc440etx/gdppc440etx.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index e1890ff..a661057 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -145,8 +145,6 @@ int misc_init_r(void) int checkboard(void) { char *s = getenv("serial#"); - u8 rev; - u8 val; printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module"); -- 1.6.1

1 0

[U-Boot] [PATCH] ppc4xx: Remove CONFIG_SYS_IGNORE_405_UART_ERRATA_59 from config files
by Matthias Fuchs 26 Jan '09

26 Jan '09

Lot's of 405 board config files use CONFIG_SYS_IGNORE_405_UART_ERRATA_59. Either they define or undef it. Because it's not used in any source files this patch removes any references to it. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- include/configs/ASH405.h | 1 - include/configs/CATcenter.h | 1 - include/configs/CMS700.h | 1 - include/configs/CPCI2DP.h | 1 - include/configs/CPCI405.h | 1 - include/configs/CPCI4052.h | 1 - include/configs/CPCI405AB.h | 1 - include/configs/CPCI405DT.h | 1 - include/configs/DP405.h | 1 - include/configs/G2000.h | 1 - include/configs/HH405.h | 1 - include/configs/HUB405.h | 1 - include/configs/OCRTC.h | 1 - include/configs/ORSG.h | 1 - include/configs/PCI405.h | 1 - include/configs/PLU405.h | 1 - include/configs/PMC405.h | 1 - include/configs/PPChameleonEVB.h | 1 - include/configs/VOH405.h | 1 - include/configs/VOM405.h | 1 - include/configs/WUH405.h | 1 - include/configs/csb272.h | 1 - include/configs/csb472.h | 1 - include/configs/sbc405.h | 1 - 24 files changed, 0 insertions(+), 24 deletions(-) diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index a694083..70a720b 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index a44f3e1..062bbe4 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -184,7 +184,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index d0e2464..02fdd6c 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 3287734..5c88c47 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -112,7 +112,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 89ba139..f032a8d 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index d0b4d11..2677cfb 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -134,7 +134,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 69c8c6e..aae0d73 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -133,7 +133,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index be8c238..2333208 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -135,7 +135,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 884f3fe..187547d 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -117,7 +117,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h index d299044..37e1eff 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -152,7 +152,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 80e59bb..246416e 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -177,7 +177,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index b3c7046..87e5ddd 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -118,7 +118,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 32814d4..2591f1d 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -105,7 +105,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 58e9328..13d6e04 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -105,7 +105,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index d0a37d7..4e39799 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -111,7 +111,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 11ce008..07eeac1 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -138,7 +138,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 8d07d77..43e9532 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -132,7 +132,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 09a9641..45e5de3 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -192,7 +192,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 10ef620..6edb232 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -134,7 +134,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 90efc6d..db00c65 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -121,7 +121,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 01cdf3a..4ebe33b 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -122,7 +122,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 874f2c0..5d3b09a 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -162,7 +162,6 @@ * */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ -#undef CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #undef CONFIG_SYS_BASE_BAUD #define CONFIG_BAUDRATE 38400 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 2e30e69..a33efde 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -161,7 +161,6 @@ * */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */ -#undef CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_BAUDRATE 38400 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index c156820..7197aaf 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -147,7 +147,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ -- 1.5.6.3

2 1

[U-Boot] [PATCH 00/15] i386 Modifications and new board (eNET)
by Graeme Russ 26 Jan '09

26 Jan '09

The following patch series follows from a previous set of preliminary i386 patches (see http://lists.denx.de/pipermail/u-boot/2008-November/043681.html) This set of patches adds supports for the board I am developing with (eNET) and makes a few changes to the arrangement of the i386 code in U-Boot. These changes are intended to provide better hooks for cpu and board specific functionality. This patch series includes support for the SC520 MMCR reset functionality which was implied by the configuration options but never implemented. A couple of minor tidy-ups have been performed (moved ali512x.h to a more logical location, changed the configuration settings to CONFIG_SYS_ for example). This patch set, however, is not a full scale style cleanup. There may be places where non-conforming style has been used - For the time being, I am focusing on getting code into the right place. A more complete coding style cleanup will follow. Regards, Graeme

4 33

[U-Boot] DM9161 AT91SAM9263
by Josef Baumann 26 Jan '09

26 Jan '09

Hi, i have a little bit of trouble with U-Boot and ATMEL AT91SAM9263. I made a new board with AT91SAM9263 and DM9161. Starting U-Boot and Linux is ok. TFTP on U-Boot is working well. The only problem I have, is that the system starts in half duplex mode. How can I change this behavior? best regards Josef Baumann Prime Mess- und Regeltechnik Prinz-Eugen-Str. 65 94034 Passau Tel.: +49-851-41041 Fax.: +49-851-41042 web: www.prime-micro.de

1 0

[U-Boot] [PATCH v6] ppc4xx: Add GDsys PowerPC 440 ETX board support.
by Dirk Eibach 26 Jan '09

26 Jan '09

Board support for the Guntermann & Drunck PowerPC 440 ETX module. Based on the AMCC Yosemite board support by Stefan Roese. Signed-off-by: Dirk Eibach <eibach(a)gdsys.de> --- Depends on [PATCH v3] ppc4xx: Improve DDR autodetect More whitespace rework. checkpatch does not find tab after define. Grrr. MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/gdsys/gdppc440etx/Makefile | 51 +++++ board/gdsys/gdppc440etx/config.mk | 44 +++++ board/gdsys/gdppc440etx/gdppc440etx.c | 325 +++++++++++++++++++++++++++++++++ board/gdsys/gdppc440etx/init.S | 75 ++++++++ board/gdsys/gdppc440etx/u-boot.lds | 144 +++++++++++++++ include/configs/gdppc440etx.h | 194 ++++++++++++++++++++ 9 files changed, 838 insertions(+), 0 deletions(-) create mode 100644 board/gdsys/gdppc440etx/Makefile create mode 100644 board/gdsys/gdppc440etx/config.mk create mode 100644 board/gdsys/gdppc440etx/gdppc440etx.c create mode 100644 board/gdsys/gdppc440etx/init.S create mode 100644 board/gdsys/gdppc440etx/u-boot.lds create mode 100644 include/configs/gdppc440etx.h diff --git a/MAINTAINERS b/MAINTAINERS index 127604b..b836263 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -132,6 +132,7 @@ Jon Diekema <jon.diekema(a)smiths-aerospace.com> Dirk Eibach <eibach(a)gdsys.de> + gdppc440etx PPC440EP/GR neo PPC405EP Dave Ellis <DGE(a)sixnetio.com> diff --git a/MAKEALL b/MAKEALL index dbed268..3789bb9 100755 --- a/MAKEALL +++ b/MAKEALL @@ -188,6 +188,7 @@ LIST_4xx=" \ EXBITGEN \ fx12mm \ G2000 \ + gdppc440etx \ glacier \ haleakala \ haleakala_nand \ diff --git a/Makefile b/Makefile index befb608..d77ab3a 100644 --- a/Makefile +++ b/Makefile @@ -1315,6 +1315,9 @@ fx12mm_config: unconfig G2000_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000 +gdppc440etx_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx gdppc440etx gdsys + hcu4_config: unconfig @mkdir -p $(obj)board/netstal/common @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile new file mode 100644 index 0000000..b93f2c3 --- /dev/null +++ b/board/gdsys/gdppc440etx/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk new file mode 100644 index 0000000..045f3e9 --- /dev/null +++ b/board/gdsys/gdppc440etx/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# G&D 440EP/GR ETX-Module +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c new file mode 100644 index 0000000..e1890ff --- /dev/null +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de + * + * Based on board/amcc/yosemite/yosemite.c + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +int board_early_init_f(void) +{ + register uint reg; + + /* + * Setup the external bus controller/chip selects + */ + mfebc(xbcfg, reg); + mtebc(xbcfg, reg | 0x04000000); /* Set ATC */ + + /* + * Setup the GPIO pins + */ + + /* setup Address lines for flash size 64Meg. */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000); + + /* setup emac */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); + out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); + + /* UART0 and UART1*/ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000); + out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000); + + /* disable boot-eeprom WP */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000); + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000); + out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000); + + /* external interrupts IRQ0...3 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); + out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); + + + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /* + * Setup other serial configuration + */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + + return 0; +} + +int misc_init_r(void) +{ + uint pbcr; + int size_val; + uint sz; + + /* Re-do sizing to get full correct info */ + mfebc(pb0cr, pbcr); + + if (gd->bd->bi_flashsize > 0x08000000) + panic("Max. flash banksize is 128 MB!\n"); + + for (sz = gd->bd->bi_flashsize, size_val = 7; + ((sz & 0x08000000) == 0) && (size_val > 0); --size_val) + sz <<= 1; + + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtebc(pb0cr, pbcr); + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CONFIG_SYS_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + u8 rev; + u8 val; + + printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +/* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + */ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /* + * Set priority for all PLB3 devices to 0. + * Set PLB3 arbiter to fair mode. + */ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /* + * Set priority for all PLB4 devices to 0. + */ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /* + * Set Nebula PLB4 arbiter to fair mode. + */ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + /* enable 66 MHz ext. Clock */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); + out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000); + + return 1; +} +#endif /* defined(CONFIG_PCI) */ + +/* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + */ +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /* + * Set up Direct MMIO registers + */ + + /* + * PowerPC440 EP PCI Master configuration. + * Map one 1Gig range of PLB/processor addresses to PCI memory space. + * PLB address 0xA0000000-0xDFFFFFFF + * ==> PCI address 0xA0000000-0xDFFFFFFF + * Use byte reversed out routines to handle endianess. + * Make this region non-prefetchable. + */ + out32r(PCIX0_PMM0MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIX0_PMM0PCIHA, 0x00000000); + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCIHA, 0x00000000); + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); + out32r(PCIX0_PTM1LA, 0); + out32r(PCIX0_PTM2MS, 0); + out32r(PCIX0_PTM2LA, 0); + + /* + * Set up Configuration registers + */ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ + +/* + * pci_master_init + * + */ +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /* + * Write the PowerPC440 EP PCI Configuration regs. + * Enable PowerPC440 EP to be a master on the PCI bus (PMM). + * Enable PowerPC440 EP to act as a PCI memory target (PTM). + */ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ + +/* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + */ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return 1; +} +#endif /* defined(CONFIG_PCI) */ diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S new file mode 100644 index 0000000..0bbd45a --- /dev/null +++ b/board/gdsys/gdppc440etx/init.S @@ -0,0 +1,75 @@ +/* +* (C) Copyright 2008 +* Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de +* +* based on board/amcc/yosemite/init.S +* original Copyright not specified there +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +#include <asm/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use + * the speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, + 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, + 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, + 0, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, + 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/gdsys/gdppc440etx/u-boot.lds b/board/gdsys/gdppc440etx/u-boot.lds new file mode 100644 index 0000000..1df817b --- /dev/null +++ b/board/gdsys/gdppc440etx/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/gdsys/gdppc440etx/init.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h new file mode 100644 index 0000000..d193919 --- /dev/null +++ b/include/configs/gdppc440etx.h @@ -0,0 +1,194 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de + * + * Based on include/configs/yosemite.h + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_440GR 1 /* Specific PPC440GR support */ +#define CONFIG_HOSTNAME gdppc440etx +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ +#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 + +/*Don't change either of these*/ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripheral*/ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ +/*Don't change either of these*/ + +#define CONFIG_SYS_USB_DEVICE 0x50000000 +#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 + +/* + * Initial RAM & stack pointer (placed in SDRAM) + */ +#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/ +#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes init data*/ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Serial Port + */ +#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_UART1_CONSOLE + +/* + * Environment + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* + * DDR SDRAM + */ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ +#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ +#define CONFIG_SYS_SDRAM_BANKS (2) + +#define CONFIG_SDRAM_BANK0 +#define CONFIG_SDRAM_BANK1 + +#define CONFIG_SYS_SDRAM0_TR0 0x410a4012 +#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 +#define CONFIG_SYS_SDRAM0_RTR 0x04080000 +#define CONFIG_SYS_SDRAM0_CFG0 0x80000000 + +#undef CONFIG_SDRAM_ECC + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc180000\0" \ + "" + +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY1_ADDR 3 + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#endif + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_PCI +#undef CONFIG_CMD_EEPROM + +/* + * PCI stuff + */ + +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/ +#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ + CONFIG_SYS_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT +#define CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ + +/* + * External Bus Controller (EBC) Setup + */ +#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x03017200 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) + +#endif /* __CONFIG_H */ -- 1.5.6.5

2 1

[U-Boot] [PATCH v3] ppc4xx: Improve DDR autodetect
by Dirk Eibach 26 Jan '09

26 Jan '09

Added support for a second memory bank to DDR autodetection for 440 platforms. Made hardcoded values configurable. Signed-off-by: Dirk Eibach <eibach(a)gdsys.de> --- Whitespace fix. cpu/ppc4xx/sdram.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 50 insertions(+), 5 deletions(-) diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 6d5f8d6..4365df9 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -259,6 +259,7 @@ phys_size_t initdram(int board_type) #ifndef CONFIG_SYS_SDRAM_TABLE sdram_conf_t mb0cf[] = { {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */ + {(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4) */ {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */ }; #else @@ -269,6 +270,18 @@ sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE; #define CONFIG_SYS_SDRAM0_TR0 0x41094012 #endif +#ifndef CONFIG_SYS_SDRAM0_WDDCTR +#define CONFIG_SYS_SDRAM0_WDDCTR 0x00000000 /* wrcp=0 dcd=0 */ +#endif + +#ifndef CONFIG_SYS_SDRAM0_RTR +#define CONFIG_SYS_SDRAM0_RTR 0x04100000 /* 7.8us @ 133MHz PLB */ +#endif + +#ifndef CONFIG_SYS_SDRAM0_CFG0 +#define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */ +#endif + #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) #define NUM_TRIES 64 @@ -378,7 +391,7 @@ phys_size_t initdram(int board_type) mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram(mem_wddctr, CONFIG_SYS_SDRAM0_WDDCTR); mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* @@ -387,31 +400,63 @@ phys_size_t initdram(int board_type) mtsdram(mem_b0cr, mb0cf[i].reg); mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0); mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ - mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ + mtsdram(mem_rtr, CONFIG_SYS_SDRAM0_RTR); mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/ udelay(400); /* Delay 200 usecs (min) */ /* * Enable the controller, then wait for DCEN to complete */ - mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */ + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { + phys_size_t size = mb0cf[i].size; /* * Optimize TR1 to current hardware environment */ sdram_tr1_set(0x00000000, &tr1_bank1); mtsdram(mem_tr1, (tr1_bank1 | 0x80800800)); + + /* + * OK, size detected. Enable second bank if + * defined (assumes same type as bank 0) + */ +#ifdef CONFIG_SDRAM_BANK1 + mtsdram(mem_cfg0, 0); + mtsdram(mem_b1cr, mb0cf[i].size | mb0cf[i].reg); + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); + udelay(10000); + + /* + * Check if 2nd bank is really available. + * If the size not equal to the size of the first + * bank, then disable the 2nd bank completely. + */ + if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) + != mb0cf[i].size) { + mtsdram(mem_cfg0, 0); + mtsdram(mem_b1cr, 0); + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); + udelay(10000); + } else { + /* + * We have two identical banks, so the size + * is twice the bank size + */ + size = 2 * size; + } +#endif + #ifdef CONFIG_SDRAM_ECC - ecc_init(0, mb0cf[i].size); + ecc_init(0, size); #endif /* * OK, size detected -> all done */ - return mb0cf[i].size; + return size; } } -- 1.5.6.5

2 1

[U-Boot] [PATCH v2 0/5] OMAP3: Add OMAP3 board support
by Jason Kridner 25 Jan '09

25 Jan '09

Basic OMAP3 SoC support is added to u-boot-arm master branch [1] by applying OMAP3 patches 1-8 from v6 patch series [2]. Now, add missing EVM, Overo, Beagle, Pandora and Zoom1 boards (patches 9-15 from OMAP3 v6 series). This patch series is against u-boot-arm master branch, commit d5254f149da9e6cd649d887b042ce577ef3ba78d "Initial support for Nomadik 8815 development board". Changes in v2: * Rebase to u-boot-arm master * Remove trailing blank lines Dirk and Jason [1] http://git.denx.de/?p=u-boot/u-boot-arm.git;a=summary [2] http://lists.denx.de/pipermail/u-boot/2008-December/044787.html Dirk Behme (4): OMAP3: Add Overo board OMAP3: Add EVM board OMAP3: Add Pandora support OMAP3: Add Zoom1 board support Jason Kridner (1): OMAP3: Add common power code, README, and BeagleBoard MAINTAINERS | 20 ++ MAKEALL | 30 ++- Makefile | 19 ++ board/omap3/beagle/Makefile | 49 +++++ board/omap3/beagle/beagle.c | 90 +++++++++ board/omap3/beagle/beagle.h | 376 +++++++++++++++++++++++++++++++++++ board/omap3/beagle/config.mk | 33 +++ board/omap3/beagle/u-boot.lds | 63 ++++++ board/omap3/common/Makefile | 53 +++++ board/omap3/common/power.c | 74 +++++++ board/omap3/evm/Makefile | 48 +++++ board/omap3/evm/config.mk | 33 +++ board/omap3/evm/evm.c | 122 +++++++++++ board/omap3/evm/evm.h | 396 ++++++++++++++++++++++++++++++++++++ board/omap3/evm/u-boot.lds | 63 ++++++ board/omap3/overo/Makefile | 48 +++++ board/omap3/overo/config.mk | 29 +++ board/omap3/overo/overo.c | 88 ++++++++ board/omap3/overo/overo.h | 381 +++++++++++++++++++++++++++++++++++ board/omap3/overo/u-boot.lds | 63 ++++++ board/omap3/pandora/Makefile | 49 +++++ board/omap3/pandora/config.mk | 33 +++ board/omap3/pandora/pandora.c | 92 +++++++++ board/omap3/pandora/pandora.h | 420 +++++++++++++++++++++++++++++++++++++++ board/omap3/pandora/u-boot.lds | 63 ++++++ board/omap3/zoom1/Makefile | 49 +++++ board/omap3/zoom1/config.mk | 33 +++ board/omap3/zoom1/u-boot.lds | 63 ++++++ board/omap3/zoom1/zoom1.c | 77 +++++++ board/omap3/zoom1/zoom1.h | 135 +++++++++++++ doc/README.omap3 | 116 +++++++++++ include/configs/omap3_beagle.h | 325 ++++++++++++++++++++++++++++++ include/configs/omap3_evm.h | 345 ++++++++++++++++++++++++++++++++ include/configs/omap3_overo.h | 318 +++++++++++++++++++++++++++++ include/configs/omap3_pandora.h | 320 +++++++++++++++++++++++++++++ include/configs/omap3_zoom1.h | 326 ++++++++++++++++++++++++++++++ 36 files changed, 4833 insertions(+), 9 deletions(-) create mode 100644 board/omap3/beagle/Makefile create mode 100644 board/omap3/beagle/beagle.c create mode 100644 board/omap3/beagle/beagle.h create mode 100644 board/omap3/beagle/config.mk create mode 100644 board/omap3/beagle/u-boot.lds create mode 100644 board/omap3/common/Makefile create mode 100644 board/omap3/common/power.c create mode 100644 board/omap3/evm/Makefile create mode 100644 board/omap3/evm/config.mk create mode 100644 board/omap3/evm/evm.c create mode 100644 board/omap3/evm/evm.h create mode 100644 board/omap3/evm/u-boot.lds create mode 100644 board/omap3/overo/Makefile create mode 100644 board/omap3/overo/config.mk create mode 100644 board/omap3/overo/overo.c create mode 100644 board/omap3/overo/overo.h create mode 100644 board/omap3/overo/u-boot.lds create mode 100644 board/omap3/pandora/Makefile create mode 100644 board/omap3/pandora/config.mk create mode 100644 board/omap3/pandora/pandora.c create mode 100644 board/omap3/pandora/pandora.h create mode 100644 board/omap3/pandora/u-boot.lds create mode 100644 board/omap3/zoom1/Makefile create mode 100644 board/omap3/zoom1/config.mk create mode 100644 board/omap3/zoom1/u-boot.lds create mode 100644 board/omap3/zoom1/zoom1.c create mode 100644 board/omap3/zoom1/zoom1.h create mode 100644 doc/README.omap3 create mode 100644 include/configs/omap3_beagle.h create mode 100644 include/configs/omap3_evm.h create mode 100644 include/configs/omap3_overo.h create mode 100644 include/configs/omap3_pandora.h create mode 100644 include/configs/omap3_zoom1.h

1 5

[U-Boot] R: Re: Strange arm9 behaviour reading long(s) not aligned to 4 bytes boundary
by dibacco＠libero.it 25 Jan '09

25 Jan '09

>> I have something like this on a 32 bit little endian arm9 board (SAM9 >> L9260): >> >> char buffer[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; >> >> long A = * ( (long*) >> buffer ); >> long B = * ( (long*) (buffer + 2) ); >> >> printf("A: % 08x B: %08x", A, >> B); >> >> I would expect that A = 0x03020100 and B = 0x05040302 >> instead I get the >> right value for A but B is 0x01000302 or something like this but anyway not >> what I expect. >> Is there something wrong on the board? It seems that only 4 >> bytes aligned long are read correctly. > >ARM9 does not support unaligned load/store. Yours is apparently >configured in the round-and-rotate mode. >e Then my code is simply wrong, that is, not allowed? If I have to port code from a PPC (that handles unaligned accesses) to an ARM9 it is painful operation..., isn't it? Bye, Antonio.

3 2

[U-Boot] [PATCH-OMAP3] OMAP3: Add Beagle Board and common power code
by Jason Kridner 25 Jan '09

25 Jan '09

Add Beagle Board support and common power code for OMAP3 boards. Restructured from patches by Dirk Behme <dirk.behme(a)googlemail.com>, Steve Sakoman <steve(a)sakoman.com>, and Søren Steen Christensen <sorenschristensen(a)stofanet.dk>. Signed-off-by: Jason Kridner <jkridner(a)beagleboard.org> --- MAINTAINERS | 4 + MAKEALL | 26 ++- Makefile | 7 + board/omap3/beagle/Makefile | 49 ++++++ board/omap3/beagle/beagle.c | 90 ++++++++++ board/omap3/beagle/beagle.h | 385 +++++++++++++++++++++++++++++++++++++++++ board/omap3/beagle/config.mk | 35 ++++ board/omap3/beagle/u-boot.lds | 63 +++++++ board/omap3/common/Makefile | 50 ++++++ board/omap3/common/power.c | 74 ++++++++ doc/README.omap3 | 68 +++++++ 11 files changed, 842 insertions(+), 9 deletions(-) create mode 100644 board/omap3/beagle/Makefile create mode 100644 board/omap3/beagle/beagle.c create mode 100644 board/omap3/beagle/beagle.h create mode 100644 board/omap3/beagle/config.mk create mode 100644 board/omap3/beagle/u-boot.lds create mode 100644 board/omap3/common/Makefile create mode 100644 board/omap3/common/power.c create mode 100644 doc/README.omap3 diff --git a/MAINTAINERS b/MAINTAINERS index f048795..5c6334b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -477,6 +477,10 @@ Rowel Atienza <rowel(a)diwalabs.com> armadillo ARM720T +Dirk Behme <dirk.behme(a)gmail.com> + + omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC) + Rishi Bhattacharya <rishi(a)ti.com> omap5912osk ARM926EJS diff --git a/MAKEALL b/MAKEALL index cc49a98..e2f0df7 100755 --- a/MAKEALL +++ b/MAKEALL @@ -539,6 +539,13 @@ LIST_ARM11=" \ " ######################################################################### +## ARM Cortex-A8 Systems +######################################################################### +LIST_ARM_CORTEX_A8=" \ + omap3_beagle \ +" + +######################################################################### ## AT91 Systems ######################################################################### @@ -592,15 +599,16 @@ LIST_ixp=" \ ## ARM groups ######################################################################### -LIST_arm=" \ - ${LIST_SA} \ - ${LIST_ARM7} \ - ${LIST_ARM9} \ - ${LIST_ARM10} \ - ${LIST_ARM11} \ - ${LIST_at91} \ - ${LIST_pxa} \ - ${LIST_ixp} \ +LIST_arm=" \ + ${LIST_SA} \ + ${LIST_ARM7} \ + ${LIST_ARM9} \ + ${LIST_ARM10} \ + ${LIST_ARM11} \ + ${LIST_ARM_CORTEX_A8} \ + ${LIST_at91} \ + ${LIST_pxa} \ + ${LIST_ixp} \ " ######################################################################### diff --git a/Makefile b/Makefile index 4df4812..43b8f44 100644 --- a/Makefile +++ b/Makefile @@ -2840,6 +2840,13 @@ SMN42_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292 ######################################################################### +## ARM CORTEX Systems +######################################################################### + +omap3_beagle_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle omap3 omap3 + +######################################################################### ## XScale Systems ######################################################################### diff --git a/board/omap3/beagle/Makefile b/board/omap3/beagle/Makefile new file mode 100644 index 0000000..0b8852a --- /dev/null +++ b/board/omap3/beagle/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := beagle.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### \ No newline at end of file diff --git a/board/omap3/beagle/beagle.c b/board/omap3/beagle/beagle.c new file mode 100644 index 0000000..ecdea09 --- /dev/null +++ b/board/omap3/beagle/beagle.c @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include "beagle.h" + +/****************************************************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/****************************************************************************** + * Routine: misc_init_r + * Description: Configure board specific parts + *****************************************************************************/ +int misc_init_r(void) +{ + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + + power_init_r(); + + /* Configure GPIOs to output */ + writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); + writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); + + /* Set GPIOs */ + writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1, + &gpio6_base->setdataout); + writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + + return 0; +} + +/****************************************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + *****************************************************************************/ +void set_muxconf_regs(void) +{ + MUX_BEAGLE(); +} diff --git a/board/omap3/beagle/beagle.h b/board/omap3/beagle/beagle.h new file mode 100644 index 0000000..839e629 --- /dev/null +++ b/board/omap3/beagle/beagle.h @@ -0,0 +1,385 @@ +/* + * (C) Copyright 2008 + * Dirk Behme <dirk.behme(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _BEAGLE_H_ +#define _BEAGLE_H_ + +const omap3_sysinfo sysinfo = { + SDP_3430_V1, + SDP_3430_V2, + DDR_STACKED, + "3530", + "OMAP3 Beagle board", +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "OneNAND", +#else + "NAND", +#endif +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_BEAGLE() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + /* For Beagle Rev 2 boards*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1))\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1))\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0))\ + /* till here */\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + /* - CAM_RESET*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\ + MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\ + MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\ + /* - BT_WAKEUP*/\ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ + MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ + MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\ + /* USB EHCI (port 2) */\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA2*/\ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA7*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA4*/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA5*/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA6*/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA3*/\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 - PEN_IRQ */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + /* - LCD_ENVDD*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + /* - LAN_INTR0*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + /* - MMC2_WP*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \ + /* - LCD_ENBKL*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/ + +#endif diff --git a/board/omap3/beagle/config.mk b/board/omap3/beagle/config.mk new file mode 100644 index 0000000..c785011 --- /dev/null +++ b/board/omap3/beagle/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2006 +# Texas Instruments, <www.ti.com> +# +# Beagle Board uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + diff --git a/board/omap3/beagle/u-boot.lds b/board/omap3/beagle/u-boot.lds new file mode 100644 index 0000000..69d8ac9 --- /dev/null +++ b/board/omap3/beagle/u-boot.lds @@ -0,0 +1,63 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm_cortexa8/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } + __exidx_start = .; + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } + __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3/common/Makefile b/board/omap3/common/Makefile new file mode 100644 index 0000000..28fbf54 --- /dev/null +++ b/board/omap3/common/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS-$(CONFIG_OMAP3_BEAGLE) += power.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omap3/common/power.c b/board/omap3/common/power.c new file mode 100644 index 0000000..4908e5b --- /dev/null +++ b/board/omap3/common/power.c @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> + +/****************************************************************************** + * Routine: power_init_r + * Description: Configure power supply + *****************************************************************************/ +void power_init_r(void) +{ + unsigned char byte; + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + /* + * Configure OMAP3 supply voltages in power management + * companion chip. + */ + + /* set VAUX3 to 2.8V */ + byte = DEV_GRP_P1; + i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEV_GRP, 1, &byte, 1); + byte = VAUX3_VSEL_28; + i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEDICATED, 1, &byte, 1); + + /* set VPLL2 to 1.8V */ + byte = DEV_GRP_ALL; + i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEV_GRP, 1, &byte, 1); + byte = VPLL2_VSEL_18; + i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEDICATED, 1, &byte, 1); + + /* set VDAC to 1.8V */ + byte = DEV_GRP_P1; + i2c_write(PWRMGT_ADDR_ID4, VDAC_DEV_GRP, 1, &byte, 1); + byte = VDAC_VSEL_18; + i2c_write(PWRMGT_ADDR_ID4, VDAC_DEDICATED, 1, &byte, 1); + + /* enable LED */ + byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON; + i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1); +} diff --git a/doc/README.omap3 b/doc/README.omap3 new file mode 100644 index 0000000..ff3fca0 --- /dev/null +++ b/doc/README.omap3 @@ -0,0 +1,68 @@ + +Summary +======= + +This README is about U-Boot support for TI's ARM Cortex-A8 based OMAP3 [1] +family of SoCs. TI's OMAP3 SoC family contains an ARM Cortex-A8 core running +at ~600MHz. Additionally some family members contain a TMS320C64x+ DSP ~430MHz +and/or an Imagination SGX 2D/3D graphics processor and various other standard +peripherals. + +Currently the following boards are supported: + +* OMAP3530 BeagleBoard [1] + +Toolchain +========= + +While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile +with -march=armv5 to allow more compilers to work. For U-Boot code this has +no performance impact. + +Build +===== + +* BeagleBoard: + +make omap3_beagle_config +make + +Custom commands +=============== + +To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot +for OMAP3 supports custom user command + +nandecc hw/sw + +To be compatible with NAND drivers using SW ECC (e.g. kernel code) + +nandecc sw + +enables SW ECC calculation. HW ECC enabled with + +nandecc hw + +is typically used to write 2nd stage bootloader (known as 'x-loader') which is +executed by OMAP3's boot rom and therefore has to be written with HW ECC. + +For all other commands see + +help + +Acknowledgements +================ + +OMAP3 U-Boot is based on U-Boot tar ball [2] for BeagleBoard and EVM done by +several TI employees. + +Links +===== + +[1] OMAP3530 BeagleBoard: + +http://beagleboard.org/ + +[2] TI OMAP3 U-Boot: + +http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz -- 1.6.0.4.790.gaa14a

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[U-Boot] Patches for new at91 board / lowlevel_init.S
by Michael Roth 25 Jan '09

25 Jan '09

Hello, I'm having patches for a new at91sam9261 based board in my queue I would like to publish for the current merge window. However, this patch needs a way to supply its own lowlevel_init.S instead the at91 default. A week ago I asked a question about that topic and there was a hint to look for the ronetix patches and a note that the next U-Boot release will contain a solution. However, the mentioned ronetix patch followed a discussion about possible ways to address this topic but as far I can see, no solution was selected. Additionally, in the current git tree there is still no solution for this topic, too (or I'm missing something). So my question is: How should I proceed? Should I post my solution? Or should I wait a couple of more days for an "official" solution? Michael Roth

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