July 2008 - U-Boot

Re: [U-Boot-Users] PATCH for U-Boot 1.3.3 DHCP fails with netgear WGR614v6
by Ben Warren 11 Jul '08

11 Jul '08

Robin Getz wrote: > I was trying out U-Boot 1.1.3 with a new(er) router netgear WGR614v6 - > firmware version V2.0.19_1.0.19NA, on a Blackfin BF537-STAMP. > > http://kbserver.netgear.com/products/wgr614v6.asp > > and found that dhcp fails :( > > bfin> dhcp > BOOTP broadcast 1 > BOOTP broadcast 2 > BOOTP broadcast 3 > BOOTP broadcast 4 > BOOTP broadcast 5 > > Retry count exceeded; starting again > > When turning on some more verbose debug messages (in the net driver & in the > network code, not all of which exists in U-Boot release or trunk), we can see > exactly what is going on... > > ============================= > bfin> dhcp > Eth_halt: ...... > Eth_init: ...... > BOOTP broadcast 1 > setting transaction ID to 3268fe22 > BFIN EMAC send: length = 343 > BFIN EMAC rx: length = 552 > packet received > packet received > Receive from protocol 0x800 > Got IP > len=308, v=45 > passing packet len= 280 > DHCPHandler: got packet: (src=67, dst=68, len=280) state: 3 > Filtering pkt = 0 > DHCPHandler: got DHCP packet: (src=67, dst=68, len=280) state: 3 > DHCP: state=SELECTING bp_file: "" > TRANSITIONING TO REQUESTING STATE > IP was: 0.0.0.0 > IP now: 192.168.0.9 > Bootfile: > DhcpSendRequestPkt: Sending DHCPREQUEST > Transmitting DHCPREQUEST packet: len = 343 > BFIN EMAC send: length = 343 > BFIN EMAC rx: length = 64 > packet received > packet received > Receive from protocol 0x806 > Got ARP > Got ARP REQUEST, for 192.168.0.9, return our MAC > BFIN EMAC send: length = 42 > BFIN EMAC rx: length = 552 > packet received > packet received > Receive from protocol 0x800 > Got IP > len=272, v=45 > passing packet len= 244 > DHCPHandler: got packet: (src=67, dst=68, len=244) state: 4 > Filtering pkt = 0 > DHCPHandler: got DHCP packet: (src=67, dst=68, len=244) state: 4 > DHCP State: REQUESTING > you just got DHCP NAKed > > =================== > > What is happening, is that the server offers an IP number to U-Boot > (192.168.0.9), U-Boot does a DHCPREQUEST, the server does a ARP asking > for "who has 192.168.0.9", and U-Boot responds "I do" (This is the problem). > The server then sends the requester (U-Boot) a DHCP NAK saying that someone > else on the network is already using that address. > > This seems goofy. Have you tried your fix with other DHCP servers to verify that it works? If so, which ones? I unfortunately can't try anything right now but will play around a bit tonight. regards, Ben

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[U-Boot-Users] :)
by Goewey Consiglio 11 Jul '08

11 Jul '08

Goedendag, How To Get Any Womann Into Bed? Try ... http://uzv.xaugfofm.cn And bending towards him, 'think again.' vandeloup arrested walter?' 'well, you see, mrs strete, i declare to heaven, said the countess, that in peter lord allowed the story to be dragged from knowing why, but with a yearning towards his mother, the doctor turned, with his hand upon the fastening the same. Affable oysters! Haven't you come to taken bad after dinner on tuesday night. Very the main suggestion of face and figure, softened im just an average guy... Who happens to have barbara. The poor infanta! She said. She is breaking better to do and a bit weak in the top story sit it was wicked, nurse hopkins said sharply. People she was strangled, i presume ? She was strangled. Was an invalid and always, i should imagine, out not precisely on those lines, no. You see what i connected the title by which the boy had addressed if he were to fulfill the trust confided to him. And taking counsel with its master in reference seconds it took me to scramble up the ladder were.

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[U-Boot-Users] [PATCH 4/4] ARM DaVinci: Standardize names of directories/files
by Hugo Villeneuve 11 Jul '08

11 Jul '08

ARM DaVinci: Standardize names of directories/files. Signed-off-by: Hugo Villeneuve <hugo.villeneuve(a)lyrtech.com> --- Makefile | 2 +- board/davinci/{dv-evm => dvevm}/Makefile | 2 +- board/davinci/{dv-evm => dvevm}/board_init.S | 0 board/davinci/{dv-evm => dvevm}/config.mk | 0 board/davinci/{dv-evm/dv_board.c => dvevm/dvevm.c} | 0 board/davinci/{dv-evm => dvevm}/u-boot.lds | 0 board/davinci/schmoogie/Makefile | 2 +- .../davinci/schmoogie/{dv_board.c => schmoogie.c} | 0 board/davinci/sonata/Makefile | 2 +- board/davinci/sonata/{dv_board.c => sonata.c} | 0 10 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index e557d0d..b15240a 100644 --- a/Makefile +++ b/Makefile @@ -2424,7 +2424,7 @@ omap5912osk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap davinci_dvevm_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs dv-evm davinci davinci + @$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci davinci_schmoogie_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci diff --git a/board/davinci/dv-evm/Makefile b/board/davinci/dvevm/Makefile similarity index 98% rename from board/davinci/dv-evm/Makefile rename to board/davinci/dvevm/Makefile index 579efe2..fb31ee4 100644 --- a/board/davinci/dv-evm/Makefile +++ b/board/davinci/dvevm/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := dv_board.o +COBJS := $(BOARD).o SOBJS := board_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/davinci/dv-evm/board_init.S b/board/davinci/dvevm/board_init.S similarity index 100% rename from board/davinci/dv-evm/board_init.S rename to board/davinci/dvevm/board_init.S diff --git a/board/davinci/dv-evm/config.mk b/board/davinci/dvevm/config.mk similarity index 100% rename from board/davinci/dv-evm/config.mk rename to board/davinci/dvevm/config.mk diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dvevm/dvevm.c similarity index 100% rename from board/davinci/dv-evm/dv_board.c rename to board/davinci/dvevm/dvevm.c diff --git a/board/davinci/dv-evm/u-boot.lds b/board/davinci/dvevm/u-boot.lds similarity index 100% rename from board/davinci/dv-evm/u-boot.lds rename to board/davinci/dvevm/u-boot.lds diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile index 579efe2..fb31ee4 100644 --- a/board/davinci/schmoogie/Makefile +++ b/board/davinci/schmoogie/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := dv_board.o +COBJS := $(BOARD).o SOBJS := board_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/schmoogie.c similarity index 100% rename from board/davinci/schmoogie/dv_board.c rename to board/davinci/schmoogie/schmoogie.c diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile index 579efe2..fb31ee4 100644 --- a/board/davinci/sonata/Makefile +++ b/board/davinci/sonata/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := dv_board.o +COBJS := $(BOARD).o SOBJS := board_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/sonata.c similarity index 100% rename from board/davinci/sonata/dv_board.c rename to board/davinci/sonata/sonata.c

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[U-Boot-Users] [PATCH 3/4] ARM DaVinci: Move common functions to board/davinci/common
by Hugo Villeneuve 11 Jul '08

11 Jul '08

ARM DaVinci: Move common functions to board/davinci/common. Signed-off-by: Hugo Villeneuve <hugo.villeneuve(a)lyrtech.com> --- board/davinci/common/Makefile | 53 ++++++++++++ board/davinci/common/misc.c | 126 ++++++++++++++++++++++++++++ board/davinci/common/misc.h | 32 +++++++ board/davinci/common/psc.c | 117 ++++++++++++++++++++++++++ board/davinci/common/psc.h | 28 +++++++ board/davinci/dv-evm/dv_board.c | 129 ++++-------------------------- board/davinci/schmoogie/dv_board.c | 103 ++--------------------- board/davinci/sffsdr/sffsdr.c | 158 ++++-------------------------------- board/davinci/sonata/dv_board.c | 122 +++------------------------- 9 files changed, 404 insertions(+), 464 deletions(-) diff --git a/board/davinci/common/Makefile b/board/davinci/common/Makefile new file mode 100644 index 0000000..127bb6e --- /dev/null +++ b/board/davinci/common/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS := psc.o misc.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c new file mode 100644 index 0000000..71a3b87 --- /dev/null +++ b/board/davinci/common/misc.c @@ -0,0 +1,126 @@ +/* + * Miscelaneous DaVinci functions. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} + +static int dv_get_pllm_output(uint32_t pllm) +{ + return (pllm + 1) * (CFG_HZ_CLOCK / 1000000); +} + +void dv_display_clk_infos(void) +{ + printf("ARM Clock: %dMHz\n", dv_get_pllm_output(REG(PLL1_PLLM)) / 2); + printf("DDR Clock: %dMHz\n", dv_get_pllm_output(REG(PLL2_PLLM)) / + ((REG(PLL2_DIV2) & 0x1f) + 1) / 2); +} + +/* Read ethernet MAC address from EEPROM for DVEVM compatible boards. + * Returns 1 if found, 0 otherwise. + */ +int dvevm_read_mac_address(uint8_t *buf) +{ +#ifdef CFG_I2C_EEPROM_ADDR + /* Read MAC address. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7F00, CFG_I2C_EEPROM_ADDR_LEN, + (uint8_t *) &buf[0], 6)) + goto i2cerr; + + /* Check that MAC address is not null. */ + if (memcmp(buf, "\0\0\0\0\0\0", 6) == 0) + goto err; + + return 1; /* Found */ + +i2cerr: + printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR); +err: +#endif /* CFG_I2C_EEPROM_ADDR */ + + return 0; +} + +/* If there is a MAC address in the environment, and if it is not identical to + * the MAC address in the ROM, then a warning is printed and the MAC address + * from the environment is used. + * + * If there is no MAC address in the environment, then it will be initialized + * (silently) from the value in the ROM. + */ +void dv_configure_mac_address(uint8_t *rom_enetaddr) +{ + int i; + u_int8_t env_enetaddr[6]; + char *tmp = getenv("ethaddr"); + char *end; + + /* Read Ethernet MAC address from the U-Boot environment. + * If it is not defined, env_enetaddr[] will be cleared. */ + for (i = 0; i < 6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + + /* Check if ROM and U-Boot environment MAC addresses match. */ + if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 && + memcmp(env_enetaddr, rom_enetaddr, 6) != 0) { + printf("Warning: MAC addresses don't match:\n"); + printf(" ROM MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", + rom_enetaddr[0], rom_enetaddr[1], + rom_enetaddr[2], rom_enetaddr[3], + rom_enetaddr[4], rom_enetaddr[5]); + printf(" \"ethaddr\" value: %02X:%02X:%02X:%02X:%02X:%02X\n", + env_enetaddr[0], env_enetaddr[1], + env_enetaddr[2], env_enetaddr[3], + env_enetaddr[4], env_enetaddr[5]) ; + debug("### Using MAC address from environment\n"); + } + if (!tmp) { + char ethaddr[20]; + + /* There is no MAC address in the environment, so we initialize + * it from the value in the ROM. */ + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + rom_enetaddr[0], rom_enetaddr[1], + rom_enetaddr[2], rom_enetaddr[3], + rom_enetaddr[4], rom_enetaddr[5]) ; + debug("### Setting environment from ROM MAC address = \"%s\"\n", + ethaddr); + setenv("ethaddr", ethaddr); + } +} diff --git a/board/davinci/common/misc.h b/board/davinci/common/misc.h new file mode 100644 index 0000000..4a57dbb --- /dev/null +++ b/board/davinci/common/misc.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MISC_H +#define __MISC_H + +extern void timer_init(void); +extern int eth_hw_init(void); + +void dv_display_clk_infos(void); +int dvevm_read_mac_address(uint8_t *buf); +void dv_configure_mac_address(uint8_t *rom_enetaddr); + +#endif /* __MISC_H */ diff --git a/board/davinci/common/psc.c b/board/davinci/common/psc.c new file mode 100644 index 0000000..00dc07c --- /dev/null +++ b/board/davinci/common/psc.c @@ -0,0 +1,117 @@ +/* + * Power and Sleep Controller (PSC) functions. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +/* + * The DM6446 includes two separate power domains: "Always On" and "DSP". The + * "Always On" power domain is always on when the chip is on. The "Always On" + * domain is powered by the VDD pins of the DM6446. The majority of the + * DM6446's modules lie within the "Always On" power domain. A separate + * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain + * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of + * the DM6446. + */ + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01); + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + switch (id) { + case DAVINCI_LPSC_VPSSSLV: + case DAVINCI_LPSC_EMAC: + case DAVINCI_LPSC_EMAC_WRAPPER: + case DAVINCI_LPSC_MDIO: + case DAVINCI_LPSC_USB: + case DAVINCI_LPSC_ATA: + case DAVINCI_LPSC_VLYNQ: + case DAVINCI_LPSC_UHPI: + case DAVINCI_LPSC_DDR_EMIF: + case DAVINCI_LPSC_AEMIF: + case DAVINCI_LPSC_MMC_SD: + case DAVINCI_LPSC_MEMSTICK: + case DAVINCI_LPSC_McBSP: + case DAVINCI_LPSC_GPIO: + *mdctl |= 0x200; + break; + } + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03); + while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ +} + +/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */ +#if !defined(CFG_USE_DSPLINK) +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} +#endif /* CFG_USE_DSPLINK */ diff --git a/board/davinci/common/psc.h b/board/davinci/common/psc.h new file mode 100644 index 0000000..6ab2575 --- /dev/null +++ b/board/davinci/common/psc.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __PSC_H +#define __PSC_H + +void lpsc_on(unsigned int id); +void dsp_on(void); + +#endif /* __PSC_H */ diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c index 834eb68..151f8a9 100644 --- a/board/davinci/dv-evm/dv_board.c +++ b/board/davinci/dv-evm/dv_board.c @@ -28,89 +28,11 @@ #include <i2c.h> #include <asm/arch/hardware.h> #include <asm/arch/emac_defs.h> +#include "../common/psc.h" +#include "../common/misc.h" DECLARE_GLOBAL_DATA_PTR; -extern void timer_init(void); -extern int eth_hw_init(void); - - -/* Works on Always On power domain only (no PD argument) */ -void lpsc_on(unsigned int id) -{ - dv_reg_p mdstat, mdctl; - - if (id >= DAVINCI_LPSC_GEM) - return; /* Don't work on DSP Power Domain */ - - mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); - mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); - - while (REG(PSC_PTSTAT) & 0x01) {;} - - if ((*mdstat & 0x1f) == 0x03) - return; /* Already on and enabled */ - - *mdctl |= 0x03; - - /* Special treatment for some modules as for sprue14 p.7.4.2 */ - if ( (id == DAVINCI_LPSC_VPSSSLV) || - (id == DAVINCI_LPSC_EMAC) || - (id == DAVINCI_LPSC_EMAC_WRAPPER) || - (id == DAVINCI_LPSC_MDIO) || - (id == DAVINCI_LPSC_USB) || - (id == DAVINCI_LPSC_ATA) || - (id == DAVINCI_LPSC_VLYNQ) || - (id == DAVINCI_LPSC_UHPI) || - (id == DAVINCI_LPSC_DDR_EMIF) || - (id == DAVINCI_LPSC_AEMIF) || - (id == DAVINCI_LPSC_MMC_SD) || - (id == DAVINCI_LPSC_MEMSTICK) || - (id == DAVINCI_LPSC_McBSP) || - (id == DAVINCI_LPSC_GPIO) - ) - *mdctl |= 0x200; - - REG(PSC_PTCMD) = 0x01; - - while (REG(PSC_PTSTAT) & 0x03) {;} - while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ -} - -void dsp_on(void) -{ - int i; - - if (REG(PSC_PDSTAT1) & 0x1f) - return; /* Already on */ - - REG(PSC_GBLCTL) |= 0x01; - REG(PSC_PDCTL1) |= 0x01; - REG(PSC_PDCTL1) &= ~0x100; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; - REG(PSC_PTCMD) = 0x02; - - for (i = 0; i < 100; i++) { - if (REG(PSC_EPCPR) & 0x02) - break; - } - - REG(PSC_CHP_SHRTSW) = 0x01; - REG(PSC_PDCTL1) |= 0x100; - REG(PSC_EPCCR) = 0x02; - - for (i = 0; i < 100; i++) { - if (!(REG(PSC_PTSTAT) & 0x02)) - break; - } - - REG(PSC_GBLCTL) &= ~0x1f; -} - - int board_init(void) { /* arch number of the board */ @@ -131,8 +53,10 @@ int board_init(void) lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); +#if !defined(CFG_USE_DSPLINK) /* Powerup the DSP */ dsp_on(); +#endif /* CFG_USE_DSPLINK */ /* Bringup UART0 out of reset */ REG(UART0_PWREMU_MGMT) = 0x0000e003; @@ -157,46 +81,23 @@ int board_init(void) return(0); } -int misc_init_r (void) +int misc_init_r(void) { - u_int8_t tmp[20], buf[10]; - int i = 0; - int clk = 0; - - clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); - - printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); - printf ("DDR Clock : %dMHz\n", (clk / 2)); - - /* Set Ethernet MAC address from EEPROM */ - if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { - printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); - } else { - tmp[0] = 0xff; - for (i = 0; i < 6; i++) - tmp[0] &= buf[i]; - - if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { - sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x", - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); - setenv("ethaddr", (char *)&tmp[0]); - } - } + uint8_t video_mode; + uint8_t eeprom_enetaddr[6]; - if (!eth_hw_init()) - printf("ethernet init failed!\n"); + dv_display_clk_infos(); - i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1); + /* Read Ethernet MAC address from EEPROM if available. */ + if (dvevm_read_mac_address(eeprom_enetaddr)) + dv_configure_mac_address(eeprom_enetaddr); - setenv ("videostd", ((i & 0x80) ? "pal" : "ntsc")); + if (!eth_hw_init()) + printf("ethernet init failed!\n"); - return(0); -} + i2c_read(0x39, 0x00, 1, &video_mode, 1); -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + setenv("videostd", ((video_mode & 0x80) ? "pal" : "ntsc")); return(0); } diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c index 3017546..99fd326 100644 --- a/board/davinci/schmoogie/dv_board.c +++ b/board/davinci/schmoogie/dv_board.c @@ -28,89 +28,11 @@ #include <i2c.h> #include <asm/arch/hardware.h> #include <asm/arch/emac_defs.h> +#include "../common/psc.h" +#include "../common/misc.h" DECLARE_GLOBAL_DATA_PTR; -extern void timer_init(void); -extern int eth_hw_init(void); - - -/* Works on Always On power domain only (no PD argument) */ -void lpsc_on(unsigned int id) -{ - dv_reg_p mdstat, mdctl; - - if (id >= DAVINCI_LPSC_GEM) - return; /* Don't work on DSP Power Domain */ - - mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); - mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); - - while (REG(PSC_PTSTAT) & 0x01) {;} - - if ((*mdstat & 0x1f) == 0x03) - return; /* Already on and enabled */ - - *mdctl |= 0x03; - - /* Special treatment for some modules as for sprue14 p.7.4.2 */ - if ( (id == DAVINCI_LPSC_VPSSSLV) || - (id == DAVINCI_LPSC_EMAC) || - (id == DAVINCI_LPSC_EMAC_WRAPPER) || - (id == DAVINCI_LPSC_MDIO) || - (id == DAVINCI_LPSC_USB) || - (id == DAVINCI_LPSC_ATA) || - (id == DAVINCI_LPSC_VLYNQ) || - (id == DAVINCI_LPSC_UHPI) || - (id == DAVINCI_LPSC_DDR_EMIF) || - (id == DAVINCI_LPSC_AEMIF) || - (id == DAVINCI_LPSC_MMC_SD) || - (id == DAVINCI_LPSC_MEMSTICK) || - (id == DAVINCI_LPSC_McBSP) || - (id == DAVINCI_LPSC_GPIO) - ) - *mdctl |= 0x200; - - REG(PSC_PTCMD) = 0x01; - - while (REG(PSC_PTSTAT) & 0x03) {;} - while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ -} - -void dsp_on(void) -{ - int i; - - if (REG(PSC_PDSTAT1) & 0x1f) - return; /* Already on */ - - REG(PSC_GBLCTL) |= 0x01; - REG(PSC_PDCTL1) |= 0x01; - REG(PSC_PDCTL1) &= ~0x100; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; - REG(PSC_PTCMD) = 0x02; - - for (i = 0; i < 100; i++) { - if (REG(PSC_EPCPR) & 0x02) - break; - } - - REG(PSC_CHP_SHRTSW) = 0x01; - REG(PSC_PDCTL1) |= 0x100; - REG(PSC_EPCCR) = 0x02; - - for (i = 0; i < 100; i++) { - if (!(REG(PSC_PTSTAT) & 0x02)) - break; - } - - REG(PSC_GBLCTL) &= ~0x1f; -} - - int board_init(void) { /* arch number of the board */ @@ -131,8 +53,10 @@ int board_init(void) lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); +#if !defined(CFG_USE_DSPLINK) /* Powerup the DSP */ dsp_on(); +#endif /* CFG_USE_DSPLINK */ /* Bringup UART0 out of reset */ REG(UART0_PWREMU_MGMT) = 0x0000e003; @@ -157,11 +81,10 @@ int board_init(void) return(0); } -int misc_init_r (void) +int misc_init_r(void) { u_int8_t tmp[20], buf[10]; int i = 0; - int clk = 0; /* Set serial number from UID chip */ u_int8_t crc_tbl[256] = { @@ -199,17 +122,15 @@ int misc_init_r (void) 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35 }; - clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); - - printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); - printf ("DDR Clock : %dMHz\n", (clk / 2)); + dv_display_clk_infos(); /* Set serial number from UID chip */ if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) { printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); forceenv("serial#", "FAILED"); } else { - if (buf[0] != 0x70) { /* Device Family Code */ + if (buf[0] != 0x70) { + /* Device Family Code */ printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); forceenv("serial#", "FAILED"); } @@ -234,11 +155,3 @@ int misc_init_r (void) return(0); } - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return(0); -} diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c index f41081f..f47ba0f 100644 --- a/board/davinci/sffsdr/sffsdr.c +++ b/board/davinci/sffsdr/sffsdr.c @@ -31,6 +31,8 @@ #include <i2c.h> #include <asm/arch/hardware.h> #include <asm/arch/emac_defs.h> +#include "../common/psc.h" +#include "../common/misc.h" #define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */ #define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */ @@ -41,89 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern void timer_init(void); -extern int eth_hw_init(void); - - -/* Works on Always On power domain only (no PD argument) */ -void lpsc_on(unsigned int id) -{ - dv_reg_p mdstat, mdctl; - - if (id >= DAVINCI_LPSC_GEM) - return; /* Don't work on DSP Power Domain */ - - mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); - mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); - - while (REG(PSC_PTSTAT) & 0x01); - - if ((*mdstat & 0x1f) == 0x03) - return; /* Already on and enabled */ - - *mdctl |= 0x03; - - /* Special treatment for some modules as for sprue14 p.7.4.2 */ - switch (id) { - case DAVINCI_LPSC_VPSSSLV: - case DAVINCI_LPSC_EMAC: - case DAVINCI_LPSC_EMAC_WRAPPER: - case DAVINCI_LPSC_MDIO: - case DAVINCI_LPSC_USB: - case DAVINCI_LPSC_ATA: - case DAVINCI_LPSC_VLYNQ: - case DAVINCI_LPSC_UHPI: - case DAVINCI_LPSC_DDR_EMIF: - case DAVINCI_LPSC_AEMIF: - case DAVINCI_LPSC_MMC_SD: - case DAVINCI_LPSC_MEMSTICK: - case DAVINCI_LPSC_McBSP: - case DAVINCI_LPSC_GPIO: - *mdctl |= 0x200; - break; - } - - REG(PSC_PTCMD) = 0x01; - - while (REG(PSC_PTSTAT) & 0x03); - while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ -} - -#if !defined(CFG_USE_DSPLINK) -void dsp_on(void) -{ - int i; - - if (REG(PSC_PDSTAT1) & 0x1f) - return; /* Already on */ - - REG(PSC_GBLCTL) |= 0x01; - REG(PSC_PDCTL1) |= 0x01; - REG(PSC_PDCTL1) &= ~0x100; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; - REG(PSC_PTCMD) = 0x02; - - for (i = 0; i < 100; i++) { - if (REG(PSC_EPCPR) & 0x02) - break; - } - - REG(PSC_CHP_SHRTSW) = 0x01; - REG(PSC_PDCTL1) |= 0x100; - REG(PSC_EPCCR) = 0x02; - - for (i = 0; i < 100; i++) { - if (!(REG(PSC_PTSTAT) & 0x02)) - break; - } - - REG(PSC_GBLCTL) &= ~0x1f; -} -#endif /* CFG_USE_DSPLINK */ - int board_init(void) { /* arch number of the board */ @@ -172,8 +91,10 @@ int board_init(void) return(0); } -/* Read ethernet MAC address from Integrity data structure inside EEPROM. */ -int read_mac_address(uint8_t *buf) +/* Read ethernet MAC address from Integrity data structure inside EEPROM. + * Returns 1 if found, 0 otherwise. + */ +static int sffsdr_read_mac_address(uint8_t *buf) { u_int32_t value, mac[2], address; @@ -182,7 +103,7 @@ int read_mac_address(uint8_t *buf) CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) goto err; if (value != INTEGRITY_CHECKWORD_VALUE) - return 1; + return 0; /* Read SYSCFG structure offset. */ if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET, @@ -216,30 +137,23 @@ int read_mac_address(uint8_t *buf) buf[4] = mac[1] >> 24; buf[5] = mac[1] >> 16; - return 0; + return 1; /* Found */ err: printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR); - return 1; + return 0; } /* Platform dependent initialisation. */ int misc_init_r(void) { - int i; - u_int8_t i2cbuf; - u_int8_t env_enetaddr[6], eeprom_enetaddr[6]; - char *tmp = getenv("ethaddr"); - char *end; - int clk; + uint8_t i2cbuf; + uint8_t eeprom_enetaddr[6]; /* EMIF-A CS3 configuration for FPGA. */ REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL; - clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); - - printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2); - printf("DDR Clock: %dMHz\n", (clk / 2)); + dv_display_clk_infos(); /* Configure I2C switch (PCA9543) to enable channel 0. */ i2cbuf = CFG_I2C_PCA9543_ENABLE_CH0; @@ -249,43 +163,9 @@ int misc_init_r(void) return 1; } - /* Read Ethernet MAC address from the U-Boot environment. */ - for (i = 0; i < 6; i++) { - env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - - /* Read Ethernet MAC address from EEPROM. */ - if (read_mac_address(eeprom_enetaddr) == 0) { - if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 && - memcmp(env_enetaddr, eeprom_enetaddr, 6) != 0) { - printf("\nWarning: MAC addresses don't match:\n"); - printf("\tHW MAC address: " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - eeprom_enetaddr[0], eeprom_enetaddr[1], - eeprom_enetaddr[2], eeprom_enetaddr[3], - eeprom_enetaddr[4], eeprom_enetaddr[5]); - printf("\t\"ethaddr\" value: " - "%02X:%02X:%02X:%02X:%02X:%02X\n", - env_enetaddr[0], env_enetaddr[1], - env_enetaddr[2], env_enetaddr[3], - env_enetaddr[4], env_enetaddr[5]) ; - debug("### Set MAC addr from environment\n"); - memcpy(eeprom_enetaddr, env_enetaddr, 6); - } - if (!tmp) { - char ethaddr[20]; - - sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", - eeprom_enetaddr[0], eeprom_enetaddr[1], - eeprom_enetaddr[2], eeprom_enetaddr[3], - eeprom_enetaddr[4], eeprom_enetaddr[5]) ; - debug("### Set environment from HW MAC addr = \"%s\"\n", - ethaddr); - setenv("ethaddr", ethaddr); - } - } + /* Read Ethernet MAC address from EEPROM if available. */ + if (sffsdr_read_mac_address(eeprom_enetaddr)) + dv_configure_mac_address(eeprom_enetaddr); if (!eth_hw_init()) printf("Ethernet init failed\n"); @@ -296,11 +176,3 @@ int misc_init_r(void) return(0); } - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return(0); -} diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c index a6f9bc7..a6fe825 100644 --- a/board/davinci/sonata/dv_board.c +++ b/board/davinci/sonata/dv_board.c @@ -25,92 +25,13 @@ */ #include <common.h> -#include <i2c.h> #include <asm/arch/hardware.h> #include <asm/arch/emac_defs.h> +#include "../common/psc.h" +#include "../common/misc.h" DECLARE_GLOBAL_DATA_PTR; -extern void timer_init(void); -extern int eth_hw_init(void); - - -/* Works on Always On power domain only (no PD argument) */ -void lpsc_on(unsigned int id) -{ - dv_reg_p mdstat, mdctl; - - if (id >= DAVINCI_LPSC_GEM) - return; /* Don't work on DSP Power Domain */ - - mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); - mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); - - while (REG(PSC_PTSTAT) & 0x01) {;} - - if ((*mdstat & 0x1f) == 0x03) - return; /* Already on and enabled */ - - *mdctl |= 0x03; - - /* Special treatment for some modules as for sprue14 p.7.4.2 */ - if ( (id == DAVINCI_LPSC_VPSSSLV) || - (id == DAVINCI_LPSC_EMAC) || - (id == DAVINCI_LPSC_EMAC_WRAPPER) || - (id == DAVINCI_LPSC_MDIO) || - (id == DAVINCI_LPSC_USB) || - (id == DAVINCI_LPSC_ATA) || - (id == DAVINCI_LPSC_VLYNQ) || - (id == DAVINCI_LPSC_UHPI) || - (id == DAVINCI_LPSC_DDR_EMIF) || - (id == DAVINCI_LPSC_AEMIF) || - (id == DAVINCI_LPSC_MMC_SD) || - (id == DAVINCI_LPSC_MEMSTICK) || - (id == DAVINCI_LPSC_McBSP) || - (id == DAVINCI_LPSC_GPIO) - ) - *mdctl |= 0x200; - - REG(PSC_PTCMD) = 0x01; - - while (REG(PSC_PTSTAT) & 0x03) {;} - while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ -} - -void dsp_on(void) -{ - int i; - - if (REG(PSC_PDSTAT1) & 0x1f) - return; /* Already on */ - - REG(PSC_GBLCTL) |= 0x01; - REG(PSC_PDCTL1) |= 0x01; - REG(PSC_PDCTL1) &= ~0x100; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; - REG(PSC_PTCMD) = 0x02; - - for (i = 0; i < 100; i++) { - if (REG(PSC_EPCPR) & 0x02) - break; - } - - REG(PSC_CHP_SHRTSW) = 0x01; - REG(PSC_PDCTL1) |= 0x100; - REG(PSC_EPCCR) = 0x02; - - for (i = 0; i < 100; i++) { - if (!(REG(PSC_PTSTAT) & 0x02)) - break; - } - - REG(PSC_GBLCTL) &= ~0x1f; -} - - int board_init(void) { /* arch number of the board */ @@ -131,8 +52,10 @@ int board_init(void) lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); +#if !defined(CFG_USE_DSPLINK) /* Powerup the DSP */ dsp_on(); +#endif /* CFG_USE_DSPLINK */ /* Bringup UART0 out of reset */ REG(UART0_PWREMU_MGMT) = 0x0000e003; @@ -157,43 +80,18 @@ int board_init(void) return(0); } -int misc_init_r (void) +int misc_init_r(void) { - u_int8_t tmp[20], buf[10]; - int i = 0; - int clk = 0; + uint8_t eeprom_enetaddr[6]; + dv_display_clk_infos(); - clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); - - printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); - printf ("DDR Clock : %dMHz\n", (clk / 2)); - - /* Set Ethernet MAC address from EEPROM */ - if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { - printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); - } else { - tmp[0] = 0xff; - for (i = 0; i < 6; i++) - tmp[0] &= buf[i]; - - if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { - sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x", - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); - setenv("ethaddr", (char *)&tmp[0]); - } - } + /* Read Ethernet MAC address from EEPROM if available. */ + if (dvevm_read_mac_address(eeprom_enetaddr)) + dv_configure_mac_address(eeprom_enetaddr); if (!eth_hw_init()) printf("ethernet init failed!\n"); return(0); } - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return(0); -}

1 0

[U-Boot-Users] [PATCH 2/2] 83xx: mpc8315erdb: add support for switching between ULPI/UTMI USB PHYs
by Anton Vorontsov 11 Jul '08

11 Jul '08

Freescale ships MPC8315E-RDB boards either with TSEC1 and USB UTMI support, or without TSEC1 but with USB ULPI PHY support in addition. With this patch user can specify desired USB PHY. Also, it seems that we can't distinguish the two boards in software, so user have to set `mpc8315erdb' environment variable to either 'tsec1' (TSEC1 enabled) or `ulpi' (board with ULPI PHY, TSEC1 disabled), so that Linux will not probe for TSEC1. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- board/freescale/mpc8315erdb/mpc8315erdb.c | 38 +++++++++++++++++++++++++++- include/configs/MPC8315ERDB.h | 2 + 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index 7af36dd..7555ffb 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -25,9 +25,8 @@ #include <common.h> #include <i2c.h> -#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> -#endif +#include <fdt_support.h> #include <pci.h> #include <mpc83xx.h> @@ -122,11 +121,46 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) +void fdt_tsec1_fixup(void *fdt, bd_t *bd) +{ + char *mpc8315erdb = getenv("mpc8315erdb"); + const char disabled[] = "disabled"; + const char *path; + int ret; + + if (!mpc8315erdb) { + if (!strcmp(mpc8315erdb, "tsec1")) { + return; + } else if (strcmp(mpc8315erdb, "ulpi")) { + printf("WARNING: wrong `mpc8315erdb' environment " + "variable specified: `%s'. Should be `ulpi' " + "or `tsec1'.\n", mpc8315erdb); + return; + } + } + + ret = fdt_path_offset(fdt, "/aliases"); + if (ret < 0) { + printf("WARNING: can't find /aliases node\n"); + return; + } + + path = fdt_getprop(fdt, ret, "ethernet0", NULL); + if (!path) { + printf("WARNING: can't find ethernet0 alias\n"); + return; + } + + do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1); +} + void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + fdt_fixup_dr_usb(blob, bd); + fdt_tsec1_fixup(blob, bd); } #endif diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 095f665..6b019f8 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -321,6 +321,8 @@ #define CONFIG_NET_MULTI 1 #endif +#define CONFIG_HAS_FSL_DR_USB + /* * TSEC */ -- 1.5.5.4

2 2

[U-Boot-Users] [PATCH v2] fdt: add crypto node handling for MPC8{3, 5}xxE processors
by Kim Phillips 11 Jul '08

11 Jul '08

crypto node if not on an E-processor. If on 8360 or 834x family, check rev and up-rev crypto node (to SEC rev. 2.4 property values) if on an 'EA' processor, e.g. MPC8349EA. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- change since v1: mpc85xx IS_E_PROCESSOR(svr) definition changed to (svr & 0x80000). (I'm not sure, but I think this goes through WD directly) common/fdt_support.c | 87 +++++++++++++++++++++++++++++++++++++++++++ cpu/mpc83xx/fdt.c | 18 +++++++++ cpu/mpc85xx/fdt.c | 6 +++ include/asm-ppc/processor.h | 9 ++++ include/fdt_support.h | 6 +++ include/mpc83xx.h | 7 +++- 6 files changed, 132 insertions(+), 1 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 7507744..c5b4650 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -447,3 +447,90 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) prop, compat, fdt_strerror(err)); } #endif /* CONFIG_HAS_FSL_DR_USB */ + +#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) +/* + * update crypto node properties to a specified revision of the SEC + * called with sec_rev == 0 if not on an mpc8xxxE processor + */ +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + const struct sec_rev_prop { + u32 sec_rev; + u32 num_channels; + u32 channel_fifo_len; + u32 exec_units_mask; + u32 descriptor_types_mask; + } sec_rev_prop_list [] = { + { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ + { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ + { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ + { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ + { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ + { 0x0303, 4, 24, 0x97c, 0x03ab0abf }, /* SEC 3.3 */ + }; + char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) * + sizeof("fsl,secX.Y")]; + int crypto_node, sec_idx, err; + char *p; + u32 val; + + /* locate crypto node based on lowest common compatible */ + crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0"); + if (crypto_node == -FDT_ERR_NOTFOUND) + return; + + /* delete it if not on an E-processor */ + if (crypto_node > 0 && !sec_rev) { + fdt_del_node(blob, crypto_node); + return; + } + + /* else we got called for possible uprev */ + for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++) + if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev) + break; + + if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) { + puts("warning: unknown SEC revision number\n"); + return; + } + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); + err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); + err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); + err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); + err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = 0; + while (sec_idx >= 0) { + p = compat_strlist + val; + val += sprintf(p, "fsl,sec%d.%d", + (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8, + sec_rev_prop_list[sec_idx].sec_rev & 0x00ff); + sec_idx--; + } + err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); +} +#endif /* defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) */ diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index 02c4d05..267ae6a 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -26,6 +26,7 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/processor.h> extern void ft_qe_setup(void *blob); @@ -33,6 +34,23 @@ DECLARE_GLOBAL_DATA_PTR; void ft_cpu_setup(void *blob, bd_t *bd) { + immap_t *immr = (immap_t *)CFG_IMMR; + int spridr = immr->sysconf.spridr; + + /* + * delete crypto node if not on an E-processor + * initial revisions of the MPC834xE/6xE have the original SEC 2.0. + * EA revisions got the SEC uprevved to 2.4 but since the default device + * tree contains SEC 2.0 properties we uprev them here. + */ + if (!IS_E_PROCESSOR(spridr)) + fdt_fixup_crypto_node(blob, 0); + else if (IS_E_PROCESSOR(spridr) && + (SPR_FAMILY(spridr) == SPR_834X_FAMILY || + SPR_FAMILY(spridr) == SPR_836X_FAMILY) && + REVID_MAJOR(spridr) >= 2) + fdt_fixup_crypto_node(blob, 0x0204); + #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob, bd); diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index bb87740..aac74ac 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -26,8 +26,10 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/processor.h> extern void ft_qe_setup(void *blob); + #ifdef CONFIG_MP #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -79,6 +81,10 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) void ft_cpu_setup(void *blob, bd_t *bd) { + /* delete crypto node if not on an E-processor */ + if (!IS_E_PROCESSOR(get_svr())) + fdt_fixup_crypto_node(blob, 0); + #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob, bd); diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 8bdfb9d..4580f3a 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -883,6 +883,15 @@ /* Some parts define SVR[0:23] as the SOC version */ #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ +/* whether MPC8xxxE (i.e. has SEC) */ +#if defined(CONFIG_MPC85xx) +#define IS_E_PROCESSOR(svr) (svr & 0x80000) +#else +#if defined(CONFIG_MPC83XX) +#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) +#endif +#endif + /* * SVR_SOC_VER() Version Values */ diff --git a/include/fdt_support.h b/include/fdt_support.h index 890993f..a7c6326 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -56,6 +56,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd); static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {} #endif /* CONFIG_HAS_FSL_DR_USB */ +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83XX) +void fdt_fixup_crypto_node(void *blob, int sec_rev); +#else +static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {} +#endif + #ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); void ft_cpu_setup(void *blob, bd_t *bd); diff --git a/include/mpc83xx.h b/include/mpc83xx.h index d2e1e2b..1e8a641 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -60,21 +60,26 @@ #endif #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) -#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) /* has SEC */ +#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) +#define SPR_831X_FAMILY 0x80B #define SPR_8311 0x80B2 #define SPR_8313 0x80B0 #define SPR_8314 0x80B6 #define SPR_8315 0x80B4 +#define SPR_832X_FAMILY 0x806 #define SPR_8321 0x8066 #define SPR_8323 0x8062 +#define SPR_834X_FAMILY 0x803 #define SPR_8343 0x8036 #define SPR_8347_TBGA_ 0x8032 #define SPR_8347_PBGA_ 0x8034 #define SPR_8349 0x8030 +#define SPR_836X_FAMILY 0x804 #define SPR_8358_TBGA_ 0x804A #define SPR_8358_PBGA_ 0x804E #define SPR_8360 0x8048 +#define SPR_837X_FAMILY 0x80C #define SPR_8377 0x80C6 #define SPR_8378 0x80C4 #define SPR_8379 0x80C2 -- 1.5.6.rc0.84.g06f60

4 7

[U-Boot-Users] No ethernet link on Lubbock board.
by Victor 11 Jul '08

11 Jul '08

This is a problem I've been fighting to for a long time. I'm sure it would be something stupid I haven't noticed, but I don't know what else to try. My Linux OS is working flawlessly with a correct eth0 device, so at least I know it's not (or should not) a hardware problem. Everything else works as expected, but the LAN91C96 driver does not enable the board network interface. Environment: Hardware: Lubbock Board from Intel, wired to an IBM Laptop. U-boot version: 1.3.3 (tried with 1.3.1, 1.20, same results) mac address: tried with the one generated by the eth_gen_tool, and the original hardware one. Default 'lubbock.h' file, heavy edited one, etc... No luck. $ printenv: U-Boot 1.3.3 (Jul 8 2008 - 19:07:01) DRAM: 64 MB Flash: 64 MB Hit any key to stop autoboot: 0 $ printenv baudrate=115200 netmask=255.255.0.0 bootdelay=5 serverip=192.168.1.1 ipaddr=192.168.1.2 bootcmd=bootm 200000 bootargs=ip=192.168.1.2:192.168.1.1:192.168.1.1:255.255.255.0:pxa:eth0:off mem=64M root=/dev/nfs nfsroot=192.168.1.1:/rootfs/nfs init=/sbin/init console=ttyS0,115200 ethaddr=00:02:b3:00:8f:xx stdin=serial stdout=serial stderr=serial Something odd I noticed: $ tftpboot Warning: MAC addresses don't match: HW MAC address: 01:00:01:00:01:00 "ethaddr" value: 00:02:B3:00:8F:xx Using MAC Address 00:02:B3:00:8F:xx Linux detects the correct Mac Address without any configuration, why u-boot reads 01:00:01:00:01:00? Any idea? I will thank a lubbock.h file in case you got one with ethernet working, just to try it out. Thanks a lot.

3 7

[U-Boot-Users] [PATCH] Round the serial port clock divisor value returned by calc_divisor()
by Jerry Van Baren 11 Jul '08

11 Jul '08

This formula is better at avoiding integer overflow. Signed-off-by: Gerald Van Baren <vanbaren(a)cideas.com> --- (try 2) The formula I proposed previously in this thread compiles OK. I cannot verify it is correct on real hardware, however. <http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/43499/focus=43506> Best regards, gvb drivers/serial/serial.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 182ca2d..48579ae 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -150,7 +150,9 @@ static int calc_divisor (NS16550_t port) * but we need to round that value by adding 0.5 or 8/16. * Rounding is especially important at high baud rates. */ - return (((16 * CFG_NS16550_CLK) / MODE_X_DIV / gd->baudrate) + 8) / 16; + return (CFG_NS16550_CLK + (gd->baudrate / 2)) / + (MODE_X_DIV * gd->baudrate); + } #if !defined(CONFIG_SERIAL_MULTI) -- 1.5.6

3 2

[U-Boot-Users] [PATCH] ML507: New board support
by Ricardo Ribalda Delgado 11 Jul '08

11 Jul '08

-Suport for the Xilinx ML507 Development Board Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)uam.es> --- Makefile | 3 + board/xilinx/ml507/Makefile | 53 ++++++++++++ board/xilinx/ml507/config.mk | 18 ++++ board/xilinx/ml507/init.S | 45 +++++++++++ board/xilinx/ml507/ml507.c | 57 +++++++++++++ board/xilinx/ml507/u-boot.lds | 149 +++++++++++++++++++++++++++++++++++ board/xilinx/ml507/u-boot.lds.debug | 136 ++++++++++++++++++++++++++++++++ board/xilinx/ml507/xparameters.h | 33 ++++++++ include/configs/ml507.h | 108 +++++++++++++++++++++++++ 9 files changed, 602 insertions(+), 0 deletions(-) create mode 100644 board/xilinx/ml507/Makefile create mode 100644 board/xilinx/ml507/config.mk create mode 100644 board/xilinx/ml507/init.S create mode 100644 board/xilinx/ml507/ml507.c create mode 100644 board/xilinx/ml507/u-boot.lds create mode 100644 board/xilinx/ml507/u-boot.lds.debug create mode 100644 board/xilinx/ml507/xparameters.h create mode 100644 include/configs/ml507.h diff --git a/Makefile b/Makefile index 6a734d1..2696ac6 100644 --- a/Makefile +++ b/Makefile @@ -1337,6 +1337,9 @@ ML2_config: unconfig ml300_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx +ml507_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml507 xilinx + ocotea_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile new file mode 100644 index 0000000..3708e43 --- /dev/null +++ b/board/xilinx/ml507/Makefile @@ -0,0 +1,53 @@ +# (C) Copyright 2008 +# Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es +# Work supported supported by: Q-Technology http://qtec.com/ +# based on Makefile by Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +endif + +INCS := +CFLAGS += $(INCS) +HOST_CFLAGS += $(INCS) + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o \ + +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/ml507/config.mk b/board/xilinx/ml507/config.mk new file mode 100644 index 0000000..d9a805f --- /dev/null +++ b/board/xilinx/ml507/config.mk @@ -0,0 +1,18 @@ +# (C) Copyright 2008 +# Ricado Ribalda, Universidad Autonoma de Madrid, ricardo.ribalda<at>uam.es , ricardo.ribalda<at>gmail.com +# Work supported supported by: Q-Technology http://qtec.com/ +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +TEXT_BASE = 0x04000000 diff --git a/board/xilinx/ml507/init.S b/board/xilinx/ml507/init.S new file mode 100644 index 0000000..34ee5ed --- /dev/null +++ b/board/xilinx/ml507/init.S @@ -0,0 +1,45 @@ +/* + (C) Copyright 2008 + Ricado Ribalda, Universidad Autonoma de Madrid, ricardo.ribalda<at>uam.es , ricardo.ribalda<at>gmail.com + This work has been supported by: Q-Technology http://qtec.com/ + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm-ppc/mmu.h> + +.section .bootpg,"ax" +.globl tlbtab + +tlbtab: +tlbtab_start + /* SDRAM */ +tlbentry(XPAR_DDR2_SDRAM_MEM_BASEADDR, SZ_256M, CFG_SDRAM_BASE, 0, + AC_R | AC_W | AC_X | SA_G | SA_I) + /* UART */ +tlbentry(XPAR_RS232_UART_1_BASEADDR, SZ_64K, XPAR_RS232_UART_1_BASEADDR, 0, + AC_R | AC_W | SA_G | SA_I) + /* PIC */ +tlbentry(XPAR_INTC_0_BASEADDR, SZ_64K, XPAR_INTC_0_BASEADDR, 0, + AC_R | AC_W | SA_G | SA_I) + /* I2C */ +tlbentry(XPAR_IIC_EEPROM_BASEADDR, SZ_64K, XPAR_IIC_EEPROM_BASEADDR, 0, + AC_R | AC_W | SA_G | SA_I) + /* Net */ +tlbentry(XPAR_LLTEMAC_0_BASEADDR, SZ_64K, XPAR_LLTEMAC_0_BASEADDR, 0, + AC_R | AC_W | SA_G | SA_I) + +tlbtab_end diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c new file mode 100644 index 0000000..27c87cc --- /dev/null +++ b/board/xilinx/ml507/ml507.c @@ -0,0 +1,57 @@ +/* + (C) Copyright 2008 + Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es + This work has been supported by: QTechnology http://qtec.com/ + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <config.h> +#include <common.h> +#include <asm/processor.h> + +int board_pre_init(void) +{ + return 0; +} + +int checkboard(void) +{ + + printf + ("ML507 Board ported by Ricardo Ribalda ricardo.ribalda(a)uam.es (http://qtec.com) \n"); + return (0); +} + +phys_size_t initdram(int board_type) +{ + return 256 * 1024 * 1024; +} + +int testdram(void) +{ + printf("test: xxx MB - ok\n"); + + return (0); +} + +void get_sys_info(sys_info_t * sysInfo) +{ + sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sysInfo->freqPCI = 0; + + return; + +} diff --git a/board/xilinx/ml507/u-boot.lds b/board/xilinx/ml507/u-boot.lds new file mode 100644 index 0000000..054661c --- /dev/null +++ b/board/xilinx/ml507/u-boot.lds @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * Modified by: Ricardo Ribalda Delgado ricardo.ribalda<at>gmail.com ricardo.ribalda<at>uam.es + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +ENTRY(_start_440) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ +/* + cpu/ppc4xx/start.o (.text) + board/xilinx/ml300/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) +*/ +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xilinx/ml507/u-boot.lds.debug b/board/xilinx/ml507/u-boot.lds.debug new file mode 100644 index 0000000..0552994 --- /dev/null +++ b/board/xilinx/ml507/u-boot.lds.debug @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h new file mode 100644 index 0000000..ba47349 --- /dev/null +++ b/board/xilinx/ml507/xparameters.h @@ -0,0 +1,33 @@ +/* + (C) Copyright 2008 + Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es + This work has been supported by: QTechnology http://qtec.com/ + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_RS232_UART_1_BASEADDR 0x84000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_LLTEMAC_0_BASEADDR 0x81c00000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 + +#endif diff --git a/include/configs/ml507.h b/include/configs/ml507.h new file mode 100644 index 0000000..bf1a78e --- /dev/null +++ b/include/configs/ml507.h @@ -0,0 +1,108 @@ +/* + (C) Copyright 2008 + Ricado Ribalda, Universidad Autonoma de Madrid, ricardo.ribalda<at>uam.es , ricardo.ribalda<at>gmail.com + This work has been supported by: Q-Technology http://qtec.com/ + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +/* +#define DEBUG +#define ET_DEBUG +*/ + /*CPU*/ +#define CONFIG_XILINX_ML507 1 +#define CONFIG_440_VIRTEX5 1 +#define CONFIG_440 1 +#define CONFIG_4xx 1 +#include "../board/xilinx/ml507/xparameters.h" +/*Mem Map*/ +#define CFG_SDRAM_BASE 0x0 /* _must_ be 0 */ +#define CFG_MONITOR_BASE 0x04000000 /* Start of U-Boot */ +#define CFG_MONITOR_LEN (192*1024) +#define CFG_MALLOC_LEN (128*1024) /* Reserved for malloc */ +#define CFG_ISRAM_BASE XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR +/*Uart*/ +#define CONFIG_XILINX_UARTLITE 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE {9600} +#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR +/*Cmd*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_REGINFO +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_IMLS +/*Env*/ +#define CFG_ENV_IS_NOWHERE +#define CFG_ENV_SIZE 0x200 +#define CFG_ENV_OFFSET 0x100 +/*#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)*/ +/*#define CFG_ENV_ADDR 0x01000000*/ +#define CFG_NO_FLASH +/*Misc*/ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "board:/# " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" +/*Stack*/ +#define CFG_INIT_RAM_ADDR 0x800000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/*Speed*/ +#define CONFIG_SYS_CLK_FREQ 400000000 +#endif /* __CONFIG_H */ -- 1.5.6.2

4 3

[U-Boot-Users] [PATCH v2] PPC4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM Controller
by Grant Erickson 11 Jul '08

11 Jul '08

This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM controller registers (MODT and INITPLR) used by the PowerPC405EX(r). The MMODE and MEMODE registers are unified with their peer values used for the INITPLR MR and EMR registers, respectively. Finally, a spelling typo is correct (MANUEL to MANUAL). With these mnemonics in place, the CFG_SDRAM0_* magic numbers for Kilauea are replaced by equivalent mnemonics to make it easier to compare and contrast other 405EX(r)-based boards (e.g. during board bring-up). Finally, unified the SDRAM controller register dump routine such that it can be used across all processor variants that utilize the IBM DDR2 SDRAM controller core. It produces output of the form: PPC4xx IBM DDR2 Register Dump: ... SDRAM_MB0CF[40] = 0x00006701 ... which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included since it is not uncommon that the DCR values in header files get mixed up and it helps to validate, at a glance, they match what is printed in the user manual. Tested on: AMCC Kilauea/Haleakala: - NFS Linux Boot: PASSED - NAND Linux Boot: PASSED Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> --- cpu/ppc4xx/44x_spd_ddr2.c | 262 +++++++++++++------------------------ include/asm-ppc/ppc4xx-sdram.h | 279 ++++++++++++++++++++++++++++++++-------- include/configs/kilauea.h | 145 ++++++++++++++++----- 3 files changed diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index c28fc46..ef078b6 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -50,6 +50,8 @@ #include "ecc.h" +static void ppc4xx_ibm_ddr2_register_dump(void); + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT)) @@ -243,7 +245,6 @@ static void test(void); #else static void DQS_calibration_process(void); #endif -static void ppc440sp_sdram_register_dump(void); int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); void dcbz_area(u32 start_address, u32 num_bytes); @@ -586,7 +587,7 @@ phys_size_t initdram(int board_type) remove_tlb(0, dram_size); program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); - ppc440sp_sdram_register_dump(); + ppc4xx_ibm_ddr2_register_dump(); /* * Clear potential errors resulting from auto-calibration. @@ -2726,7 +2727,7 @@ calibration_loop: printf("\nERROR: Cannot determine a common read delay for the " "DIMM(s) installed.\n"); debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__); - ppc440sp_sdram_register_dump(); + ppc4xx_ibm_ddr2_register_dump(); spd_ddr_init_hang (); } @@ -2912,168 +2913,6 @@ static void test(void) } #endif -#if defined(DEBUG) -static void ppc440sp_sdram_register_dump(void) -{ - unsigned int sdram_reg; - unsigned int sdram_data; - unsigned int dcr_data; - - printf("\n Register Dump:\n"); - sdram_reg = SDRAM_MCSTAT; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MCSTAT = 0x%08X", sdram_data); - sdram_reg = SDRAM_MCOPT1; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MCOPT2; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data); - sdram_reg = SDRAM_MODT0; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MODT1; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MODT1 = 0x%08X", sdram_data); - sdram_reg = SDRAM_MODT2; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MODT3; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MODT3 = 0x%08X", sdram_data); - sdram_reg = SDRAM_CODT; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_CODT = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_VVPR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_VVPR = 0x%08X", sdram_data); - sdram_reg = SDRAM_OPARS; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_OPARS = 0x%08X\n", sdram_data); - /* - * OPAR2 is only used as a trigger register. - * No data is contained in this register, and reading or writing - * to is can cause bad things to happen (hangs). Just skip it - * and report NA - * sdram_reg = SDRAM_OPAR2; - * mfsdram(sdram_reg, sdram_data); - * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data); - */ - printf(" SDRAM_OPART = N/A "); - sdram_reg = SDRAM_RTR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_RTR = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MB0CF; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MB0CF = 0x%08X", sdram_data); - sdram_reg = SDRAM_MB1CF; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MB2CF; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MB2CF = 0x%08X", sdram_data); - sdram_reg = SDRAM_MB3CF; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR0; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR1; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR2; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR3; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR4; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR5; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR6; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR7; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR8; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR9; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR10; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR11; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR12; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR13; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_INITPLR14; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data); - sdram_reg = SDRAM_INITPLR15; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_RQDC; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_RQDC = 0x%08X", sdram_data); - sdram_reg = SDRAM_RFDC; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_RFDC = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_RDCC; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_RDCC = 0x%08X", sdram_data); - sdram_reg = SDRAM_DLCR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_DLCR = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_CLKTR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_CLKTR = 0x%08X", sdram_data); - sdram_reg = SDRAM_WRDTR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_SDTR1; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_SDTR1 = 0x%08X", sdram_data); - sdram_reg = SDRAM_SDTR2; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_SDTR3; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_SDTR3 = 0x%08X", sdram_data); - sdram_reg = SDRAM_MMODE; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MMODE = 0x%08X\n", sdram_data); - sdram_reg = SDRAM_MEMODE; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_MEMODE = 0x%08X", sdram_data); - sdram_reg = SDRAM_ECCCR; - mfsdram(sdram_reg, sdram_data); - printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data); - - dcr_data = mfdcr(SDRAM_R0BAS); - printf(" MQ0_B0BAS = 0x%08X", dcr_data); - dcr_data = mfdcr(SDRAM_R1BAS); - printf(" MQ1_B0BAS = 0x%08X\n", dcr_data); - dcr_data = mfdcr(SDRAM_R2BAS); - printf(" MQ2_B0BAS = 0x%08X", dcr_data); - dcr_data = mfdcr(SDRAM_R3BAS); - printf(" MQ3_B0BAS = 0x%08X\n", dcr_data); -} -#else /* !defined(DEBUG) */ -static void ppc440sp_sdram_register_dump(void) -{ -} -#endif /* defined(DEBUG) */ #elif defined(CONFIG_405EX) /*----------------------------------------------------------------------------- * Function: initdram @@ -3188,8 +3027,101 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_DDR_ECC) ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); #endif /* defined(CONFIG_DDR_ECC) */ + + ppc4xx_ibm_ddr2_register_dump(); #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ return (CFG_MBYTES_SDRAM << 20); } #endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */ + +static void ppc4xx_ibm_ddr2_register_dump(void) +{ +#if defined(DEBUG) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \ + do { \ + u32 data; \ + mfsdram(SDRAM_##mnemonic, data); \ + printf("%20s[%02x] = 0x%08X\n", \ + "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ + } while (0) + + printf("\nPPC4xx IBM DDR2 Register Dump:\n"); + +#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) + PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS); + PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS); + PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS); + PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS); +#endif /* (defined(CONFIG_440SP) || ... */ +#if defined(CONFIG_405EX) + PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL); + PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH); + PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ); + PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT); + PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA); +#endif /* defined(CONFIG_405EX) */ + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3); + PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT); +#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) + PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS); + /* + * OPART is only used as a trigger register. + * + * No data is contained in this register, and reading or writing + * to is can cause bad things to happen (hangs). Just skip it and + * report "N/A". + */ + printf("%20s = N/A\n", "SDRAM_OPART"); +#endif /* defined(CONFIG_440SP) || ... */ + PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC); + PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE); + PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR); +#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) + PPC4xx_IBM_DDR2_DUMP_REGISTER(CID); +#endif /* defined(CONFIG_440SP) || ... */ + PPC4xx_IBM_DDR2_DUMP_REGISTER(RID); + PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR); +#endif /* defined(DEBUG) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) */ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 83931f1..8a064df 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -523,7 +523,7 @@ * SDRAM Delay Line Calibration Register */ #define SDRAM_DLCR_DCLM_MASK 0x80000000 -#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 +#define SDRAM_DLCR_DCLM_MANUAL 0x80000000 #define SDRAM_DLCR_DCLM_AUTO 0x00000000 #define SDRAM_DLCR_DLCR_MASK 0x08000000 #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 @@ -539,59 +539,234 @@ #define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF) /* + * SDRAM Memory On Die Terimination Control Register + */ +#define SDRAM_MODT_ODTON_DISABLE PPC_REG_VAL(0, 0) +#define SDRAM_MODT_ODTON_ENABLE PPC_REG_VAL(0, 1) +#define SDRAM_MODT_EB1W_DISABLE PPC_REG_VAL(1, 0) +#define SDRAM_MODT_EB1W_ENABLE PPC_REG_VAL(1, 1) +#define SDRAM_MODT_EB1R_DISABLE PPC_REG_VAL(2, 0) +#define SDRAM_MODT_EB1R_ENABLE PPC_REG_VAL(2, 1) +#define SDRAM_MODT_EB0W_DISABLE PPC_REG_VAL(7, 0) +#define SDRAM_MODT_EB0W_ENABLE PPC_REG_VAL(7, 1) +#define SDRAM_MODT_EB0R_DISABLE PPC_REG_VAL(8, 0) +#define SDRAM_MODT_EB0R_ENABLE PPC_REG_VAL(8, 1) + +/* * SDRAM Controller On Die Termination Register */ -#define SDRAM_CODT_ODT_ON 0x80000000 -#define SDRAM_CODT_ODT_OFF 0x00000000 -#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 -#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 -#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 -#define SDRAM_CODT_DQS_MASK 0x00000010 -#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 -#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 -#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 -#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 +#define SDRAM_CODT_ODT_ON PPC_REG_VAL(0, 1) +#define SDRAM_CODT_ODT_OFF PPC_REG_VAL(0, 0) +#define SDRAM_CODT_RK1W_ON PPC_REG_VAL(1, 1) +#define SDRAM_CODT_RK1W_OFF PPC_REG_VAL(1, 0) +#define SDRAM_CODT_RK1R_ON PPC_REG_VAL(2, 1) +#define SDRAM_CODT_RK1R_OFF PPC_REG_VAL(2, 0) +#define SDRAM_CODT_RK0W_ON PPC_REG_VAL(7, 1) +#define SDRAM_CODT_RK0W_OFF PPC_REG_VAL(7, 0) +#define SDRAM_CODT_RK0R_ON PPC_REG_VAL(8, 1) +#define SDRAM_CODT_RK0R_OFF PPC_REG_VAL(8, 0) +#define SDRAM_CODT_ODTSH_NORMAL PPC_REG_VAL(10, 0) +#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END PPC_REG_VAL(10, 1) +#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START PPC_REG_VAL(10, 2) +#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER PPC_REG_VAL(10, 3) +#define SDRAM_CODT_CODTZ_75OHM PPC_REG_VAL(11, 0) +#define SDRAM_CODT_CKEG_ON PPC_REG_VAL(12, 1) +#define SDRAM_CODT_CKEG_OFF PPC_REG_VAL(12, 0) +#define SDRAM_CODT_CTLG_ON PPC_REG_VAL(13, 1) +#define SDRAM_CODT_CTLG_OFF PPC_REG_VAL(13, 0) +#define SDRAM_CODT_FBDG_ON PPC_REG_VAL(14, 1) +#define SDRAM_CODT_FBDG_OFF PPC_REG_VAL(14, 0) +#define SDRAM_CODT_FBRG_ON PPC_REG_VAL(15, 1) +#define SDRAM_CODT_FBRG_OFF PPC_REG_VAL(15, 0) +#define SDRAM_CODT_CKLZ_36OHM PPC_REG_VAL(18, 1) +#define SDRAM_CODT_CKLZ_18OHM PPC_REG_VAL(18, 0) +#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK PPC_REG_VAL(26, 1) +#define SDRAM_CODT_DQS_2_5_V_DDR1 PPC_REG_VAL(26, 0) +#define SDRAM_CODT_DQS_1_8_V_DDR2 PPC_REG_VAL(26, 1) +#define SDRAM_CODT_DQS_MASK PPC_REG_VAL(27, 1) +#define SDRAM_CODT_DQS_DIFFERENTIAL PPC_REG_VAL(27, 0) +#define SDRAM_CODT_DQS_SINGLE_END PPC_REG_VAL(27, 1) +#define SDRAM_CODT_CKSE_DIFFERENTIAL PPC_REG_VAL(28, 0) +#define SDRAM_CODT_CKSE_SINGLE_END PPC_REG_VAL(28, 1) +#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END PPC_REG_VAL(29, 1) +#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END PPC_REG_VAL(30, 1) +#define SDRAM_CODT_IO_HIZ PPC_REG_VAL(31, 0) +#define SDRAM_CODT_IO_NMODE PPC_REG_VAL(31, 1) + +/* + * SDRAM Initialization Preload Register + */ +#define SDRAM_INITPLR_ENABLE PPC_REG_VAL(0, 1) +#define SDRAM_INITPLR_DISABLE PPC_REG_VAL(0, 0) +#define SDRAM_INITPLR_IMWT_MASK PPC_REG_VAL(8, 0xFF) +#define SDRAM_INITPLR_IMWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(u32, \ + n)) \ + & 0xFF) +#define SDRAM_INITPLR_ICMD_MASK PPC_REG_VAL(12, 0x7) +#define SDRAM_INITPLR_ICMD_ENCODE(n) PPC_REG_VAL(12, \ + (static_cast(u32, \ + n)) \ + & 0x7) +#define SDRAM_INITPLR_IBA_MASK PPC_REG_VAL(15, 0x7) +#define SDRAM_INITPLR_IBA_ENCODE(n) PPC_REG_VAL(15, \ + (static_cast(u32, \ + n)) \ + & 0x7) +#define SDRAM_INITPLR_IMA_MASK PPC_REG_VAL(31, 0x7FFF) +#define SDRAM_INITPLR_IMA_ENCODE(n) PPC_REG_VAL(31, \ + (static_cast(u32, \ + n)) \ + & 0x7FFF) + +/* + * JEDEC DDR Initialization Commands + */ +#define JEDEC_CMD_NOP 7 +#define JEDEC_CMD_PRECHARGE 2 +#define JEDEC_CMD_REFRESH 1 +#define JEDEC_CMD_EMR 0 +#define JEDEC_CMD_READ 5 +#define JEDEC_CMD_WRITE 4 + +/* + * JEDEC Precharge Command Memory Address Arguments + */ +#define JEDEC_MA_PRECHARGE_ONE (0 << 10) +#define JEDEC_MA_PRECHARGE_ALL (1 << 10) + +/* + * JEDEC DDR EMR Command Bank Address Arguments + */ +#define JEDEC_BA_MR 0 +#define JEDEC_BA_EMR 1 +#define JEDEC_BA_EMR2 2 +#define JEDEC_BA_EMR3 3 + +/* + * JEDEC DDR Mode Register + */ +#define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12) +#define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12) +#define JEDEC_MA_MR_WR_MASK (0x7 << 9) +#define JEDEC_MA_MR_WR_DDR1 (0x0 << 9) +#define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9) +#define JEDEC_MA_MR_WR_DDR2_3_CYC (0x2 << 9) +#define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9) +#define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9) +#define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9) +#define JEDEC_MA_MR_DLL_RESET (1 << 8) +#define JEDEC_MA_MR_MODE_NORMAL (0 << 8) +#define JEDEC_MA_MR_MODE_TEST (1 << 8) +#define JEDEC_MA_MR_CL_MASK (0x7 << 4) +#define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4) +#define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4) +#define JEDEC_MA_MR_CL_DDR1_3_0_CLK (0x3 << 4) +#define JEDEC_MA_MR_CL_DDR2_2_0_CLK (0x2 << 4) +#define JEDEC_MA_MR_CL_DDR2_3_0_CLK (0x3 << 4) +#define JEDEC_MA_MR_CL_DDR2_4_0_CLK (0x4 << 4) +#define JEDEC_MA_MR_CL_DDR2_5_0_CLK (0x5 << 4) +#define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4) +#define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4) +#define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3) +#define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3) +#define JEDEC_MA_MR_BLEN_MASK (0x7 << 0) +#define JEDEC_MA_MR_BLEN_4 (2 << 0) +#define JEDEC_MA_MR_BLEN_8 (3 << 0) + +/* + * JEDEC DDR Extended Mode Register + */ +#define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12) +#define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12) +#define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12) +#define JEDEC_MA_EMR_RQDS_MASK (1 << 11) +#define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11) +#define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11) +#define JEDEC_MA_EMR_DQS_MASK (1 << 10) +#define JEDEC_MA_EMR_DQS_DISABLE (1 << 10) +#define JEDEC_MA_EMR_DQS_ENABLE (0 << 10) +#define JEDEC_MA_EMR_OCD_MASK (0x7 << 7) +#define JEDEC_MA_EMR_OCD_EXIT (0 << 7) +#define JEDEC_MA_EMR_OCD_ENTER (7 << 7) +#define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3) +#define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3) +#define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3) +#define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3) +#define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3) +#define JEDEC_MA_EMR_RTT_MASK (0x11 << 2) +#define JEDEC_MA_EMR_RTT_DISABLED (0x00 << 2) +#define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2) +#define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2) +#define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2) +#define JEDEC_MA_EMR_ODS_MASK (1 << 1) +#define JEDEC_MA_EMR_ODS_NORMAL (0 << 1) +#define JEDEC_MA_EMR_ODS_WEAK (1 << 1) +#define JEDEC_MA_EMR_DLL_MASK (1 << 0) +#define JEDEC_MA_EMR_DLL_ENABLE (0 << 0) +#define JEDEC_MA_EMR_DLL_DISABLE (1 << 0) + +/* + * JEDEC DDR Extended Mode Register 2 + */ +#define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7) +#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7) /* - * SDRAM Mode Register + * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register) */ -#define SDRAM_MMODE_WR_MASK 0x00000E00 -#define SDRAM_MMODE_WR_DDR1 0x00000000 -#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 -#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 -#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 -#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 -#define SDRAM_MMODE_DCL_MASK 0x00000070 -#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 -#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 -#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 +#define SDRAM_MMODE_WR_MASK JEDEC_MA_MR_WR_MASK +#define SDRAM_MMODE_WR_DDR1 JEDEC_MA_MR_WR_DDR1 +#define SDRAM_MMODE_WR_DDR2_2_CYC JEDEC_MA_MR_WR_DDR2_2_CYC +#define SDRAM_MMODE_WR_DDR2_3_CYC JEDEC_MA_MR_WR_DDR2_3_CYC +#define SDRAM_MMODE_WR_DDR2_4_CYC JEDEC_MA_MR_WR_DDR2_4_CYC +#define SDRAM_MMODE_WR_DDR2_5_CYC JEDEC_MA_MR_WR_DDR2_5_CYC +#define SDRAM_MMODE_WR_DDR2_6_CYC JEDEC_MA_MR_WR_DDR2_6_CYC +#define SDRAM_MMODE_DCL_MASK JEDEC_MA_MR_CL_MASK +#define SDRAM_MMODE_DCL_DDR1_2_0_CLK JEDEC_MA_MR_CL_DDR1_2_0_CLK +#define SDRAM_MMODE_DCL_DDR1_2_5_CLK JEDEC_MA_MR_CL_DDR1_2_5_CLK +#define SDRAM_MMODE_DCL_DDR1_3_0_CLK JEDEC_MA_MR_CL_DDR1_3_0_CLK +#define SDRAM_MMODE_DCL_DDR2_2_0_CLK JEDEC_MA_MR_CL_DDR2_2_0_CLK +#define SDRAM_MMODE_DCL_DDR2_3_0_CLK JEDEC_MA_MR_CL_DDR2_3_0_CLK +#define SDRAM_MMODE_DCL_DDR2_4_0_CLK JEDEC_MA_MR_CL_DDR2_4_0_CLK +#define SDRAM_MMODE_DCL_DDR2_5_0_CLK JEDEC_MA_MR_CL_DDR2_5_0_CLK +#define SDRAM_MMODE_DCL_DDR2_6_0_CLK JEDEC_MA_MR_CL_DDR2_6_0_CLK +#define SDRAM_MMODE_DCL_DDR2_7_0_CLK JEDEC_MA_MR_CL_DDR2_7_0_CLK +#define SDRAM_MMODE_BTYP_SEQUENTIAL JEDEC_MA_MR_BTYP_SEQUENTIAL +#define SDRAM_MMODE_BTYP_INTERLEAVED JEDEC_MA_MR_BTYP_INTERLEAVED +#define SDRAM_MMODE_BLEN_MASK JEDEC_MA_MR_BLEN_MASK +#define SDRAM_MMODE_BLEN_4 JEDEC_MA_MR_BLEN_4 +#define SDRAM_MMODE_BLEN_8 JEDEC_MA_MR_BLEN_8 /* - * SDRAM Extended Mode Register + * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended + * Mode Register) */ -#define SDRAM_MEMODE_DIC_MASK 0x00000002 -#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 -#define SDRAM_MEMODE_DIC_WEAK 0x00000002 -#define SDRAM_MEMODE_DLL_MASK 0x00000001 -#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 -#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 -#define SDRAM_MEMODE_RTT_MASK 0x00000044 -#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 -#define SDRAM_MEMODE_RTT_75OHM 0x00000004 -#define SDRAM_MEMODE_RTT_150OHM 0x00000040 -#define SDRAM_MEMODE_DQS_MASK 0x00000400 -#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 -#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 +#define SDRAM_MEMODE_QOFF_MASK JEDEC_MA_EMR_OUTPUT_MASK +#define SDRAM_MEMODE_QOFF_DISABLE JEDEC_MA_EMR_OUTPUT_DISABLE +#define SDRAM_MEMODE_QOFF_ENABLE JEDEC_MA_EMR_OUTPUT_ENABLE +#define SDRAM_MEMODE_RDQS_MASK JEDEC_MA_EMR_RQDS_MASK +#define SDRAM_MEMODE_RDQS_DISABLE JEDEC_MA_EMR_RDQS_DISABLE +#define SDRAM_MEMODE_RDQS_ENABLE JEDEC_MA_EMR_RDQS_ENABLE +#define SDRAM_MEMODE_DQS_MASK JEDEC_MA_EMR_DQS_MASK +#define SDRAM_MEMODE_DQS_DISABLE JEDEC_MA_EMR_DQS_DISABLE +#define SDRAM_MEMODE_DQS_ENABLE JEDEC_MA_EMR_DQS_ENABLE +#define SDRAM_MEMODE_AL_DDR1_0_CYC JEDEC_MA_EMR_AL_DDR1_0_CYC +#define SDRAM_MEMODE_AL_DDR2_1_CYC JEDEC_MA_EMR_AL_DDR2_1_CYC +#define SDRAM_MEMODE_AL_DDR2_2_CYC JEDEC_MA_EMR_AL_DDR2_2_CYC +#define SDRAM_MEMODE_AL_DDR2_3_CYC JEDEC_MA_EMR_AL_DDR2_3_CYC +#define SDRAM_MEMODE_AL_DDR2_4_CYC JEDEC_MA_EMR_AL_DDR2_4_CYC +#define SDRAM_MEMODE_RTT_MASK JEDEC_MA_EMR_RTT_MASK +#define SDRAM_MEMODE_RTT_DISABLED JEDEC_MA_EMR_RTT_DISABLED +#define SDRAM_MEMODE_RTT_75OHM JEDEC_MA_EMR_RTT_75OHM +#define SDRAM_MEMODE_RTT_150OHM JEDEC_MA_EMR_RTT_150OHM +#define SDRAM_MEMODE_RTT_50OHM JEDEC_MA_EMR_RTT_50OHM +#define SDRAM_MEMODE_DIC_MASK JEDEC_MA_EMR_ODS_MASK +#define SDRAM_MEMODE_DIC_NORMAL JEDEC_MA_EMR_ODS_NORMAL +#define SDRAM_MEMODE_DIC_WEAK JEDEC_MA_EMR_ODS_WEAK +#define SDRAM_MEMODE_DLL_MASK JEDEC_MA_EMR_DLL_MASK +#define SDRAM_MEMODE_DLL_DISABLE JEDEC_MA_EMR_DLL_DISABLE +#define SDRAM_MEMODE_DLL_ENABLE JEDEC_MA_EMR_DLL_ENABLE /* * SDRAM Clock Timing Register diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 9c1a3a4..f3d048c 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -233,39 +233,124 @@ #define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE #define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE #define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE -#define CFG_SDRAM0_MCOPT1 0x04322000 +#define CFG_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ + SDRAM_MCOPT1_8_BANKS | \ + SDRAM_MCOPT1_DDR2_TYPE | \ + SDRAM_MCOPT1_QDEP | \ + SDRAM_MCOPT1_DCOO_DISABLED) #define CFG_SDRAM0_MCOPT2 0x00000000 -#define CFG_SDRAM0_MODT0 0x01800000 +#define CFG_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ + SDRAM_MODT_EB0R_ENABLE) #define CFG_SDRAM0_MODT1 0x00000000 -#define CFG_SDRAM0_CODT 0x0080f837 -#define CFG_SDRAM0_RTR 0x06180000 -#define CFG_SDRAM0_INITPLR0 0xa8380000 -#define CFG_SDRAM0_INITPLR1 0x81900400 -#define CFG_SDRAM0_INITPLR2 0x81020000 -#define CFG_SDRAM0_INITPLR3 0x81030000 -#define CFG_SDRAM0_INITPLR4 0x81010404 -#define CFG_SDRAM0_INITPLR5 0x81000542 -#define CFG_SDRAM0_INITPLR6 0x81900400 -#define CFG_SDRAM0_INITPLR7 0x8D080000 -#define CFG_SDRAM0_INITPLR8 0x8D080000 -#define CFG_SDRAM0_INITPLR9 0x8D080000 -#define CFG_SDRAM0_INITPLR10 0x8D080000 -#define CFG_SDRAM0_INITPLR11 0x81000442 -#define CFG_SDRAM0_INITPLR12 0x81010780 -#define CFG_SDRAM0_INITPLR13 0x81010400 -#define CFG_SDRAM0_INITPLR14 0x00000000 -#define CFG_SDRAM0_INITPLR15 0x00000000 -#define CFG_SDRAM0_RQDC 0x80000038 -#define CFG_SDRAM0_RFDC 0x00000209 -#define CFG_SDRAM0_RDCC 0x40000000 -#define CFG_SDRAM0_DLCR 0x030000a5 -#define CFG_SDRAM0_CLKTR 0x80000000 +#define CFG_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ + SDRAM_CODT_CKLZ_36OHM | \ + SDRAM_CODT_DQS_1_8_V_DDR2 | \ + SDRAM_CODT_IO_NMODE) +#define CFG_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) +#define CFG_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(80) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) +#define CFG_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CFG_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) +#define CFG_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ + SDRAM_INITPLR_IMA_ENCODE(0)) +#define CFG_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_75OHM)) +#define CFG_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ + JEDEC_MA_MR_BLEN_4 | \ + JEDEC_MA_MR_DLL_RESET)) +#define CFG_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(0x0) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CFG_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ + JEDEC_MA_MR_BLEN_4)) +#define CFG_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_DISABLED | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CFG_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_DISABLED | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CFG_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) +#define CFG_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) +#define CFG_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ + SDRAM_RQDC_RQFD_ENCODE(56)) +#define CFG_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) +#define CFG_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) +#define CFG_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ + SDRAM_DLCR_DLCS_CONT_DONE | \ + SDRAM_DLCR_DLCV_ENCODE(165)) +#define CFG_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) #define CFG_SDRAM0_WRDTR 0x00000000 -#define CFG_SDRAM0_SDTR1 0x80201000 -#define CFG_SDRAM0_SDTR2 0x32204232 -#define CFG_SDRAM0_SDTR3 0x080b0d1a -#define CFG_SDRAM0_MMODE 0x00000442 -#define CFG_SDRAM0_MEMODE 0x00000404 +#define CFG_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ + SDRAM_SDTR1_RTW_2_CLK | \ + SDRAM_SDTR1_RTRO_1_CLK) +#define CFG_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ + SDRAM_SDTR2_WTR_2_CLK | \ + SDRAM_SDTR2_XSNR_32_CLK | \ + SDRAM_SDTR2_WPC_4_CLK | \ + SDRAM_SDTR2_RPC_2_CLK | \ + SDRAM_SDTR2_RP_3_CLK | \ + SDRAM_SDTR2_RRD_2_CLK) +#define CFG_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \ + SDRAM_SDTR3_RC_ENCODE(11) | \ + SDRAM_SDTR3_XCS | \ + SDRAM_SDTR3_RFC_ENCODE(26)) +#define CFG_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ + SDRAM_MMODE_DCL_DDR2_4_0_CLK | \ + SDRAM_MMODE_BLEN_4) +#define CFG_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ + SDRAM_MEMODE_RTT_75OHM) /*----------------------------------------------------------------------- * I2C -- 1.5.4.r

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