May 2008 - U-Boot

[U-Boot-Users] [Patch 11/17] U-Boot-V2:ARM:OMAP3: Add support for OMAP3 Silicon files
by Menon, Nishanth 04 Jun '08

04 Jun '08

This patch introduces support for OMAP3430 - provides for base OMAP3 files. Signed-off-by: Nishanth Menon<x0nishan(a)ti.com> --- arch/arm/mach-omap/Kconfig | 65 +++++ arch/arm/mach-omap/Makefile | 25 ++ arch/arm/mach-omap/omap3_core.S | 101 ++++++++ arch/arm/mach-omap/omap3_generic.c | 416 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap/syslib.c | 97 ++++++++ 5 files changed, 704 insertions(+) Index: u-boot-v2.git/arch/arm/mach-omap/Kconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/arch/arm/mach-omap/Kconfig 2008-05-20 18:10:50.000000000 -0500 @@ -0,0 +1,65 @@ +# +# OMAP Architecture specific features +# +# (C) Copyright 2008 +# Texas Instruments, <www.ti.com> +# Nishanth Menon <x0nishan(a)ti.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +menu "OMAP Features" + depends on ARCH_OMAP + +choice + prompt "Select OMAP Variant" + +config ARCH_OMAP3 + bool "OMAP3" + select ARMCORTEXA8 + select ARCH_HAS_LOWLEVEL_INIT + help + Say Y here if you are using Texas Instrument's OMAP343x based platform + +endchoice + +config OMAP_CONFIG_STACKSIZE + prompt "STACKSIZE" + hex + default 0x00020000 + help + Select the Stack Size + +config OMAP_MALLOC_LEN + prompt "MALLOC LENGTH" + hex + default 0x00001000 + help + Select the Malloc Length + +config ARCH_TEXT_BASE + prompt "ARCH TEXT BASE" + hex + default 0x80e80000 + help + Select the load address + +config OMAP3_CLOCK_CONFIG + depends on ARCH_OMAP + bool "Clock Configuration" + help + Say Y here if you like to have OMAP3 Clock configuration done. + +endmenu Index: u-boot-v2.git/arch/arm/mach-omap/Makefile =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/arch/arm/mach-omap/Makefile 2008-05-20 18:10:50.000000000 -0500 @@ -0,0 +1,25 @@ +# OMAP Architecture Makefile +# +# (C) Copyright 2008 +# Texas Instruments, <www.ti.com> +# Nishanth Menon <x0nishan(a)ti.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +obj-$(CONFIG_ARCH_OMAP) += syslib.o +obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o +obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o +obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock_core.o omap3_clock.o Index: u-boot-v2.git/arch/arm/mach-omap/omap3_core.S =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/arch/arm/mach-omap/omap3_core.S 2008-05-20 18:10:50.000000000 -0500 @@ -0,0 +1,101 @@ +/** + * @file + * @brief Provide Architecture level Initialization + * + * FileName: arch/arm/mach-omap/omap3_core.S + * + * This provides OMAP3 Architecture initialization. Among these, + * @li OMAP ROM Code is located in SRAM, we can piggy back on + * the same addresses + * @li If clock initialization is required, call the same. + * @li Setup a temporary SRAM stack which is necessary to call C + * functions. + * @li Call architecture initialization function a_init + * + * arch_init_lowlevel is enabled if CONFIG_ARCH_HAS_LOWLEVEL_INIT is defined + * cpy_clk_code is called if CONFIG_OMAP3_COPY_CLOCK_SRAM is defined + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/silicon.h> +#include <asm/arch/wdt.h> +#include <asm/arch/clocks.h> + +#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT +.globl arch_init_lowlevel +arch_init_lowlevel: + /* Copy vectors to mask ROM indirect addr */ + mov r0, pc /* Store the current pc address */ + sub r0, r0, #8 /* Reduce offset */ + ldr r1, arch_start /* Load the link address for arch_int */ + ldr r2, uboot_start /* load the link address of start_init*/ + sub r1, r1, r2 /* get the offset */ + /* subtract the offset from PC of arch=Current start */ + sub r0, r0, r1 + mov r2, #OMAP_SRAM_INTVECT_COPYSIZE /* r2 <- size to copy */ + add r2, r0, r2 /* r2 <- source end address */ + ldr r1, SRAM_INTVECT /* build vect addr */ +next: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + ble next /* loop until equal */ + +#ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM + /* No need to copy/exec the clock code - DPLL adjust already done + * in Perip/NAND/oneNAND Boot. + * Put dpll adjust code behind vectors. r1 has address to copy to + */ + bl cpy_clk_code +#endif + ldr r1, SRAM_INTVECT /* build vect addr */ + /* Read the interrupt vector base address */ + mrc p15, #0, r0, c12, c0, #0 + /* Clear the vector base 4:0 is reserved. */ + and r0, r0, #0xF + /* Store the SRAM_INTVECT address */ + orr r0, r0, r1 + /* Store the new vector address */ + mcr p15, #0, r0, c12, c0, #0 + /* Setup a temporary stack so that we can call C functions */ + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + str lr, [sp] /* stash current link register */ + mov ip, lr /* save link reg across call */ + bl a_init /* Architecture init */ + ldr lr, [sp] /* restore current link register */ + ldr ip, [sp] /* restore save ip */ + + /* back to arch calling code */ + mov pc, lr + +arch_start: + .word arch_init_lowlevel +uboot_start: + .word _start +SRAM_INTVECT: + .word OMAP_SRAM_INTVECT + +SRAM_STACK: + .word OMAP_SRAM_STACK +#endif /* CONFIG_ARCH_HAS_LOWLEVEL_INIT */ Index: u-boot-v2.git/arch/arm/mach-omap/omap3_generic.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/arch/arm/mach-omap/omap3_generic.c 2008-05-20 18:10:50.000000000 -0500 @@ -0,0 +1,416 @@ +/** + * @file + * @brief Provide Generic implementations for OMAP3 architecture + * + * FileName: arch/arm/mach-omap/omap3_generic.c + * + * This file contains the generic implementations of various OMAP3 + * relevant functions + * For more info on OMAP34XX, see http://focus.ti.com/pdfs/wtbu/swpu114g.pdf + * + * Important one is @ref a_init which is architecture init code. + * The implemented functions are present in sys_info.h + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <init.h> +#include <asm/io.h> +#include <asm/sizes.h> +#include <asm/arch/silicon.h> +#include <asm/arch/gpmc.h> +#include <asm/arch/sdrc.h> +#include <asm/arch/control.h> +#include <asm/arch/omap3-smx.h> +#include <asm/arch/clocks.h> +#include <asm/arch/wdt.h> +#include <asm/arch/sys_info.h> +#include <asm/arch/syslib.h> + +/** + * @brief Reset the CPU + * + * In case of crashes, reset the CPU + * + * @param[in] addr -Cause of crash + * + * @return void + */ +void reset_cpu(ulong addr) +{ + /* FIXME: Enable WDT and cause reset */ + hang(); +} +EXPORT_SYMBOL(reset_cpu); + +/** + * @brief Low level CPU type + * + * @return CPU_3430 + */ +u32 get_cpu_type(void) +{ + /* FIXME: need to get register defines for 3430 */ + return (CPU_3430); +} + +/** + * @brief Extract the OMAP ES rev + * + * @return CPU_ES version + */ +u32 get_cpu_rev(void) +{ + u32 idcode_val; + idcode_val = __raw_readl(IDCODE_REG); + if ((idcode_val & (HAWKEYE_MASK | VERSION_MASK)) == HAWKEYE_ES2_1) + return CPU_ES2P1; + if ((idcode_val & HAWKEYE_MASK) == HAWKEYE_ES2) + return CPU_ES2; + /* unsupported! */ + return CPU_ES1; +} + +/** + * @brief Get size of chip select 0/1 + * + * @param[in] offset give the offset if we need CS1 + * + * @return return the sdram size. + */ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + /* get ram size field */ + size = __raw_readl(SDRC_REG(MCFG_0) + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/** + * @brief Get the initial SYSBOOT value + * + * SYSBOOT is useful to know which state OMAP booted from. + * + * @return - Return the value of SYSBOOT. + */ +inline u32 get_sysboot_value(void) +{ + return (0x0000003F & __raw_readl(CONTROL_REG(STATUS))); +} + +/** + * @brief Return the current CS0 base address + * + * Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * + * @return base address + */ +u32 get_gpmc0_base(void) +{ + u32 b; + b = __raw_readl(GPMC_REG(CONFIG7_0)); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/** + * @brief Get the upper address of current execution + * + * we can use this to figure out if we are running in SRAM / + * XIP Flash or in SDRAM + * + * @return base address + */ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/** + * @brief Are we running in Flash XIP? + * + * If the base is in GPMC address space, we probably are! + * + * @return 1 if we are running in XIP mode, else return 0 + */ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/** + * @brief Are we running in OMAP internal SRAM? + * + * If in SRAM address, then yes! + * + * @return 1 if we are running in SRAM, else return 0 + */ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/** + * @brief Are we running in SDRAM? + * + * if we are not in GPMC nor in SRAM address space, + * we are in SDRAM execution area + * + * @return 1 if we are running from SDRAM, else return 0 + */ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} +EXPORT_SYMBOL(running_in_sdram); + +/** + * @brief Is this an XIP type device or a stream one + * + * Sysboot bits 4-0 specify type. Bit 5, sys mem/perif + * + * @return Boot type + */ +u32 get_boot_type(void) +{ + u32 v; + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + return v; +} + +/** + * @brief What type of device are we? + * + * are we on a GP/HS/EMU/TEST device? + * + * @return device type + */ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_REG(STATUS)) & (DEVICE_MASK); + return (mode >>= 8); +} + +/** + * @brief Setup security registers for access + * + * This can be done for GP Device only. for HS/EMU devices, read TRM. + * + * @return void + */ +static void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ +#define UNLOCK_1 0xFFFFFFFF +#define UNLOCK_2 0x00000000 +#define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT) */ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + +/** + * @brief Come out of secure mode + * If chip is EMU and boot type is external configure + * secure registers and exit secure world general use. + * + * @return void + */ +static void secureworld_exit(void) +{ + unsigned long i; + + /* configrue non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); + /* allow allocation of locked TLBs and L2 lines in NS world */ + /* allow use of PLE registers in NS world also */ + __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i)); + + /* Enable ASA in ACR register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i)); +} + +/** + * @brief Shut down the watchdogs + * + * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + * + * @return void + */ +static void watchdog_init(void) +{ + int pending = 1; + + sr32(CM_REG(FCLKEN_WKUP), 5, 1, 1); + sr32(CM_REG(ICLKEN_WKUP), 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_REG(IDLEST_WKUP), 5); + + __raw_writel(WDT_DISABLE_CODE1, WDT_REG(WSPR)); + + do { + pending = __raw_readl(WDT_REG(WWPS)); + } while (pending); + + __raw_writel(WDT_DISABLE_CODE2, WDT_REG(WSPR)); +} + +/** + * @brief Write to AuxCR desired value using SMI. + * general use. + * + * @return void + */ +static void setup_auxcr(void) +{ + unsigned long i; + volatile unsigned int j; + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* GP Device ROM code API usage here */ + /* r12 = AUXCR Write function and r0 value */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + /* Enabling ASA */ + __asm__ __volatile__("orr r0, r0, #0x10"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); +} + +/** + * @brief Try to unlock the SRAM for general use + * + * If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + * + * @return void + */ +static void try_unlock_memory(void) +{ + int mode; + int in_sdram = running_in_sdram(); + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T */ + mode = get_device_type(); + if (mode == GP_DEVICE) + secure_unlock_mem(); + /* If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/** + * @brief OMAP3 Architecture specific Initialization + * + * Does early system init of disabling the watchdog, enable + * memory and configuring the clocks. + * + * prcm_init is called only if CONFIG_OMAP3_CLOCK_CONFIG is defined. + * We depend on link time clean up to remove a_init if no caller exists. + * + * @warning Called path is with SRAM stack + * + * @return void + */ +void a_init(void) +{ + watchdog_init(); + + try_unlock_memory(); + + /* Writing to AuxCR in U-boot using SMI for GP DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + if (get_device_type() == GP_DEVICE) + setup_auxcr(); + + sdelay(100); + +#ifdef CONFIG_OMAP3_CLOCK_CONFIG + prcm_init(); +#endif + +} Index: u-boot-v2.git/arch/arm/mach-omap/syslib.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/arch/arm/mach-omap/syslib.c 2008-05-20 18:10:50.000000000 -0500 @@ -0,0 +1,97 @@ +/** + * @file + * @brief Provide OMAP independent utility APIs + * + * FileName: arch/arm/mach-omap/syslib.c + * + * Provide APIs which can be used from platform/architecture code + * to operate on + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/arch/syslib.h> + +/** + * @brief simple spin loop + * + * Will be constant time as its generally used in bypass conditions only. + * This is necessary until timers are accessible. if you need timed delays + * use @ref mdelay or @udelay instead + * + * @param[in] loops number of loops + * + * @return void + */ +void sdelay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/** + * @brief clear & set a value in a bit range for a 32 bit address + * + * @param[in] addr Address to set/read from + * @param[in] start_bit Where to put the value + * @param[in] num_bits number of bits the value should be set + * @param[in] value the value to set + * + * @return void + */ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/** + * @brief common routine to allow waiting for changes in volatile regs. + * + * @param[in] read_bit_mask the bit mask to read + * @param[in] match_value match to which value + * @param[in] read_addr address to read from + * @param[in] bound max iterations + * + * @return 1 if match_value is found, else if bound iterations reached, + * returns 0 + */ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} +

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[U-Boot-Users] [Patch 10/17] U-Boot-V2:ARM:OMAP3: Add support for OMAP and Cortex A8
by Menon, Nishanth 04 Jun '08

04 Jun '08

This patch adds support for OMAP3 platforms. This is mainly to setup the infrastructure. ARMV7 requires a different I/D cache cleanup code which is introduced in this patch. Thanks to Laurent in pointing out the Cortex-A8 D-Cache issue with my first rev patch. Signed-off-by: Nishanth Menon<x0nishan(a)ti.com> --- arch/arm/Kconfig | 24 ++++++++++++++++++++ arch/arm/Makefile | 6 +++++ arch/arm/cpu/Makefile | 1 arch/arm/cpu/start-arm.S | 54 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 84 insertions(+), 1 deletion(-) Index: u-boot-v2.git/arch/arm/Kconfig =================================================================== --- u-boot-v2.git.orig/arch/arm/Kconfig 2008-05-20 18:20:54.000000000 -0500 +++ u-boot-v2.git/arch/arm/Kconfig 2008-05-21 10:41:17.000000000 -0500 @@ -47,6 +47,9 @@ config ARM926EJS bool +config ARMCORTEXA8 + bool + # i.MX1, i.MXL, i.MX27 and i.MX31 are quite similar and thus # handled in one arch config ARCH_IMX @@ -74,6 +77,10 @@ bool select ARM926EJS +config ARCH_OMAP + bool +# ARM versions used varies on based on OMAP versions + choice prompt "Select your board" @@ -135,6 +142,13 @@ Say Y here if your are using Phytec's phyCORE-i.MX31 (pcm037) equipped with a Freescale i.MX31 Processor +config MACH_OMAP + bool "Texas Instruments' OMAP based platforms" + select ARCH_OMAP + select MACH_CAN_MODIFY_MALLOC_START + help + Say Y if you are using Texas Instrument's OMAP based platforms + endchoice config IMX_CLKO @@ -144,8 +158,9 @@ The i.MX SoCs have a Pin which can output different reference frequencies. Say y here if you want to have the clko command which lets you select the frequency to output on this pin. - + source arch/arm/mach-netx/Kconfig +source arch/arm/mach-omap/Kconfig menu "Arm specific settings " @@ -190,6 +205,13 @@ Provide the alternate malloc start address. Remember that the area that will be used will be (this address) to (this address - CFG_MALLOC_LEN - CONFIG_STACKSIZE) +config ARMCORTEXA8_DCACHE_SKIP + bool "Skip DCache Invlidate" + depends on ARMCORTEXA8 + default n + help + If your architecture configuration uses some other method of disabling caches, enable this + So that the D-Cache invalidation logic is skipped endmenu source common/Kconfig Index: u-boot-v2.git/arch/arm/Makefile =================================================================== --- u-boot-v2.git.orig/arch/arm/Makefile 2008-05-20 18:20:54.000000000 -0500 +++ u-boot-v2.git/arch/arm/Makefile 2008-05-20 18:20:54.000000000 -0500 @@ -6,6 +6,7 @@ machine-$(CONFIG_ARCH_IMX) := imx machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200 +machine-$(CONFIG_ARCH_OMAP) := omap board-$(CONFIG_MACH_MX1ADS) := mx1ads board-$(CONFIG_MACH_ECO920) := eco920 board-$(CONFIG_MACH_SCB9328) := scb9328 @@ -13,6 +14,7 @@ board-$(CONFIG_MACH_IMX27ADS) := imx27ads board-$(CONFIG_MACH_NXDB500) := netx board-$(CONFIG_MACH_PCM037) := pcm037 +board-$(CONFIG_MACH_OMAP) := omap # FIXME "cpu-y" never used on ARM! cpu-$(CONFIG_ARM920T) := arm920t cpu-$(CONFIG_ARM926EJS) := arm926ejs @@ -22,6 +24,10 @@ CPPFLAGS += -mabi=apcs-gnu -DTEXT_BASE=$(TEXT_BASE) -P CFLAGS += -Os +# Add architecture specific flags +ifeq ($(CONFIG_ARMCORTEXA8),y) +CPPFLAGS += -march=armv7a +endif # Add cleanup flags CPPFLAGS += -fdata-sections -ffunction-sections Index: u-boot-v2.git/arch/arm/cpu/Makefile =================================================================== --- u-boot-v2.git.orig/arch/arm/cpu/Makefile 2008-05-20 18:18:43.000000000 -0500 +++ u-boot-v2.git/arch/arm/cpu/Makefile 2008-05-20 18:20:54.000000000 -0500 @@ -6,4 +6,5 @@ # obj-$(CONFIG_ARM920T) += start-arm.o obj-$(CONFIG_ARM926EJS) += start-arm.o +obj-$(CONFIG_ARMCORTEXA8) += start-arm.o obj-$(CONFIG_ARCH_IMX31) += start-arm.o Index: u-boot-v2.git/arch/arm/cpu/start-arm.S =================================================================== --- u-boot-v2.git.orig/arch/arm/cpu/start-arm.S 2008-05-20 18:20:54.000000000 -0500 +++ u-boot-v2.git/arch/arm/cpu/start-arm.S 2008-05-21 10:44:14.000000000 -0500 @@ -143,12 +143,66 @@ #ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT bl arch_init_lowlevel #endif + +#ifdef CONFIG_ARMCORTEXA8 + /* + * Invalidate v7 I/D caches + */ + mov r0, #0 /* set up for MCR */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + /* Invalidate all Dcaches */ +#ifndef CONFIG_ARMCORTEXA8_DCACHE_SKIP + /* If Arch specific ROM code SMI handling does not exist */ + mrc p15, 1, r0, c0, c0, 1 /* read clidr */ + ands r3, r0, #0x7000000 /* extract loc from clidr */ + mov r3, r3, lsr #23 /* left align loc bit field */ + beq finished_inval /* if loc is 0, then no need to clean */ + mov r10, #0 /* start clean at cache level 0 */ +inval_loop1: + add r2, r10, r10, lsr #1 /* work out 3x current cache level */ + mov r1, r0, lsr r2 /* extract cache type bits from clidr */ + and r1, r1, #7 /* mask of the bits for current cache only */ + cmp r1, #2 /* see what cache we have at this level */ + blt skip_inval /* skip if no cache, or just i-cache */ + mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */ + isb /* isb to sych the new cssr&csidr */ + mrc p15, 1, r1, c0, c0, 0 /* read the new csidr */ + and r2, r1, #7 /* extract the length of the cache lines */ + add r2, r2, #4 /* add 4 (line length offset) */ + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 /* find maximum number on the way size*/ + clz r5, r4 /* find bit position of way size increment */ + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 /* extract max number of the index size */ +inval_loop2: + mov r9, r4 /* create working copy of max way size */ +inval_loop3: + orr r11, r10, r9, lsl r5 /* factor way and cache number into r11*/ + orr r11, r11, r7, lsl r2 /* factor index number into r11 */ + mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */ + subs r9, r9, #1 /* decrement the way */ + bge inval_loop3 + subs r7, r7, #1 /* decrement the index */ + bge inval_loop2 +skip_inval: + add r10, r10, #2 /* increment cache number */ + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 /* swith back to cache level 0 */ + mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */ + isb +#endif /* CONFIG_ARMCORTEXA8_DCACHE_SKIP */ + +#else /* * flush v4 I/D caches */ mov r0, #0 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ +#endif /* * disable MMU stuff and caches

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[U-Boot-Users] [Patch 09/17] U-Boot-V2:Serial: Add support for NS16550 Driver.`
by Menon, Nishanth 04 Jun '08

04 Jun '08

This introduces support for NS16550 and related OMAP support. This driver is a port from Uboot v1 driver from OMAP's Uboot tree. OMAP U-Boot V1 source is available here: http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz Signed-off-by: Nishanth Menon<x0nishan(a)ti.com> --- drivers/serial/Kconfig | 42 ++++++ drivers/serial/Makefile | 1 drivers/serial/serial_ns16550.c | 248 ++++++++++++++++++++++++++++++++++++++++ drivers/serial/serial_ns16550.h | 183 +++++++++++++++++++++++++++++ include/ns16550.h | 46 +++++++ 5 files changed, 520 insertions(+) Index: u-boot-v2.git/drivers/serial/Kconfig =================================================================== --- u-boot-v2.git.orig/drivers/serial/Kconfig 2008-05-20 17:59:26.000000000 -0500 +++ u-boot-v2.git/drivers/serial/Kconfig 2008-05-20 18:02:28.000000000 -0500 @@ -24,4 +24,46 @@ depends on BLACKFIN default y bool "Blackfin serial driver" + +config DRIVER_SERIAL_NS16550 + default n + bool "NS16550 serial driver" + help + Enable this to get support for NS16550 based serial devices +choice + prompt "NS16550 register size" + depends on DRIVER_SERIAL_NS16550 + +config DRIVER_SERIAL_NS16550_REG_SIZE_8_BITS + bool "8 bit register" + help + Say Y here if you are using a 8 bit register for NS16550 + +config DRIVER_SERIAL_NS16550_REG_SIZE_16_BITS + bool "16 bit register" + help + Say Y here if you are using a 16 bit register for NS16550 + +config DRIVER_SERIAL_NS16550_REG_SIZE_32_BITS + bool "32 bit register" + help + Say Y here if you are using a 32 bit register for NS16550 + +config DRIVER_SERIAL_NS16550_REG_SIZE_8_BITS_PAD_TO_32 + bool "8 bit register Padded to 32 bit" + help + Say Y here if you are using a 8 bit register padded to 32 bits for NS16550 + +config DRIVER_SERIAL_NS16550_REG_SIZE_8_BITS_PAD_TO_64 + bool "8 bit register Padded to 64 bit" + help + Say Y here if you are using a 8 bit register padded to 64 bits for NS16550 +endchoice + +config DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS + bool "OMAP Extensions for NS16550" + depends on DRIVER_SERIAL_NS16550 + depends on ARCH_OMAP + help + Say Y here if you are using OMAP extensions to NS16550 endmenu Index: u-boot-v2.git/drivers/serial/Makefile =================================================================== --- u-boot-v2.git.orig/drivers/serial/Makefile 2008-05-20 17:59:25.000000000 -0500 +++ u-boot-v2.git/drivers/serial/Makefile 2008-05-20 18:02:28.000000000 -0500 @@ -10,3 +10,4 @@ obj-$(CONFIG_DRIVER_SERIAL_LINUX_COMSOLE) += linux_console.o obj-$(CONFIG_DRIVER_SERIAL_MPC5XXX) += serial_mpc5xxx.o obj-$(CONFIG_DRIVER_SERIAL_BLACKFIN) += serial_blackfin.o +obj-$(CONFIG_DRIVER_SERIAL_NS16550) += serial_ns16550.o Index: u-boot-v2.git/drivers/serial/serial_ns16550.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/drivers/serial/serial_ns16550.c 2008-05-20 18:04:13.000000000 -0500 @@ -0,0 +1,248 @@ +/** + * @file + * @brief NS16550 Driver implementation + * + * FileName: drivers/serial/serial_ns16550.c + * + * NS16550 support + * Modified from U-Boot V1 drivers/serial.c and drivers/ns16550.c + * originally from linux source (arch/ppc/boot/ns16550.c) + * modified to use CFG_ISA_MEM and new defines + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt(a)flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <driver.h> +#include <init.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> + +#include "serial_ns16550.h" +#include <ns16550.h> + +/* Forward declaration */ +static unsigned int ns16550_calc_divisor(struct console_device *cdev, + unsigned int baudrate); +static void ns16550_serial_init_port(struct console_device *cdev); +static void ns16550_putc(struct console_device *cdev, char c); +static int ns16550_getc(struct console_device *cdev); +static int ns16550_tstc(struct console_device *cdev); +static int ns16550_setbaudrate(struct console_device *cdev, int baud_rate); +static int ns16550_probe(struct device_d *dev); +static int ns16550_serial_init(void); + +/*********** Private Functions **********************************/ + +/** + * @brief ns16550_calc_divisor - compute the divisor for a baud rate + * + * @param[in] cdev - pointer to console device + * @param[in] baudrate - baud rate + * + * @return divisor to be set + */ +static unsigned int ns16550_calc_divisor(struct console_device *cdev, + unsigned int baudrate) +{ + unsigned int clk = ((struct NS16550_plat *) + (cdev->dev->platform_data))->clock; +#ifdef CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS + /* FIXME: Legacy Code copied from U-Boot V1 implementation + */ +#ifdef CONFIG_ARCH_OMAP1510 + NS16550_t com_port = (NS16550_t) (cdev->dev->map_base); + /* If can't cleanly clock 115200 set div to 1 */ + if ((clk == 12000000) && (baudrate == 115200)) { + /* enable 6.5 * divisor */ + com_port->osc_12m_sel = OSC_12M_SEL; + return (1); /* return 1 for base divisor */ + } + com_port->osc_12m_sel = 0; /* clear if previsouly set */ +#elif defined(CONFIG_ARCH_OMAP1610) + /* If can't cleanly clock 115200 set div to 1 */ + if ((clk == 48000000) && (baudrate == 115200)) + return (26); /* return 26 for base divisor */ +#endif + +#endif /* End of OMAP specific handling */ + return (clk / MODE_X_DIV / baudrate); + +} + +/** + * @brief ns16550_serial_init_port - initialize the device + * + * @param cdev[in] - pointer to console device + */ +static void ns16550_serial_init_port(struct console_device *cdev) +{ + unsigned int baud_divisor; + NS16550_t com_port = (NS16550_t) (cdev->dev->map_base); + + /* Setup the serial port with the defaults first */ + baud_divisor = ns16550_calc_divisor(cdev, CONFIG_BAUDRATE); + + /* initializing the device for the first time */ + com_port->ier = 0x00; +#ifdef CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS + com_port->mdr1 = 0x7; /* Disable */ +#endif + com_port->lcr = LCR_BKSE | LCRVAL; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; +#ifdef CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS + com_port->mdr1 = 0; /* enable uart mode */ +#endif +} + +/*********** Exposed Functions **********************************/ + +/** + * @brief ns16550_putc- put a character to the serial port + * + * @param cdev[in] - pointer to console device + * @param c[in] - character to put + */ +static void ns16550_putc(struct console_device *cdev, char c) +{ + NS16550_t com_port = (NS16550_t) (cdev->dev->map_base); + /* Loop Doing Nothing */ + while ((com_port->lsr & LSR_THRE) == 0) ; + com_port->thr = c; +} + +/** + * @brief ns16550_getc - retrieve a character from serial port + * + * @param cdev[in] - pointer to console device + * + * @return return the character read + */ +static int ns16550_getc(struct console_device *cdev) +{ + NS16550_t com_port = (NS16550_t) (cdev->dev->map_base); + /* Loop Doing Nothing */ + while ((com_port->lsr & LSR_DR) == 0) ; + return (com_port->rbr); +} + +/** + * @brief ns16550_tstc - test if character is available + * + * @param cdev[in] -pointer to console device + * + * @return - status based on data availability + */ +static int ns16550_tstc(struct console_device *cdev) +{ + NS16550_t com_port = (NS16550_t) (cdev->dev->map_base); + return ((com_port->lsr & LSR_DR) != 0); +} + +/** + * @brief ns16550_setbaudrate - set the baudrate for the uart port + * + * @param cdev[in] - console device + * @param baud_rate[in] - baud rate to set + * + * @return 0-implied to support the baudrate + */ +static int ns16550_setbaudrate(struct console_device *cdev, int baud_rate) +{ + NS16550_t com_port = (NS16550_t) (cdev->dev->map_base); + unsigned int baud_divisor = ns16550_calc_divisor(cdev, baud_rate); + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; + return 0; +} + +/** + * @brief ns16550_probe - Probe entry point -called on the first + * match for device + * + * @param dev[in] - matched device + * + * @return EINVAL if platform_data is not populated, + * ENOMEM if calloc failed + * else return result of console_register + */ +static int ns16550_probe(struct device_d *dev) +{ + struct console_device *cdev; + struct NS16550_plat *plat = (struct NS16550_plat *)dev->platform_data; + + /* we do expect platform specific data */ + if (plat == NULL) + return -EINVAL; + cdev = calloc(1, sizeof(struct console_device)); + if (cdev == NULL) + return -ENOMEM; + + dev->type_data = cdev; + cdev->dev = dev; + cdev->f_caps = plat->f_caps; + cdev->tstc = ns16550_tstc; + cdev->putc = ns16550_putc; + cdev->getc = ns16550_getc; + cdev->setbrg = ns16550_setbaudrate; + + ns16550_serial_init_port(cdev); + + return console_register(cdev); +} + +/** + * @brief Driver registration structure + */ +static struct driver_d ns16550_serial_driver = { + .name = "serial_ns16550", + .probe = ns16550_probe, + .type = DEVICE_TYPE_CONSOLE, +}; + +/** + * @brief ns16550_serial_init - driver initialization function + * + * @return result of register_driver + */ +static int ns16550_serial_init(void) +{ + return register_driver(&ns16550_serial_driver); +} + +console_initcall(ns16550_serial_init); Index: u-boot-v2.git/drivers/serial/serial_ns16550.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/drivers/serial/serial_ns16550.h 2008-05-20 18:02:28.000000000 -0500 @@ -0,0 +1,183 @@ +/** + * @file + * @brief Serial NS16550 header + * + * FileName: drivers/serial/serial_ns16550.h + * + * @code struct NS16550 @endcode + * Register definitions for NS16550 device + */ +/* + * This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * NS16550 Serial Port + * originally from linux source (arch/ppc/boot/ns16550.h) + * modified slightly to + * have addresses as offsets from CFG_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + * + * added support for port on 64-bit bus + * by Richard Danter (richard.danter(a)windriver.com), (C) 2005 Wind River Systems + */ + + +#ifndef __SERIAL_NS16550__H +#define __SERIAL_NS16550__H +#ifdef CONFIG_DRIVER_SERIAL_NS16550_REG_SIZE_8_BITS +struct NS16550 { + /** RBR register */ + unsigned char rbr; /* 0 */ + unsigned char ier; /* 1 */ + unsigned char fcr; /* 2 */ + unsigned char lcr; /* 3 */ + unsigned char mcr; /* 4 */ + unsigned char lsr; /* 5 */ + unsigned char msr; /* 6 */ + unsigned char scr; /* 7 */ +#ifdef CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS + unsigned char mdr1; /* 8 */ + unsigned char reg9; /* 9 */ + unsigned char regA; /* A */ + unsigned char regB; /* B */ + unsigned char regC; /* C */ + unsigned char regD; /* D */ + unsigned char regE; /* E */ + unsigned char regF; /* F */ + unsigned char reg10; /* 10 */ + unsigned char ssr; /* 11 */ +#endif +} __attribute__ ((packed)); +#elif defined(DRIVER_SERIAL_NS16550_REG_SIZE_16_BITS) +struct NS16550 { + unsigned short rbr; /* 0 */ + unsigned short ier; /* 1 */ + unsigned short fcr; /* 2 */ + unsigned short lcr; /* 3 */ + unsigned short mcr; /* 4 */ + unsigned short lsr; /* 5 */ + unsigned short msr; /* 6 */ + unsigned short scr; /* 7 */ +} __attribute__ ((packed)); +#elif defined(DRIVER_SERIAL_NS16550_REG_SIZE_32_BITS) +struct NS16550 { + unsigned long rbr; /* 0 r */ + unsigned long ier; /* 1 rw */ + unsigned long fcr; /* 2 w */ + unsigned long lcr; /* 3 rw */ + unsigned long mcr; /* 4 rw */ + unsigned long lsr; /* 5 r */ + unsigned long msr; /* 6 r */ + unsigned long scr; /* 7 rw */ +}; /* No need to pack an already aligned struct */ +#elif defined(CONFIG_DRIVER_SERIAL_NS16550_REG_SIZE_8_BITS_PAD_TO_32) +struct NS16550 { + unsigned char rbr; /* 0 */ + unsigned int pad1:24; + unsigned char ier; /* 1 */ + unsigned int pad2:24; + unsigned char fcr; /* 2 */ + unsigned int pad3:24; + unsigned char lcr; /* 3 */ + unsigned int pad4:24; + unsigned char mcr; /* 4 */ + unsigned int pad5:24; + unsigned char lsr; /* 5 */ + unsigned int pad6:24; + unsigned char msr; /* 6 */ + unsigned int pad7:24; + unsigned char scr; /* 7 */ + unsigned int pad8:24; +#ifdef CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS + unsigned char mdr1; /* mode select reset TL16C750 */ +#ifdef CONFIG_ARCH_OMAP1510 + unsigned int pad9:24; + unsigned long pad[10]; + unsigned char osc_12m_sel; + unsigned int pad10:24; +#endif /* CONFIG_ARCH_OMAP1510 */ +#endif /* CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS */ +} __attribute__ ((packed)); + +#elif defined(DRIVER_SERIAL_NS16550_REG_SIZE_8_BITS_PAD_TO_64) +struct NS16550 { + unsigned char rbr; /* 0 */ + unsigned char pad0[7]; + unsigned char ier; /* 1 */ + unsigned char pad1[7]; + unsigned char fcr; /* 2 */ + unsigned char pad2[7]; + unsigned char lcr; /* 3 */ + unsigned char pad3[7]; + unsigned char mcr; /* 4 */ + unsigned char pad4[7]; + unsigned char lsr; /* 5 */ + unsigned char pad5[7]; + unsigned char msr; /* 6 */ + unsigned char pad6[7]; + unsigned char scr; /* 7 */ + unsigned char pad7[7]; +} __attribute__ ((packed)); +#else +#error "Please define NS16550 registers size." +#endif + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +/** @brief typedef for register access */ +typedef volatile struct NS16550 *NS16550_t; + +#define FCR_FIFO_EN 0x01 /* Fifo enable */ +#define FCR_RXSR 0x02 /* Receiver soft reset */ +#define FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_DMA_EN 0x04 +#define MCR_TX_DFR 0x08 + +#define LCR_WLS_MSK 0x03 /* character length select mask */ +#define LCR_WLS_5 0x00 /* 5 bit character length */ +#define LCR_WLS_6 0x01 /* 6 bit character length */ +#define LCR_WLS_7 0x02 /* 7 bit character length */ +#define LCR_WLS_8 0x03 /* 8 bit character length */ +/* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define LCR_STB 0x04 +#define LCR_PEN 0x08 /* Parity eneble */ +#define LCR_EPS 0x10 /* Even Parity Select */ +#define LCR_STKP 0x20 /* Stick Parity */ +#define LCR_SBRK 0x40 /* Set Break */ +#define LCR_BKSE 0x80 /* Bank select enable */ + +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +#ifdef CONFIG_ARCH_OMAP1510 +#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */ +#endif + +/* useful defaults for LCR */ +#define LCR_8N1 0x03 + +#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ +#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ +/* Clear & enable FIFOs */ +#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) + +#define MODE_X_DIV 16 + +#endif /* __SERIAL_NS16550__H */ Index: u-boot-v2.git/include/ns16550.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/ns16550.h 2008-05-20 18:02:28.000000000 -0500 @@ -0,0 +1,46 @@ +/** + * @file + * @brief Serial NS16550 platform specific header + * + * FileName: include/ns16550.h + * @code struct NS16550_plat @endcode + * represents The specifics of the device present in the system. + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __NS16650_PLATFORM_H_ +#define __NS16650_PLATFORM_H_ + +/** + * @brief Platform dependent feature: + * Pass pointer to this structure as part of device_d -> platform_data + */ +struct NS16550_plat { + /** Clock speed */ + unsigned int clock; + /** Console capabilities: + * CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR @see console.h + */ + unsigned char f_caps; +}; + +#endif /* __NS16650_PLATFORM_H_ */

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[U-Boot-Users] [Patch 08/17] U-Boot-V2:Commands: Unbreak loadb support
by Menon, Nishanth 04 Jun '08

04 Jun '08

This patch provides support for loadb and loady and enables the broken feature. xyzModem.c is brought in from U-Boot V1, Lindent, checkpatch and sparse cleaned :). Signed-off-by: Nishanth Menon<x0nishan(a)ti.com> --- commands/Kconfig | 14 commands/Makefile | 1 commands/loadb.c | 182 ++++++++--- commands/xyzModem.c | 792 ++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/Makefile | 1 5 files changed, 932 insertions(+), 58 deletions(-) Index: u-boot-v2.git/commands/Kconfig =================================================================== --- u-boot-v2.git.orig/commands/Kconfig 2008-05-20 17:53:55.000000000 -0500 +++ u-boot-v2.git/commands/Kconfig 2008-05-20 17:54:18.000000000 -0500 @@ -121,13 +121,23 @@ endmenu menu "memory " +config LOAD_ADDR + depends on CMD_LOADB + hex + prompt "default load address" + help + Provide the default load address for the platform config CMD_LOADB - depends on BROKEN select CRC16 - tristate + bool prompt "loadb" +config CMD_LOADY + select CRC16 + bool + prompt "loady" + config CMD_LOADS depends on BROKEN tristate Index: u-boot-v2.git/commands/Makefile =================================================================== --- u-boot-v2.git.orig/commands/Makefile 2008-05-20 17:53:55.000000000 -0500 +++ u-boot-v2.git/commands/Makefile 2008-05-20 17:54:18.000000000 -0500 @@ -1,5 +1,6 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_LOADB) += loadb.o xyzModem.o +obj-$(CONFIG_CMD_LOADY) += loadb.o xyzModem.o obj-$(CONFIG_CMD_LOADS) += loads.o obj-$(CONFIG_CMD_ECHO) += echo.o obj-$(CONFIG_CMD_MEMORY) += mem.o Index: u-boot-v2.git/commands/loadb.c =================================================================== --- u-boot-v2.git.orig/commands/loadb.c 2008-05-20 17:53:55.000000000 -0500 +++ u-boot-v2.git/commands/loadb.c 2008-05-20 17:58:05.000000000 -0500 @@ -1,3 +1,12 @@ +/** + * @file + * @brief LoadB and LoadY support. + * + * Provides loadb (over Kermit) and LoadY(over Y modem) support to download + * images. + * + * FileName: commands/loadb.c + */ /* * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. @@ -26,14 +35,16 @@ */ #include <common.h> #include <command.h> -#include <s_record.h> -#include <net.h> -#include <exports.h> #include <xyzModem.h> +#include <console.h> +#include <errno.h> +#include <environment.h> +#include <cache.h> -DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_CMD_LOADY static ulong load_serial_ymodem (ulong offset); +#endif #define XON_CHAR 17 #define XOFF_CHAR 19 @@ -50,36 +61,70 @@ #define tochar(x) ((char) (((x) + SPACE) & 0xff)) #define untochar(x) ((int) (((x) - SPACE) & 0xff)) -extern int os_data_count; -extern int os_data_header[8]; static void set_kerm_bin_mode(unsigned long *); static int k_recv(void); static ulong load_serial_bin (ulong offset); -char his_eol; /* character he needs at end of packet */ -int his_pad_count; /* number of pad chars he needs */ -char his_pad_char; /* pad chars he needs */ -char his_quote; /* quote chars he'll use */ +static char his_eol; /* character he needs at end of packet */ +static int his_pad_count; /* number of pad chars he needs */ +static char his_pad_char; /* pad chars he needs */ +static char his_quote; /* quote chars he'll use */ + -int do_load_serial_bin (cmd_tbl_t *cmdtp, int argc, char *argv[]) +/** + * @brief returns current used console device + * + * @return console device which is registered with CONSOLE_STDIN and + * CONSOLE_STDOUT + */ +static struct console_device *get_current_console(void) +{ + struct console_device *cdev; + /* + * Assumption to have BOTH CONSOLE_STDIN AND STDOUT in the + * same output console + */ + for_each_console(cdev) { + if ((cdev->f_active & (CONSOLE_STDIN | CONSOLE_STDOUT))) + return cdev; + } + return NULL; +} + +/** + * @brief provide the loadb(Kermit) or loadY mode support + * + * @param cmdtp + * @param argc + * @param argv + * + * @return success or failure + */ +static int do_load_serial_bin(cmd_tbl_t *cmdtp, int argc, char *argv[]) { ulong offset = 0; ulong addr; int load_baudrate, current_baudrate; int rcode = 0; char *s; + struct console_device *cdev = get_current_console(); + if (NULL == cdev) { + printf("No device with STDIN and STDOUT\n"); + return -ENODEV; + } - /* pre-set offset from CFG_LOAD_ADDR */ - offset = CFG_LOAD_ADDR; + /* pre-set offset from CONFIG_LOAD_ADDR */ + offset = CONFIG_LOAD_ADDR; /* pre-set offset from $loadaddr */ - if ((s = getenv("loadaddr")) != NULL) { + s = (char *) getenv("loadaddr"); + if (s != NULL) offset = simple_strtoul(s, NULL, 16); - } - load_baudrate = current_baudrate = gd->baudrate; + load_baudrate = current_baudrate = + simple_strtoul(cdev->baudrate_string, NULL, 10); if (argc >= 2) { offset = simple_strtoul(argv[1], NULL, 16); @@ -96,15 +141,14 @@ printf ("## Switch baudrate to %d bps and press ENTER ...\n", load_baudrate); udelay(50000); - gd->baudrate = load_baudrate; - serial_setbrg (); + cdev->setbrg(cdev, load_baudrate); udelay(50000); for (;;) { if (getc() == '\r') break; } } - +#ifdef CONFIG_CMD_LOADY if (strcmp(argv[0],"loady")==0) { printf ("## Ready for binary (ymodem) download " "to 0x%08lX at %d bps...\n", @@ -113,7 +157,10 @@ addr = load_serial_ymodem (offset); - } else { + } +#endif +#ifdef CONFIG_CMD_LOADB + if (strcmp(argv[0],"loadb")==0) { printf ("## Ready for binary (kermit) download " "to 0x%08lX at %d bps...\n", @@ -122,20 +169,18 @@ addr = load_serial_bin (offset); if (addr == ~0) { - load_addr = 0; printf ("## Binary (kermit) download aborted\n"); rcode = 1; } else { printf ("## Start Addr = 0x%08lX\n", addr); - load_addr = addr; } } +#endif if (load_baudrate != current_baudrate) { printf ("## Switch baudrate to %d bps and press ESC ...\n", current_baudrate); udelay (50000); - gd->baudrate = current_baudrate; - serial_setbrg (); + cdev->setbrg(cdev, current_baudrate); udelay (50000); for (;;) { if (getc() == 0x1B) /* ESC */ @@ -147,6 +192,14 @@ } +#ifdef CONFIG_CMD_LOADB +/** + * @brief loadb Support over kermit protocol + * + * @param offset where to download to + * + * @return downloaded address + */ static ulong load_serial_bin (ulong offset) { int size, i; @@ -175,17 +228,18 @@ return offset; } +#endif -void send_pad (void) +static void send_pad (void) { int count = his_pad_count; while (count-- > 0) - putc (his_pad_char); + console_putc (CONSOLE_STDOUT, his_pad_char); } /* converts escaped kermit char to binary char */ -char ktrans (char in) +static char ktrans(char in) { if ((in & 0x60) == 0x40) { return (char) (in & ~0x40); @@ -195,7 +249,7 @@ return in; } -int chk1 (char *buffer) +static int chk1 (char *buffer) { int total = 0; @@ -205,16 +259,16 @@ return (int) ((total + ((total >> 6) & 0x03)) & 0x3f); } -void s1_sendpacket (char *packet) +static void s1_sendpacket (char *packet) { send_pad (); while (*packet) { - putc (*packet++); + console_putc (CONSOLE_STDOUT, *packet++); } } static char a_b[24]; -void send_ack (int n) +static void send_ack (int n) { a_b[0] = START_CHAR; a_b[1] = tochar (3); @@ -227,7 +281,7 @@ s1_sendpacket (a_b); } -void send_nack (int n) +static void send_nack (int n) { a_b[0] = START_CHAR; a_b[1] = tochar (3); @@ -246,14 +300,15 @@ if image is binary, no header is stored in os_data_header. */ -void (*os_data_init) (void); -void (*os_data_char) (char new_char); +static void (*os_data_init) (void); +static void (*os_data_char) (char new_char); static int os_data_state, os_data_state_saved; -int os_data_count; +static int os_data_count; static int os_data_count_saved; static char *os_data_addr, *os_data_addr_saved; static char *bin_start_address; -int os_data_header[8]; +/* FIXME: carry over feature to use this. commented for sparse warning +static int os_data_header[8]; */ static void bin_data_init (void) { os_data_state = 0; @@ -291,22 +346,22 @@ /* k_data_* simply handles the kermit escape translations */ static int k_data_escape, k_data_escape_saved; -void k_data_init (void) +static void k_data_init(void) { k_data_escape = 0; os_data_init (); } -void k_data_save (void) +static void k_data_save(void) { k_data_escape_saved = k_data_escape; os_data_save (); } -void k_data_restore (void) +static void k_data_restore(void) { k_data_escape = k_data_escape_saved; os_data_restore (); } -void k_data_char (char new_char) +static void k_data_char(char new_char) { if (k_data_escape) { /* last char was escape - translate this character */ @@ -324,12 +379,12 @@ } #define SEND_DATA_SIZE 20 -char send_parms[SEND_DATA_SIZE]; -char *send_ptr; +static char send_parms[SEND_DATA_SIZE]; +static char *send_ptr; /* handle_send_packet interprits the protocol info and builds and sends an appropriate ack for what we can do */ -void handle_send_packet (int n) +static void handle_send_packet(int n) { int length = 3; int bytes; @@ -588,11 +643,19 @@ return ((ulong) os_data_addr - (ulong) bin_start_address); } +#ifdef CONFIG_CMD_LOADY static int getcxmodem(void) { if (tstc()) return (getc()); return -1; } +/** + * @brief LoadY over ymodem protocol + * + * @param offset address to download to + * + * @return address downloaded + */ static ulong load_serial_ymodem (ulong offset) { int size; @@ -633,19 +696,26 @@ return offset; } +#endif -U_BOOT_CMD( - loadb, 3, 0, do_load_serial_bin, - "loadb - load binary file over serial line (kermit mode)\n", - "[ off ] [ baud ]\n" - " - load binary file over serial line" - " with offset 'off' and baudrate 'baud'\n" -); - -U_BOOT_CMD( - loady, 3, 0, do_load_serial_bin, - "loady - load binary file over serial line (ymodem mode)\n", +static const __maybe_unused char cmd_loadb_help[] = "[ off ] [ baud ]\n" " - load binary file over serial line" - " with offset 'off' and baudrate 'baud'\n" -); + " with offset 'off' and baudrate 'baud'\n"; +#ifdef CONFIG_CMD_LOADB +U_BOOT_CMD_START(loadb) + .maxargs = 3, + .cmd = do_load_serial_bin, + .usage = "load binary file over serial line (kermit mode)", + U_BOOT_CMD_HELP(cmd_loadb_help) +U_BOOT_CMD_END +#endif + +#ifdef CONFIG_CMD_LOADY +U_BOOT_CMD_START(loady) + .maxargs = 3, + .cmd = do_load_serial_bin, + .usage = "load binary file over serial line (ymodem mode)", + U_BOOT_CMD_HELP(cmd_loadb_help) +U_BOOT_CMD_END +#endif Index: u-boot-v2.git/commands/xyzModem.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/commands/xyzModem.c 2008-05-20 17:54:18.000000000 -0500 @@ -0,0 +1,792 @@ +/** + * @file + * @brief RedBoot stream handler for xyzModem protocol + * + * FileName: commands/xyzModem.c + * Originally from U-Boot V1 xyzModem.c + */ +/* + * 2008 - Nishanth Menon <x0nishan(a)ti.com> + * Modified for sparse and checkpatch.pl compliance + */ +/* + *========================================================================== + * + * xyzModem.c + * + * RedBoot stream handler for xyzModem protocol + * + *========================================================================== + *####ECOSGPLCOPYRIGHTBEGIN#### + * ------------------------------------------- + * This file is part of eCos, the Embedded Configurable Operating System. + * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + * Copyright (C) 2002 Gary Thomas + * + * eCos is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 or (at your option) any later version. + * + * eCos is distributed in the hope that it will be useful, but WITHOUT ANY + * WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with eCos; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * As a special exception, if other files instantiate templates or use macros + * or inline functions from this file, or you compile this file and link it + * with other works to produce a work based on this file, this file does not + * by itself cause the resulting work to be covered by the GNU General Public + * License. However the source code for this file must still be made available + * in accordance with section (3) of the GNU General Public License. + * + * This exception does not invalidate any other reasons why a work based on + * this file might be covered by the GNU General Public License. + * + * Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. + * at http: *sources.redhat.com/ecos/ecos-license/ + * ------------------------------------------- + *####ECOSGPLCOPYRIGHTEND#### + *========================================================================== + *#####DESCRIPTIONBEGIN#### + * + * Author(s): gthomas + * Contributors: gthomas, tsmith, Yoshinori Sato + * Date: 2000-07-14 + * Purpose: + * Description: + * + * This code is part of RedBoot (tm). + * + *####DESCRIPTIONEND#### + * + *========================================================================== + */ +#include <common.h> +#include <xyzModem.h> +#include <stdarg.h> +#include <stdio.h> +#include <console.h> +#include <crc.h> + +/* Assumption - run xyzModem protocol over the console port */ + +/* Values magic to the protocol */ +#define SOH 0x01 +#define STX 0x02 +#define EOT 0x04 +#define ACK 0x06 +#define BSP 0x08 +#define NAK 0x15 +#define CAN 0x18 +#define EOF 0x1A /* ^Z for DOS officionados */ + +#define USE_YMODEM_LENGTH + +/* Data & state local to the protocol */ +static struct { +#ifdef REDBOOT + hal_virtual_comm_table_t *__chan; +#else + int *__chan; +#endif + unsigned char pkt[1024], *bufp; + unsigned char blk, cblk, crc1, crc2; + unsigned char next_blk; /* Expected block */ + int len, mode, total_retries; + int total_SOH, total_STX, total_CAN; + bool crc_mode, at_eof, tx_ack; +#ifdef USE_YMODEM_LENGTH + unsigned long file_length, read_length; +#endif +} xyz; + +#define xyzModem_CHAR_TIMEOUT 2000 /* 2 seconds */ +#define xyzModem_MAX_RETRIES 20 +#define xyzModem_MAX_RETRIES_WITH_CRC 10 +/* Wait for 3 CAN before quitting */ +#define xyzModem_CAN_COUNT 3 + +#ifndef REDBOOT /*SB */ +typedef int cyg_int32; +static int CYGACC_COMM_IF_GETC_TIMEOUT(char chan, char *c) +{ +#define DELAY 20 + unsigned long counter = 0; + while (!tstc() && (counter < xyzModem_CHAR_TIMEOUT * 1000 / DELAY)) { + udelay(DELAY); + counter++; + } + if (tstc()) { + *c = getc(); + return 1; + } + return 0; +} + +static void CYGACC_COMM_IF_PUTC(char x, char y) +{ + console_putc(CONSOLE_STDOUT, y); +} + +/* Validate a hex character */ +static inline bool _is_hex(char c) +{ + return (((c >= '0') && (c <= '9')) || + ((c >= 'A') && (c <= 'F')) || ((c >= 'a') && (c <= 'f'))); +} + +/* Convert a single hex nibble */ +static inline int _from_hex(char c) +{ + int ret = 0; + + if ((c >= '0') && (c <= '9')) + ret = (c - '0'); + else if ((c >= 'a') && (c <= 'f')) + ret = (c - 'a' + 0x0a); + else if ((c >= 'A') && (c <= 'F')) + ret = (c - 'A' + 0x0A); + + return ret; +} + +/* Convert a character to lower case */ +static inline char _tolower(char c) +{ + if ((c >= 'A') && (c <= 'Z')) + c = (c - 'A') + 'a'; + return c; +} + +/* Parse (scan) a number */ +static bool parse_num(char *s, unsigned long *val, char **es, char *delim) +{ + bool first = true; + int radix = 10; + char c; + unsigned long result = 0; + int digit; + + while (*s == ' ') + s++; + while (*s) { + if (first && (s[0] == '0') && (_tolower(s[1]) == 'x')) { + radix = 16; + s += 2; + } + first = false; + c = *s++; + if (_is_hex(c)) + digit = _from_hex(c); + if (_is_hex(c) && (digit < radix)) { + /* Valid digit */ +#ifdef CYGPKG_HAL_MIPS + /* FIXME: tx49 compiler generates 0x2539018 for + * MUL which isn't any good. */ + if (16 == radix) + result = result << 4; + else + result = 10 * result; + result += digit; +#else + result = (result * radix) + digit; +#endif + } else { + if (delim != (char *)0) { + /* See if this character is one of the + * delimiters */ + char *dp = delim; + while (*dp && (c != *dp)) + dp++; + if (*dp) + break; /* Found a good delimiter */ + } + return false; /* Malformatted number */ + } + } + *val = result; + if (es != (char **)0) + *es = s; + return true; +} + +#endif + +#define USE_SPRINTF +#ifdef DEBUG +#ifndef USE_SPRINTF +/* + * Note: this debug setup only works if the target platform has two serial ports + * available so that the other one (currently only port 1) can be used for debug + * messages. + */ +static int zm_dprintf(char *fmt, ...) +{ + int cur_console; + va_list args; + + va_start(args, fmt); +#ifdef REDBOOT + cur_console = + CYGACC_CALL_IF_SET_CONSOLE_COMM + (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + CYGACC_CALL_IF_SET_CONSOLE_COMM(1); +#endif + diag_vprintf(fmt, args); +#ifdef REDBOOT + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur_console); +#endif +} + +static void zm_flush(void) +{ +} + +#else +/* + * Note: this debug setup works by storing the strings in a fixed buffer + */ +#define FINAL +#ifdef FINAL +static char *zm_out = (char *)0x00380000; +static char *zm_out_start = (char *)0x00380000; +#else +static char zm_buf[8192]; +static char *zm_out = zm_buf; +static char *zm_out_start = zm_buf; + +#endif +static int zm_dprintf(char *fmt, ...) +{ + int len; + va_list args; + + va_start(args, fmt); + len = diag_vsprintf(zm_out, fmt, args); + zm_out += len; + return len; +} + +static void zm_flush(void) +{ +#ifdef REDBOOT + char *p = zm_out_start; + while (*p) + mon_write_char(*p++); +#endif + zm_out = zm_out_start; +} +#endif + +static void zm_dump_buf(void *buf, int len) +{ +#ifdef REDBOOT + diag_vdump_buf_with_offset(zm_dprintf, buf, len, 0); +#else + +#endif +} + +static unsigned char zm_buf[2048]; +static unsigned char *zm_bp; + +static void zm_new(void) +{ + zm_bp = zm_buf; +} + +static void zm_save(unsigned char c) +{ + *zm_bp++ = c; +} + +static void zm_dump(int line) +{ + zm_dprintf("Packet at line: %d\n", line); + zm_dump_buf(zm_buf, zm_bp - zm_buf); +} + +#define ZM_DEBUG(x) x +#else +#define ZM_DEBUG(x) +#endif + +/* Wait for the line to go idle */ +static void xyzModem_flush(void) +{ + int res; + char c; + while (true) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c); + if (!res) + return; + } +} + +static int xyzModem_get_hdr(void) +{ + char c; + int res; + bool hdr_found = false; + int i, can_total, hdr_chars; + unsigned short cksum; + + ZM_DEBUG(zm_new()); + /* Find the start of a header */ + can_total = 0; + hdr_chars = 0; + + if (xyz.tx_ack) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + xyz.tx_ack = false; + } + while (!hdr_found) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c); + ZM_DEBUG(zm_save(c)); + if (res) { + hdr_chars++; + switch (c) { + case SOH: + xyz.total_SOH++; + case STX: + if (c == STX) + xyz.total_STX++; + hdr_found = true; + break; + case CAN: + xyz.total_CAN++; + ZM_DEBUG(zm_dump(__LINE__)); + if (++can_total == xyzModem_CAN_COUNT) { + return xyzModem_cancel; + } else { + /* Wait for multiple CAN to avoid + * early quits */ + break; + } + case EOT: + /* EOT only supported if no noise */ + if (hdr_chars == 1) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + ZM_DEBUG(zm_dprintf + ("ACK on EOT #%d\n", + __LINE__)); + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_eof; + } + default: + /* Ignore, waiting for start of header */ + ; + } + } else { + /* Data stream timed out */ + xyzModem_flush(); /* Toss any current input */ + ZM_DEBUG(zm_dump(__LINE__)); + CYGACC_CALL_IF_DELAY_US((cyg_int32) 250000); + return xyzModem_timeout; + } + } + + /* Header found, now read the data */ + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.blk); + ZM_DEBUG(zm_save(xyz.blk)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.cblk); + ZM_DEBUG(zm_save(xyz.cblk)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } + xyz.len = (c == SOH) ? 128 : 1024; + xyz.bufp = xyz.pkt; + for (i = 0; i < xyz.len; i++) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c); + ZM_DEBUG(zm_save(c)); + if (res) { + xyz.pkt[i] = c; + } else { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } + } + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.crc1); + ZM_DEBUG(zm_save(xyz.crc1)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } + if (xyz.crc_mode) { + res = + CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.crc2); + ZM_DEBUG(zm_save(xyz.crc2)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } + } + ZM_DEBUG(zm_dump(__LINE__)); + /* Validate the message */ + if ((xyz.blk ^ xyz.cblk) != (unsigned char)0xFF) { + ZM_DEBUG(zm_dprintf + ("Framing error - blk: %x/%x/%x\n", xyz.blk, xyz.cblk, + (xyz.blk ^ xyz.cblk))); + ZM_DEBUG(zm_dump_buf(xyz.pkt, xyz.len)); + xyzModem_flush(); + return xyzModem_frame; + } + /* Verify checksum/CRC */ + if (xyz.crc_mode) { + cksum = cyg_crc16(xyz.pkt, xyz.len); + if (cksum != ((xyz.crc1 << 8) | xyz.crc2)) { + ZM_DEBUG(zm_dprintf + ("CRC error - recvd: %02x%02x, computed: %x\n", + xyz.crc1, xyz.crc2, cksum & 0xFFFF)); + return xyzModem_cksum; + } + } else { + cksum = 0; + for (i = 0; i < xyz.len; i++) + cksum += xyz.pkt[i]; + if (xyz.crc1 != (cksum & 0xFF)) { + ZM_DEBUG(zm_dprintf + ("Checksum error - recvd: %x, computed: %x\n", + xyz.crc1, cksum & 0xFF)); + return xyzModem_cksum; + } + } + /* If we get here, the message passes [structural] muster */ + return 0; +} + +int xyzModem_stream_open(connection_info_t *info, int *err) +{ +#ifdef REDBOOT + int console_chan; +#endif + int stat = 0; + int retries = xyzModem_MAX_RETRIES; + int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC; + +/* ZM_DEBUG(zm_out = zm_out_start); */ +#ifdef xyzModem_zmodem + if (info->mode == xyzModem_zmodem) { + *err = xyzModem_noZmodem; + return -1; + } +#endif + +#ifdef REDBOOT + /* Set up the I/O channel. Note: this allows for using a different + * port in the future */ + console_chan = + CYGACC_CALL_IF_SET_CONSOLE_COMM + (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + if (info->chan >= 0) + CYGACC_CALL_IF_SET_CONSOLE_COMM(info->chan); + else + CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan); + + xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS(); + + CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan); + CYGACC_COMM_IF_CONTROL(*xyz.__chan, __COMMCTL_SET_TIMEOUT, + xyzModem_CHAR_TIMEOUT); +#else +/* TODO: CHECK ! */ + int dummy; + xyz.__chan = &dummy; +#endif + xyz.len = 0; + xyz.crc_mode = true; + xyz.at_eof = false; + xyz.tx_ack = false; + xyz.mode = info->mode; + xyz.total_retries = 0; + xyz.total_SOH = 0; + xyz.total_STX = 0; + xyz.total_CAN = 0; +#ifdef USE_YMODEM_LENGTH + xyz.read_length = 0; + xyz.file_length = 0; +#endif + + CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); + + if (xyz.mode == xyzModem_xmodem) { + /* X-modem doesn't have an information header - exit here */ + xyz.next_blk = 1; + return 0; + } + + while (retries-- > 0) { + stat = xyzModem_get_hdr(); + if (stat == 0) { + /* Y-modem file information header */ + if (xyz.blk == 0) { +#ifdef USE_YMODEM_LENGTH + /* skip filename */ + while (*xyz.bufp++) ; + /* get the length */ + parse_num((char *)xyz.bufp, &xyz.file_length, + NULL, " "); +#endif + /* The rest of the file name data block + * quietly discarded + */ + xyz.tx_ack = true; + } + xyz.next_blk = 1; + xyz.len = 0; + return 0; + } else if (stat == xyzModem_timeout) { + if (--crc_retries <= 0) + xyz.crc_mode = false; + /* Extra delay for startup */ + CYGACC_CALL_IF_DELAY_US(5 * 100000); + CYGACC_COMM_IF_PUTC(*xyz.__chan, + (xyz.crc_mode ? 'C' : NAK)); + xyz.total_retries++; + ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__)); + } + if (stat == xyzModem_cancel) + break; + } + *err = stat; + ZM_DEBUG(zm_flush()); + return -1; +} + +int xyzModem_stream_read(char *buf, int size, int *err) +{ + int stat, total, len; + int retries; + + total = 0; + stat = xyzModem_cancel; + /* Try and get 'size' bytes into the buffer */ + while (!xyz.at_eof && (size > 0)) { + if (xyz.len == 0) { + retries = xyzModem_MAX_RETRIES; + while (retries-- > 0) { + stat = xyzModem_get_hdr(); + if (stat == 0) { + if (xyz.blk == xyz.next_blk) { + xyz.tx_ack = true; + ZM_DEBUG(zm_dprintf + ("ACK block %d (%d)\n", + xyz.blk, __LINE__)); + xyz.next_blk = + (xyz.next_blk + 1) & 0xFF; + +#if defined(xyzModem_zmodem) || defined(USE_YMODEM_LENGTH) + if (xyz.mode == xyzModem_xmodem + || xyz.file_length == 0) { +#else + if (1) { +#endif + /* WARNING - Leaving formatting aside for code + * clarity */ + /* Data blocks can be padded with ^Z (EOF) characters */ + /* This code tries to detect and remove them */ + if ((xyz.bufp[xyz.len - 1] == EOF) + && (xyz.bufp[xyz.len - 2] == EOF) + && (xyz.bufp[xyz.len - 3] == EOF)) { + while (xyz.len && + (xyz.bufp[xyz.len - 1] == EOF)) + xyz.len--; + } + } +#ifdef USE_YMODEM_LENGTH + /* WARNING - Leaving formatting aside for code + * clarity */ + /* + * See if accumulated length exceeds that of the file. + * If so, reduce size (i.e., cut out pad bytes) + * Only do this for Y-modem (and Z-modem should it ever + * be supported since it can fall back to Y-modem mode). + */ + if (xyz.mode != xyzModem_xmodem + && 0 != xyz.file_length) { + xyz.read_length += xyz.len; + if (xyz.read_length > xyz.file_length) + xyz.len -= (xyz.read_length - + xyz.file_length); + } +#endif + break; + } else if (xyz.blk == + ((xyz.next_blk - 1) & + 0xFF)) { + /* Just re-ACK this so sender + * will get on with it */ + CYGACC_COMM_IF_PUTC(*xyz.__chan, + ACK); + /* Need new header */ + continue; + } else + stat = xyzModem_sequence; + } + if (stat == xyzModem_cancel) + break; + if (stat == xyzModem_eof) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + ZM_DEBUG(zm_dprintf + ("ACK (%d)\n", __LINE__)); + if (xyz.mode == xyzModem_ymodem) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, + (xyz. + crc_mode ? + 'C' : + NAK)); + xyz.total_retries++; + ZM_DEBUG(zm_dprintf + ("Reading Final Header\n")); + stat = xyzModem_get_hdr(); + CYGACC_COMM_IF_PUTC(*xyz.__chan, + ACK); + ZM_DEBUG(zm_dprintf + ("FINAL ACK (%d)\n", + __LINE__)); + } + xyz.at_eof = true; + break; + } + CYGACC_COMM_IF_PUTC(*xyz.__chan, + (xyz.crc_mode ? 'C' : NAK)); + xyz.total_retries++; + ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__)); + } + if (stat < 0) { + *err = stat; + xyz.len = -1; + return total; + } + } + /* Don't "read" data from the EOF protocol package */ + if (!xyz.at_eof) { + len = xyz.len; + if (size < len) + len = size; + memcpy(buf, xyz.bufp, len); + size -= len; + buf += len; + total += len; + xyz.len -= len; + xyz.bufp += len; + } + } + return total; +} + +void xyzModem_stream_close(int *err) +{ + diag_printf + ("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets," + " %d retries\n", + xyz.crc_mode ? "CRC" : "Cksum", xyz.total_SOH, xyz.total_STX, + xyz.total_CAN, xyz.total_retries); + ZM_DEBUG(zm_flush()); +} + +/* Need to be able to clean out the input buffer, so have to take the */ +/* getc */ +void xyzModem_stream_terminate(bool abort, int (*getc) (void)) +{ + int c; + + if (abort) { + ZM_DEBUG(zm_dprintf("!!!! TRANSFER ABORT !!!!\n")); + switch (xyz.mode) { + case xyzModem_xmodem: + case xyzModem_ymodem: + /* The X/YMODEM Spec seems to suggest that multiple CAN + * followed by an equal number of Backspaces is a + * friendly way to get the other end to abort. */ + CYGACC_COMM_IF_PUTC(*xyz.__chan, CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan, CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan, CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan, CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan, BSP); + CYGACC_COMM_IF_PUTC(*xyz.__chan, BSP); + CYGACC_COMM_IF_PUTC(*xyz.__chan, BSP); + CYGACC_COMM_IF_PUTC(*xyz.__chan, BSP); + /* Now consume the rest of what's waiting on the line.*/ + ZM_DEBUG(zm_dprintf("Flushing serial line.\n")); + xyzModem_flush(); + xyz.at_eof = true; + break; +#ifdef xyzModem_zmodem + case xyzModem_zmodem: + /* Might support it some day I suppose. */ +#endif + break; + } + } else { + ZM_DEBUG(zm_dprintf("Engaging cleanup mode...\n")); + /* + * Consume any trailing crap left in the inbuffer from + * previous recieved blocks. Since very few files are an + * exact multiple of the transfer block size, there will + * almost always be some gunk here. + * If we don't eat it now, RedBoot will think the user typed it. + */ + ZM_DEBUG(zm_dprintf("Trailing gunk:\n")); + while ((c = (*getc) ()) > -1) ; + ZM_DEBUG(zm_dprintf("\n")); + /* + * Make a small delay to give terminal programs like minicom + * time to get control again after their file transfer program + * exits. + */ + CYGACC_CALL_IF_DELAY_US((cyg_int32) 250000); + } +} + +char *xyzModem_error(int err) +{ + switch (err) { + case xyzModem_access: + return "Can't access file"; + break; + case xyzModem_noZmodem: + return "Sorry, zModem not available yet"; + break; + case xyzModem_timeout: + return "Timed out"; + break; + case xyzModem_eof: + return "End of file"; + break; + case xyzModem_cancel: + return "Cancelled"; + break; + case xyzModem_frame: + return "Invalid framing"; + break; + case xyzModem_cksum: + return "CRC/checksum error"; + break; + case xyzModem_sequence: + return "Block sequence error"; + break; + default: + return "Unknown error"; + break; + } +} + +/* + * RedBoot interface + */ +#if 0 /* SB */ +GETC_IO_FUNCS(xyzModem_io, xyzModem_stream_open, xyzModem_stream_close, + xyzModem_stream_terminate, xyzModem_stream_read, xyzModem_error); +RedBoot_load(xmodem, xyzModem_io, false, false, xyzModem_xmodem); +RedBoot_load(ymodem, xyzModem_io, false, false, xyzModem_ymodem); +#endif Index: u-boot-v2.git/lib/Makefile =================================================================== --- u-boot-v2.git.orig/lib/Makefile 2008-05-20 17:53:55.000000000 -0500 +++ u-boot-v2.git/lib/Makefile 2008-05-20 17:54:18.000000000 -0500 @@ -19,6 +19,7 @@ obj-$(CONFIG_BZLIB) += bzlib.o bzlib_crctable.o bzlib_decompress.o bzlib_huffman.o bzlib_randtable.o obj-$(CONFIG_ZLIB) += zlib.o gunzip.o obj-$(CONFIG_CRC32) += crc32.o +obj-$(CONFIG_CRC16) += crc16.o obj-$(CONFIG_CMDLINE_EDITING) += readline.o obj-$(CONFIG_SIMPLE_READLINE) += readline_simple.o obj-$(CONFIG_GLOB) += fnmatch.o

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[U-Boot-Users] [Patch 04/17] U-Boot-V2:ARM: Remove unwanted flags from Makefile
by Menon, Nishanth 04 Jun '08

04 Jun '08

CFLAGS: "-D __ARM__" should have been "-D__ARM__". This breaks sparse check. Further common flags defines else where are being re-defined here. This patch removes them. Signed-off-by: Nishanth Menon<x0nishan(a)ti.com> --- arch/arm/Makefile | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) Index: u-boot-v2.git/arch/arm/Makefile =================================================================== --- u-boot-v2.git.orig/arch/arm/Makefile 2008-05-20 17:19:43.000000000 -0500 +++ u-boot-v2.git/arch/arm/Makefile 2008-05-20 17:26:33.000000000 -0500 @@ -1,6 +1,6 @@ -CPPFLAGS += -fno-builtin -ffreestanding -nostdinc -Wall \ - -pipe -D __ARM__ -fno-strict-aliasing +CPPFLAGS += -fno-builtin -ffreestanding\ + -pipe -D__ARM__ machine-$(CONFIG_ARCH_IMX) := imx @@ -20,7 +20,8 @@ TEXT_BASE = $(CONFIG_TEXT_BASE) CPPFLAGS += -mabi=apcs-gnu -DTEXT_BASE=$(TEXT_BASE) -P -CFLAGS := -fno-common -msoft-float -Os +CFLAGS += -Os + # Add cleanup flags CPPFLAGS += -fdata-sections -ffunction-sections

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[U-Boot-Users] [PATCH v2] 85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define it
by Kumar Gala 04 Jun '08

04 Jun '08

Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- Fix warning that the first version introduced. - k cpu/mpc85xx/cpu.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 9873383..58d23f4 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -75,8 +75,12 @@ int checkcpu (void) uint ver; uint major, minor; int i; - u32 ddr_ratio; +#ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; +#else + u32 ddr_ratio = 0; +#endif svr = get_svr(); ver = SVR_SOC_VER(svr); @@ -118,7 +122,7 @@ int checkcpu (void) puts("Clock Configuration:\n"); printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); - ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + switch (ddr_ratio) { case 0x0: printf(" DDR:%4lu MHz (%lu MT/s data rate), ", -- 1.5.4.5

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[U-Boot-Users] [PATCH] M18 flash (Sibley) support (attempt 2)
by Vasiliy Leoenenko 03 Jun '08

03 Jun '08

Hi Wolfgang, > Your patch was corrupted by your mailer which wrapped long lines. It > cannot be applied. Thank you very much for your reply. Gmail wrapped long lines. So I changed mail box. This is the second attempt. The patch was verified on different kinds of NOR using Mainstone II platform - no issues are found on u-boot (versions 1.3.0-rc1 and 1.3.0-rc2). Any comments and suggestions are welcome. Thanks, Signed-off-by: Vasiliy Leonenko <vasiliy.leonenko(a)mail.ru> Signed-off-by: Alexey Korolev <akorolex(a)gmail.com> ==================================================== --- u-boot-1.3.0-rc1.base/drivers/cfi_flash.c 2007-09-07 19:43:36.000000000 +0400 +++ u-boot-1.3.0-rc1/drivers/cfi_flash.c 2007-09-24 16:07:10.000000000 +0400 @@ -74,6 +74,7 @@ #define FLASH_CMD_PROTECT_CLEAR 0xD0 #define FLASH_CMD_CLEAR_STATUS 0x50 #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_TO_BUFFER_EXT 0xE9 #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 #define FLASH_STATUS_DONE 0x80 @@ -136,6 +137,7 @@ #define CFI_CMDSET_MITSU_STANDARD 256 #define CFI_CMDSET_MITSU_EXTENDED 257 #define CFI_CMDSET_SST 258 +#define CFI_CMDSET_INTEL_PROG_REGIONS 512 #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ # undef FLASH_CMD_RESET @@ -184,8 +186,8 @@ flash_info_t flash_info[CFG_MAX_FLASH_BA typedef unsigned long flash_sect_t; static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); -static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf); +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, ulong cmd); static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); @@ -474,6 +476,7 @@ int flash_erase (flash_info_t * info, in for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS); @@ -522,6 +525,9 @@ void flash_print_info (flash_info_t * in info->size >> 20, info->sector_count); printf (" "); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: + printf ("Intel Prog Regions"); + break; case CFI_CMDSET_INTEL_STANDARD: printf ("Intel Standard"); break; @@ -771,6 +777,7 @@ static int flash_is_busy (flash_info_t * int retval; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); @@ -825,6 +832,7 @@ static int flash_full_status_check (flas retcode = flash_status_check (info, sector, tout, prompt); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: if ((retcode == ERR_OK) @@ -903,7 +911,7 @@ static void flash_add_byte (flash_info_t /*----------------------------------------------------------------------- * make a proper sized command based on the port and chip widths */ -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf) { int i; uchar *cp = (uchar *) cmdbuf; @@ -913,13 +921,13 @@ static void flash_make_cmd (flash_info_t #else for (i = 1; i <= info->portwidth; i++) #endif - *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; + *cp++ = (i > info->chipwidth) ? '\0' : *((uchar *)&cmd + info->portwidth - i); } /* * Write a proper sized command to the correct address */ -static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, ulong cmd) { volatile cfiptr_t addr; @@ -1090,6 +1098,7 @@ static void flash_read_jedec_ids (flash_ info->device_id2 = 0; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); @@ -1209,6 +1218,7 @@ ulong flash_get_size (ulong base, int ba flash_printqry (info, 0); #endif switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: default: @@ -1289,6 +1299,7 @@ ulong flash_get_size (ulong base, int ba * Only read protection status from supported devices (intel...) */ switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: info->protect[sect_cnt] = @@ -1377,6 +1388,7 @@ static int flash_write_cfiword (flash_in flag = disable_interrupts (); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); @@ -1422,15 +1434,19 @@ static int flash_write_cfibuffer (flash_ int retcode; volatile cfiptr_t src; volatile cfiptr_t dst; + uchar write_cmd; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: src.cp = cp; dst.cp = (uchar *) dest; sector = find_sector (info, dest); + write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? + FLASH_CMD_WRITE_TO_BUFFER_EXT : FLASH_CMD_WRITE_TO_BUFFER; flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + flash_write_cmd (info, sector, 0, write_cmd); if ((retcode = flash_status_check (info, sector, info->buffer_write_tout, "write to buffer")) == ERR_OK) { /* reduce the number of loops by the width of the port */ @@ -1451,7 +1467,7 @@ static int flash_write_cfibuffer (flash_ return ERR_INVAL; break; } - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + flash_write_cmd (info, sector, 0, cnt - 1); while (cnt-- > 0) { switch (info->portwidth) { case FLASH_CFI_8BIT:

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[U-Boot-Users] [PATCH] 4xx: Cleanup CPCI405 variant's config file
by Matthias Fuchs 03 Jun '08

03 Jun '08

This patch removes some dead code from CPCI405 board's config files. JFFS2 support is also removed. It's not used and CPCI4052 does not build anymore without some size reduction. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- include/configs/CPCI4052.h | 38 -------------------------------------- include/configs/CPCI405AB.h | 22 ---------------------- include/configs/CPCI405DT.h | 33 --------------------------------- 3 files changed, 0 insertions(+), 93 deletions(-) diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index b248639..fd49f56 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -88,32 +88,17 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_ELF #define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_BSP #define CONFIG_CMD_EEPROM - -#if 0 /* test-only */ -#define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI - -#ifdef CONFIG_NET_MULTI -#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ -#endif -#endif - #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -#if 0 /* test-only */ -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#endif - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -256,29 +241,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition, use whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci4052-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)" -*/ - #if 0 /* Use NVRAM for environment variables */ /*----------------------------------------------------------------------- * NVRAM organization diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 1e9597d..55dd629 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -88,7 +88,6 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_ELF #define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING @@ -238,27 +237,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/* - * JFFS2 partitions - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci405ab-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)" -*/ - /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC32) for environment */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index a8029ea..6b585be 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -87,23 +87,12 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_ELF #define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_BSP #define CONFIG_CMD_EEPROM - -#if 0 /* test-only */ -#define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI - -#ifdef CONFIG_NET_MULTI -#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ -#endif -#endif - #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -260,27 +249,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/* - * JFFS2 partitions - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci405dt-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci405dt-0:-(jffs2)" -*/ - #if 0 /* Use NVRAM for environment variables */ /*----------------------------------------------------------------------- * NVRAM organization @@ -416,7 +384,6 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - /* * Internal Definitions * -- 1.5.3

2 1

[U-Boot-Users] [PATCH] Remove shell variable UNDEF_SYM.
by Kenneth Johansson 03 Jun '08

03 Jun '08

UNDEF_SYM is a shell variable in the main Makefile used to force the linker to add all u-boot commands to the final image. It has no use here. Signed-off-by: Kenneth Johansson <kenneth(a)southpole.se> --- nand_spl/board/amcc/acadia/Makefile | 2 +- nand_spl/board/amcc/bamboo/Makefile | 2 +- nand_spl/board/amcc/canyonlands/Makefile | 2 +- nand_spl/board/amcc/kilauea/Makefile | 2 +- nand_spl/board/amcc/sequoia/Makefile | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index 4272108..931f04b 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -51,7 +51,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile index aed7960..e1c1467 100644 --- a/nand_spl/board/amcc/bamboo/Makefile +++ b/nand_spl/board/amcc/bamboo/Makefile @@ -50,7 +50,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile index 47c7d02..fb86752 100644 --- a/nand_spl/board/amcc/canyonlands/Makefile +++ b/nand_spl/board/amcc/canyonlands/Makefile @@ -55,7 +55,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile index 84bd298..f47261f 100644 --- a/nand_spl/board/amcc/kilauea/Makefile +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -50,7 +50,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile index 93150aa..fba0322 100644 --- a/nand_spl/board/amcc/sequoia/Makefile +++ b/nand_spl/board/amcc/sequoia/Makefile @@ -50,7 +50,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(nandobj)u-boot-spl: $(OBJS) - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl --

2 1

[U-Boot-Users] [PATCH 2/2 v3] PPC4xx: Enable Primordial Stack for 40x and Unify ECC Handling
by Grant Erickson 03 Jun '08

03 Jun '08

This patch (Part 2 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> --- board/amcc/kilauea/init.S | 227 ++++++++++++++++--------------- board/amcc/kilauea/memory.c | 5 + board/amcc/makalu/Makefile | 2 +- board/amcc/makalu/init.S | 125 +----------------- board/amcc/makalu/makalu.c | 5 + board/amcc/makalu/memory.c | 188 -------------------------- include/configs/kilauea.h | 108 +++++++++++++-- include/configs/makalu.h | 114 ++++++++++++++-- 8 files changed diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S index 8cd534c..bf47d6b 100644 --- a/board/amcc/kilauea/init.S +++ b/board/amcc/kilauea/init.S @@ -1,8 +1,11 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * - * Based on code provided from UDTech and AMCC + * Originally based on code provided from UDTech and AMCC * * See file CREDITS for list of people who contributed to this * project. @@ -30,125 +33,135 @@ #include <ppc_defs.h> #define mtsdram_as(reg, value) \ - addi r4,0,reg ; \ - mtdcr memcfga,r4 ; \ - addis r4,0,value@h ; \ - ori r4,r4,value@l ; \ - mtdcr memcfgd,r4 ; + addi r4,0,reg ; \ + mtdcr memcfga,r4 ; \ + addis r4,0,value@h ; \ + ori r4,r4,value@l ; \ + mtdcr memcfgd,r4 ; + +#if defined(CONFIG_DDR_ECC) + .extern ecc_init +#endif /* defined(CONFIG_DDR_ECC) */ .globl ext_bus_cntlr_init ext_bus_cntlr_init: +#if !defined(CFG_INIT_DCACHE_CS) #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) /* - * DDR2 setup + * DDR2 SDRAM Controller Setup */ - /* Following the DDR Core Manual, here is the initialization */ - - /* Step 1 */ - - /* Step 2 */ - - /* Step 3 */ - - /* base=00000000, size=256MByte (6), mode=7 (n*10*8) */ - mtsdram_as(SDRAM_MB0CF, 0x00006701); - - /* SET SDRAM_MB1CF - Not enabled */ - mtsdram_as(SDRAM_MB1CF, 0x00000000); - - /* SET SDRAM_MB2CF - Not enabled */ - mtsdram_as(SDRAM_MB2CF, 0x00000000); - - /* SET SDRAM_MB3CF - Not enabled */ - mtsdram_as(SDRAM_MB3CF, 0x00000000); - - /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ - mtsdram_as(SDRAM_CLKTR, 0x80000000); - - /* Refresh Time register (0x30) Refresh every 7.8125uS */ - mtsdram_as(SDRAM_RTR, 0x06180000); + /* Set Memory Bank Configuration Registers */ + mtsdram_as(SDRAM_MB0CF, CFG_SDRAM0_MB0CF); + mtsdram_as(SDRAM_MB1CF, CFG_SDRAM0_MB1CF); + mtsdram_as(SDRAM_MB2CF, CFG_SDRAM0_MB2CF); + mtsdram_as(SDRAM_MB3CF, CFG_SDRAM0_MB3CF); + + /* Set Memory Clock Timing Register */ + mtsdram_as(SDRAM_CLKTR, CFG_SDRAM0_CLKTR); + + /* Set Refresh Time Register */ + mtsdram_as(SDRAM_RTR, CFG_SDRAM0_RTR); + + /* Set SDRAM Timing Registers */ + mtsdram_as(SDRAM_SDTR1, CFG_SDRAM0_SDTR1); + mtsdram_as(SDRAM_SDTR2, CFG_SDRAM0_SDTR2); + mtsdram_as(SDRAM_SDTR3, CFG_SDRAM0_SDTR3); + + /* Set Mode and Extended Mode Registers */ + mtsdram_as(SDRAM_MMODE, CFG_SDRAM0_MMODE); + mtsdram_as(SDRAM_MEMODE, CFG_SDRAM0_MEMODE); + + /* Set Memory Controller Options 1 Register */ + mtsdram_as(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1); + + /* Set Manual Initialization Control Registers */ + mtsdram_as(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0); + mtsdram_as(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1); + mtsdram_as(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2); + mtsdram_as(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3); + mtsdram_as(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4); + mtsdram_as(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5); + mtsdram_as(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6); + mtsdram_as(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7); + mtsdram_as(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8); + mtsdram_as(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9); + mtsdram_as(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10); + mtsdram_as(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11); + mtsdram_as(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12); + mtsdram_as(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13); + mtsdram_as(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14); + mtsdram_as(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15); + + /* Set On-Die Termination Registers */ + mtsdram_as(SDRAM_CODT, CFG_SDRAM0_CODT); + mtsdram_as(SDRAM_MODT0, CFG_SDRAM0_MODT0); + mtsdram_as(SDRAM_MODT1, CFG_SDRAM0_MODT1); + + /* Set Write Timing Register */ + mtsdram_as(SDRAM_WRDTR, CFG_SDRAM0_WRDTR); - /* SDRAM_SDTR1 */ - mtsdram_as(SDRAM_SDTR1, 0x80201000); - - /* SDRAM_SDTR2 */ - mtsdram_as(SDRAM_SDTR2, 0x32204232); + /* + * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and + * SDRAM0_MCOPT2[IPTR] = 1 + */ + mtsdram_as(SDRAM_MCOPT2, SDRAM_MCOPT2_SREN_EXIT | \ + SDRAM_MCOPT2_IPTR_EXECUTE); - /* SDRAM_SDTR3 */ - mtsdram_as(SDRAM_SDTR3, 0x080b0d1a); + /* + * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the + * completion of initialization. + * + * do { + * mfsdram(SDRAM_MCSTAT, val); + * } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP); + */ + li r4,SDRAM_MCSTAT + lis r2,SDRAM_MCSTAT_MIC_COMP@h + ori r2,r2,SDRAM_MCSTAT_MIC_COMP@l +0: mtdcr memcfga,r4 + mfdcr r3,memcfgd + clrrwi r3,r3,31 + cmpw cr7,r3,r2 + bne+ cr7,0b + + /* Set Delay Control Registers */ + mtsdram_as(SDRAM_DLCR, CFG_SDRAM0_DLCR); + mtsdram_as(SDRAM_RDCC, CFG_SDRAM0_RDCC); + mtsdram_as(SDRAM_RQDC, CFG_SDRAM0_RQDC); + mtsdram_as(SDRAM_RFDC, CFG_SDRAM0_RFDC); - mtsdram_as(SDRAM_MMODE, 0x00000442); - mtsdram_as(SDRAM_MEMODE, 0x00000404); + /* + * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: + * + * mcopt2 = mfsdram(SDRAM_MCOPT2); + */ + li r4,SDRAM_MCOPT2 + mtdcr memcfga,r4 + mfdcr r3,memcfgd - /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ - mtsdram_as(SDRAM_MCOPT1, 0x04322000); + /* + * mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE); + */ + mtdcr memcfga,r4 + oris r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@h + ori r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@l + mtdcr memcfgd,r3 - /* NOP */ - mtsdram_as(SDRAM_INITPLR0, 0xa8380000); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR1, 0x81900400); - /* EMR2 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR2, 0x81020000); - /* EMR3 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR3, 0x81030000); - /* EMR DLL ENABLE twr = 2tck */ - mtsdram_as(SDRAM_INITPLR4, 0x81010404); - /* MR w/ DLL reset - * Note: 5 is CL. May need to be changed +#if defined(CONFIG_DDR_ECC) + /* + * ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); */ - mtsdram_as(SDRAM_INITPLR5, 0x81000542); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR6, 0x81900400); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR7, 0x8D080000); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR8, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR9, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR10, 0x8D080000); - /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ - mtsdram_as(SDRAM_INITPLR11, 0x81000442); - mtsdram_as(SDRAM_INITPLR12, 0x81010780); - mtsdram_as(SDRAM_INITPLR13, 0x81010400); - mtsdram_as(SDRAM_INITPLR14, 0x00000000); - mtsdram_as(SDRAM_INITPLR15, 0x00000000); - - /* SET MCIF0_CODT Die Termination On */ - mtsdram_as(SDRAM_CODT, 0x0080f837); - mtsdram_as(SDRAM_MODT0, 0x01800000); - mtsdram_as(SDRAM_MODT1, 0x00000000); - - mtsdram_as(SDRAM_WRDTR, 0x00000000); - - /* SDRAM0_MCOPT2 (0X21) Start initialization */ - mtsdram_as(SDRAM_MCOPT2, 0x20000000); - - /* Step 5 */ - lis r3,0x1 /* 400000 = wait 100ms */ - mtctr r3 - -pll_wait: - bdnz pll_wait - - /* Step 6 */ - - /* SDRAM_DLCR */ - mtsdram_as(SDRAM_DLCR, 0x030000a5); - - /* SDRAM_RDCC */ - mtsdram_as(SDRAM_RDCC, 0x40000000); - - /* SDRAM_RQDC */ - mtsdram_as(SDRAM_RQDC, 0x80000038); - - /* SDRAM_RFDC */ - mtsdram_as(SDRAM_RFDC, 0x00000209); - - /* Enable memory controller */ - mtsdram_as(SDRAM_MCOPT2, 0x28000000); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ + mflr r13 + lis r3,CFG_SDRAM_BASE@h + ori r3,r3,CFG_SDRAM_BASE@l + lis r4,(CFG_MBYTES_SDRAM << 20)@h + ori r4,r4,(CFG_MBYTES_SDRAM << 20)@l + bl ecc_init + mtlr r13 +#endif /* defined(CONFIG_DDR_ECC) */ +#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ +#endif /* !defined(CFG_INIT_DCACHE_CS) */ blr diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c index 1d7a3fa..b7e2344 100644 --- a/board/amcc/kilauea/memory.c +++ b/board/amcc/kilauea/memory.c @@ -1,4 +1,7 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * @@ -30,10 +33,12 @@ void sdram_init(void) return; } +#if defined(CONFIG_NAND_U_BOOT) long int initdram(int board_type) { return (CFG_MBYTES_SDRAM << 20); } +#endif /* defined(CONFIG_NAND_U_BOOT) */ #if defined(CFG_DRAM_TEST) int testdram (void) diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile index 39328c2..4def0d4 100644 --- a/board/amcc/makalu/Makefile +++ b/board/amcc/makalu/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cmd_pll.o memory.o +COBJS = $(BOARD).o cmd_pll.o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S index 11c5b19..4d0f460 100644 --- a/board/amcc/makalu/init.S +++ b/board/amcc/makalu/init.S @@ -1,8 +1,11 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * - * Based on code provided from Senao and AMCC + * Originally based on code provided from Senao and AMCC * * See file CREDITS for list of people who contributed to this * project. @@ -23,126 +26,6 @@ * MA 02111-1307 USA */ -#include <config.h> -#include <ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#define mtsdram_as(reg, value) \ - addi r4,0,reg ; \ - mtdcr memcfga,r4 ; \ - addis r4,0,value@h ; \ - ori r4,r4,value@l ; \ - mtdcr memcfgd,r4 ; - .globl ext_bus_cntlr_init ext_bus_cntlr_init: - - /* - * DDR2 setup - */ - - /* Following the DDR Core Manual, here is the initialization */ - - /* Step 1 */ - - /* Step 2 */ - - /* Step 3 */ - - /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */ - mtsdram_as(SDRAM_MB0CF, 0x00005201); - - /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */ - mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201); - - /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ - mtsdram_as(SDRAM_CLKTR,0x80000000); - - /* Refresh Time register (0x30) Refresh every 7.8125uS */ - mtsdram_as(SDRAM_RTR, 0x06180000); - - /* SDRAM_SDTR1 */ - mtsdram_as(SDRAM_SDTR1, 0x80201000); - - /* SDRAM_SDTR2 */ - mtsdram_as(SDRAM_SDTR2, 0x32204232); - - /* SDRAM_SDTR3 */ - mtsdram_as(SDRAM_SDTR3, 0x080b0d1a); - - mtsdram_as(SDRAM_MMODE, 0x00000442); - mtsdram_as(SDRAM_MEMODE, 0x00000404); - - /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ - mtsdram_as(SDRAM_MCOPT1, 0x04322000); - - /* NOP */ - mtsdram_as(SDRAM_INITPLR0, 0xa8380000); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR1, 0x81900400); - /* EMR2 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR2, 0x81020000); - /* EMR3 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR3, 0x81030000); - /* EMR DLL ENABLE twr = 2tck */ - mtsdram_as(SDRAM_INITPLR4, 0x81010404); - /* MR w/ DLL reset - * Note: 5 is CL. May need to be changed - */ - mtsdram_as(SDRAM_INITPLR5, 0x81000542); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR6, 0x81900400); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR7, 0x8D080000); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR8, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR9, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR10, 0x8D080000); - /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ - mtsdram_as(SDRAM_INITPLR11, 0x81000442); - mtsdram_as(SDRAM_INITPLR12, 0x81010780); - mtsdram_as(SDRAM_INITPLR13, 0x81010400); - mtsdram_as(SDRAM_INITPLR14, 0x00000000); - mtsdram_as(SDRAM_INITPLR15, 0x00000000); - - /* SET MCIF0_CODT Die Termination On */ - mtsdram_as(SDRAM_CODT, 0x0080f837); - mtsdram_as(SDRAM_MODT0, 0x01800000); -#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */ - mtsdram_as(SDRAM_MODT1, 0x00000000); -#endif - - mtsdram_as(SDRAM_WRDTR, 0x00000000); - - /* SDRAM0_MCOPT2 (0X21) Start initialization */ - mtsdram_as(SDRAM_MCOPT2, 0x20000000); - - /* Step 5 */ - lis r3,0x1 /* 400000 = wait 100ms */ - mtctr r3 - -pll_wait: - bdnz pll_wait - - /* Step 6 */ - - /* SDRAM_DLCR */ - mtsdram_as(SDRAM_DLCR, 0x030000a5); - - /* SDRAM_RDCC */ - mtsdram_as(SDRAM_RDCC, 0x40000000); - - /* SDRAM_RQDC */ - mtsdram_as(SDRAM_RQDC, 0x80000038); - - /* SDRAM_RFDC */ - mtsdram_as(SDRAM_RFDC, 0x00000209); - - /* Enable memory controller */ - mtsdram_as(SDRAM_MCOPT2, 0x28000000); - blr diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c index 9baec9a..adf604f 100644 --- a/board/amcc/makalu/makalu.c +++ b/board/amcc/makalu/makalu.c @@ -351,3 +351,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_strerror(rc)); } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +void sdram_init(void) +{ + return; +} diff --git a/board/amcc/makalu/memory.c b/board/amcc/makalu/memory.c deleted file mode 100644 index b03b60b..0000000 --- a/board/amcc/makalu/memory.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> - -void sdram_init(void) -{ - return; -} - -long int initdram(int board_type) -{ - /* - * Same as on Kilauea, Makalu generates exception 0x200 - * (machine check) after trap_init() in board_init_f, - * when SDRAM is initialized here (late) and d-cache is - * used earlier as INIT_RAM. - * So for now, initialize DDR2 in init.S very early and - * also use it for INIT_RAM. Then this exception doesn't - * occur. - */ -#if 0 - u32 val; - - /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */ - mtsdram(SDRAM_MB0CF, 0x00005201); - - /* SET SDRAM_MB1CF - Not enabled */ - mtsdram(SDRAM_MB1CF, 0x00000000); - - /* SET SDRAM_MB2CF - Not enabled */ - mtsdram(SDRAM_MB2CF, 0x00000000); - - /* SET SDRAM_MB3CF - Not enabled */ - mtsdram(SDRAM_MB3CF, 0x00000000); - - /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ - mtsdram(SDRAM_CLKTR, 0x80000000); - - /* Refresh Time register (0x30) Refresh every 7.8125uS */ - mtsdram(SDRAM_RTR, 0x06180000); - - /* SDRAM_SDTR1 */ - mtsdram(SDRAM_SDTR1, 0x80201000); - - /* SDRAM_SDTR2 */ - mtsdram(SDRAM_SDTR2, 0x32204232); - - /* SDRAM_SDTR3 */ - mtsdram(SDRAM_SDTR3, 0x080b0d1a); - - mtsdram(SDRAM_MMODE, 0x00000442); - mtsdram(SDRAM_MEMODE, 0x00000404); - - /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ - mtsdram(SDRAM_MCOPT1, 0x04322000); - - /* NOP */ - mtsdram(SDRAM_INITPLR0, 0xa8380000); - /* precharge 3 DDR clock cycle */ - mtsdram(SDRAM_INITPLR1, 0x81900400); - /* EMR2 twr = 2tck */ - mtsdram(SDRAM_INITPLR2, 0x81020000); - /* EMR3 twr = 2tck */ - mtsdram(SDRAM_INITPLR3, 0x81030000); - /* EMR DLL ENABLE twr = 2tck */ - mtsdram(SDRAM_INITPLR4, 0x81010404); - /* MR w/ DLL reset - * Note: 5 is CL. May need to be changed - */ - mtsdram(SDRAM_INITPLR5, 0x81000542); - /* precharge 3 DDR clock cycle */ - mtsdram(SDRAM_INITPLR6, 0x81900400); - /* Auto-refresh trfc = 26tck */ - mtsdram(SDRAM_INITPLR7, 0x8D080000); - /* Auto-refresh trfc = 26tck */ - mtsdram(SDRAM_INITPLR8, 0x8D080000); - /* Auto-refresh */ - mtsdram(SDRAM_INITPLR9, 0x8D080000); - /* Auto-refresh */ - mtsdram(SDRAM_INITPLR10, 0x8D080000); - /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ - mtsdram(SDRAM_INITPLR11, 0x81000442); - mtsdram(SDRAM_INITPLR12, 0x81010780); - mtsdram(SDRAM_INITPLR13, 0x81010400); - mtsdram(SDRAM_INITPLR14, 0x00000000); - mtsdram(SDRAM_INITPLR15, 0x00000000); - - /* SET MCIF0_CODT Die Termination On */ - mtsdram(SDRAM_CODT, 0x0080f837); - mtsdram(SDRAM_MODT0, 0x01800000); - mtsdram(SDRAM_MODT1, 0x00000000); - - mtsdram(SDRAM_WRDTR, 0x00000000); - - /* SDRAM0_MCOPT2 (0X21) Start initialization */ - mtsdram(SDRAM_MCOPT2, 0x20000000); - - /* Step 5 */ - do { - mfsdram(SDRAM_MCSTAT, val); - } while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP); - - /* Step 6 */ - - /* SDRAM_DLCR */ - mtsdram(SDRAM_DLCR, 0x030000a5); - - /* SDRAM_RDCC */ - mtsdram(SDRAM_RDCC, 0x40000000); - - /* SDRAM_RQDC */ - mtsdram(SDRAM_RQDC, 0x80000038); - - /* SDRAM_RFDC */ - mtsdram(SDRAM_RFDC, 0x00000209); - - /* Enable memory controller */ - mfsdram(SDRAM_MCOPT2, val); - val |= SDRAM_MCOPT2_DCEN_ENABLE; - mtsdram(SDRAM_MCOPT2, val); -#endif - return (CFG_MBYTES_SDRAM << 20); -} - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - printf ("testdram\n"); -#if defined (CONFIG_NAND_U_BOOT) - return 0; -#endif - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x00001000; - uint *p; - - for (p = pstart; p < pend; p++) { - *p = 0xaaaaaaaa; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } - - for (p = pstart; p < pend; p++) { - *p = 0x55555555; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test passed!!!\n"); -#endif - return 0; -} -#endif diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index a596768..035a40e 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -1,4 +1,7 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * @@ -54,20 +57,56 @@ #define CFG_MONITOR_BASE (TEXT_BASE) /*----------------------------------------------------------------------- - * Initial RAM & stack pointer - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END (4 << 10) + * Initial RAM & Stack Pointer Configuration Options + * + * There are traditionally three options for the primordial + * (i.e. initial) stack usage on the 405-series: + * + * 1) On-chip Memory (OCM) (i.e. SRAM) + * 2) Data cache + * 3) SDRAM + * + * For the 405EX(r), there is no OCM, so we are left with (2) or (3) + * the latter of which is less than desireable since it requires + * setting up the SDRAM and ECC in assembly code. + * + * To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip + * select on the External Bus Controller (EBC) and then select a + * value for 'CFG_INIT_RAM_ADDR' outside of the range of valid, + * physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and + * select a value for 'CFG_INIT_RAM_ADDR' within the range of valid, + * physical SDRAM to use (3). + *-----------------------------------------------------------------------*/ + +#define CFG_INIT_DCACHE_CS 4 + +#if defined(CFG_INIT_DCACHE_CS) +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */ +#else +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */ +#endif /* defined(CFG_INIT_DCACHE_CS) */ + +#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -/* reserve some memory for POST and BOOT limit info */ -#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) -/* extra data in init-ram */ -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) -#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8) -#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12) -#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */ +/* + * If the data cache is being used for the primordial stack and global + * data area, the POST word must be placed somewhere else. The General + * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves + * its compare and mask register contents across reset, so it is used + * for the POST word. + */ + +#if defined(CFG_INIT_DCACHE_CS) +# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) +#else +# define CFG_INIT_EXTRA_SIZE 16 +# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE) +# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR +#endif /* defined(CFG_INIT_DCACHE_CS) */ /*----------------------------------------------------------------------- * Serial Port @@ -187,6 +226,50 @@ *----------------------------------------------------------------------*/ #define CFG_MBYTES_SDRAM (256) /* 256MB */ +#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE) + +/* DDR1/2 SDRAM Device Control Register Data Values */ +#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \ + SDRAM_RXBAS_SDSZ_256MB | \ + SDRAM_RXBAS_SDAM_MODE7 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MCOPT1 0x04322000 +#define CFG_SDRAM0_MCOPT2 0x00000000 +#define CFG_SDRAM0_MODT0 0x01800000 +#define CFG_SDRAM0_MODT1 0x00000000 +#define CFG_SDRAM0_CODT 0x0080f837 +#define CFG_SDRAM0_RTR 0x06180000 +#define CFG_SDRAM0_INITPLR0 0xa8380000 +#define CFG_SDRAM0_INITPLR1 0x81900400 +#define CFG_SDRAM0_INITPLR2 0x81020000 +#define CFG_SDRAM0_INITPLR3 0x81030000 +#define CFG_SDRAM0_INITPLR4 0x81010404 +#define CFG_SDRAM0_INITPLR5 0x81000542 +#define CFG_SDRAM0_INITPLR6 0x81900400 +#define CFG_SDRAM0_INITPLR7 0x8D080000 +#define CFG_SDRAM0_INITPLR8 0x8D080000 +#define CFG_SDRAM0_INITPLR9 0x8D080000 +#define CFG_SDRAM0_INITPLR10 0x8D080000 +#define CFG_SDRAM0_INITPLR11 0x81000442 +#define CFG_SDRAM0_INITPLR12 0x81010780 +#define CFG_SDRAM0_INITPLR13 0x81010400 +#define CFG_SDRAM0_INITPLR14 0x00000000 +#define CFG_SDRAM0_INITPLR15 0x00000000 +#define CFG_SDRAM0_RQDC 0x80000038 +#define CFG_SDRAM0_RFDC 0x00000209 +#define CFG_SDRAM0_RDCC 0x40000000 +#define CFG_SDRAM0_DLCR 0x030000a5 +#define CFG_SDRAM0_CLKTR 0x80000000 +#define CFG_SDRAM0_WRDTR 0x00000000 +#define CFG_SDRAM0_SDTR1 0x80201000 +#define CFG_SDRAM0_SDTR2 0x32204232 +#define CFG_SDRAM0_SDTR3 0x080b0d1a +#define CFG_SDRAM0_MMODE 0x00000442 +#define CFG_SDRAM0_MEMODE 0x00000404 + /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ @@ -319,8 +402,7 @@ #define CONFIG_CMD_SNTP /* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CACHE | \ +#define CONFIG_POST (CFG_POST_CACHE | \ CFG_POST_CPU | \ CFG_POST_ETHER | \ CFG_POST_I2C | \ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index af066f3..566e611 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -1,4 +1,7 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * @@ -52,20 +55,56 @@ #define CFG_MONITOR_BASE (TEXT_BASE) /*----------------------------------------------------------------------- - * Initial RAM & stack pointer - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END (4 << 10) + * Initial RAM & Stack Pointer Configuration Options + * + * There are traditionally three options for the primordial + * (i.e. initial) stack usage on the 405-series: + * + * 1) On-chip Memory (OCM) (i.e. SRAM) + * 2) Data cache + * 3) SDRAM + * + * For the 405EX(r), there is no OCM, so we are left with (2) or (3) + * the latter of which is less than desireable since it requires + * setting up the SDRAM and ECC in assembly code. + * + * To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip + * select on the External Bus Controller (EBC) and then select a + * value for 'CFG_INIT_RAM_ADDR' outside of the range of valid, + * physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and + * select a value for 'CFG_INIT_RAM_ADDR' within the range of valid, + * physical SDRAM to use (3). + *-----------------------------------------------------------------------*/ + +#define CFG_INIT_DCACHE_CS 4 + +#if defined(CFG_INIT_DCACHE_CS) +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */ +#else +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */ +#endif /* defined(CFG_INIT_DCACHE_CS) */ + +#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -/* reserve some memory for POST and BOOT limit info */ -#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) -/* extra data in init-ram */ -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) -#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8) -#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12) -#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */ +/* + * If the data cache is being used for the primordial stack and global + * data area, the POST word must be placed somewhere else. The General + * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves + * its compare and mask register contents across reset, so it is used + * for the POST word. + */ + +#if defined(CFG_INIT_DCACHE_CS) +# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) +#else +# define CFG_INIT_EXTRA_SIZE 16 +# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE) +# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR +#endif /* defined(CFG_INIT_DCACHE_CS) */ /*----------------------------------------------------------------------- * Serial Port @@ -113,7 +152,55 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CFG_MBYTES_SDRAM 256 +#define CFG_MBYTES_SDRAM (256) /* 256MB */ + +#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE) +#define CFG_SDRAM0_MB1CF_BASE ((128 << 20) + CFG_SDRAM_BASE) + +/* DDR1/2 SDRAM Device Control Register Data Values */ +#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \ + SDRAM_RXBAS_SDSZ_128MB | \ + SDRAM_RXBAS_SDAM_MODE2 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CFG_SDRAM0_MB1CF ((CFG_SDRAM0_MB1CF_BASE >> 3) | \ + SDRAM_RXBAS_SDSZ_128MB | \ + SDRAM_RXBAS_SDAM_MODE2 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MCOPT1 0x04322000 +#define CFG_SDRAM0_MCOPT2 0x00000000 +#define CFG_SDRAM0_MODT0 0x01800000 +#define CFG_SDRAM0_MODT1 0x00000000 +#define CFG_SDRAM0_CODT 0x0080f837 +#define CFG_SDRAM0_RTR 0x06180000 +#define CFG_SDRAM0_INITPLR0 0xa8380000 +#define CFG_SDRAM0_INITPLR1 0x81900400 +#define CFG_SDRAM0_INITPLR2 0x81020000 +#define CFG_SDRAM0_INITPLR3 0x81030000 +#define CFG_SDRAM0_INITPLR4 0x81010404 +#define CFG_SDRAM0_INITPLR5 0x81000542 +#define CFG_SDRAM0_INITPLR6 0x81900400 +#define CFG_SDRAM0_INITPLR7 0x8D080000 +#define CFG_SDRAM0_INITPLR8 0x8D080000 +#define CFG_SDRAM0_INITPLR9 0x8D080000 +#define CFG_SDRAM0_INITPLR10 0x8D080000 +#define CFG_SDRAM0_INITPLR11 0x81000442 +#define CFG_SDRAM0_INITPLR12 0x81010780 +#define CFG_SDRAM0_INITPLR13 0x81010400 +#define CFG_SDRAM0_INITPLR14 0x00000000 +#define CFG_SDRAM0_INITPLR15 0x00000000 +#define CFG_SDRAM0_RQDC 0x80000038 +#define CFG_SDRAM0_RFDC 0x00000209 +#define CFG_SDRAM0_RDCC 0x40000000 +#define CFG_SDRAM0_DLCR 0x030000a5 +#define CFG_SDRAM0_CLKTR 0x80000000 +#define CFG_SDRAM0_WRDTR 0x00000000 +#define CFG_SDRAM0_SDTR1 0x80201000 +#define CFG_SDRAM0_SDTR2 0x32204232 +#define CFG_SDRAM0_SDTR3 0x080b0d1a +#define CFG_SDRAM0_MMODE 0x00000442 +#define CFG_SDRAM0_MEMODE 0x00000404 /*----------------------------------------------------------------------- * I2C @@ -244,8 +331,7 @@ #define CONFIG_CMD_SNTP /* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CACHE | \ +#define CONFIG_POST (CFG_POST_CACHE | \ CFG_POST_CPU | \ CFG_POST_ETHER | \ CFG_POST_I2C | \

2 1