May 2008 - U-Boot

[U-Boot-Users] Güvenlik Sektörünün E-Bülteni (Sayı:6)
by ISAF e-bülten 31 May '08

31 May '08

Isaffuari e-Bülten, Nisan 2008 END OF CONDITIONAL HTML HIDING --> Son yıllarda,  Tüm yıllarda artan olaylar nedeniyle güvenliğe daha fazla önem veriliyor olması ve güvenlik sistemleri kullanımının artmış olması,  Genel güvenlik amacıyla şehirlerde izleme, gözetleme sistemlerinin kullanılıyor olması, Yeni yasa ve yönetmeliklerde binaların inşa aşamasında güvenlik ve yangın projelerinin artık zorunlu olması,  Güvenlik ve yangın sistemleri ve hizmetlerinin artık lüks kullanım malzemeleri değil, ihtiyaç malzemeleri olması,  Yeni inşa edilen binalarda, toplu konutlarda akıllı bina sistemleri kullanılması ve bu sistemlerde mutlaka güvenlik ve yangın malzemelerinin de kullanılıyor olması,  Güvenlik sektöründe, yangın önleme ve engelleme sistemlerinde yaşanan hızlı gelişmeler nedeniyle, ürün ve hizmetlerin mutlaka sergilenme ihtiyacının olması,  Güvenlik sistemlerinin işyerlerinde verimi arttırmak amacıyla sadece güvenlik değil, işyerinde potansiyel takip amacıyla da kullanılıyor olması,  Özellikle orman yangınlarında ciddi oranlarda artış olması,  Ülkemizin deprem kuşağında yer almasında dolayı yaşanabilecek doğal afet riski bilincinin artmış olması, ve bu alanlarda bütçelerin artması nedeniyle sektörlerin pazarlarının genişlediği bu dönemde Isaf Fuarı'nın önemi bir kat daha artmıştır. ISAF İSTANBUL Katılım için Tıklayın Online Fuar Davetiyesi için tıklayın Güncel Yerleşim Planı Listemize girmek istiyorsanız lütfen buraya tıklayın. Listemizden çıkmak istiyorsanız lütfen buraya tıklayın. Bülten hakkında bilgi almak istiyorsanız buraya tıklayın. Bülteni arkadaşınıza tavsiye etmek için lütfen buraya tıklayın. SEKTÖRE ULUŞMANIN EN KOLAY YOLU HOCHIKI EUROPE İLK KEZ TÜRKİYE'DE BİR FUARA KATILMA KARARI ALDI. Hochiki Europe, 28 - 31 Ağustos tarihleri arasında Istanbul'da düzenlenecek olan ISAF Fuarı'na katılma kararı aldı. ISAF, Hochiki Europe'un Türkiye'de katılacağı ilk fuar olacak. Hochiki ISAF'ta yeni ürünleri analog adresli ve konvansiyonel yangın algılama sistemi EN54 ile birlikte duman dedektörleri ve yangın alarmlarını ve yeni sesli tahliye ve hava temizleme sistemlerini sergileyecek. Haberin Devamı... 10. ULUSLAR ARASI ISAF FUARI ANKARA'DA BAŞARI İLE TAMAMLANDI Türkiye'nin en büyük Güvenlik Fuarı olan Uluslararası ISAF Fuarı'nın 10.su Ankara'da organize edildi. Türkiye'nin dört bir yanından sektörün ilgisinin yanı sıra yurtdışından da Hochiki, Sony, Safco Grup gibi büyük firmalar tarafından da ziyaret edildi. Fuarı 20.000'e yakın profesyonel ziyaret etti. Haberin Devamı... ÖNCÜ GÜVENLİK SİSTEMLERİ BAYİLERİNE ÜRÜNLERİNİ TANITTI. Öncü Güvenlik Sistemleri yeni ürünlerini Mart ayında kendi binalarında düzenlediği seminerle bayilerine tanıttı. Haberin Devamı... OKUL ÇEVRELERİNDE SIKI GÜVENLİK TEDBİRİ Okul çevrelerine de MOBESE kurulacak. Polisin gözü kulağı olan sistem, suçların azalmasında ve zanlıların yakalanmasında büyük önem taşıyor. Haberin Devamı... FİLYOS KAMERALARLA İZLENECEK Zonguldak'ın Çaycuma ilçesine bağlı filyos beldesinde başta hırsızlık gibi artan mala karşı suçlar nedeniyle belediye başkanı ve emniyet güçleri harekete geçti. Haberin Devamı... TAKSİLERE GİZLİ KAMERA İstanbul Emniyet Müdürlüğü, taksici cinayetlerini, gasp olaylarını ve korsan taksileri önlemek için, büyük bir projeye imza atıyor. Önümüzdeki günlerde taksilere konacak gizli kamera ve cihazlar sayesinde emniyet birimleri, herhangi bir yasadışı olaya anında müdahale edecek, yanından geçen taksinin korsan olup olmadığını anında anlayacak. Haberin Devamı... İHALE HABERLERİ Aşağıdaki linklerden sizinle ilgili ihale detaylarına ulaşabilirsiniz. Güvenlik Sistemi ve Cihazları Yangın Malzemeleri Yangın Söndürme Cihazları Kaynak: dgmarket.com.tr BU FUAR 5174 SAYILI KANUN GEREĞİNCE TOBB (TÜRKİYE ODALAR BORSALAR BİRLİĞİ) İZNİ İLE DÜZENLENMEKTEDİR. Marmara Tanıtım Fuarcılık İstanbul (Merkez) Tel: +90 212 481 04 04 Fax: +90 212 481 04 74 Ankara (Şube) Tel: +90 312 426 64 22 Fax: +90 312 426 64 41 Izmir (Sube) Tel: +90 232 422 00 93 Fax: +90 232 422 16 33

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[U-Boot-Users] [PATCH 4/8] New board SIMPC8313 support: support for booting from NAND in start.S
by Ron Madrid 31 May '08

31 May '08

New board SIMPC8313 support: support for booting from NAND in start.S Reorganization/optimization of a few functions to fit into the 4K FCM boot RAM of the MPC8313 for nand_spl build. Signed-off-by: Ron Madrid --- cpu/mpc83xx/start.S | 310 ++++++++++++++++++++++++++++++++++++--------------- 1 files changed, 220 insertions(+), 90 deletions(-) diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 309eb30..39bcaa8 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -63,6 +63,9 @@ * Use r14 to access the GOT */ START_GOT +#if defined(CONFIG_NAND_SPL) + GOT_ENTRY(_GOT_TABLE_) +#else GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) @@ -74,6 +77,7 @@ GOT_ENTRY(__init_end) GOT_ENTRY(_end) GOT_ENTRY(__bss_start) +#endif /* CONFIG_NAND_SPL */ END_GOT /* @@ -103,7 +107,56 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii " ", CONFIG_IDENT_STRING, "\0" + .align 4 + +/*****************************************************************/ + + .globl enable_addr_trans +enable_addr_trans: + /* enable address translation */ + mfmsr r5 + ori r5, r5, (MSR_IR | MSR_DR) + mtmsr r5 + isync + blr + +/* Cache functions. + * + * Note: requires that all cache bits in + * HID0 are in the low half word. + */ + .globl icache_enable +icache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_ICE + li r4, HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_enable +dcache_enable: + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr +/*****************************************************************/ #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined @@ -165,7 +218,7 @@ boot_warm: /* time t 5 */ bl init_e300_core -#ifndef CFG_RAMBOOT +#if !defined(CFG_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) /* Inflate flash location so it appears everywhere, calculate */ /* the absolute address in final location of the FLASH, jump */ @@ -181,7 +234,7 @@ in_flash: #if 1 /* Remapping flash with LAW0. */ bl remap_flash_by_law0 #endif -#endif /* CFG_RAMBOOT */ +#endif /* !defined(CFG_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) */ /* setup the bats */ bl setup_bats @@ -234,6 +287,7 @@ in_flash: /* run low-level CPU init code (in Flash)*/ bl cpu_init_f +#if !defined(CONFIG_NAND_SPL) /* r3: BOOTFLAG */ mr r3, r21 /* run 1st part of board init code (in Flash)*/ @@ -428,6 +482,7 @@ int_return: lwz r1,GPR1(r1) SYNC rfi +#endif /* CONFIG_NAND_SPL */ /* * This code initialises the E300 processor core @@ -550,6 +605,7 @@ init_e300_core: /* time t 10 */ /*------------------------------*/ blr +#if !defined(CONFIG_NAND_SPL) .globl invalidate_bats invalidate_bats: /* invalidate BATs */ @@ -577,6 +633,7 @@ invalidate_bats: isync sync blr +#endif /* CONFIG_NAND_SPL */ /* setup_bats - set them up to some initial state */ .globl setup_bats @@ -584,148 +641,228 @@ setup_bats: addis r0, r0, 0x0000 /* IBAT 0 */ +#if ((CFG_IBAT0L == 0) && (CFG_IBAT0U == 0)) + mtspr IBAT0L, r0 + mtspr IBAT0U, r0 +#else addis r4, r0, CFG_IBAT0L@h ori r4, r4, CFG_IBAT0L@l addis r3, r0, CFG_IBAT0U@h ori r3, r3, CFG_IBAT0U@l mtspr IBAT0L, r4 mtspr IBAT0U, r3 +#endif isync /* DBAT 0 */ +#if ((CFG_DBAT0L == 0) && (CFG_DBAT0U == 0)) + mtspr DBAT0L, r0 + mtspr DBAT0U, r0 +#else addis r4, r0, CFG_DBAT0L@h ori r4, r4, CFG_DBAT0L@l addis r3, r0, CFG_DBAT0U@h ori r3, r3, CFG_DBAT0U@l mtspr DBAT0L, r4 mtspr DBAT0U, r3 +#endif isync /* IBAT 1 */ +#if ((CFG_IBAT1L == 0) && (CFG_IBAT1U == 0)) + mtspr IBAT1L, r0 + mtspr IBAT1U, r0 +#else addis r4, r0, CFG_IBAT1L@h ori r4, r4, CFG_IBAT1L@l addis r3, r0, CFG_IBAT1U@h ori r3, r3, CFG_IBAT1U@l mtspr IBAT1L, r4 mtspr IBAT1U, r3 +#endif isync /* DBAT 1 */ +#if ((CFG_DBAT1L == 0) && (CFG_DBAT1U == 0)) + mtspr DBAT1L, r0 + mtspr DBAT1U, r0 +#else addis r4, r0, CFG_DBAT1L@h ori r4, r4, CFG_DBAT1L@l addis r3, r0, CFG_DBAT1U@h ori r3, r3, CFG_DBAT1U@l mtspr DBAT1L, r4 mtspr DBAT1U, r3 +#endif isync /* IBAT 2 */ +#if ((CFG_IBAT2L == 0) && (CFG_IBAT2U == 0)) + mtspr IBAT2L, r0 + mtspr IBAT2U, r0 +#else addis r4, r0, CFG_IBAT2L@h ori r4, r4, CFG_IBAT2L@l addis r3, r0, CFG_IBAT2U@h ori r3, r3, CFG_IBAT2U@l mtspr IBAT2L, r4 mtspr IBAT2U, r3 +#endif isync /* DBAT 2 */ +#if ((CFG_DBAT2L == 0) && (CFG_DBAT2U == 0)) + mtspr DBAT2L, r0 + mtspr DBAT2U, r0 +#else addis r4, r0, CFG_DBAT2L@h ori r4, r4, CFG_DBAT2L@l addis r3, r0, CFG_DBAT2U@h ori r3, r3, CFG_DBAT2U@l mtspr DBAT2L, r4 mtspr DBAT2U, r3 +#endif isync /* IBAT 3 */ +#if ((CFG_IBAT3L == 0) && (CFG_IBAT3U == 0)) + mtspr IBAT3L, r0 + mtspr IBAT3U, r0 +#else addis r4, r0, CFG_IBAT3L@h ori r4, r4, CFG_IBAT3L@l addis r3, r0, CFG_IBAT3U@h ori r3, r3, CFG_IBAT3U@l mtspr IBAT3L, r4 mtspr IBAT3U, r3 +#endif isync /* DBAT 3 */ +#if ((CFG_DBAT3L == 0) && (CFG_DBAT3U == 0)) + mtspr DBAT3L, r0 + mtspr DBAT3U, r0 +#else addis r4, r0, CFG_DBAT3L@h ori r4, r4, CFG_DBAT3L@l addis r3, r0, CFG_DBAT3U@h ori r3, r3, CFG_DBAT3U@l mtspr DBAT3L, r4 mtspr DBAT3U, r3 +#endif isync #if (CFG_HID2 & HID2_HBE) /* IBAT 4 */ +#if ((CFG_IBAT4L == 0) && (CFG_IBAT4U == 0)) + mtspr IBAT4L, r0 + mtspr IBAT4U, r0 +#else addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l addis r3, r0, CFG_IBAT4U@h ori r3, r3, CFG_IBAT4U@l mtspr IBAT4L, r4 mtspr IBAT4U, r3 +#endif isync /* DBAT 4 */ +#if ((CFG_DBAT4L == 0) && (CFG_DBAT4U == 0)) + mtspr DBAT4L, r0 + mtspr DBAT4U, r0 +#else addis r4, r0, CFG_DBAT4L@h ori r4, r4, CFG_DBAT4L@l addis r3, r0, CFG_DBAT4U@h ori r3, r3, CFG_DBAT4U@l mtspr DBAT4L, r4 mtspr DBAT4U, r3 +#endif isync /* IBAT 5 */ +#if ((CFG_IBAT5L == 0) && (CFG_IBAT5U == 0)) + mtspr IBAT5L, r0 + mtspr IBAT5U, r0 +#else addis r4, r0, CFG_IBAT5L@h ori r4, r4, CFG_IBAT5L@l addis r3, r0, CFG_IBAT5U@h ori r3, r3, CFG_IBAT5U@l mtspr IBAT5L, r4 mtspr IBAT5U, r3 +#endif isync /* DBAT 5 */ +#if ((CFG_DBAT5L == 0) && (CFG_DBAT5U == 0)) + mtspr DBAT5L, r0 + mtspr DBAT5U, r0 +#else addis r4, r0, CFG_DBAT5L@h ori r4, r4, CFG_DBAT5L@l addis r3, r0, CFG_DBAT5U@h ori r3, r3, CFG_DBAT5U@l mtspr DBAT5L, r4 mtspr DBAT5U, r3 +#endif isync /* IBAT 6 */ +#if ((CFG_IBAT6L == 0) && (CFG_IBAT6U == 0)) + mtspr IBAT6L, r0 + mtspr IBAT6U, r0 +#else addis r4, r0, CFG_IBAT6L@h ori r4, r4, CFG_IBAT6L@l addis r3, r0, CFG_IBAT6U@h ori r3, r3, CFG_IBAT6U@l mtspr IBAT6L, r4 mtspr IBAT6U, r3 +#endif isync /* DBAT 6 */ +#if ((CFG_DBAT6L == 0) && (CFG_DBAT6U == 0)) + mtspr DBAT6L, r0 + mtspr DBAT6U, r0 +#else addis r4, r0, CFG_DBAT6L@h ori r4, r4, CFG_DBAT6L@l addis r3, r0, CFG_DBAT6U@h ori r3, r3, CFG_DBAT6U@l mtspr DBAT6L, r4 mtspr DBAT6U, r3 +#endif isync /* IBAT 7 */ +#if ((CFG_IBAT7L == 0) && (CFG_IBAT7U == 0)) + mtspr IBAT7L, r0 + mtspr IBAT7U, r0 +#else addis r4, r0, CFG_IBAT7L@h ori r4, r4, CFG_IBAT7L@l addis r3, r0, CFG_IBAT7U@h ori r3, r3, CFG_IBAT7U@l mtspr IBAT7L, r4 mtspr IBAT7U, r3 +#endif isync /* DBAT 7 */ +#if ((CFG_DBAT7L == 0) && (CFG_DBAT7U == 0)) + mtspr DBAT7L, r0 + mtspr DBAT7U, r0 +#else addis r4, r0, CFG_DBAT7L@h ori r4, r4, CFG_DBAT7L@l addis r3, r0, CFG_DBAT7U@h ori r3, r3, CFG_DBAT7U@l mtspr DBAT7L, r4 mtspr DBAT7U, r3 +#endif isync #endif @@ -744,15 +881,7 @@ setup_bats: blr - .globl enable_addr_trans -enable_addr_trans: - /* enable address translation */ - mfmsr r5 - ori r5, r5, (MSR_IR | MSR_DR) - mtmsr r5 - isync - blr - +#if !defined(CONFIG_NAND_SPL) .globl disable_addr_trans disable_addr_trans: /* disable address translation */ @@ -770,20 +899,6 @@ disable_addr_trans: * Note: requires that all cache bits in * HID0 are in the low half word. */ - .globl icache_enable -icache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_ICE - lis r4, 0 - ori r4, r4, HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - .globl icache_disable icache_disable: mfspr r3, HID0 @@ -802,20 +917,9 @@ icache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr +#endif /* CONFIG_NAND_SPL */ - .globl dcache_enable -dcache_enable: - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - ori r3, r3, HID0_DCE - ori r5, r3, HID0_DCFI - mtspr HID0, r5 /* enable + invalidate */ - mtspr HID0, r3 /* enable */ - sync - blr - +#if !defined(CONFIG_NAND_SPL) .globl dcache_disable dcache_disable: mfspr r3, HID0 @@ -835,11 +939,6 @@ dcache_status: rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 blr - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - .globl ppcDWstore ppcDWstore: lfd 1, 0(r4) @@ -853,6 +952,7 @@ ppcDWload: blr /*-------------------------------------------------------------------*/ +#endif /* CONFIG_NAND_SPL */ /* * void relocate_code (addr_sp, gd, addr_moni) @@ -872,10 +972,17 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ + +#if !defined(CONFIG_NAND_SPL) lis r4, CFG_MONITOR_BASE@h /* Source Address */ ori r4, r4, CFG_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 +#else + lis r4, CFG_NAND_BASE@h /* Source Address */ + ori r4, r4, CFG_NAND_BASE@l + li r5, 0x1000 /* 4 kbyte bootloader */ +#endif /* CONFIG_NAND_SPL */ li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ /* @@ -968,8 +1075,72 @@ relocate_code: mtlr r0 blr +#ifdef CFG_INIT_RAM_LOCK +lock_ram_in_cache: + /* Allocate Initial RAM in data cache. + */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2, ((CFG_INIT_RAM_END & ~31) + \ + (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + mtctr r2 +1: + dcbz r0, r3 + addi r3, r3, 32 + bdnz 1b + + /* Lock the data cache */ + mfspr r0, HID0 + ori r0, r0, 0x1000 + sync + mtspr HID0, r0 + sync + blr + +.globl unlock_ram_in_cache +unlock_ram_in_cache: + /* invalidate the INIT_RAM section */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2,512 + mtctr r2 +1: icbi r0, r3 + dcbi r0, r3 + addi r3, r3, 32 + bdnz 1b + sync /* Wait for all icbi to complete on bus */ + isync + + /* Unlock the data cache and invalidate it */ + mfspr r3, HID0 + li r5, HID0_DLOCK|HID0_DCFI + andc r3, r3, r5 /* no invalidate, unlock */ + ori r5, r3, HID0_DCFI /* invalidate, unlock */ + mtspr HID0, r5 /* invalidate, unlock */ + mtspr HID0, r3 /* no invalidate, unlock */ + sync + blr +#endif + in_ram: +#if defined(CONFIG_NAND_SPL) + /* + * Adjust got table entries to fix pointers to strings + */ + li r0,__got_entries@sectoff@l + la r4,GOT(_GOT_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r4,r4,-4 + beq 4f +3: lwzu r3,4(r4) + add r3,r3,r15 + stw r3,0(r4) + bdnz 3b +4: + +#else /* * Relocation Function, r14 point to got2+0x8000 * @@ -1035,8 +1206,11 @@ clear_bss: mr r3, r9 /* Global Data pointer */ mr r4, r10 /* Destination Address */ +#endif /* CONFIG_NAND_SPL */ + bl board_init_r +#if !defined(CONFIG_NAND_SPL) /* * Copy exception vector code to low memory * @@ -1120,53 +1294,7 @@ trap_reloc: blr -#ifdef CFG_INIT_RAM_LOCK -lock_ram_in_cache: - /* Allocate Initial RAM in data cache. - */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2, ((CFG_INIT_RAM_END & ~31) + \ - (CFG_INIT_RAM_ADDR & 31) + 31) / 32 - mtctr r2 -1: - dcbz r0, r3 - addi r3, r3, 32 - bdnz 1b - - /* Lock the data cache */ - mfspr r0, HID0 - ori r0, r0, 0x1000 - sync - mtspr HID0, r0 - sync - blr - -.globl unlock_ram_in_cache -unlock_ram_in_cache: - /* invalidate the INIT_RAM section */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2,512 - mtctr r2 -1: icbi r0, r3 - dcbi r0, r3 - addi r3, r3, 32 - bdnz 1b - sync /* Wait for all icbi to complete on bus */ - isync - - /* Unlock the data cache and invalidate it */ - mfspr r3, HID0 - li r5, HID0_DLOCK|HID0_DCFI - andc r3, r3, r5 /* no invalidate, unlock */ - ori r5, r3, HID0_DCFI /* invalidate, unlock */ - mtspr HID0, r5 /* invalidate, unlock */ - mtspr HID0, r3 /* no invalidate, unlock */ - sync - blr -#endif - +#if !defined(CONFIG_NAND_U_BOOT) map_flash_by_law1: /* When booting from ROM (Flash or EPROM), clear the */ /* Address Mask in OR0 so ROM appears everywhere */ @@ -1245,3 +1373,5 @@ remap_flash_by_law0: stw r4, LBLAWBAR1(r3) stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ blr +#endif /* CONFIG_NAND_U_BOOT */ +#endif /* CONFIG_NAND_SPL */ -- 1.5.5.1

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[U-Boot-Users] Dijital baskılarınız hakkında...
by Merkez Baskı 31 May '08

31 May '08

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[U-Boot-Users] [PATCH 7/8] New board SIMPC8313 support: nand support
by Ron Madrid 31 May '08

31 May '08

New board SIMPC8313 support: nand support I realize that perhaps these files should be in the drivers/mtd/nand folder, but I have been informed by Scott Wood that he will be soon working on nand support for the MPC83XX(?) family of chips. So these will be considered temporary and removed at that time. Signed-off-by: Ron Madrid --- board/sheldon/simpc8313/nand.c | 868 ++++++++++++++++++++++++++++++++++++ board/sheldon/simpc8313/nand_ecc.c | 214 +++++++++ 2 files changed, 1082 insertions(+), 0 deletions(-) create mode 100644 board/sheldon/simpc8313/nand.c create mode 100644 board/sheldon/simpc8313/nand_ecc.c diff --git a/board/sheldon/simpc8313/nand.c b/board/sheldon/simpc8313/nand.c new file mode 100644 index 0000000..a8fbf96 --- /dev/null +++ b/board/sheldon/simpc8313/nand.c @@ -0,0 +1,868 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * + * Initialized by Nick.Spence(a)freescale.com + * Wilson.Lo(a)freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#ifdef CONFIG_CMD_NAND +#if defined(CFG_NAND_LEGACY) + #error "U-Boot legacy NAND commands not supported." +#else + +#include <malloc.h> +#include <asm/errno.h> +#include <nand.h> + +#undef CFG_FCM_DEBUG +#define CFG_FCM_DEBUG_LVL 1 +#ifdef CFG_FCM_DEBUG +#define FCM_DEBUG(n, args...) \ + do { \ + if (n <= (CFG_FCM_DEBUG_LVL + 0)) \ + printf(args); \ + } while(0) +#else /* CONFIG_FCM_DEBUG */ +#define FCM_DEBUG(n, args...) do { } while(0) +#endif + +#define MIN(x, y) ((x < y) ? x : y) + +#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ + +#define FCM_TIMEOUT_USECS 100000 /* Maximum number of uSecs to wait for FCM */ + +/* Private structure holding NAND Flash device specific information */ +struct fcm_nand { + int bank; /* Chip select bank number */ + unsigned int base; /* Chip select base address */ + int pgs; /* NAND page size */ + int oobbuf; /* Pointer to OOB block */ + unsigned int page; /* Last page written to / read from */ + unsigned int fmr; /* FCM Flash Mode Register value */ + unsigned int mdr; /* UPM/FCM Data Register value */ + unsigned int use_mdr; /* Non zero if the MDR is to be set */ + u_char *addr; /* Address of assigned FCM buffer */ + unsigned int read_bytes; /* Number of bytes read during command */ + unsigned int index; /* Pointer to next byte to 'read' */ + unsigned int req_bytes; /* Number of bytes read if command ok */ + unsigned int req_index; /* New read index if command ok */ + unsigned int status; /* status read from LTESR after last op*/ +}; + + +/* These map to the positions used by the FCM hardware ECC generator */ + +/* Small Page FLASH with FMR[ECCM] = 0 */ +static struct nand_oobinfo fcm_oob_sp_eccm0 = { /* TODO */ + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 3, + .eccpos = {6, 7, 8}, + .oobfree = { {0, 5}, {9, 7} } +}; + +/* Small Page FLASH with FMR[ECCM] = 1 */ +static struct nand_oobinfo fcm_oob_sp_eccm1 = { /* TODO */ + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 3, + .eccpos = {8, 9, 10}, + .oobfree = { {0, 5}, {6, 2}, {11, 5} } +}; + +/* Large Page FLASH with FMR[ECCM] = 0 */ +static struct nand_oobinfo fcm_oob_lp_eccm0 = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 12, + .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, + .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} } +}; + +/* Large Page FLASH with FMR[ECCM] = 1 */ +static struct nand_oobinfo fcm_oob_lp_eccm1 = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 12, + .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, + .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} } +}; + +/* + * execute FCM command and wait for it to complete + */ +static int fcm_run_command(struct mtd_info *mtd) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + register struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + long long end_tick; + + /* Setup the FMR[OP] to execute without write protection */ + lbc->fmr = fcm->fmr | 3; + if (fcm->use_mdr) + lbc->mdr = fcm->mdr; + + FCM_DEBUG(5,"fcm_run_command: fmr= %08X fir= %08X fcr= %08X\n", + lbc->fmr, lbc->fir, lbc->fcr); + FCM_DEBUG(5,"fcm_run_command: fbar=%08X fpar=%08X fbcr=%08X bank=%d\n", + lbc->fbar, lbc->fpar, lbc->fbcr, fcm->bank); + + /* clear event registers */ + lbc->lteatr = 0; + lbc->ltesr |= (LTESR_FCT | LTESR_PAR | LTESR_CC); + + /* execute special operation */ + lbc->lsor = fcm->bank; + + /* wait for FCM complete flag or timeout */ + fcm->status = 0; + end_tick = usec2ticks(FCM_TIMEOUT_USECS) + get_ticks(); + + while (end_tick > get_ticks()) { + if (lbc->ltesr & LTESR_CC) { + fcm->status = lbc->ltesr & + (LTESR_FCT | LTESR_PAR | LTESR_CC); + break; + } + } + + /* store mdr value in case it was needed */ + if (fcm->use_mdr) + fcm->mdr = lbc->mdr; + + fcm->use_mdr = 0; + + FCM_DEBUG(5,"fcm_run_command: stat=%08X mdr= %08X fmr= %08X\n", + fcm->status, fcm->mdr, lbc->fmr); + + /* if the operation completed ok then set the read buffer pointers */ + if (fcm->status == LTESR_CC) { + fcm->read_bytes = fcm->req_bytes; + fcm->index = fcm->req_index; + return 0; + } + + return -1; +} + +/* + * Set up the FCM hardware block and page address fields, and the fcm + * structure addr field to point to the correct FCM buffer in memory + */ +static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + register struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + int buf_num; + + fcm->page = page_addr; + + lbc->fbar = page_addr >> (this->phys_erase_shift - this->page_shift); + if (fcm->pgs) { + lbc->fpar = ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | + ( oob ? FPAR_LP_MS : 0) | + column; + buf_num = (page_addr & 1) << 2; + } else { + lbc->fpar = ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | + ( oob ? FPAR_SP_MS : 0) | + column; + buf_num = page_addr & 7; + } + fcm->addr = (unsigned char*)(fcm->base + (buf_num * 1024)); + + /* for OOB data point to the second half of the buffer */ + if (oob) { + fcm->addr += (fcm->pgs ? 2048 : 512); + } +} + +/* not required for FCM */ +static void fcm_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + return; +} + + +/* + * FCM does not support 16 bit data busses + */ +static u16 fcm_read_word(struct mtd_info *mtd) +{ + printf("fcm_read_word: UNIMPLEMENTED.\n"); + return 0; +} +static void fcm_write_word(struct mtd_info *mtd, u16 word) +{ + printf("fcm_write_word: UNIMPLEMENTED.\n"); +} + +/* + * Write buf to the FCM Controller Data Buffer + */ +static void fcm_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + register struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + + FCM_DEBUG(3,"fcm_write_buf: writing %d bytes starting with 0x%x" + " at %d.\n", len, *((unsigned long*) buf), fcm->index); + + /* If armed catch the address of the OOB buffer so that it can be */ + /* updated with the real signature after the program comletes */ + if (!fcm->oobbuf) + fcm->oobbuf = (int) buf; + + /* copy the data into the FCM hardware buffer and update the index */ + memcpy(&(fcm->addr[fcm->index]), buf, len); + fcm->index += len; + return; +} + + +/* + * FCM does not support individual writes. Instead these are either commands + * or data being written, both of which are handled through the cmdfunc + * handler. + */ +static void fcm_write_byte(struct mtd_info *mtd, u_char byte) +{ + printf("fcm_write_byte: UNIMPLEMENTED.\n"); +} + +/* + * read a byte from either the FCM hardware buffer if it has any data left + * otherwise issue a command to read a single byte. + */ +static u_char fcm_read_byte(struct mtd_info *mtd) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + register struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + unsigned char byte; + + /* If there are still bytes in the FCM then use the next byte */ + if(fcm->index < fcm->read_bytes) { + byte = fcm->addr[(fcm->index)++]; + FCM_DEBUG(4,"fcm_read_byte: byte %u (%02X): %d of %d.\n", + byte, byte, fcm->index-1, fcm->read_bytes); + } else { + /* otherwise issue a command to read 1 byte */ + lbc->fir = (FIR_OP_RSW << FIR_OP0_SHIFT); + fcm->use_mdr = 1; + fcm->read_bytes = 0; + fcm->index = 0; + fcm->req_bytes = 0; + fcm->req_index = 0; + byte = fcm_run_command(mtd) ? ERR_BYTE : fcm->mdr & 0xff; + FCM_DEBUG(4,"fcm_read_byte: byte %u (%02X) from bus.\n", + byte, byte); + } + + return byte; +} + + +/* + * Read from the FCM Controller Data Buffer + */ +static void fcm_read_buf(struct mtd_info *mtd, u_char* buf, int len) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + register struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + int i; + int rest; + + FCM_DEBUG(3,"fcm_read_buf: reading %d bytes.\n", len); + + /* If last read failed then return error bytes */ + if (fcm->status != LTESR_CC) { + /* just keep copying bytes so that the oob works */ + memcpy(buf, &(fcm->addr[(fcm->index)]), len); + fcm->index += len; + } + else + { + /* see how much is still in the FCM buffer */ + i = min(len, (fcm->read_bytes - fcm->index)); + rest = i - len; + len = i; + + memcpy(buf, &(fcm->addr[(fcm->index)]), len); + fcm->index += len; + + /* If more data is needed then issue another block read */ + if (rest) { + FCM_DEBUG(3,"fcm_read_buf: getting %d more bytes.\n", + rest); + buf += len; + lbc->fir = (FIR_OP_RBW << FIR_OP0_SHIFT); + set_addr(mtd, 0, 0, 0); + lbc->fbcr = rest; + fcm->req_bytes = lbc->fbcr; + fcm->req_index = 0; + fcm->use_mdr = 0; + if (!fcm_run_command(mtd)) + fcm_read_buf(mtd, buf, rest); + else + memcpy(buf, fcm->addr, rest); + } + } + return; +} + + +/* + * Verify buffer against the FCM Controller Data Buffer + */ +static int fcm_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + register struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + int i; + int rest; + + FCM_DEBUG(3,"fcm_verify_buf: checking %d bytes starting with 0x%02x.\n", + len, *((unsigned long*) buf)); + /* If last read failed then return error bytes */ + if (fcm->status != LTESR_CC) { + return EFAULT; + } + + /* see how much is still in the FCM buffer */ + i = min(len, (fcm->read_bytes - fcm->index)); + rest = i - len; + len = i; + + if (memcmp(buf, &(fcm->addr[(fcm->index)]), len)) { + return EFAULT; + } + + fcm->index += len; + if (rest) { + FCM_DEBUG(3,"fcm_verify_buf: getting %d more bytes.\n", rest); + buf += len; + lbc->fir = (FIR_OP_RBW << FIR_OP0_SHIFT); + set_addr(mtd, 0, 0, 0); + lbc->fbcr = rest; + fcm->req_bytes = lbc->fbcr; + fcm->req_index = 0; + fcm->use_mdr = 0; + if (fcm_run_command(mtd)) + return EFAULT; + return fcm_verify_buf(mtd, buf, rest); + + } + return 0; +} + +/* this function is called after Program and Erase Operations to + * check for success or failure */ +static int fcm_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + struct fcm_nand *fcm = this->priv; + + if (fcm->status != LTESR_CC) { + return(0x1); /* Status Read error */ + } + + /* Use READ_STATUS command, but wait for the device to be ready */ + fcm->use_mdr = 0; + fcm->req_index = 0; + fcm->read_bytes = 0; + fcm->index = 0; + fcm->oobbuf = -1; + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_RBW << FIR_OP1_SHIFT); + lbc->fcr = (NAND_CMD_STATUS << FCR_CMD0_SHIFT); + set_addr(mtd, 0, 0, 0); + lbc->fbcr = 1; + fcm->req_bytes = lbc->fbcr; + fcm_run_command(mtd); + if (fcm->status != LTESR_CC) { + return(0x1); /* Status Read error */ + } + return this->read_byte(mtd); +} + + +/* cmdfunc send commands to the FCM */ +static void fcm_cmdfunc(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + register struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + + fcm->use_mdr = 0; + fcm->req_index = 0; + + /* clear the read buffer */ + fcm->read_bytes = 0; + if (command != NAND_CMD_PAGEPROG) { + fcm->index = 0; + fcm->oobbuf = -1; + } + + switch (command) { + /* READ0 and READ1 read the entire buffer to use hardware ECC */ + case NAND_CMD_READ1: + FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_READ1, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + fcm->req_index = column + 256; + goto read0; + case NAND_CMD_READ0: + FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_READ0, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + fcm->req_index = column; +read0: + if (fcm->pgs) { + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RBW << FIR_OP4_SHIFT); + } else { + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_RBW << FIR_OP3_SHIFT); + } + lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | + (NAND_CMD_READSTART << FCR_CMD1_SHIFT); + lbc->fbcr = 0; /* read entire page to enable ECC */ + set_addr(mtd, 0, page_addr, 0); + fcm->req_bytes = mtd->oobblock + mtd->oobsize; + goto write_cmd2; + /* READOOB read only the OOB becasue no ECC is performed */ + case NAND_CMD_READOOB: + FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_READOOB, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + if (fcm->pgs) { + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RBW << FIR_OP4_SHIFT); + lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | + (NAND_CMD_READSTART << FCR_CMD1_SHIFT); + } else { + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_RBW << FIR_OP3_SHIFT); + lbc->fcr = (NAND_CMD_READOOB << FCR_CMD0_SHIFT); + } + lbc->fbcr = mtd->oobsize - column; + set_addr(mtd, column, page_addr, 1); + goto write_cmd1; + /* READID must read all 5 possible bytes while CEB is active */ + case NAND_CMD_READID: + FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_READID.\n"); + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_UA << FIR_OP1_SHIFT) | + (FIR_OP_RBW << FIR_OP2_SHIFT); + lbc->fcr = (NAND_CMD_READID << FCR_CMD0_SHIFT); + lbc->fbcr = 5; /* 5 bytes for manuf, device and exts */ + fcm->use_mdr = 1; + fcm->mdr = 0; + goto write_cmd0; + /* ERASE1 stores the block and page address */ + case NAND_CMD_ERASE1: + FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_ERASE1, page_addr:" + " 0x%x.\n", page_addr); + set_addr(mtd, 0, page_addr, 0); + goto end; + /* ERASE2 uses the block and page address from ERASE1 */ + case NAND_CMD_ERASE2: + FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_ERASE2.\n"); + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_PA << FIR_OP1_SHIFT) | + (FIR_OP_CM1 << FIR_OP2_SHIFT); + lbc->fcr = (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | + (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT); + lbc->fbcr = 0; + goto write_cmd1; + /* SEQIN sets up the addr buffer and all registers except the length */ + case NAND_CMD_SEQIN: + FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + if (column == 0) { + lbc->fbcr = 0; /* write entire page to enable ECC */ + } else { + lbc->fbcr = 1; /* mark as partial page so no HW ECC */ + } + if (fcm->pgs) { + /* always use READ0 for large page devices */ + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_WB << FIR_OP3_SHIFT) | + (FIR_OP_CW1 << FIR_OP4_SHIFT); + lbc->fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | + (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); + set_addr(mtd, column, page_addr, 0); + } else { + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CM2 << FIR_OP1_SHIFT) | + (FIR_OP_CA << FIR_OP2_SHIFT) | + (FIR_OP_PA << FIR_OP3_SHIFT) | + (FIR_OP_WB << FIR_OP4_SHIFT) | + (FIR_OP_CW1 << FIR_OP5_SHIFT); + if (column >= mtd->oobblock) { + /* OOB area --> READOOB */ + column -= mtd->oobblock; + lbc->fcr = (NAND_CMD_READOOB << FCR_CMD0_SHIFT) + | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT) + | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); + set_addr(mtd, column, page_addr, 1); + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) + | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT) + | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); + set_addr(mtd, column, page_addr, 0); + } else { + /* Second 256 bytes --> READ1 */ + column -= 256; + lbc->fcr = (NAND_CMD_READ1 << FCR_CMD0_SHIFT) + | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT) + | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); + set_addr(mtd, column, page_addr, 0); + } + } + goto end; + /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ + case NAND_CMD_PAGEPROG: + FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_PAGEPROG" + " writing %d bytes.\n",fcm->index); + /* if the write did not start at 0 or is not a full page */ + /* then set the exact length, otherwise use a full page */ + /* write so the HW generates the ECC. */ + if (lbc->fbcr || + (fcm->index != (mtd->oobblock + mtd->oobsize))) + lbc->fbcr = fcm->index; + fcm->req_bytes = 0; + goto write_cmd2; + /* CMD_STATUS must read the status byte while CEB is active */ + /* Note - it does not wait for the ready line */ + case NAND_CMD_STATUS: + FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_STATUS.\n"); + lbc->fir = (FIR_OP_CM0 << FIR_OP0_SHIFT) | + (FIR_OP_RBW << FIR_OP1_SHIFT); + lbc->fcr = (NAND_CMD_STATUS << FCR_CMD0_SHIFT); + lbc->fbcr = 1; + goto write_cmd0; + /* RESET without waiting for the ready line */ + case NAND_CMD_RESET: + FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_RESET.\n"); + lbc->fir = (FIR_OP_CM0 << FIR_OP0_SHIFT); + lbc->fcr = (NAND_CMD_RESET << FCR_CMD0_SHIFT); + lbc->fbcr = 0; + goto write_cmd0; + default: + printk("fcm_cmdfunc: error, unsupported command.\n"); + goto end; + } + + /* Short cuts fall through to save code */ + write_cmd0: + set_addr(mtd, 0, 0, 0); + write_cmd1: + fcm->req_bytes = lbc->fbcr; + write_cmd2: + fcm_run_command(mtd); + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* if we wrote a page then read back the oob to get the ECC */ + if ((command == NAND_CMD_PAGEPROG) && + (this->eccmode > NAND_ECC_SOFT) && + (lbc->fbcr == 0) && + (fcm->oobbuf != 0) && + (fcm->oobbuf != -1)) { + int i; + uint *oob_config; + unsigned char *oob_buf; + + i = fcm->page; + oob_buf = (unsigned char*) fcm->oobbuf; + oob_config = this->autooob->eccpos; + + /* wait for the write to complete and check it passed */ + if (!(this->waitfunc(mtd, this, FL_WRITING) & 0x01)) { + /* read back the OOB */ + fcm_cmdfunc(mtd, NAND_CMD_READOOB, 0, i); + /* if it succeeded then copy the ECC bytes */ + if (fcm->status == LTESR_CC) { + for (i = 0; i < this->eccbytes; i++) { + oob_buf[oob_config[i]] = + fcm->addr[oob_config[i]]; + } + } + } + } +#endif + + end: + return; +} + +/* + * fcm_enable_hwecc - start ECC generation + */ +static void fcm_enable_hwecc(struct mtd_info *mtd, int mode) +{ + return; +} + +/* + * fcm_calculate_ecc - Calculate the ECC bytes + * This is done by hardware during the write process, so we use this + * to arm the oob buf capture on the next write_buf() call. The ECC bytes + * only need to be captured if CONFIG_MTD_NAND_VERIFY_WRITE is defined which + * reads back the pages and checks they match the data and oob buffers. + */ +static int fcm_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +{ + register struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* arm capture of oob buf ptr on next write_buf */ + fcm->oobbuf = 0; +#endif + return 0; +} + +/* + * fcm_correct_data - Detect and correct bit error(s) + * The detection and correction is done automatically by the hardware, + * if the complete page was read. If the status code is okay then there + * was no error, otherwise we return an error code indicating an uncorrectable + * error. + */ +static int fcm_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + register struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + + /* No errors */ + if (fcm->status == LTESR_CC) + return 0; + + return -1; /* uncorrectable error */ +} + + + +/* + * Dummy scan_bbt to complete setup of the FMR based on NAND size + */ +static int fcm_scan_bbt (struct mtd_info *mtd) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + register struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + unsigned int i; + unsigned int al; + + if (!fcm) { + printk (KERN_ERR "fcm_scan_bbt():" \ + " Failed to allocate chip specific data structure\n"); + return -1; + } + + /* calculate FMR Address Length field */ + al = 0; + for (i = this->pagemask >> 16; i ; i >>= 8) { + al++; + } + + /* add to ECCM mode set in fcm_init */ + fcm->fmr |= 12 << FMR_CWTO_SHIFT | /* Timeout > 12 mSecs */ + al << FMR_AL_SHIFT; + + FCM_DEBUG(1,"fcm_init: nand->options = %08X\n", this->options); + FCM_DEBUG(1,"fcm_init: nand->numchips = %10d\n", this->numchips); + FCM_DEBUG(1,"fcm_init: nand->chipsize = %10d\n", this->chipsize); + FCM_DEBUG(1,"fcm_init: nand->pagemask = %10X\n", this->pagemask); + FCM_DEBUG(1,"fcm_init: nand->eccmode = %10d\n", this->eccmode ); + FCM_DEBUG(1,"fcm_init: nand->eccsize = %10d\n", this->eccsize ); + FCM_DEBUG(1,"fcm_init: nand->eccbytes = %10d\n", this->eccbytes); + FCM_DEBUG(1,"fcm_init: nand->eccsteps = %10d\n", this->eccsteps); + FCM_DEBUG(1,"fcm_init: nand->chip_delay = %8d\n", this->chip_delay); + FCM_DEBUG(1,"fcm_init: nand->badblockpos = %7d\n", this->badblockpos); + FCM_DEBUG(1,"fcm_init: nand->chip_shift = %8d\n", this->chip_shift); + FCM_DEBUG(1,"fcm_init: nand->page_shift = %8d\n", this->page_shift); + FCM_DEBUG(1,"fcm_init: nand->phys_erase_shift = %2d\n", + this->phys_erase_shift); + FCM_DEBUG(1,"fcm_init: mtd->flags = %08X\n", mtd->flags); + FCM_DEBUG(1,"fcm_init: mtd->size = %10d\n", mtd->size); + FCM_DEBUG(1,"fcm_init: mtd->erasesize = %10d\n", mtd->erasesize); + FCM_DEBUG(1,"fcm_init: mtd->oobblock = %10d\n", mtd->oobblock); + FCM_DEBUG(1,"fcm_init: mtd->oobsize = %10d\n", mtd->oobsize); + FCM_DEBUG(1,"fcm_init: mtd->oobavail = %10d\n", mtd->oobavail); + FCM_DEBUG(1,"fcm_init: mtd->ecctype = %10d\n", mtd->ecctype); + FCM_DEBUG(1,"fcm_init: mtd->eccsize = %10d\n", mtd->eccsize); + + /* adjust Option Register and ECC to match Flash page size */ + if (mtd->oobblock == 512) + lbc->bank[fcm->bank].or &= ~(OR_FCM_PGS); + else if (mtd->oobblock == 2048) { + lbc->bank[fcm->bank].or |= OR_FCM_PGS; + /* adjust ecc setup if needed */ + if ( (lbc->bank[fcm->bank].br & BR_DECC) == BR_DECC_CHK_GEN) { + mtd->eccsize = 2048; + mtd->oobavail -= 9; + this->eccmode = NAND_ECC_HW12_2048; + this->eccsize = 2048; + this->eccbytes += 9; + this->eccsteps = 1; + this->autooob = (fcm->fmr & FMR_ECCM) ? + &fcm_oob_lp_eccm1 : &fcm_oob_lp_eccm0; + memcpy(&mtd->oobinfo, this->autooob, + sizeof(mtd->oobinfo)); + } + } + else { + printf("fcm_init: page size %d is not supported\n", + mtd->oobblock); + return -1; + } + fcm->pgs = (lbc->bank[fcm->bank].or>>OR_FCM_PGS_SHIFT) & 1; + + if (al > 2) { + printf("fcm_init: %d address bytes is not supported\n", al+2); + return -1; + } + + /* restore default scan_bbt function and call it */ + this->scan_bbt = nand_default_bbt; + return nand_default_bbt(mtd); +} + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand_new.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +int board_nand_init(struct nand_chip *nand) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + struct fcm_nand *fcm; + unsigned int bank; + + /* Enable FCM detection of timeouts, ECC errors and completion */ + lbc->ltedr &= ~(LTESR_FCT | LTESR_PAR | LTESR_CC); + + fcm = kmalloc (sizeof(struct fcm_nand), GFP_KERNEL); + if (!fcm) { + printk (KERN_ERR "board_nand_init():" \ + " Cannot allocate read buffer data structure\n"); + return -1; + } + + /* Find which chip select bank is being used for this device */ + for (bank=0; bank<8; bank++) { + if ( (lbc->bank[bank].br & BR_V) && + ( (lbc->bank[bank].br & BR_MSEL) == BR_MS_FCM ) && + ( (lbc->bank[bank].br & BR_BA) == + (lbc->bank[bank].or & OR_FCM_AM & + (unsigned int)(nand->IO_ADDR_R) ) ) ) { + fcm->bank = bank; + fcm->fmr = 0; /* rest filled in later */ + fcm->read_bytes = 0; + fcm->index = 0; + fcm->pgs = (lbc->bank[bank].or>>OR_FCM_PGS_SHIFT) & 1; + fcm->base = lbc->bank[bank].br & BR_BA; + fcm->addr = (unsigned char*) (fcm->base); + nand->priv = fcm; + fcm->oobbuf = -1; + break; + } + } + + if (!nand->priv) { + printk (KERN_ERR "board_nand_init():" \ + " Could not find matching Chip Select\n"); + return -1; + } + + /* set up nand options */ + nand->options = 0; + /* set up function call table */ + nand->hwcontrol = fcm_hwcontrol; + nand->waitfunc = fcm_wait; + nand->read_byte = fcm_read_byte; + nand->write_byte = fcm_write_byte; + nand->read_word = fcm_read_word; + nand->write_word = fcm_write_word; + nand->read_buf = fcm_read_buf; + nand->verify_buf = fcm_verify_buf; + nand->write_buf = fcm_write_buf; + nand->cmdfunc = fcm_cmdfunc; + nand->scan_bbt = fcm_scan_bbt; + + /* If CS Base Register selects full hardware ECC then use it */ + if ( ( (lbc->bank[bank].br & BR_DECC) >> BR_DECC_SHIFT) == 2) { + /* put in small page settings and adjust later if needed */ + nand->eccmode = NAND_ECC_HW3_512; + nand->autooob = (fcm->fmr & FMR_ECCM) ? + &fcm_oob_sp_eccm1 : &fcm_oob_sp_eccm0; + nand->calculate_ecc = fcm_calculate_ecc; + nand->correct_data = fcm_correct_data; + nand->enable_hwecc = fcm_enable_hwecc; + } else { + /* otherwise fall back to default software ECC */ + nand->eccmode = NAND_ECC_SOFT; + } + + return 0; +} + +#endif +#endif diff --git a/board/sheldon/simpc8313/nand_ecc.c b/board/sheldon/simpc8313/nand_ecc.c new file mode 100644 index 0000000..87db359 --- /dev/null +++ b/board/sheldon/simpc8313/nand_ecc.c @@ -0,0 +1,214 @@ +/* + * This file was copied from drivers/nand/nand_ecc.c and optimized to reduce + * the memory size and function calls to correct up to 1 bit error in each + * 256 byte block of data. + * + * Copyright (C) 2006, Freescale Semiconductor + * + * Copyright (C) 2000-2004 Steven J. Hill (sjhill(a)realitydiluted.com) + * Toshiba America Electronics Components, Inc. + * + * This file is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 or (at your option) any + * later version. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this file; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * As a special exception, if other files instantiate templates or use + * macros or inline functions from these files, or you compile these + * files and link them with other works to produce a work based on these + * files, these files do not by themselves cause the resulting work to be + * covered by the GNU General Public License. However the source code for + * these files must still be made available in accordance with section (3) + * of the GNU General Public License. + * + * This exception does not invalidate any other reasons why a work based on + * this file might be covered by the GNU General Public License. + */ + +#include <common.h> + +/* + * Pre-calculated 256-way 1 byte column parity + */ +static const u_char nand_ecc_precalc_table[] = { + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, + 0x03, 0x56, 0x55, 0x00, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, + 0x66, 0x33, 0x30, 0x65, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, + 0x65, 0x30, 0x33, 0x66, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, + 0x00, 0x55, 0x56, 0x03, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, + 0x6a, 0x3f, 0x3c, 0x69, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, + 0x0f, 0x5a, 0x59, 0x0c, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, + 0x0c, 0x59, 0x5a, 0x0f, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, + 0x69, 0x3c, 0x3f, 0x6a, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, + 0x69, 0x3c, 0x3f, 0x6a, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, + 0x0c, 0x59, 0x5a, 0x0f, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, + 0x0f, 0x5a, 0x59, 0x0c, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, + 0x6a, 0x3f, 0x3c, 0x69, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, + 0x00, 0x55, 0x56, 0x03, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, + 0x65, 0x30, 0x33, 0x66, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, + 0x66, 0x33, 0x30, 0x65, + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, + 0x03, 0x56, 0x55, 0x00 +}; + +/** + * nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @dat: raw data read from the chip + * @ecc_pos: ecc byte offsets (3 bytes per 512 data byte block) + * @blocks: Number of 512 byte blocks to be processed + * + * Detect and / or correct 1 bit error per 256 byte block + */ +int nand_correct_data (u_char * dat, const u_char * ecc_pos, int blocks) +{ + u_char tmp1, tmp2; + u_char a, b, c, d1, d2, d3, add, bit, i; + u_char idx, reg1, reg2, reg3; + int j, ctr, ret; + u_char *ecc; + + ecc = dat + CFG_NAND_PAGE_SIZE; + ctr = 0; + while (blocks--) { + + /* Initialize variables */ + ret = reg1 = reg2 = reg3 = 0; + + /* Build up column parity */ + for (j = 0; j < 256; j++) { + + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[dat[j]]; + reg1 ^= (idx & 0x3f); + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (u_char) j; + reg2 ^= ~((u_char) j); + } + } + + /* Create non-inverted ECC code from line parity */ + + /* Initialize variables */ + a = b = c = 0x80; + tmp1 = tmp2 = 0; + + /* Calculate first ECC byte */ + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + a >>= 1; + } + + /* Calculate second ECC byte */ + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ + tmp2 |= c; + c >>= 1; + if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ + tmp2 |= c; + c >>= 1; + a >>= 1; + } + + /* Calculate final ECC code */ + /* Do error detection */ + d1 = (~tmp1) ^ ecc[*(ecc_pos++)]; + d2 = (~tmp2) ^ ecc[*(ecc_pos++)]; + d3 = (((~reg1) << 2) | 0x03) ^ ecc[*(ecc_pos++)]; + + if ((d1 | d2 | d3) != 0) { + /* 1 or more errors detected */ + a = (d1 ^ (d1 >> 1)) & 0x55; + b = (d2 ^ (d2 >> 1)) & 0x55; + c = (d3 ^ (d3 >> 1)) & 0x54; + + /* Found and correct single bit error in the data */ + if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { + a = b = c = 0x80; + add = 0; + for (i = 0; i < 4; i++) { + if (d1 & b) + add |= a; + b >>= 2; + a >>= 1; + } + for (i = 0; i < 4; i++) { + if (d2 & c) + add |= a; + c >>= 2; + a >>= 1; + } + bit = 0; + b = 0x04; + c = 0x80; + for (i = 0; i < 3; i++) { + if (d3 & c) + bit |= b; + c >>= 2; + b >>= 1; + } + b = 0x01; + a = dat[add]; + a ^= (b << bit); + dat[add] = a; + ret = 1; + } else { + while (d1) { + if (d1 & 0x01) + ret++; + d1 >>= 1; + } + while (d2) { + if (d2 & 0x01) + ret++; + d2 >>= 1; + } + while (d3) { + if (d3 & 0x01) + ret++; + d3 >>= 1; + } + } + } + + /* this page had more than 1 error so it is uncorrectable */ + if (ret > 1) + return -1; + + /* advance to the next page */ + dat += 256; + ctr += ret; + } + + /* return number of ECC errors that we corrected */ + return ctr; +} -- 1.5.5.1

2 7

[U-Boot-Users] [AT91] Problems configuring bit-banged I2C
by Sergey Lapin 30 May '08

30 May '08

Hi, all! I use the following patch on my AT91SAM9260-based custom board to configure bit-banged I2C: diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index b30aad8..99fc2bd 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @ -234,3 +234,46 @@ void reset_phy(void) #endif } #endif + +#define GPIO_I2C_SCL AT91_PIN_PA24 +#define GPIO_I2C_SDA AT91_PIN_PA23 + +void at91sam9260_i2c_init(void) +{ + __raw_writel(pin_to_mask(GPIO_I2C_SCL), pin_to_controller(GPIO_I2C_SCL) + PIO_IDR); + __raw_writel(pin_to_mask(GPIO_I2C_SCL), pin_to_controller(GPIO_I2C_SCL) + PIO_PUER); + __raw_writel(pin_to_mask(GPIO_I2C_SCL), pin_to_controller(GPIO_I2C_SCL) + PIO_PER); + __raw_writel(pin_to_mask(GPIO_I2C_SCL), pin_to_controller(GPIO_I2C_SCL) + PIO_MDER); + __raw_writel(pin_to_mask(GPIO_I2C_SCL), pin_to_controller(GPIO_I2C_SCL) + PIO_SODR); + __raw_writel(pin_to_mask(GPIO_I2C_SCL), pin_to_controller(GPIO_I2C_SCL) + PIO_OER); + + __raw_writel(pin_to_mask(GPIO_I2C_SDA), pin_to_controller(GPIO_I2C_SDA) + PIO_IDR); + __raw_writel(pin_to_mask(GPIO_I2C_SDA), pin_to_controller(GPIO_I2C_SDA) + PIO_PUER); + __raw_writel(pin_to_mask(GPIO_I2C_SDA), pin_to_controller(GPIO_I2C_SDA) + PIO_PER); + __raw_writel(pin_to_mask(GPIO_I2C_SDA), pin_to_controller(GPIO_I2C_SDA) + PIO_MDER); + __raw_writel(pin_to_mask(GPIO_I2C_SDA), pin_to_controller(GPIO_I2C_SDA) + PIO_SODR); + __raw_writel(pin_to_mask(GPIO_I2C_SDA), pin_to_controller(GPIO_I2C_SDA) + PIO_OER); +} +void at91sam9260_i2c_scl(unsigned long bit) +{ + if(bit) + __raw_writel(pin_to_mask(GPIO_I2C_SCL), pin_to_controller(GPIO_I2C_SCL) + PIO_SODR); + else + __raw_writel(pin_to_mask(GPIO_I2C_SCL), pin_to_controller(GPIO_I2C_SCL) + PIO_CODR); +} + +void at91sam9260_i2c_sda(unsigned long bit) +{ + printf("Setting %u\n", bit); + if(bit) + __raw_writel(pin_to_mask(GPIO_I2C_SDA), pin_to_controller(GPIO_I2C_SDA) + PIO_SODR); + else + __raw_writel(pin_to_mask(GPIO_I2C_SDA), pin_to_controller(GPIO_I2C_SDA) + PIO_CODR); +} + +int at91sam9260_i2c_read(void) +{ + int c = (__raw_readl(pin_to_controller(GPIO_I2C_SDA) + PIO_PDSR) & pin_to_mask(GPIO_I2C_SDA)) ? 1 : 0; + printf("Reading %d\n", c); + return c; +} diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index fd9932f..5e66c9e 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -85,6 +85,8 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_CMD_USB 1 +#define CONFIG_CMD_I2C 1 +#define CONFIG_I2C_CMD_TREE 1 /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 @ -192,4 +194,20 @@ #error CONFIG_USE_IRQ not supported #endif +/* + * Software (bit-bang) I2C driver configuration + */ +#define CONFIG_SOFT_I2C 1 +#define CFG_I2C_SPEED 1000000 +#define I2C_INIT at91sam9260_i2c_init() + +#define I2C_ACTIVE +#define I2C_TRISTATE +#define I2C_SCL(bit) at91sam9260_i2c_scl(bit) +#define I2C_SDA(bit) at91sam9260_i2c_sda(bit) +#define I2C_DELAY udelay(2) +#define I2C_READ at91sam9260_i2c_read() +#define CFG_I2C_SLAVE 0 +#define DEBUG_I2C #endif + But I'm unable to read proper values from lines - they always return 0s. Any ideas on fixing? Linux i2c-gpio driver works perfectly. Thanks a lot, S.

4 4

[U-Boot-Users] eth0 not geting enabled
by Avinash Vijayvergia 30 May '08

30 May '08

Hi there I am working on at91sam9260ek. I have put kernel and rfs on dataflash. Now this board boots up but doesn't enable eth0. I searched net and found that if I do a ping it enables phy (MD9161A). But if I do that when there is no network u-boot never recovers. Can someone tell me the way out. Thanks Avinash

1 0

[U-Boot-Users] [PATCH 2/8] New board SIMPC8313 support: README
by Ron Madrid 30 May '08

30 May '08

New board SIMPC8313 support: README Signed-off-by: Ron Madrid --- doc/README.simpc8313 | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 70 insertions(+), 0 deletions(-) create mode 100644 doc/README.simpc8313 diff --git a/doc/README.simpc8313 b/doc/README.simpc8313 new file mode 100644 index 0000000..60e5ab8 --- /dev/null +++ b/doc/README.simpc8313 @@ -0,0 +1,70 @@ +Freescale MPC8313ERDB Board +------------------------------------------------------------------------------- + +1. Board Switches and Jumpers + + S2 is used to set CFG_RESET_SOURCE. + + To boot the image in Large page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | * * **** | + | * * | + +----------+ + 12345678 + + To boot the image in Large page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | *** **** | + | * | + +----------+ + 12345678 + (where the '*' indicates the position of the tab of the switch.) + +2. Memory Map + The memory map looks like this: + + 0x0000_0000 0x1fff_ffff DDR 512M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xe200_0000 0xe20f_ffff PCI IO 16M + 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K + or + 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K + 0xfa00_0000 0xfa00_7fff FPGA (CS1) 1M + +3. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make SIMPC8313_LP_config + (or make SIMPC8313_SP_config, depending on the page size + of your NAND flash) + make + +4. Downloading and Flashing Images + +4.1 Reflash U-boot Image using U-boot + + =>run update_uboot + + You may want to try + =>tftp $loadaddr $uboot + first, to make sure that the TFTP load will succeed before it + goes ahead and wipes out your current firmware. And of course, + have an alternate means of programming the flash available + if the new u-boot doesn't boot. + +4.2 Downloading and Booting Linux Kernel + + TODO: + +5 Notes + + The console baudrate for SIMPC8313 is 115200bps. -- 1.5.5.1

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[U-Boot-Users] [PATCH 5/8] New board SIMPC8313 support: nand_spl
by Ron Madrid 30 May '08

30 May '08

New board SIMPC8313 support: nand_spl Signed-off-by: Ron Madrid --- nand_spl/board/sheldon/simpc8313/Makefile | 91 +++++++++++++++++++++++++++ nand_spl/board/sheldon/simpc8313/config.mk | 50 +++++++++++++++ nand_spl/board/sheldon/simpc8313/u-boot.lds | 65 +++++++++++++++++++ 3 files changed, 206 insertions(+), 0 deletions(-) create mode 100644 nand_spl/board/sheldon/simpc8313/Makefile create mode 100644 nand_spl/board/sheldon/simpc8313/config.mk create mode 100644 nand_spl/board/sheldon/simpc8313/u-boot.lds diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile new file mode 100644 index 0000000..3ebe00d --- /dev/null +++ b/nand_spl/board/sheldon/simpc8313/Makefile @@ -0,0 +1,91 @@ +# +# (C) Copyright 2008, Sheldon Instruments, Inc. +# Adapted from Freescale MPC8313ERDB BSP +# +# (C) Copyright 2006 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o +COBJS = sdram.o nand_boot.o nand_ecc.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# from cpu directory +$(obj)start.S: + @rm -f $(obj)start.S + ln -s $(SRCTREE)/cpu/mpc83xx/start.S $(obj)start.S + +# from board directory +$(obj)sdram.c: + @rm -f $(obj)sdram.c + ln -s $(SRCTREE)/board/$(BOARDDIR)/sdram.c $(obj)sdram.c + +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c + +$(obj)nand_ecc.c: + @rm -f $(obj)nand_ecc.c + ln -s $(SRCTREE)/board/$(BOARDDIR)/nand_ecc.c $(obj)nand_ecc.c + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/sheldon/simpc8313/config.mk b/nand_spl/board/sheldon/simpc8313/config.mk new file mode 100644 index 0000000..c8c2d9a --- /dev/null +++ b/nand_spl/board/sheldon/simpc8313/config.mk @@ -0,0 +1,50 @@ +# +# (C) Copyright 2008, Sheldon Instruments, Inc. +# Adapted from Freescale MPC8313ERDB BSP +# +# (C) Copyright 2006 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# Sheldon Instrument SIMPC8313 +# +# +# TEXT_BASE for SPL: +# +# On Boot-from-NAND the FCM buffer is mapped to the boot space. This +# will be either 0x00000000 for low boot or 0xFFF00000 for high boot. +# The u-boot NAND bootload is configured to use high boot only so +# that it does not conflict with the DDR memory which is configured +# at 0x00000000. Accordingly TEXT_BASE is set to the high boot memory +# space at 0xFFF00000. +# +TEXT_BASE = 0xFFF00000 + +# PAD_TO used to generate a 16kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 0x4000 +ifndef PAD_TO +PAD_TO = 0xFFF20000 +endif + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + diff --git a/nand_spl/board/sheldon/simpc8313/u-boot.lds b/nand_spl/board/sheldon/simpc8313/u-boot.lds new file mode 100644 index 0000000..cbf9fe2 --- /dev/null +++ b/nand_spl/board/sheldon/simpc8313/u-boot.lds @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2008, Sheldon Instruments, Inc. + * Adapted from Freescale MPC8313ERDB BSP + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc:common) +SECTIONS +{ + .text : + { + start.o (.text) + + *(.text) + *(.fixup) + } + _etext = .; + + .reloc : + { + _GOT_TABLE_ = .; + *(.got*) + __got_end = .; + *(.got2) + } + __got_entries = (__got_end - _GOT_TABLE_) >> 2; + + .data : + { + *(.rodata*) + *(.data*) + *(.sdata*) + } + + _edata = .; + + __bss_start = .; + .bss : + { + *(.sbss) + *(.bss) + } + + _end = . ; +} -- 1.5.5.1

2 2

[U-Boot-Users] [PATCH 6/8] New board SIMPC8313 support: Makefile, config.mk
by Ron Madrid 30 May '08

30 May '08

New board SIMPC8313 support: Makefile, config.mk Signed-off-by: Ron Madrid --- board/sheldon/simpc8313/Makefile | 50 +++++++++++++++++++++++++++++++++++++ board/sheldon/simpc8313/config.mk | 3 ++ 2 files changed, 53 insertions(+), 0 deletions(-) create mode 100644 board/sheldon/simpc8313/Makefile create mode 100644 board/sheldon/simpc8313/config.mk diff --git a/board/sheldon/simpc8313/Makefile b/board/sheldon/simpc8313/Makefile new file mode 100644 index 0000000..6f0a19d --- /dev/null +++ b/board/sheldon/simpc8313/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o sdram.o nand.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sheldon/simpc8313/config.mk b/board/sheldon/simpc8313/config.mk new file mode 100644 index 0000000..3be029f --- /dev/null +++ b/board/sheldon/simpc8313/config.mk @@ -0,0 +1,3 @@ +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +TEXT_BASE = 0x01000000 -- 1.5.5.1

1 0

[U-Boot-Users] [PATCH 3/8] New board SIMPC8313 support: config SIMPC8313.h
by Ron Madrid 30 May '08

30 May '08

New board SIMPC8313 support: config SIMPC8313.h Signed-off-by: Ron Madrid --- include/configs/SIMPC8313.h | 505 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 505 insertions(+), 0 deletions(-) create mode 100644 include/configs/SIMPC8313.h diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h new file mode 100644 index 0000000..8afb149 --- /dev/null +++ b/include/configs/SIMPC8313.h @@ -0,0 +1,505 @@ +/* + * Copyright (C) Sheldon Instruments, Inc. 2008. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * simpc8313 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC831X 1 +#define CONFIG_MPC8313 1 /* MPC8313 specific */ + +#define CONFIG_NAND_U_BOOT + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI + +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ +#define CONFIG_83XX_PCICLK 66666666 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#define CONFIG_83XX_PCICLK 33333333 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef PCI_66M +#define CONFIG_SYS_CLK_FREQ 66666666 +#else +#define CONFIG_SYS_CLK_FREQ 33333333 +#endif +#endif + +/* System performance */ +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/*#define CFG_SCCR ( SCCR_RES \ + | SCCR_TSEC1CM_1 \ + | SCCR_TSEC1ON \ + | SCCR_TSEC2ON \ + | SCCR_ENCCM_3 \ + | SCCR_USBCM_3 \ + | SCCR_PCICM ) +*/ +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#undef CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R /* call board_init */ +#undef CONFIG_BOARD_EARLY_INIT_R + +#define CFG_RESET_ADDRESS 0x30000000 + +#define CFG_IMMR 0xE0000000 + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00001000 /* memtest region */ +#define CFG_MEMTEST_END 0x07F00000 + +/* + * DDR Setup + */ +#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ + +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#undef CONFIG_DDR_2T_TIMING + +/* + * Manually set up DDR parameters + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED (512 << 20) + +#define CFG_DDRCDR ( DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR ) + /* 0x73000002 TODO ODR & DRN ? */ + +/* + * FLASH on the Local Bus + */ +#define CFG_NO_FLASH + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + */ +#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ + +#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF ) /* 0x0004ff0f */ + +#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ + +/* drivers/nand/nand.c */ +#ifdef CONFIG_NAND_SPL +#define CFG_NAND_BASE 0xFFF00000 +#else +#define CFG_NAND_BASE 0xE2800000 +#endif +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CFG_NAND_BR_PRELIM ( CFG_NAND_BASE \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V ) /* valid */ + +#ifdef CONFIG_NAND_SP +#define CFG_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR ) +#define CFG_LBLAWAR0_PRELIM 0x8000000E /* 32KB */ +#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define NAND_CACHE_PAGES 32 +#define CFG_NAND_BAD_BLOCK_POS (5) /* Bad block marker location */ +#elif defined(CONFIG_NAND_LP) +#define CFG_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR ) +#define CFG_LBLAWAR0_PRELIM 0x80000011 /* 256KB */ +#define CFG_NAND_PAGE_SIZE (2048) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ +#define NAND_CACHE_PAGES 64 +#define CFG_NAND_BAD_BLOCK_POS (0) /* Bad block marker location */ +#else +#error Page size of NAND not defined. +#endif /* CONFIG_NAND_SP */ + +#define CFG_LBLAWBAR0_PRELIM CFG_NAND_BASE + +/* + * Swap CS0 / CS1 based upon NAND or NOR Flash Boot mode + */ +#define CFG_BR0_PRELIM CFG_NAND_BR_PRELIM +#define CFG_OR0_PRELIM CFG_NAND_OR_PRELIM + +/* + * NAND Boot Configuration, for board/../nand_boot.c + */ +#define CFG_NAND_BR0_PRELIM CFG_NAND_BR_PRELIM +#define CFG_NAND_OR0_PRELIM CFG_OR0_PRELIM +#define CFG_NAND_LBLAWBAR0_PRELIM CFG_NAND_BASE +#define CFG_NAND_LBLAWAR0_PRELIM CFG_LBLAWAR0_PRELIM + +#undef CFG_NAND_BOOT_QUIET /* Enable NAND boot status messages */ +#define CFG_NAND_BOOT_SHOW_ECC_NUM /* Show corrected ECC errors */ +#define CFG_NAND_RELOC (0x10000) /* Stage 1 load address */ +#define CFG_NAND_FMR ((14 << FMR_CWTO_SHIFT) | \ + (1 << FMR_AL_SHIFT)) + +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST (0x01000000) /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START (CFG_NAND_U_BOOT_DST + 0x120) /* NUB start */ +/* + * JFFS2 configuration + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_DEV "nand0" + +/* mtdparts command line support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand0:1M(u-boot),3M(kernel),-(jffs2)" + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_LIBFDT + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8313@0" +#define OF_SOC "soc8313@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500" + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {{0x69}} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#define CONFIG_NET_MULTI + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* + * TSEC configuration + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "TSEC0" + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_GMII 1 /* MII PHY management */ +#define TSEC1_PHY_ADDR 0x0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET ((1024<<10) - (CFG_NAND_BLOCK_SIZE<<1)) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_CMD_NAND /* NAND support */ + +#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ +#define CONFIG_CMD_XIMG /* Load part of Multi Image */ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PCI + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CORE_TO_CSB_2_5X1) + +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_NAND_LP_8BIT |\ + HRCWH_RL_EXT_NAND |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + +/* System IO Config */ +#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ +#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L ((CFG_SDRAM_BASE + 0x10000000) | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U ((CFG_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#define CFG_IBAT2L (CFG_PCI1_MEM_BASE | BATL_PP_10) +#define CFG_IBAT2U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI2 not supported on 8313 */ +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:00:95:01 + +#define CONFIG_IPADDR 10.196.31.84 +#define CONFIG_SERVERIP 10.196.31.85 + +#define CONFIG_HOSTNAME simpc8313 +#define CONFIG_ROOTPATH /tftpboot/10.196.31.85 +#define CONFIG_BOOTFILE /tftpboot/uImage + + +#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "load_uboot=tftp 100000 u-boot-nand.bin\0" \ + "burn_uboot=nand erase u-boot 80000; " \ + "nand write 100000 u-boot $filesize\0" \ + "update_uboot=run load_uboot;run burn_uboot\0" \ + "mtdids=nand0=nand0\0" \ + "mtdparts=mtdparts=nand0:1M(u-boot),3M(kernel),-(jffs2)\0" \ + "netdev=eth1\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \ + "console=ttyS0,115200\0" \ + "" +#define CONFIG_BOOTCOMMAND "nand read 500000 kernel 300000;bootm 500000 - 7e0000" +#endif /* __CONFIG_H */ -- 1.5.5.1

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