May 2008 - U-Boot

[U-Boot-Users] [PATCH 1/2 v3] PPC4xx: Enable Primordial Stack for 40x and Unify ECC Handling
by Grant Erickson 03 Jun '08

03 Jun '08

This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> --- cpu/ppc4xx/44x_spd_ddr.c | 49 +------- cpu/ppc4xx/44x_spd_ddr2.c | 120 ++++++++++++++++- cpu/ppc4xx/Makefile | 1 + cpu/ppc4xx/cpu_init.c | 85 ------------ cpu/ppc4xx/ecc.c | 121 +++++++++++++++++ cpu/ppc4xx/ecc.h | 42 ++++++ cpu/ppc4xx/sdram.c | 44 +------ cpu/ppc4xx/start.S | 314 ++++++++++++++++++++++++++++++++----------- cpu/ppc4xx/traps.c | 9 +- include/asm-ppc/processor.h | 6 +- include/ppc405.h | 191 +++++++++++++++++++++++++-- include/ppc4xx.h | 15 ++ 12 files changed diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index b9cf5cb..b7eeaf2 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -53,6 +53,8 @@ #include <ppc4xx.h> #include <asm/mmu.h> +#include "ecc.h" + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR)) @@ -296,10 +298,6 @@ static void program_tr0(unsigned long *dimm_populated, unsigned long num_dimm_banks); static void program_tr1(void); -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes); -#endif - static unsigned long program_bxcr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -418,7 +416,7 @@ long int spd_sdram(void) { /* * If ecc is enabled, initialize the parity bits. */ - program_ecc(total_size); + ecc_init(CFG_SDRAM_BASE, total_size); #endif return total_size; @@ -1402,45 +1400,4 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, return(bank_base_addr); } - -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes) -{ - unsigned long bank_base_addr; - unsigned long current_address; - unsigned long end_address; - unsigned long address_increment; - unsigned long cfg0; - - /* - * get Memory Controller Options 0 data - */ - mfsdram(mem_cfg0, cfg0); - - /* - * reset the bank_base address - */ - bank_base_addr = CFG_SDRAM_BASE; - - if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN); - - if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) - address_increment = 4; - else - address_increment = 8; - - current_address = (unsigned long)(bank_base_addr); - end_address = (unsigned long)(bank_base_addr) + num_bytes; - - while (current_address < end_address) { - *((unsigned long*)current_address) = 0x00000000; - current_address += address_increment; - } - - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | - SDRAM_CFG0_MCHK_CHK); - } -} -#endif /* CONFIG_DDR_ECC */ #endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index ec76b71..652a600 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -3,9 +3,12 @@ * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a * DDR2 controller (non Denali Core). Those currently are: * - * 405: 405EX + * 405: 405EX(r) * 440/460: 440SP/440SPe/460EX/460GT * + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * @@ -45,6 +48,8 @@ #include <asm/mmu.h> #include <asm/cache.h> +#include "ecc.h" + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT)) @@ -3064,9 +3069,116 @@ static void ppc440sp_sdram_register_dump(void) dcr_data = mfdcr(SDRAM_R3BAS); printf(" MQ3_B0BAS = 0x%08X\n", dcr_data); } -#else +#else /* !defined(DEBUG) */ static void ppc440sp_sdram_register_dump(void) { } -#endif -#endif /* CONFIG_SPD_EEPROM */ +#endif /* defined(DEBUG) */ +#elif defined(CONFIG_405EX) +/*----------------------------------------------------------------------------- + * Function: initdram + * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory + * banks. The configuration is performed using static, compile- + * time parameters. + *---------------------------------------------------------------------------*/ +long initdram(int board_type) +{ + unsigned long val; + + /* Set Memory Bank Configuration Registers */ + + mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF); + mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF); + mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF); + mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF); + + /* Set Memory Clock Timing Register */ + + mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR); + + /* Set Refresh Time Register */ + + mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR); + + /* Set SDRAM Timing Registers */ + + mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1); + mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2); + mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3); + + /* Set Mode and Extended Mode Registers */ + + mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE); + mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE); + + /* Set Memory Controller Options 1 Register */ + + mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1); + + /* Set Manual Initialization Control Registers */ + + mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0); + mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1); + mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2); + mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3); + mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4); + mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5); + mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6); + mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7); + mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8); + mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9); + mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10); + mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11); + mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12); + mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13); + mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14); + mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15); + + /* Set On-Die Termination Registers */ + + mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT); + mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0); + mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1); + + /* Set Write Timing Register */ + + mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR); + + /* + * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and + * SDRAM0_MCOPT2[IPTR] = 1 + */ + + mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT | + SDRAM_MCOPT2_IPTR_EXECUTE)); + + /* + * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the + * completion of initialization. + */ + + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP); + + /* Set Delay Control Registers */ + + mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR); + mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC); + mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC); + mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC); + + /* + * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: + */ + + mfsdram(SDRAM_MCOPT2, val); + mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE); + +#if defined(CONFIG_DDR_ECC) + ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); +#endif /* defined(CONFIG_DDR_ECC) */ + + return (CFG_MBYTES_SDRAM << 20); +} +#endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 178c5c6..800bb41 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -45,6 +45,7 @@ COBJS += cpu.o COBJS += cpu_init.o COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o +COBJS += ecc.o COBJS += fdt.o COBJS += gpio.o COBJS += i2c.o diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 42eabfe..1e9423a 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -32,73 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#ifdef CFG_INIT_DCACHE_CS -# if (CFG_INIT_DCACHE_CS == 0) -# define PBxAP pb0ap -# define PBxCR pb0cr -# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) -# define PBxAP_VAL CFG_EBC_PB0AP -# define PBxCR_VAL CFG_EBC_PB0CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 1) -# define PBxAP pb1ap -# define PBxCR pb1cr -# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) -# define PBxAP_VAL CFG_EBC_PB1AP -# define PBxCR_VAL CFG_EBC_PB1CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 2) -# define PBxAP pb2ap -# define PBxCR pb2cr -# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) -# define PBxAP_VAL CFG_EBC_PB2AP -# define PBxCR_VAL CFG_EBC_PB2CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 3) -# define PBxAP pb3ap -# define PBxCR pb3cr -# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) -# define PBxAP_VAL CFG_EBC_PB3AP -# define PBxCR_VAL CFG_EBC_PB3CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 4) -# define PBxAP pb4ap -# define PBxCR pb4cr -# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) -# define PBxAP_VAL CFG_EBC_PB4AP -# define PBxCR_VAL CFG_EBC_PB4CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 5) -# define PBxAP pb5ap -# define PBxCR pb5cr -# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) -# define PBxAP_VAL CFG_EBC_PB5AP -# define PBxCR_VAL CFG_EBC_PB5CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 6) -# define PBxAP pb6ap -# define PBxCR pb6cr -# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) -# define PBxAP_VAL CFG_EBC_PB6AP -# define PBxCR_VAL CFG_EBC_PB6CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 7) -# define PBxAP pb7ap -# define PBxCR pb7cr -# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) -# define PBxAP_VAL CFG_EBC_PB7AP -# define PBxCR_VAL CFG_EBC_PB7CR -# endif -# endif -#endif /* CFG_INIT_DCACHE_CS */ - #ifndef CFG_PLL_RECONFIG #define CFG_PLL_RECONFIG 0 #endif @@ -353,24 +286,6 @@ int cpu_init_r (void) uint pvr = get_pvr(); #endif -#ifdef CFG_INIT_DCACHE_CS - /* - * Flush and invalidate dcache, then disable CS for temporary stack. - * Afterwards, this CS can be used for other purposes - */ - dcache_disable(); /* flush and invalidate dcache */ - mtebc(PBxAP, 0); - mtebc(PBxCR, 0); /* disable CS for temporary stack */ - -#if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) - /* - * Write new value into CS register - */ - mtebc(PBxAP, PBxAP_VAL); - mtebc(PBxCR, PBxCR_VAL); -#endif -#endif /* CFG_INIT_DCACHE_CS */ - /* * Write Ethernetaddress into on-chip register */ diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c new file mode 100644 index 0000000..95b941d --- /dev/null +++ b/cpu/ppc4xx/ecc.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * (C) Copyright 2002 + * Jun Gu, Artesyn Technology, jung(a)artesyncp.com + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter(a)attbi.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements generic DRAM ECC initialization for + * PowerPC processors using a SDRAM DDR/DDR2 controller, + * including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and + * 460EX/GT. + */ + +#include <common.h> +#include <ppc4xx.h> +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/processor.h> +#include <asm/io.h> + +#include "ecc.h" + +#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) +#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) +/* + * void ecc_init() + * + * Description: + * This routine initializes a range of DRAM ECC memory with known + * data and enables ECC checking. + * + * TO DO: + * - Improve performance by utilizing cache. + * - Further generalize to make usable by other 4xx variants (e.g. + * 440EPx, et al). + * + * Input(s): + * start - A pointer to the start of memory covered by ECC requiring + * initialization. + * size - The size, in bytes, of the memory covered by ECC requiring + * initialization. + * + * Output(s): + * start - A pointer to the start of memory covered by ECC with + * CFG_ECC_PATTERN written to all locations and ECC data + * primed. + * + * Returns: + * N/A + */ +void ecc_init(unsigned long * const start, unsigned long size) +{ + const unsigned long pattern = CFG_ECC_PATTERN; + unsigned * const end = (unsigned long * const)((long)start + size); + unsigned long * current = start; + unsigned long mcopt1; + long increment; + + if (start >= end) + return; + + mfsdram(SDRAM_MCOPT1, mcopt1); + + /* Enable ECC generation without checking or reporting */ + + mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | + SDRAM_MCOPT1_MCHK_GEN)); + + increment = sizeof(u32); + +#if defined(CONFIG_440) + /* + * Look at the geometry of SDRAM (data width) to determine whether we + * can skip words when writing. + */ + + if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) != SDRAM_MCOPT1_DMWD_32) + increment = sizeof(u64); +#endif /* defined(CONFIG_440) */ + + while (current < end) { + *current = pattern; + current = (unsigned long *)((long)current + increment); + } + + /* Wait until the writes are finished. */ + + sync(); + + /* Enable ECC generation with checking and no reporting */ + + mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | + SDRAM_MCOPT1_MCHK_CHK)); +} +#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ +#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h new file mode 100644 index 0000000..da1c4fd --- /dev/null +++ b/cpu/ppc4xx/ecc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * + * Copyright (c) 2007 DENX Software Engineering, GmbH + * Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements ECC initialization for PowerPC processors + * using the SDRAM DDR2 controller, including the 405EX(r), + * 440SP(E), 460EX and 460GT. + * + */ + +#ifndef _ECC_H_ +#define _ECC_H_ + +#if !defined(CFG_ECC_PATTERN) +#define CFG_ECC_PATTERN 0x00000000 +#endif /* !defined(CFG_ECC_PATTERN) */ + +extern void ecc_init(unsigned long * const start, unsigned long size); + +#endif /* _ECC_H_ */ diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 2724d91..901d650 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -31,6 +31,7 @@ #include <ppc4xx.h> #include <asm/processor.h> #include "sdram.h" +#include "ecc.h" #ifdef CONFIG_SDRAM_BANK0 @@ -332,49 +333,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -#ifdef CONFIG_SDRAM_ECC -static void ecc_init(ulong start, ulong size) -{ - ulong current_addr; /* current byte address */ - ulong end_addr; /* end of memory region */ - ulong addr_inc; /* address skip between writes */ - ulong cfg0_reg; /* for restoring ECC state */ - - /* - * TODO: Enable dcache before running this test (speedup) - */ - - mfsdram(mem_cfg0, cfg0_reg); - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN); - - /* - * look at geometry of SDRAM (data width) to determine whether we - * can skip words when writing - */ - if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32) - addr_inc = 4; - else - addr_inc = 8; - - current_addr = start; - end_addr = start + size; - - while (current_addr < end_addr) { - *((ulong *)current_addr) = 0x00000000; - current_addr += addr_inc; - } - - /* - * TODO: Flush dcache and disable it again - */ - - /* - * Enable ecc checking and parity errors - */ - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK); -} -#endif - /* * Autodetect onboard DDR SDRAM on 440 platforms * diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 0008170..a5d9ec9 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -3,6 +3,8 @@ * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd(a)denx.de> * Copyright (C) 2007 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> * * See file CREDITS for list of people who contributed to this * project. @@ -79,34 +81,100 @@ # if (CFG_INIT_DCACHE_CS == 0) # define PBxAP pb0ap # define PBxCR pb0cr +# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +# define PBxAP_VAL CFG_EBC_PB0AP +# define PBxCR_VAL CFG_EBC_PB0CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 1) # define PBxAP pb1ap # define PBxCR pb1cr +# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) +# define PBxAP_VAL CFG_EBC_PB1AP +# define PBxCR_VAL CFG_EBC_PB1CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 2) # define PBxAP pb2ap # define PBxCR pb2cr +# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) +# define PBxAP_VAL CFG_EBC_PB2AP +# define PBxCR_VAL CFG_EBC_PB2CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 3) # define PBxAP pb3ap # define PBxCR pb3cr +# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) +# define PBxAP_VAL CFG_EBC_PB3AP +# define PBxCR_VAL CFG_EBC_PB3CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 4) # define PBxAP pb4ap # define PBxCR pb4cr +# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) +# define PBxAP_VAL CFG_EBC_PB4AP +# define PBxCR_VAL CFG_EBC_PB4CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 5) # define PBxAP pb5ap # define PBxCR pb5cr +# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) +# define PBxAP_VAL CFG_EBC_PB5AP +# define PBxCR_VAL CFG_EBC_PB5CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 6) # define PBxAP pb6ap # define PBxCR pb6cr +# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) +# define PBxAP_VAL CFG_EBC_PB6AP +# define PBxCR_VAL CFG_EBC_PB6CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 7) # define PBxAP pb7ap # define PBxCR pb7cr +# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) +# define PBxAP_VAL CFG_EBC_PB7AP +# define PBxCR_VAL CFG_EBC_PB7CR +# endif +# endif +# ifndef PBxAP_VAL +# define PBxAP_VAL 0 +# endif +# ifndef PBxCR_VAL +# define PBxCR_VAL 0 +# endif +/* + * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB + * used as temporary stack pointer for the primordial stack + */ +# ifndef CFG_INIT_DCACHE_PBxAR +# define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(2) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +# endif /* CFG_INIT_DCACHE_PBxAR */ +# ifndef CFG_INIT_DCACHE_PBxCR +# define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) +# endif /* CFG_INIT_DCACHE_PBxCR */ +# ifndef CFG_INIT_RAM_PATTERN +# define CFG_INIT_RAM_PATTERN 0xDEADDEAD # endif #endif /* CFG_INIT_DCACHE_CS */ @@ -114,6 +182,23 @@ #error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END! #endif +/* + * Unless otherwise overriden, enable two 128MB cachable instruction regions + * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering + * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions. + */ +#if !defined(CFG_ICACHE_SACR_VALUE) +# define CFG_ICACHE_SACR_VALUE \ + (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \ + PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \ + PPC_128MB_SACR_VALUE(CFG_FLASH_BASE)) +#endif /* !defined(CFG_ICACHE_SACR_VALUE) */ + +#if !defined(CFG_DCACHE_SACR_VALUE) +# define CFG_DCACHE_SACR_VALUE \ + (0x00000000) +#endif /* !defined(CFG_DCACHE_SACR_VALUE) */ + #define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ @@ -840,16 +925,16 @@ _start: /* make sure above stores all comlete before going on */ sync - /*----------------------------------------------------------------------- */ - /* Enable two 128MB cachable regions. */ - /*----------------------------------------------------------------------- */ - addis r1,r0,0xc000 - addi r1,r1,0x0001 - mticcr r1 /* instruction cache */ + /* Set-up icache cacheability. */ + lis r1, CFG_ICACHE_SACR_VALUE@h + ori r1, r1, CFG_ICACHE_SACR_VALUE@l + mticcr r1 + isync - addis r1,r0,0x0000 - addi r1,r1,0x0000 - mtdccr r1 /* data cache */ + /* Set-up dcache cacheability. */ + lis r1, CFG_DCACHE_SACR_VALUE@h + ori r1, r1, CFG_DCACHE_SACR_VALUE@l + mtdccr r1 addis r1,r0,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ @@ -892,27 +977,20 @@ _start: /* dbsr is cleared by setting bits to 1) */ mtdbsr r4 /* clear/reset the dbsr */ - /*----------------------------------------------------------------------- */ - /* Invalidate I and D caches. Enable I cache for defined memory regions */ - /* to speed things up. Leave the D cache disabled for now. It will be */ - /* enabled/left disabled later based on user selected menu options. */ - /* Be aware that the I cache may be disabled later based on the menu */ - /* options as well. See miscLib/main.c. */ - /*----------------------------------------------------------------------- */ + /* Invalidate the i- and d-caches. */ bl invalidate_icache bl invalidate_dcache - /*----------------------------------------------------------------------- */ - /* Enable two 128MB cachable regions. */ - /*----------------------------------------------------------------------- */ - lis r4,0xc000 - ori r4,r4,0x0001 - mticcr r4 /* instruction cache */ + /* Set-up icache cacheability. */ + lis r4, CFG_ICACHE_SACR_VALUE@h + ori r4, r4, CFG_ICACHE_SACR_VALUE@l + mticcr r4 isync - lis r4,0x0000 - ori r4,r4,0x0000 - mtdccr r4 /* data cache */ + /* Set-up dcache cacheability. */ + lis r4, CFG_DCACHE_SACR_VALUE@h + ori r4, r4, CFG_DCACHE_SACR_VALUE@l + mtdccr r4 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX) /*----------------------------------------------------------------------- */ @@ -922,9 +1000,9 @@ _start: #endif #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) /* - * Boards like the Kilauea (405EX) don't have OCM and can't use - * DCache for init-ram. So setup stack here directly after the - * SDRAM is initialized. + * For boards that don't have OCM and can't use the data cache + * for their primordial stack, setup stack here directly after the + * SDRAM is initialized in ext_bus_cntlr_init. */ lis r1, CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ @@ -1043,47 +1121,86 @@ start_ram: /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ /*----------------------------------------------------------------------- */ #ifdef CFG_INIT_DCACHE_CS - /*----------------------------------------------------------------------- */ - /* Memory Bank x (nothingness) initialization 1GB+64MEG */ - /* used as temporary stack pointer for stage0 */ - /*----------------------------------------------------------------------- */ - li r4,PBxAP - mtdcr ebccfga,r4 - lis r4,0x0380 - ori r4,r4,0x0480 - mtdcr ebccfgd,r4 - - addi r4,0,PBxCR - mtdcr ebccfga,r4 - lis r4,0x400D - ori r4,r4,0xa000 - mtdcr ebccfgd,r4 - - /* turn on data cache for this region */ - lis r4,0x0080 + li r4, PBxAP + mtdcr ebccfga, r4 + lis r4, CFG_INIT_DCACHE_PBxAR@h + ori r4, r4, CFG_INIT_DCACHE_PBxAR@l + mtdcr ebccfgd, r4 + + addi r4, 0, PBxCR + mtdcr ebccfga, r4 + lis r4, CFG_INIT_DCACHE_PBxCR@h + ori r4, r4, CFG_INIT_DCACHE_PBxCR@l + mtdcr ebccfgd, r4 + + /* + * Enable the data cache for the 128MB storage access control region + * at CFG_INIT_RAM_ADDR. + */ + mfdccr r4 + oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h + ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l mtdccr r4 - /* set stack pointer and clear stack to known value */ + /* + * Preallocate data cache lines to be used to avoid a subsequent + * cache miss and an ensuing machine check exception when exceptions + * are enabled. + */ + li r0, 0 - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l - li r4,2048 /* we store 2048 words to stack */ + lis r4, CFG_INIT_RAM_END@h + ori r4, r4, CFG_INIT_RAM_END@l + + /* + * Convert the size, in bytes, to the number of cache lines/blocks + * to preallocate. + */ + clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) + srwi r5, r4, L1_CACHE_SHIFT + beq ..load_counter + addi r5, r5, 0x0001 +..load_counter: + mtctr r5 + + /* Preallocate the computed number of cache blocks. */ +..alloc_dcache_block: + dcba r0, r3 + addi r3, r3, L1_CACHE_BYTES + bdnz ..alloc_dcache_block + sync + + /* + * Load the initial stack pointer and data area and convert the size, + * in bytes, to the number of words to initialize to a known value. + */ + lis r1, CFG_INIT_RAM_ADDR@h + ori r1, r1, CFG_INIT_SP_OFFSET@l + + lis r4, (CFG_INIT_RAM_END >> 2)@h + ori r4, r4, (CFG_INIT_RAM_END >> 2)@l mtctr r4 - lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */ - ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */ + lis r2, CFG_INIT_RAM_ADDR@h + ori r2, r2, CFG_INIT_RAM_END@l - lis r4,0xdead /* we store 0xdeaddead in the stack */ - ori r4,r4,0xdead + lis r4, CFG_INIT_RAM_PATTERN@h + ori r4, r4, CFG_INIT_RAM_PATTERN@l ..stackloop: - stwu r4,-4(r2) + stwu r4, -4(r2) bdnz ..stackloop - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Make room for stack frame header and clear final stack frame so + * that stack backtraces terminate cleanly. + */ + stwu r0, -4(r1) + stwu r0, -4(r1) + /* * Set up a dummy frame to store reset vector as return address. * this causes stack underflow to reset board. @@ -1328,33 +1445,72 @@ in32r: * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize + * r3 = Relocated stack pointer + * r4 = Relocated global data pointer + * r5 = Relocated text pointer */ .globl relocate_code relocate_code: -#ifdef CONFIG_4xx_DCACHE +#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) /* - * We need to flush the Init Data before the dcache will be - * invalidated + * We need to flush the initial global data (gd_t) before the dcache + * will be invalidated. */ - /* save regs */ - mr r9,r3 - mr r10,r4 - mr r11,r5 + /* Save registers */ + mr r9, r3 + mr r10, r4 + mr r11, r5 - mr r3,r4 - addi r4,r4,0x200 /* should be enough for init data */ + /* Flush initial global data range */ + mr r3, r4 + addi r4, r4, CFG_GBL_DATA_SIZE@l bl flush_dcache_range - /* restore regs */ - mr r3,r9 - mr r4,r10 - mr r5,r11 -#endif +#if defined(CFG_INIT_DCACHE_CS) + /* + * Undo the earlier data cache set-up for the primordial stack and + * data area. First, invalidate the data cache and then disable data + * cacheability for that area. Finally, restore the EBC values, if + * any. + */ + + /* Invalidate the primordial stack and data area in cache */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + + lis r4, CFG_INIT_RAM_END@h + ori r4, r4, CFG_INIT_RAM_END@l + add r4, r4, r3 + + bl invalidate_dcache_range + + /* Disable cacheability for the region */ + mfdccr r3 + lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h + ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l + and r3, r3, r4 + mtdccr r3 + + /* Restore the EBC parameters */ + li r3, PBxAP + mtdcr ebccfga, r3 + lis r3, PBxAP_VAL@h + ori r3, r3, PBxAP_VAL@l + mtdcr ebccfgd, r3 + + li r3, PBxCR + mtdcr ebccfga, r3 + lis r3, PBxCR_VAL@h + ori r3, r3, PBxCR_VAL@l + mtdcr ebccfgd, r3 +#endif /* defined(CFG_INIT_DCACHE_CS) */ + + /* Restore registers */ + mr r3, r9 + mr r4, r10 + mr r5, r11 +#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */ #ifdef CFG_INIT_RAM_DCACHE /* @@ -1396,13 +1552,13 @@ relocate_code: addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */ #else addi r1,r0,0x0000 /* Default TLB entry is #0 */ -#endif +#endif /* CFG_TLB_FOR_BOOT_FLASH */ tlbre r0,r1,0x0002 /* Read contents */ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ tlbwe r0,r1,0x0002 /* Save it out */ sync isync -#endif +#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */ mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Init Data pointer */ mr r10, r5 /* Save copy of Destination Address */ @@ -1425,7 +1581,7 @@ relocate_code: /* First our own GOT */ add r14, r14, r15 - /* the the one used by the C code */ + /* then the one used by the C code */ add r30, r30, r15 /* diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 38b6f89..8b7e32a 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -170,7 +170,7 @@ MachineCheckException(struct pt_regs *regs) val = get_esr(); -#if !defined(CONFIG_440) +#if !defined(CONFIG_440) && !defined(CONFIG_405EX) if (val& ESR_IMCP) { printf("Instruction"); mtspr(ESR, val & ~ESR_IMCP); @@ -179,7 +179,7 @@ MachineCheckException(struct pt_regs *regs) } printf(" machine check.\n"); -#elif defined(CONFIG_440) +#elif defined(CONFIG_440) || defined(CONFIG_405EX) if (val& ESR_IMCP){ printf("Instruction Synchronous Machine Check exception\n"); mtspr(SPRN_ESR, val & ~ESR_IMCP); @@ -187,10 +187,15 @@ MachineCheckException(struct pt_regs *regs) val = mfspr(MCSR); if (val & MCSR_IB) printf("Instruction Read PLB Error\n"); +#if defined(CONFIG_440) if (val & MCSR_DRB) printf("Data Read PLB Error\n"); if (val & MCSR_DWB) printf("Data Write PLB Error\n"); +#else + if (val & MCSR_DB) + printf("Data PLB Error\n"); +#endif if (val & MCSR_TLBP) printf("TLB Parity Error\n"); if (val & MCSR_ICP){ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 8bdfb9d..cfd8440 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -460,17 +460,19 @@ #define SPRN_PID2 0x27a /* Process ID Register 2 */ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ #define SPRN_MCAR 0x23d /* Machine Check Address register */ -#ifdef CONFIG_440 #define MCSR_MCS 0x80000000 /* Machine Check Summary */ #define MCSR_IB 0x40000000 /* Instruction PLB Error */ +#if defined(CONFIG_440) #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ +#else +#define MCSR_DB 0x20000000 /* Data PLB Error */ +#endif /* defined(CONFIG_440) */ #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ -#endif #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) diff --git a/include/ppc405.h b/include/ppc405.h index d953378..c994289 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -22,6 +22,10 @@ #ifndef __PPC405_H__ #define __PPC405_H__ +/* Define bits and masks for real-mode storage attribute control registers */ +#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) +#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) + #ifndef CONFIG_IOP480 #define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ #else @@ -363,6 +367,120 @@ #endif /* defined(CONFIG_405EZ) */ /****************************************************************************** + * External Bus Controller (EBC) + *****************************************************************************/ + +/* Bank Configuration Register */ +#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) +#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \ + EBC_BXCR_BAS_MASK) << 0) +#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) +#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) +#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) +#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) +#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) +#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) +#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) +#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) +#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) +#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) +#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) +#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) +#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) +#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) + +/* Bank Access Parameter Register */ +#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) +#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) +#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(unsigned long, n)) \ + & 0xFF) +#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \ + (static_cast(unsigned long, n)) \ + & 0x1F) +#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(unsigned long, n)) \ + & 0x7) +#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) +#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) +#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) +#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) +#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) +#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \ + (static_cast(unsigned long, n)) \ + & 0x7) +#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) +#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) +#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) +#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) +#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) +#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) +#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) +#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) + +/* Configuration Register */ +#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) +#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) +#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) +#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) +#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) +#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) +#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) +#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) +#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) +#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) +#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) +#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) +#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) +#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) +#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) +#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) +#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) +#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) +#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) +#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) +#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) +#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0) +#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1) +#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) +#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) +#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) +#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) +#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) +#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \ + (static_cast(unsigned long, n)) \ + & 0x1F) +#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) +#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) +#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) +#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) +#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) + +/****************************************************************************** * SDRAM Controller ******************************************************************************/ /* values for memcfga register - indirect addressing of these regs */ @@ -1218,19 +1336,43 @@ /*-----------------------------------------------------------------------------+ | Memory Bank 0-7 configuration -+-----------------------------------------------------------------------------*/ -#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */ -#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */ -#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */ -#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */ -#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */ -#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */ -#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */ -#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */ -#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */ -#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */ -#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */ -#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */ ++----------------------------------------------------------------------------*/ +#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF) +#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0) +#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1) +#define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2) +#define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3) +#define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4) +#define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5) +#define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6) +#define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7) +#define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8) +#define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9) +#define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA) +#define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB) +#define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB +#define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB +#define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB +#define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB +#define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB +#define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB +#define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB +#define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB +#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB +#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB +#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB +#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0) +#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1) +#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2) +#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3) +#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4) +#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5) +#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6) +#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7) +#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8) +#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9) +#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0) +#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1) /*-----------------------------------------------------------------------------+ | Memory Controller Status @@ -1612,4 +1754,27 @@ #define SDR0_PFC1_GPT_FREQ 0x0000000f #endif +/* General Purpose Timer (GPT) Register Offsets */ +#define GPT0_TBC 0x00000000 +#define GPT0_IM 0x00000018 +#define GPT0_ISS 0x0000001C +#define GPT0_ISC 0x00000020 +#define GPT0_IE 0x00000024 +#define GPT0_COMP0 0x00000080 +#define GPT0_COMP1 0x00000084 +#define GPT0_COMP2 0x00000088 +#define GPT0_COMP3 0x0000008C +#define GPT0_COMP4 0x00000090 +#define GPT0_COMP5 0x00000094 +#define GPT0_COMP6 0x00000098 +#define GPT0_MASK0 0x000000C0 +#define GPT0_MASK1 0x000000C4 +#define GPT0_MASK2 0x000000C8 +#define GPT0_MASK3 0x000000CC +#define GPT0_MASK4 0x000000D0 +#define GPT0_MASK5 0x000000D4 +#define GPT0_MASK6 0x000000D8 +#define GPT0_DCT0 0x00000110 +#define GPT0_DCIS 0x0000011C + #endif /* __PPC405_H__ */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 76fe872..4a6eb86 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -29,6 +29,21 @@ #endif /* + * Macro for generating register field mnemonics + */ +#define PPC_REG_BITS 32 +#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) + +/* + * Elide casts when assembling register mnemonics + */ +#ifndef __ASSEMBLY__ +#define static_cast(type, val) (type)(val) +#else +#define static_cast(type, val) (val) +#endif + +/* * Common stuff for 4xx (405 and 440) */

2 1

[U-Boot-Users] [PATCH 0/12] 85xx: various fixes for TQM85xx and support for TQM8548
by Wolfgang Grandegger 03 Jun '08

03 Jun '08

This series of patches fixes various issues with TQM85xx modules and adds support for TQM8548 modules from TQ Components GmbH (http://www.tqc.de). Note: The patches rely on "[PATCH] TQM: move TQM boards to board/tqc" sent a few minutes ago to this list. Wolfgang.

5 25

[U-Boot-Users] [Patch 02/17] U-Boot-V2:Common:Clock Handle case of clock rollover for get_time_ns
by Menon, Nishanth 03 Jun '08

03 Jun '08

get_time_ns does a simplistic delta = cycle_now - cycle_last. It is possible that the h/w counter reached max and reset back to 0. This patch addresses this issue by checking for rollover condition. NOTE 1: This does not guarantee that you cannot confuse get_time_ns. You could possibly wait for two reset cycles and then get a messed up value. To fix that we may need interrupt mode timer tick - something on the lines of jiffies on linux. NOTE 2: the question of cs->mask is not clear. if the mask is for the tick, then it is better done with (cycle_now & cs->mask) - (cs->cycle_last & cs->mask). Do we need min and max for register read? Signed-off-by: Nishanth Menon<x0nishan(a)ti.com> --- common/clock.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) Index: u-boot-v2.git/common/clock.c =================================================================== --- u-boot-v2.git.orig/common/clock.c 2008-05-20 17:19:44.000000000 -0500 +++ u-boot-v2.git/common/clock.c 2008-05-20 17:26:31.000000000 -0500 @@ -37,14 +37,24 @@ uint64_t get_time_ns(void) { struct clocksource *cs = current_clock; - uint64_t cycle_now, cycle_delta; + uint64_t cycle_now, cycle_delta = 0; uint64_t ns_offset; /* read clocksource: */ cycle_now = cs->read(); /* calculate the delta since the last call: */ - cycle_delta = (cycle_now - cs->cycle_last) & cs->mask; + + /* Handle rollover case */ + if (cycle_now < cs->cycle_last) { + /* FIXME: I am not convinced about the cs->mask operation.. + * I am assuming cs->mask is max! Probably need to change + * clocksource structure to have min and max + */ + cycle_delta = cs->mask - (cs->cycle_last & cs->mask); + cs->cycle_last = 0; + } + cycle_delta += (cycle_now & cs->mask) - (cs->cycle_last & cs->mask); /* convert to nanoseconds: */ ns_offset = cyc2ns(cs, cycle_delta);

2 6

[U-Boot-Users] [PATCH] ColdFire: Add 10 base ethernet support for mcf5445x
by Tsi-Chung.Liew 03 Jun '08

03 Jun '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- drivers/net/mcffec.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 5ab4726..8d4e248 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -125,11 +125,17 @@ void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) } if ((dup_spd & 0xFFFF) == _100BASET) { +#ifdef CONFIG_MCF5445x + fecp->rcr &= ~0x200; /* disabled 10T base */ +#endif #ifdef MII_DEBUG printf("100Mbps\n"); #endif bd->bi_ethspeed = 100; } else { +#ifdef CONFIG_MCF5445x + fecp->rcr |= 0x200; /* enabled 10T base */ +#endif #ifdef MII_DEBUG printf("10Mbps\n"); #endif -- 1.5.4.1

3 2

[U-Boot-Users] [PATCH] MPC85xx: Change traps.c to not reference non-addressable memory
by becky.bruce＠freescale.com 03 Jun '08

03 Jun '08

From: Becky Bruce <becky.bruce(a)freescale.com> Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd. Signed-off-by: Becky Bruce <becky.bruce(a)freescale.com> --- cpu/mpc85xx/traps.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 2381fb0..fd36658 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -50,10 +50,12 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0; extern unsigned long search_exception_table(unsigned long); /* - * End of memory as shown by board info and determined by DDR setup. + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. */ -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) - +extern ulong get_effective_memsize(void); +#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) static __inline__ void set_tsr(unsigned long val) { -- 1.5.4.1

4 5

[U-Boot-Users] [PATCH]env_nand.c Added bad block management for environment variables
by Stuart Wood 02 Jun '08

02 Jun '08

Hi All, This is my first attempt at submitting a change so please be patient and kind. This change allows for the environment variables to be stored in a rand of nand flash. If the first block is bad then the environment is stored in the next one, and so on. It introduces CFG_ENV_RANGE to define the size of the area that way contain the environment data. This will allow the environment to be loaded over an area with bad blocks from the factory without a problem. diff --git a/common/env_nand.c b/common/env_nand.c index 49742f5..29aafa2 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -155,27 +155,53 @@ int env_init(void) int saveenv(void) { size_t total; + size_t offset; int ret = 0; env_ptr->flags++; total = CFG_ENV_SIZE; + if (CFG_ENV_RANGE < CFG_ENV_SIZE) + return 1; if(gd->env_valid == 1) { - puts ("Erasing redundant Nand..."); - if (nand_erase(&nand_info[0], - CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) + puts ("Erasing redundant Nand...\n"); + for (offset = CFG_ENV_OFFSET_REDUND; offset < + CFG_ENV_OFFSET_REDUND + CFG_ENV_RANGE; ) + { + if (nand_erase(&nand_info[0], + offset, CFG_ENV_SIZE)) { + offset += CFG_ENV_SIZE; + } else { + break; + } + } + if (offset >= CFG_ENV_OFFSET_REDUND + CFG_ENV_RANGE) { + puts ("Redundant Nand area is completely bad!\n"); + gd->env_valid = 2; return 1; + } puts ("Writing to redundant Nand... "); - ret = nand_write(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, + ret = nand_write(&nand_info[0], offset, &total, (u_char*) env_ptr); } else { - puts ("Erasing Nand..."); - if (nand_erase(&nand_info[0], - CFG_ENV_OFFSET, CFG_ENV_SIZE)) + puts ("Erasing Nand...\n"); + for (offset = CFG_ENV_OFFSET; offset < + CFG_ENV_OFFSET + CFG_ENV_RANGE; ) + { + if (nand_erase(&nand_info[0], + offset, CFG_ENV_SIZE)) { + offset += CFG_ENV_SIZE; + } else { + break; + } + } + if (offset >= CFG_ENV_OFFSET + CFG_ENV_RANGE) { + puts ("Nand area is completely bad!\n"); + gd->env_valid = 1; return 1; - + } puts ("Writing to Nand... "); - ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, + ret = nand_write(&nand_info[0], offset, &total, (u_char*) env_ptr); } if (ret || total != CFG_ENV_SIZE) @@ -189,15 +215,30 @@ int saveenv(void) int saveenv(void) { size_t total; + size_t offset; int ret = 0; - puts ("Erasing Nand..."); - if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE)) + if (CFG_ENV_RANGE < CFG_ENV_SIZE) return 1; + puts ("Erasing Nand...\n"); + for (offset = CFG_ENV_OFFSET; offset < + CFG_ENV_OFFSET + CFG_ENV_RANGE; ) + { + if (nand_erase(&nand_info[0], + offset, CFG_ENV_SIZE)) { + offset += CFG_ENV_SIZE; + } else { + break; + } + } + if (offset >= CFG_ENV_OFFSET + CFG_ENV_RANGE) { + puts ("Nand area is completely bad!\n"); + return 1; + } puts ("Writing to Nand... "); total = CFG_ENV_SIZE; - ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); + ret = nand_write(&nand_info[0], offset, &total, (u_char*)env_ptr); if (ret || total != CFG_ENV_SIZE) return 1; @@ -212,6 +253,7 @@ void env_relocate_spec (void) { #if !defined(ENV_IS_EMBEDDED) size_t total; + size_t offset; int crc1_ok = 0, crc2_ok = 0; env_t *tmp_env1, *tmp_env2; @@ -220,10 +262,25 @@ void env_relocate_spec (void) tmp_env1 = (env_t *) malloc(CFG_ENV_SIZE); tmp_env2 = (env_t *) malloc(CFG_ENV_SIZE); - nand_read(&nand_info[0], CFG_ENV_OFFSET, &total, - (u_char*) tmp_env1); - nand_read(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, - (u_char*) tmp_env2); + for (offset = CFG_ENV_OFFSET; offset < CFG_ENV_OFFSET + CFG_ENV_RANGE ; ) { + if (nand_block_isbad (&nand_info[0], offset)) { + offset += CFG_ENV_SIZE; + } else { + nand_read(&nand_info[0], offset, &total, + (u_char*) tmp_env1); + break; + } + } + for (offset = CFG_ENV_OFFSET_REDUND; offset < + CFG_ENV_OFFSET_REDUND + CFG_ENV_RANGE ; ) { + if (nand_block_isbad (&nand_info[0], offset)) { + offset += CFG_ENV_SIZE; + } else { + nand_read(&nand_info[0], offset, &total, + (u_char*) tmp_env2); + break; + } + } crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc); crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc); -- Stuart Wood Lab X Technologies, LLC 176 Anderson Ave. Suite 302 Rochester, NY 14607 Phone: (585) 271-7790 x207 Fax: (585) 473.4707

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[U-Boot-Users] [PATCH 8/8] New board SIMPC8313 support: nand_boot.c, sdram.c, simpc8313.c
by Ron Madrid 02 Jun '08

02 Jun '08

New board SIMPC8313 support: nand_boot.c, sdram.c, simpc8313.c Remaining board specific files. Signed-off-by: Ron Madrid --- board/sheldon/simpc8313/nand_boot.c | 424 +++++++++++++++++++++++++++++++++++ board/sheldon/simpc8313/sdram.c | 204 +++++++++++++++++ board/sheldon/simpc8313/simpc8313.c | 113 ++++++++++ 3 files changed, 741 insertions(+), 0 deletions(-) create mode 100644 board/sheldon/simpc8313/nand_boot.c create mode 100644 board/sheldon/simpc8313/sdram.c create mode 100644 board/sheldon/simpc8313/simpc8313.c diff --git a/board/sheldon/simpc8313/nand_boot.c b/board/sheldon/simpc8313/nand_boot.c new file mode 100644 index 0000000..39a5616 --- /dev/null +++ b/board/sheldon/simpc8313/nand_boot.c @@ -0,0 +1,424 @@ +/* + * Copyright 2008 Sheldon Instruments, Inc. + * + * Origin from MPC8313EMDS of Nick.Spence(a)freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <mpc83xx.h> +#include <ns16550.h> +#include <nand.h> +#include <asm/processor.h> + +/* NAND ECC checking method - 0 = no hardware ECC check */ +#define NAND_HARD_ECC ((CFG_NAND_BR0_PRELIM >> BR_DECC_SHIFT) & 3) + +/* NAND Page Size : 0 = small page (512 bytes ), 1 = large page (2048 bytes) */ +#define NAND_PGS ((CFG_NAND_OR0_PRELIM >> OR_FCM_PGS_SHIFT) & 1) + +/* Timeout in case FCM does not complete */ +#define NAND_TIMEOUT (1000000) + +/* Delay before restarting after a fatal u-boot error */ +#define RESTART_DELAY (0x4000000) + +/* Error codes returned from nand_read_next_block() */ +#define NAND_OK (1) /* read block okay */ +#define NAND_BAD_BLOCK (0) /* block marked bad - skip block */ +#define NAND_ERR_TIMEOUT (-1) /* timeout error - fatal error */ +#define NAND_ERR_ECC (-2) /* uncorrectable ecc - fatal error */ + +/* Macros to control selected serial port */ +#if CONFIG_CONS_INDEX == 1 && defined(CFG_NS16550_COM1) +#define NS16550_COM ((NS16550_t)CFG_NS16550_COM1) +#elif CONFIG_CONS_INDEX == 2 && defined(CFG_NS16550_COM2) +#define NS16550_COM ((NS16550_t)CFG_NS16550_COM2) +#else +#warning "*****************************" +#warning "** No console port defined **" +#warning "*****************************" +#define NS16550_COM ((NS16550_t)0) +#define CFG_NAND_BOOT_QUIET +#endif /* CONFIG_CONS_INDEX */ + +/* Quiet Boot - only prints fatal error messages */ +#if defined(CFG_NAND_BOOT_QUIET) +#define status_putc(c) { while (0); } +#define status_puts(s) { while (0); } +#else +#define status_putc(c) { putc(c); } +#define status_puts(s) { puts(s); } +#endif /* CFG_NAND_BOOT_QUIET */ + +#if !(NAND_HARD_ECC) +const u_char ecc_pos[] = { +#if (NAND_PGS) + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63 +#else + 0, 1, 2, 3, 6, 7 +#endif /* NAND_PGS */ +}; +#endif /* !(NAND_HARD_ECC) */ + +/* u-boot version string from start.S */ +extern char version_string[]; + +/* nand_ecc.c */ +extern int nand_correct_data (u_char * dat, const u_char * ecc_pos, int blocks); + +/* hang */ +void hang (void) +{ + while(1); +} + +#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ +#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ +#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ + +static +void NS16550a_init (int baud_divisor) +{ + if (NS16550_COM) { + NS16550_COM->ier = 0x00; + NS16550_COM->lcr = LCR_BKSE | LCRVAL; + NS16550_COM->dll = baud_divisor & 0xff; + NS16550_COM->dlm = (baud_divisor >> 8) & 0xff; + NS16550_COM->lcr = LCRVAL; + NS16550_COM->mcr = MCRVAL; + NS16550_COM->fcr = FCRVAL; + } +} + +/* print a single character, with an extra line feed for return characters */ +void putc (const char c) +{ + if (NS16550_COM) { + if (c == '\n') { + while ((NS16550_COM->lsr & LSR_THRE) == 0); + NS16550_COM->thr = '\r'; + } + while ((NS16550_COM->lsr & LSR_THRE) == 0); + NS16550_COM->thr = c; + } +} + +/* print an entire null terminated string */ +void puts (const char *s) +{ + while (*s) { + putc (*s++); + } +} + +/* read the next block from NAND flash and store it at the supplied address + * + * return values: + * NAND_OK - block was successfully read and copied to the destination + * NAND_BAD_BLOCK - block was marked bad so should be skipped + * NAND_ERR_TIMEOUT - page read did not complete (fatal error) + * NAND_ERR_ECC - uncorrectable ECC (fatal error) + */ +static +int nand_read_next_block (unsigned int *dst) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc = &im->lbus; + int buf_num; + int page; + unsigned char *srcc; + unsigned int *src; + int ecc_err; + int ctr; + unsigned int status; +#if !(NAND_HARD_ECC) + int ecc_cnt; + char ecc_char; + + ecc_cnt = 0; +#endif /* !(NAND_HARD_ECC) */ + + ecc_err = 0; + srcc = 0; + + /* Enable FCM detection of timeouts, ECC errors and completion */ + lbc->ltedr = 0; + + lbc->fbcr = 0; /* read entire page to enable ECC */ + lbc->fbar++; /* read next block, follows boot loaded block */ +#if (NAND_PGS) + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RBW << FIR_OP4_SHIFT); +#else + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_RBW << FIR_OP3_SHIFT); +#endif /* NAND_PGS */ + lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | + (NAND_CMD_READSTART << FCR_CMD1_SHIFT); + + /* read in each page of the block */ + for (page = 0; page < (CFG_NAND_BLOCK_SIZE / CFG_NAND_PAGE_SIZE); + page++) { + if (NAND_PGS) { + lbc->fpar = ((page << FPAR_LP_PI_SHIFT) & FPAR_LP_PI); + buf_num = (page & 1) << 2; + } else { + lbc->fpar = ((page << FPAR_SP_PI_SHIFT) & FPAR_SP_PI); + buf_num = page & 7; + } + lbc->fmr = CFG_NAND_FMR | 2; + + /* clear event registers */ + lbc->ltesr = lbc->ltesr; + lbc->lteatr = 0; + + /* execute special operation on bank 0 */ + lbc->lsor = 0; + asm ("sync"); + + /* copy previous page to RAM */ + if (srcc) { +#if !(NAND_HARD_ECC) + status = + nand_correct_data (srcc, ecc_pos, + sizeof (ecc_pos) / 3); + ecc_cnt += status; + if (status < 0) + ecc_err = 1; +#endif /* !(NAND_HARD_ECC) */ + src = (unsigned int *)srcc; + for (ctr = CFG_NAND_PAGE_SIZE / sizeof (unsigned int); + ctr; ctr--) { + *(dst++) = *(src++); + } + } + + /* store the source address for the next page */ + srcc = (unsigned char *)((CFG_NAND_BR0_PRELIM & BR_BA) + + (buf_num * 1024)); + + /* wait for FCM complete flag or timeout */ + status = 0; + for (ctr = NAND_TIMEOUT; ctr; ctr--) { + status = lbc->ltesr; + if (status) { + break; + } + } + + /* check for timeout or hardware ECC errors */ + if (status != LTESR_CC) { +#if (NAND_HARD_ECC) + if (status & LTESR_PAR) { + status_putc ('E'); + ecc_err = 1; + } else +#endif /* NAND_HARD_ECC */ + { + status_putc ('T'); + return NAND_ERR_TIMEOUT; + } + } + + /* Check if the block is marked as bad */ + if (page < 2) { + if (srcc[CFG_NAND_PAGE_SIZE + CFG_NAND_BAD_BLOCK_POS] != + 0xFF) { + status_putc ('B'); + return NAND_BAD_BLOCK; + } + } + } + + /* copy last page to RAM */ +#if !(NAND_HARD_ECC) + status = nand_correct_data (srcc, ecc_pos, sizeof (ecc_pos) / 3); + ecc_cnt += status; + if (status < 0) + ecc_err = 1; +#endif /* !(NAND_HARD_ECC) */ + src = (unsigned int *)srcc; + for (ctr = CFG_NAND_PAGE_SIZE / sizeof (unsigned int); ctr; ctr--) { + *(dst++) = *(src++); + } + + /* abort if any of the pages had uncorrectable errors */ + if (ecc_err && (page > 1)) { + status_putc ('U'); + return NAND_ERR_ECC; + } +#if (NAND_HARD_ECC) + status_putc ('.'); +#else +#ifdef CFG_NAND_BOOT_SHOW_ECC_NONE + ecc_char = '.'; +#else + if (ecc_cnt <= 0) { + ecc_char = '.'; +#ifdef CFG_NAND_BOOT_SHOW_ECC_NUM + } else if (ecc_cnt <= 9) { + ecc_char = '0' + ecc_cnt; + } else { + ecc_char = 'a' + ecc_cnt - 10; +#else + } else { + ecc_char = 'c'; +#endif /* CFG_NAND_BOOT_SHOW_ECC_NUM */ + } +#endif /* CFG_NAND_BOOT_SHOW_ECC_NONE */ + status_putc (ecc_char); +#endif /* NAND_HARD_ECC */ + + return NAND_OK; /* block read completed ok */ +} + +/* initial C code called from start.S prior to relocating code to DDR + * + * This performs minimal CPU initailization, DDR initialization, a few + * print statements and the calls relocate_code() to copy the code from + * the NAND flash buffer to DDR. + */ +void cpu_init_f (volatile immap_t * im) +{ + u8 spmf; + u8 clkin_div; + u32 csb_clk; + + /* RMR - Reset Mode Register - enable checkstop reset enable */ + im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT)); + +#if defined(CFG_NAND_BR0_PRELIM) \ + && defined(CFG_NAND_OR0_PRELIM) \ + && defined(CFG_NAND_LBLAWBAR0_PRELIM) \ + && defined(CFG_NAND_LBLAWAR0_PRELIM) + im->lbus.bank[0].br = CFG_NAND_BR0_PRELIM; + im->lbus.bank[0].or = CFG_NAND_OR0_PRELIM; + im->sysconf.lblaw[0].bar = CFG_NAND_LBLAWBAR0_PRELIM; + im->sysconf.lblaw[0].ar = CFG_NAND_LBLAWAR0_PRELIM; +#else +#error CFG_NAND_BR0_PRELIM, CFG_NAND_OR0_PRELIM, CFG_NAND_LBLAWBAR0_PRELIM & CFG_NAND_LBLAWAR0_PRELIM must be defined +#endif + clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); + spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT); + + if (im->reset.rcwh & HRCWH_PCI_HOST) { +#if defined(CONFIG_83XX_CLKIN) + csb_clk = CONFIG_83XX_CLKIN * spmf; +#else + csb_clk = 0; +#endif /* CONFIG_83XX_CLKIN */ + } else { +#if defined(CONFIG_83XX_PCICLK) + csb_clk = CONFIG_83XX_PCICLK * spmf * (1 + clkin_div); +#else + csb_clk = 0; +#endif /* CONFIG_83XX_PCICLK */ + } + + /* initialize selected port with appropriate baud rate */ + NS16550a_init (csb_clk / 16 / CONFIG_BAUDRATE); + + status_puts ("\nNAND-SPL "); + status_puts ((char *)(&version_string)); + + /* board specific DDR initialization */ + initdram (0); + + /* copy code to DDR and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code (CFG_NAND_RELOC + 0x10000, 0, CFG_NAND_RELOC); + + /* should never get here */ + puts ("\nRelocate failed\n"); + + /* delay then restart */ + hang (); +} + +/* called after code is moved to DDR, to complete boot loading */ +void board_init_r (gd_t * id, ulong dest_addr) +{ + int blockcopy_count; + unsigned char *dst; + void (*uboot) (void* dummy, void* immr); + int ret; + + icache_enable (); /* faster execution */ + + status_puts ("\nLoading from NAND: "); + + /* + * Load U-Boot image from NAND into RAM + */ + dst = (unsigned char *)CFG_NAND_U_BOOT_DST; + blockcopy_count = ((CFG_NAND_U_BOOT_SIZE + CFG_NAND_BLOCK_SIZE - 1) + / CFG_NAND_BLOCK_SIZE); + + while (blockcopy_count) { + ret = nand_read_next_block ((unsigned int *)dst); + switch (ret) { + case NAND_OK: + /* advance to the next block */ + dst += CFG_NAND_BLOCK_SIZE; + blockcopy_count--; + break; + case NAND_BAD_BLOCK: + /* skip bad block */ + break; + default: /* fatal error */ +#if defined(CFG_NAND_BOOT_QUIET) + puts ("\nNAND SPL - "); +#else + putc ('\n'); +#endif /* CFG_NAND_BOOT_QUIET */ + if (ret == NAND_ERR_TIMEOUT) + puts ("**FATAL** : Timeout\n"); + else + puts ("**FATAL** : ECC Error\n"); + while (1) + ; + + /* delay then restart */ + hang (); + break; + } + } + + /* + * Jump to U-Boot image + */ + while(1){ + uboot = (void (*)(void* dummy, void* immr))CFG_NAND_U_BOOT_START; + (*uboot) (NULL, (void*) CFG_IMMR); + } +} + + diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c new file mode 100644 index 0000000..9230225 --- /dev/null +++ b/board/sheldon/simpc8313/sdram.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) Sheldon Instruments, Inc. 2008. + * + * Initialized by ron_madrid(a)hotmail.com + * Adapted from ../freescale/mpc8313erdb/sdram.c + * + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + */ + +#include <common.h> +#include <ioports.h> +#include <mpc83xx.h> +#include <asm/mmu.h> +#include <spd.h> +#include <command.h> + +int fixed_sdram(void); + +#if defined(CONFIG_NAND_SPL) +#define puts(v) {} +#define udelay(x) { int i,j; for (i=0; i<x; i++) for (j=0;j<10000;j++); } + +void si_read_i2c(int, int, u8*); +void si_wait_i2c(void); +#endif + +#define DDRLAWAR_SIZE 0x0000003F + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + puts("Initializing\n"); + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + + msize = fixed_sdram(); + + /* Local Bus setup lbcr and mrtpr */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("sync"); + + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +/************************************************************************* + * fixed sdram init -- reads values from boot sequencer I2C + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msizelog2, msize = 1; +#if defined(CONFIG_NAND_SPL) + u32 i; + u8 buffer[135]; + u32 lbyte = 0, count = 135; + u32 addr = 0, data = 0; + + si_read_i2c(lbyte, count, buffer); + + for (i = 18; i < count; i+=7){ + addr = (u32)buffer[i]; + addr <<= 8; + addr |= (u32)buffer[i + 1]; + addr <<= 2; + data = (u32)buffer[i + 2]; + data <<= 8; + data |= (u32)buffer[i + 3]; + data <<= 8; + data |= (u32)buffer[i + 4]; + data <<= 8; + data |= (u32)buffer[i + 5]; + + *((u32 *)(CFG_IMMR + addr)) = data; + } + + udelay(200); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; +#endif /* (CONFIG_NAND_SPL) */ + + msizelog2 = ((im->sysconf.ddrlaw[0].ar & DDRLAWAR_SIZE) + 1); + msize <<= (msizelog2 - 20); + + return msize; +} + +#if defined(CONFIG_NAND_SPL) +void si_read_i2c(int lbyte, int count, u8 *buffer) +{ + u8 chip = 0x50; /* boot sequencer I2C */ + u8 ubyte; + u8 dummy; + u32 i; + volatile immap_t *im = (immap_t *) CFG_IMMR; + + chip <<= 1; + ubyte = (lbyte&0xff00)>>8; + lbyte &= 0xff; + + /* + * Set up controller + */ + im->i2c[0].cr = 0x00; + im->i2c[0].fdr = 0x3f; + im->i2c[0].dfsrr = 0x10; + im->i2c[0].adr = 0x00; + im->i2c[0].sr = 0x80; + im->i2c[0].dr = 0; + + while (im->i2c[0].sr & 0x20) + ; + + /* + * Writing address to device + */ + im->i2c[0].cr = 0xb0; + im->i2c[0].dr = chip; + si_wait_i2c(); + + im->i2c[0].cr = 0xb0; + im->i2c[0].dr = ubyte; + + si_wait_i2c(); + im->i2c[0].dr = lbyte; + si_wait_i2c(); + im->i2c[0].cr = 0xb4; + im->i2c[0].dr = chip + 1; + si_wait_i2c(); + im->i2c[0].cr = 0xa0; + + /* + * Dummy read + */ + dummy = im->i2c[0].dr; + + si_wait_i2c(); + + /* + * Read actual data + */ + for (i = 0; i < count; i++) + { + if (i == (count - 2)) /* Reached next to last byte */ + im->i2c[0].cr = 0xa8; + if (i == (count - 1)) /* Reached last byte */ + im->i2c[0].cr = 0x88; + + /* Read byte of data */ + buffer[i] = im->i2c[0].dr; + + if (i ==(count - 1)) + break; + si_wait_i2c(); + + } + + /* + * Reset controller + */ + im->i2c[0].cr = 0x80; + im->i2c[0].sr = 0x00; + + return; +} + +void si_wait_i2c(void){ + volatile immap_t *im = (immap_t *) CFG_IMMR; + + while (!(im->i2c[0].sr & 0x02)) + ; + im->i2c[0].sr = 0; + return; +} +#endif /* CONFIG_NAND_SPL */ diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c new file mode 100644 index 0000000..387bc06 --- /dev/null +++ b/board/sheldon/simpc8313/simpc8313.c @@ -0,0 +1,113 @@ +/* + * Copyright (C) Sheldon Instruments, Inc. 2008. + * + * Initialized by ron_madrid(a)hotmail.com + * Adapted from ../freescale/mpc8313/mpc8313erdb.c + * + * ChangeLog + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + */ + +#include <common.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif /* defined(CONFIG_OF_LIBFDT) */ +#include <pci.h> +#include <mpc83xx.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ /* + * Nothing to implement here yet + */ + return 0; +} + +int checkboard(void) +{ + puts("Board: Sheldon Instruments SIMPC8313\n"); + + return 0; +} + +static struct pci_region pci_regions[] = { + { + bus_start: CFG_PCI1_MEM_BASE, + phys_start: CFG_PCI1_MEM_PHYS, + size: CFG_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI1_MMIO_BASE, + phys_start: CFG_PCI1_MMIO_PHYS, + size: CFG_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCI1_IO_BASE, + phys_start: CFG_PCI1_IO_PHYS, + size: CFG_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + int warmboot; + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; +#ifndef CFG_8313ERDB_BROKEN_PMC + warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; +#endif /* CFG_8313ERDB_BROKEN_PMC */ + + mpc83xx_pci_init(1, reg, warmboot); +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) + +extern void ft_cpu_setup(void *blob, bd_t *bd); +extern void ft_pci_setup(void *blob, bd_t *bd); + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif /* CONFIG_PCI */ +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ -- 1.5.5.1

3 4

[U-Boot-Users] [MIPS] Update <asm/addrspace.h> header
by Shinya Kuribayashi 31 May '08

31 May '08

- Fix traditional KSEG names - Fix PHYSADDR Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- board/gth2/gth2.c | 2 - board/incaip/incaip.c | 2 - board/purple/purple.c | 14 ++-- board/tb0229/vr4131-pci.c | 56 +++++++------- cpu/mips/cache.S | 6 +- include/asm-mips/addrspace.h | 167 +++++++++++++++++++++++++++++++----------- include/asm-mips/io.h | 4 + 7 files changed, 167 insertions(+), 84 deletions(-) diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c index 9bc4d3f..3e56678 100644 --- a/board/gth2/gth2.c +++ b/board/gth2/gth2.c @@ -36,7 +36,7 @@ static int wdi_status = 0; #define SDRAM_SIZE ((64*1024*1024)-(12*4096)) -#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096)) +#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096)) void inline log_serial_char(char c){ char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER; diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c index c624b3d..dc51373 100644 --- a/board/incaip/incaip.c +++ b/board/incaip/incaip.c @@ -63,7 +63,7 @@ long int initdram(int board_type) /* Can't probe for RAM size unless we are running from Flash. */ - if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1)) + if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) { return max_sdram_size(); } diff --git a/board/purple/purple.c b/board/purple/purple.c index 89cb906..72d5734 100644 --- a/board/purple/purple.c +++ b/board/purple/purple.c @@ -85,16 +85,16 @@ static void sdram_timing_init (ulong size) while (p4 < 32 && done == 0) { WRITE_MC_IOGP_1; - for (addr = KSEG1 + 0x4000; - addr < KSEG1ADDR (size); + for (addr = CKSEG1 + 0x4000; + addr < CKSEG1ADDR (size); addr = addr + 4) { *(uint *) addr = 0xaa55aa55; } pass = 1; - for (addr = KSEG1 + 0x4000; - addr < KSEG1ADDR (size) && pass == 1; + for (addr = CKSEG1 + 0x4000; + addr < CKSEG1ADDR (size) && pass == 1; addr = addr + 4) { if (*(uint *) addr != 0xaa55aa55) pass = 0; @@ -138,7 +138,7 @@ long int initdram(int board_type) ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB; void (* sdram_init) (ulong); - sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init); + sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init); sdram_init(0x10000); @@ -260,14 +260,14 @@ void copy_code (ulong dest_addr) /* flush caches */ - start = KSEG0; + start = CKSEG0; end = start + CFG_DCACHE_SIZE; while(start < end) { cache_unroll(start,Index_Writeback_Inv_D); start += CFG_CACHELINE_SIZE; } - start = KSEG0; + start = CKSEG0; end = start + CFG_ICACHE_SIZE; while(start < end) { cache_unroll(start,Index_Invalidate_I); diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c index 0ee4bf3..4c91923 100644 --- a/board/tb0229/vr4131-pci.c +++ b/board/tb0229/vr4131-pci.c @@ -13,34 +13,34 @@ #include <pci.h> #include <asm/addrspace.h> -#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00) -#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04) -#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08) -#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c) -#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10) -#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14) -#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18) -#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c) -#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24) -#define VR4131_INTCNTSTAREG (volatile unsigned int*)(KSEG1 + 0x0f000c28) -#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c) -#define VR4131_PCIRECONTREG (volatile unsigned int*)(KSEG1 + 0x0f000c30) -#define VR4131_PCIENREG (volatile unsigned int*)(KSEG1 + 0x0f000c34) -#define VR4131_PCICLKSELREG (volatile unsigned int*)(KSEG1 + 0x0f000c38) -#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c) -#define VR4131_PCICLKRUNREG (volatile unsigned int*)(KSEG1 + 0x0f000c60) -#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00) -#define VR4131_VENDORIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) -#define VR4131_DEVICEIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) -#define VR4131_COMMANDREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) -#define VR4131_STATUSREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) -#define VR4131_REVREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) -#define VR4131_CLASSREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) -#define VR4131_CACHELSREG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) -#define VR4131_LATTIMERRG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) -#define VR4131_MAILBAREG (volatile unsigned int*)(KSEG1 + 0x0f000d10) -#define VR4131_PCIMBA1REG (volatile unsigned int*)(KSEG1 + 0x0f000d14) -#define VR4131_PCIMBA2REG (volatile unsigned int*)(KSEG1 + 0x0f000d18) +#define VR4131_PCIMMAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c00) +#define VR4131_PCIMMAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c04) +#define VR4131_PCITAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c08) +#define VR4131_PCITAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c0c) +#define VR4131_PCIMIOAWREG (volatile unsigned int *)(CKSEG1 + 0x0f000c10) +#define VR4131_PCICONFDREG (volatile unsigned int *)(CKSEG1 + 0x0f000c14) +#define VR4131_PCICONFAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c18) +#define VR4131_PCIMAILREG (volatile unsigned int *)(CKSEG1 + 0x0f000c1c) +#define VR4131_BUSERRADREG (volatile unsigned int *)(CKSEG1 + 0x0f000c24) +#define VR4131_INTCNTSTAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c28) +#define VR4131_PCIEXACCREG (volatile unsigned int *)(CKSEG1 + 0x0f000c2c) +#define VR4131_PCIRECONTREG (volatile unsigned int *)(CKSEG1 + 0x0f000c30) +#define VR4131_PCIENREG (volatile unsigned int *)(CKSEG1 + 0x0f000c34) +#define VR4131_PCICLKSELREG (volatile unsigned int *)(CKSEG1 + 0x0f000c38) +#define VR4131_PCITRDYREG (volatile unsigned int *)(CKSEG1 + 0x0f000c3c) +#define VR4131_PCICLKRUNREG (volatile unsigned int *)(CKSEG1 + 0x0f000c60) +#define VR4131_PCIHOSTCONFIG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) +#define VR4131_VENDORIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) +#define VR4131_DEVICEIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) +#define VR4131_COMMANDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04) +#define VR4131_STATUSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04) +#define VR4131_REVREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08) +#define VR4131_CLASSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08) +#define VR4131_CACHELSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c) +#define VR4131_LATTIMERRG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c) +#define VR4131_MAILBAREG (volatile unsigned int *)(CKSEG1 + 0x0f000d10) +#define VR4131_PCIMBA1REG (volatile unsigned int *)(CKSEG1 + 0x0f000d14) +#define VR4131_PCIMBA2REG (volatile unsigned int *)(CKSEG1 + 0x0f000d18) /*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */ /*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */ diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 7966079..ee5d411 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -40,7 +40,7 @@ */ #define MIPS_MAX_CACHE_SIZE 0x10000 -#define INDEX_BASE KSEG0 +#define INDEX_BASE CKSEG0 .macro cache_op op addr .set push @@ -218,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra) /* * Now clear that much memory starting from zero. */ - PTR_LI a0, KSEG1 + PTR_LI a0, CKSEG1 PTR_ADDU a1, a0, v0 2: PTR_ADDIU a0, 64 f_fill64 a0, -64, zero @@ -318,7 +318,7 @@ LEAF(dcache_enable) .globl mips_cache_lock .ent mips_cache_lock mips_cache_lock: - li a1, K0BASE - CACHE_LOCK_SIZE + li a1, CKSEG0 - CACHE_LOCK_SIZE addu a0, a1 li a2, CACHE_LOCK_SIZE li a3, CFG_CACHELINE_SIZE diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 0e6abd7..767804c 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -3,16 +3,94 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996 by Ralf Baechle - * Copyright (C) 2000 by Maciej W. Rozycki - * - * Defitions for the address spaces of the MIPS CPUs. + * Copyright (C) 1996, 99 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. + */ +#ifndef _ASM_ADDRSPACE_H +#define _ASM_ADDRSPACE_H + +/* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ATYPE_ +#define _ATYPE32_ +#define _ATYPE64_ +#define _CONST64_(x) x +#else +#define _ATYPE_ __PTRDIFF_TYPE__ +#define _ATYPE32_ int +#define _ATYPE64_ __s64 +#ifdef CONFIG_64BIT +#define _CONST64_(x) x ## L +#else +#define _CONST64_(x) x ## LL +#endif +#endif + +/* + * 32-bit MIPS address spaces + */ +#ifdef __ASSEMBLY__ +#define _ACAST32_ +#define _ACAST64_ +#else +#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ +#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ +#endif + +/* + * Returns the kernel segment base of a given address + */ +#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) + +/* + * Returns the physical address of a CKSEGx / XKPHYS address + */ +#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) +#define XPHYSADDR(a) ((_ACAST64_(a)) & \ + _CONST64_(0x000000ffffffffff)) + +#ifdef CONFIG_64BIT + +/* + * Memory segments (64bit kernel mode addresses) + * The compatibility segments use the full 64-bit sign extended value. Note + * the R8000 doesn't have them so don't reference these in generic MIPS code. + */ +#define XKUSEG _CONST64_(0x0000000000000000) +#define XKSSEG _CONST64_(0x4000000000000000) +#define XKPHYS _CONST64_(0x8000000000000000) +#define XKSEG _CONST64_(0xc000000000000000) +#define CKSEG0 _CONST64_(0xffffffff80000000) +#define CKSEG1 _CONST64_(0xffffffffa0000000) +#define CKSSEG _CONST64_(0xffffffffc0000000) +#define CKSEG3 _CONST64_(0xffffffffe0000000) + +#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) + +#else + +#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) + +/* + * Map an address to a certain kernel segment */ -#ifndef __ASM_MIPS_ADDRSPACE_H -#define __ASM_MIPS_ADDRSPACE_H +#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) +#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) +#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) +#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) /* * Memory segments (32bit kernel mode addresses) + * These are the traditional names used in the 32-bit universe. */ #define KUSEG 0x00000000 #define KSEG0 0x80000000 @@ -20,25 +98,34 @@ #define KSEG2 0xc0000000 #define KSEG3 0xe0000000 -#define K0BASE KSEG0 +#define CKUSEG 0x00000000 +#define CKSEG0 0x80000000 +#define CKSEG1 0xa0000000 +#define CKSEG2 0xc0000000 +#define CKSEG3 0xe0000000 + +#endif /* - * Returns the kernel segment base of a given address + * Cache modes for XKPHYS address conversion macros */ -#ifndef __ASSEMBLY__ -#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000) -#else -#define KSEGX(a) ((a) & 0xe0000000) -#endif +#define K_CALG_COH_EXCL1_NOL2 0 +#define K_CALG_COH_SHRL1_NOL2 1 +#define K_CALG_UNCACHED 2 +#define K_CALG_NONCOHERENT 3 +#define K_CALG_COH_EXCL 4 +#define K_CALG_COH_SHAREABLE 5 +#define K_CALG_NOTUSED 6 +#define K_CALG_UNCACHED_ACCEL 7 /* - * Returns the physical address of a KSEG0/KSEG1 address + * 64-bit address conversions */ -#ifndef __ASSEMBLY__ -#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) -#else -#define PHYSADDR(a) ((a) & 0x1fffffff) -#endif +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) +#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) +#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ + (_CONST64_(cm) << 59) | (a)) /* * Returns the uncached address of a sdram address @@ -52,31 +139,27 @@ #define UNCACHED_SDRAM(a) KSEG1ADDR(a) #endif /* CONFIG_AU1X00 */ #endif /* __ASSEMBLY__ */ + /* - * Map an address to a certain kernel segment + * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting + * the region, 3 bits for the CCA mode. This leaves 59 bits of which the + * R8000 implements most with its 48-bit physical address space. */ -#ifndef __ASSEMBLY__ -#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0)) -#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) -#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2)) -#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) -#else -#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0) -#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) -#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2) -#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3) -#endif +#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ + +#ifndef CONFIG_CPU_R8000 /* - * Memory segments (64bit kernel mode addresses) + * The R8000 doesn't have the 32-bit compat spaces so we don't define them + * in order to catch bugs in the source code. */ -#define XKUSEG 0x0000000000000000 -#define XKSSEG 0x4000000000000000 -#define XKPHYS 0x8000000000000000 -#define XKSEG 0xc000000000000000 -#define CKSEG0 0xffffffff80000000 -#define CKSEG1 0xffffffffa0000000 -#define CKSSEG 0xffffffffc0000000 -#define CKSEG3 0xffffffffe0000000 - -#endif /* __ASM_MIPS_ADDRSPACE_H */ + +#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) +#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ + +#endif + +#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) +#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) + +#endif /* _ASM_ADDRSPACE_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 7137072..3a0f33f 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -120,7 +120,7 @@ static inline void set_io_port_base(unsigned long base) */ extern inline unsigned long virt_to_phys(volatile void * address) { - return PHYSADDR(address); + return CPHYSADDR(address); } extern inline void * phys_to_virt(unsigned long address) @@ -133,7 +133,7 @@ extern inline void * phys_to_virt(unsigned long address) */ extern inline unsigned long virt_to_bus(volatile void * address) { - return PHYSADDR(address); + return CPHYSADDR(address); } extern inline void * bus_to_virt(unsigned long address)

1 1

[U-Boot-Users] [PATCH] [resend] mips: Support to set CFG_HZ to 1000, consistent with other architectures
by Jason McMullan 31 May '08

31 May '08

All existing MIPS boards define CFG_HZ to be the number of ticks per second for the timebase. However, CFG_HZ should be a constant 1000 for all boards. This patch set CFG_HZ to be defined as 1000 for all MIPS boards, and uses the new configuration value CFG_MIPS_CLOCK to calculate the timebase. The MIPS time code now has a software maintained 64-bit counter, however get_timer() must be called every few seconds for this counter to be fully reliable. Per-board patches to board config files are included. Signed-off-by: Jason McMullan <mcmullan(a)netapp.com> --- include/configs/dbau1x00.h | 3 ++- include/configs/gth2.h | 3 ++- include/configs/incaip.h | 3 ++- include/configs/pb1x00.h | 3 ++- include/configs/purple.h | 3 ++- include/configs/qemu-mips.h | 3 ++- include/configs/tb0229.h | 3 ++- lib_mips/time.c | 36 +++++++++++++++++++++++++++++++++++- 8 files changed, 49 insertions(+), 8 deletions(-) diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index b2f606f..b4cc0c2 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -148,7 +148,8 @@ #error "Invalid CPU frequency - must be multiple of 12!" #endif -#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ +#define CFG_MIPS_CLOCK (CFG_MHZ * 1000000) +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/gth2.h b/include/configs/gth2.h index c2a50c1..656eccb 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -117,8 +117,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 #define CFG_MHZ 500 +#define CFG_MIPS_CLOCK (CFG_MHZ * 1000000) -#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 5ca00b3..c0e26f2 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -118,7 +118,8 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ (incaip_get_cpuclk() / 2) +#define CFG_MIPS_CLOCK (incaip_get_cpuclk() / 2) +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 810e0f0..5cb5069 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -81,7 +81,8 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */ +#define CFG_MIPS_CLOCK 396000000 +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/purple.h b/include/configs/purple.h index 1be4e05..9fe98f2 100644 --- a/include/configs/purple.h +++ b/include/configs/purple.h @@ -114,7 +114,8 @@ #define CFG_PROMPT "PURPLE # " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_HZ (CPU_CLOCK_RATE/2) +#define CFG_MIPS_CLOCK (CPU_CLOCK_RATE/2) +#define CFG_HZ 1000 #define CFG_MAXARGS 16 /* max number of command args*/ #define CFG_LOAD_ADDR 0x80500000 /* default load address */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index d6bcc8e..6889d7f 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -119,8 +119,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 #define CFG_MHZ 132 +#define CFG_MIPS_CLOCK (132 * 1000000) -#define CFG_HZ (CFG_MHZ * 1000000) +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h index dadf5d3..82206d5 100644 --- a/include/configs/tb0229.h +++ b/include/configs/tb0229.h @@ -122,7 +122,8 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ (CPU_TCLOCK_RATE/4) +#define CFG_MIPS_CLOCK (CPU_TCLOCK_RATE/4) +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 diff --git a/lib_mips/time.c b/lib_mips/time.c index cd8dc72..4807f1a 100644 --- a/lib_mips/time.c +++ b/lib_mips/time.c @@ -23,23 +23,57 @@ #include <common.h> +/* CFG_MIPS_CLOCK is the number of ticks per second of the MIPS C0 Clock timer. + * + * For most implementations, this is the same as the CPU speed in HZ + * divided by 2. Some embedded MIPS implementations may use a /4 + * or /1 divider, so see your CPU reference manual for specific details. + */ +#ifndef CFG_MIPS_CLOCK +#error CFG_MIPS_CLOCK must be set in the board configuration file +#endif +static struct { + uint32_t lo; + uint32_t hi; +} mips_ticks; /* Last number of ticks seen */ + +/* Input is in CFG_HZ ticks */ static inline void mips_compare_set(u32 v) { + v *= (CFG_MIPS_CLOCK / CFG_HZ); asm volatile ("mtc0 %0, $11" : : "r" (v)); } +/* Input is in CFG_HZ ticks */ static inline void mips_count_set(u32 v) { + v *= (CFG_MIPS_CLOCK / CFG_HZ); + mips_ticks.lo = v; + mips_ticks.hi = 0; asm volatile ("mtc0 %0, $9" : : "r" (v)); } +/* Returns CFG_HZ ticks + * + * NOTE: This must be called at least once every + * few seconds to be reliable. + */ static inline u32 mips_count_get(void) { u32 count; asm volatile ("mfc0 %0, $9" : "=r" (count) :); + + /* Handle 32-bit timer overflow */ + if (count < mips_ticks.lo) { + mips_ticks.hi++; + } + mips_ticks.lo = count; + count =(mips_ticks.lo / (CFG_MIPS_CLOCK / CFG_HZ)) + + (mips_ticks.hi * (0x100000000ULL / (CFG_MIPS_CLOCK / CFG_HZ))); + return count; } @@ -75,7 +109,7 @@ void udelay (unsigned long usec) ulong tmo; ulong start = get_timer(0); - tmo = usec * (CFG_HZ / 1000000); + tmo = usec * CFG_HZ / 1000; while ((ulong)((mips_count_get() - start)) < tmo) /*NOP*/; } -- 1.5.4.3

5 13

[U-Boot-Users] [PATCH] mips: Add an 'include/asm/errno.h', like all other architectures
by Jason McMullan 31 May '08

31 May '08

All other u-boot architectures have an include/asm/errno.h, so this change adds it to the mips include/asm-mips headers also. Stolen from Linux 2.6.25. Signed-off-by: Jason McMullan <mcmullan(a)netapp.com> --- include/asm-mips/errno.h | 143 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 143 insertions(+), 0 deletions(-) create mode 100644 include/asm-mips/errno.h diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h new file mode 100644 index 0000000..1665a63 --- /dev/null +++ b/include/asm-mips/errno.h @@ -0,0 +1,143 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle + */ +#ifndef _ASM_MIPS_ERRNO_H +#define _ASM_MIPS_ERRNO_H + +/* + * These first 34 error codes are from Linux 2.6, <asm-generic/errno-base.h> + */ +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +/* + * These error numbers are intended to be MIPS ABI compatible + */ +#define ENOMSG 35 /* No message of desired type */ +#define EIDRM 36 /* Identifier removed */ +#define ECHRNG 37 /* Channel number out of range */ +#define EL2NSYNC 38 /* Level 2 not synchronized */ +#define EL3HLT 39 /* Level 3 halted */ +#define EL3RST 40 /* Level 3 reset */ +#define ELNRNG 41 /* Link number out of range */ +#define EUNATCH 42 /* Protocol driver not attached */ +#define ENOCSI 43 /* No CSI structure available */ +#define EL2HLT 44 /* Level 2 halted */ +#define EDEADLK 45 /* Resource deadlock would occur */ +#define ENOLCK 46 /* No record locks available */ +#define EBADE 50 /* Invalid exchange */ +#define EBADR 51 /* Invalid request descriptor */ +#define EXFULL 52 /* Exchange full */ +#define ENOANO 53 /* No anode */ +#define EBADRQC 54 /* Invalid request code */ +#define EBADSLT 55 /* Invalid slot */ +#define EDEADLOCK 56 /* File locking deadlock error */ +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EDOTDOT 73 /* RFS specific error */ +#define EMULTIHOP 74 /* Multihop attempted */ +#define EBADMSG 77 /* Not a data message */ +#define ENAMETOOLONG 78 /* File name too long */ +#define EOVERFLOW 79 /* Value too large for defined data type */ +#define ENOTUNIQ 80 /* Name not unique on network */ +#define EBADFD 81 /* File descriptor in bad state */ +#define EREMCHG 82 /* Remote address changed */ +#define ELIBACC 83 /* Can not access a needed shared library */ +#define ELIBBAD 84 /* Accessing a corrupted shared library */ +#define ELIBSCN 85 /* .lib section in a.out corrupted */ +#define ELIBMAX 86 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 87 /* Cannot exec a shared library directly */ +#define EILSEQ 88 /* Illegal byte sequence */ +#define ENOSYS 89 /* Function not implemented */ +#define ELOOP 90 /* Too many symbolic links encountered */ +#define ERESTART 91 /* Interrupted system call should be restarted */ +#define ESTRPIPE 92 /* Streams pipe error */ +#define ENOTEMPTY 93 /* Directory not empty */ +#define EUSERS 94 /* Too many users */ +#define ENOTSOCK 95 /* Socket operation on non-socket */ +#define EDESTADDRREQ 96 /* Destination address required */ +#define EMSGSIZE 97 /* Message too long */ +#define EPROTOTYPE 98 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 99 /* Protocol not available */ +#define EPROTONOSUPPORT 120 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 121 /* Socket type not supported */ +#define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 123 /* Protocol family not supported */ +#define EAFNOSUPPORT 124 /* Address family not supported by protocol */ +#define EADDRINUSE 125 /* Address already in use */ +#define EADDRNOTAVAIL 126 /* Cannot assign requested address */ +#define ENETDOWN 127 /* Network is down */ +#define ENETUNREACH 128 /* Network is unreachable */ +#define ENETRESET 129 /* Network dropped connection because of reset */ +#define ECONNABORTED 130 /* Software caused connection abort */ +#define ECONNRESET 131 /* Connection reset by peer */ +#define ENOBUFS 132 /* No buffer space available */ +#define EISCONN 133 /* Transport endpoint is already connected */ +#define ENOTCONN 134 /* Transport endpoint is not connected */ +#define EUCLEAN 135 /* Structure needs cleaning */ +#define ENOTNAM 137 /* Not a XENIX named type file */ +#define ENAVAIL 138 /* No XENIX semaphores available */ +#define EISNAM 139 /* Is a named type file */ +#define EREMOTEIO 140 /* Remote I/O error */ +#define EINIT 141 /* Reserved */ +#define EREMDEV 142 /* Error 142 */ +#define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 144 /* Too many references: cannot splice */ +#define ETIMEDOUT 145 /* Connection timed out */ +#define ECONNREFUSED 146 /* Connection refused */ +#define EHOSTDOWN 147 /* Host is down */ +#define EHOSTUNREACH 148 /* No route to host */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define EALREADY 149 /* Operation already in progress */ +#define EINPROGRESS 150 /* Operation now in progress */ +#define ESTALE 151 /* Stale NFS file handle */ +#define ECANCELED 158 /* AIO operation canceled */ + +#endif /* _ASM_MIPS_ERRNO_H */ -- 1.5.4.3

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