April 2008 - U-Boot

Re: [U-Boot-Users] drivers MMCplus for at91sam9x
by Andy Fleming 22 Apr '08

22 Apr '08

On Tue, Apr 15, 2008 at 5:18 AM, Pierre Savary <pierre.savary(a)kerlink.fr> wrote: > Then my MMC 4GB works with my Linux kernel but if I can't load my kernel > (located on the first part of this MMC) ... it's not really interesting :( > > So, somebody does already use MMC v4 with U-boot??? I've got one that works. However, I don't have a 4GB MMC card with v4. I thought I did, but it turned out the card just takes advantage of the fact that older versions can address 4GB, even though the spec says 2GB is the max. However, I'm fairly confident in the code (it's been tested in simulated environments, and reflects what the Linux code does). I'm currently working on bringing it forward to the top of tree (I started it before drivers/ got rearranged). I'm actually hoping to generalize it some so we can share it between all MMC/SD users. Andy

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[U-Boot-Users] [PATCH] 4xx: Update CPU strapping for PMC440 boards
by Matthias Fuchs 22 Apr '08

22 Apr '08

This patch removes the temporary 'test' strapping option of the sbe command. The '667' strapping option now uses a PLB/PCI divider of 3. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- board/esd/pmc440/cmd_pmc440.c | 13 +------------ 1 files changed, 1 insertions(+), 12 deletions(-) diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index e9e9746..ef54e67 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -293,20 +293,9 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] sdsdp[2]=0x40082350; sdsdp[3]=0x0d050000; } else if (!strcmp(argv[1], "667")) { - /* PLB=133MHz, PLB/PCI=4 */ + /* PLB=133MHz, PLB/PCI=3 */ printf("Bootstrapping for 667MHz\n"); sdsdp[0]=0x8778a256; - sdsdp[1]=0x0947a030; - sdsdp[2]=0x40082350; - sdsdp[3]=0x0d050000; - } else if (!strcmp(argv[1], "test")) { - /* - * TODO: this will replace the 667 MHz config above. - * But it needs some more testing on a real 667 MHz CPU. - */ - printf("Bootstrapping for test" - " (667MHz PLB=133PLB PLB/PCI=3)\n"); - sdsdp[0]=0x8778a256; sdsdp[1]=0x095fa030; sdsdp[2]=0x40082350; sdsdp[3]=0x0d050000; -- 1.5.3

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[U-Boot-Users] [PATCH 5/5] 4xx: Remove unused APC405 strataflash driver
by Matthias Fuchs 22 Apr '08

22 Apr '08

The APC405 board support has been migrated to use the common CFI flash driver. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- board/esd/apc405/strataflash.c | 789 ---------------------------------------- 1 files changed, 0 insertions(+), 789 deletions(-) delete mode 100644 board/esd/apc405/strataflash.c diff --git a/board/esd/apc405/strataflash.c b/board/esd/apc405/strataflash.c deleted file mode 100644 index ad7a71d..0000000 --- a/board/esd/apc405/strataflash.c +++ /dev/null @@ -1,789 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp(a)seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#else - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - - CFG_MONITOR_LEN, - - 1, &flash_info[1]); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO - int k; - int size; - int erased; - volatile unsigned long *flash; - - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) - { - if (*flash++ != 0xffffffff) - { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - /* print empty and read-only info */ - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ -- 1.5.3

2 1

[U-Boot-Users] [PATCH 4/5] 4xx: Update APC405 configuration
by Matthias Fuchs 22 Apr '08

22 Apr '08

- enable esd's auto_update mechanism - support alternative flash layout on rev. 1.8 boards - update default environment - use common CFI flash driver - coding style cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- include/configs/APC405.h | 346 ++++++++++++++++++++++++++-------------------- 1 files changed, 193 insertions(+), 153 deletions(-) diff --git a/include/configs/APC405.h b/include/configs/APC405.h index f6495e4..5b04888 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -1,4 +1,7 @@ /* + * (C) Copyright 2005-2008 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs(a)esd-electronics.com + * * (C) Copyright 2001-2004 * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com * @@ -24,7 +27,6 @@ /* * board/config.h - configuration options, board specific */ - #ifndef __CONFIG_H #define __CONFIG_H @@ -32,42 +34,78 @@ * High Level Configuration Options * (easy to change) */ - #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_APCG405 1 /* ...on a APC405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_BOARD_EARLY_INIT_R 1 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000 ffca0000" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000" -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#define CFG_USB_LOAD_COMMAND "fatload usb 0 200000 pImage;" \ + "fatload usb 0 300000 pImage.initrd" +#define CFG_USB_SELF_COMMAND "usb start;run usb_load;usb stop;" \ + "run ramargs addip addcon usbargs;" \ + "bootm 200000 300000" +#define CFG_USB_ARGS "setenv bootargs $(bootargs) usbboot=1" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=abg405\0" \ + "bd_type=abg405\0" \ + "serial#=AA0000\0" \ + "kernel_addr=fe000000\0" \ + "ramdisk_addr=fe100000\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname)::off panic=1\0" \ + "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)" \ + " $(optargs)\0" \ + "flash_self=run ramargs addip addcon;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;" \ + "bootm\0" \ + "rootpath=/tftpboot/abg405/target_root\0" \ + "img=/tftpboot/abg405/pImage\0" \ + "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0" \ + "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ + "cp.b 100000 fff80000 80000\0" \ + "ipaddr=10.0.111.111\0" \ + "netmask=255.255.0.0\0" \ + "serverip=10.0.0.190\0" \ + "splashimage=ffe80000\0" \ + "usb_load="CFG_USB_LOAD_COMMAND"\0" \ + "usb_self="CFG_USB_SELF_COMMAND"\0" \ + "usbargs="CFG_USB_ARGS"\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self;run usb_self" + +#define CONFIG_ETHADDR 00:02:27:8e:00:00 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - /* * BOOTP options */ @@ -76,7 +114,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -93,95 +130,86 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_EEPROM +#define CONFIG_CMD_USB +#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_AUTO_UPDATE 1 /* autoupdate via CF or USB */ -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#if 1 /* test-only */ #define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ -#else -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#endif /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ /* Only interrupt boot if space is pressed */ /* If a long serial cable is connected but */ /* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" -#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#undef CONFIG_AUTOBOOT_DELAY_STR #define CONFIG_AUTOBOOT_STOP_STR " " -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ -/*----------------------------------------------------------------------- +/* * PCI stuff - *----------------------------------------------------------------------- */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ +#define CONFIG_PCI_SKIP_HOST_BRIDGE 1 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ @@ -192,119 +220,123 @@ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -/*----------------------------------------------------------------------- +/* * IDE/ATA stuff - *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS) /* max. 1 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ -/*----------------------------------------------------------------------- +/* * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_MONITOR_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */ +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Init. Memory map for Linux */ -/*----------------------------------------------------------------------- +/* * FLASH organization */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BASE 0xFE000000 /* test-only...*/ -#define CFG_FLASH_INCREMENT 0x01000000 /* test-only */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#ifndef __ASSEMBLY__ +extern int flash_banks; +#endif -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CFG_MAX_FLASH_BANKS flash_banks /* max num of flash banks */ + /* updated in board_early_init_r */ +#define CFG_MAX_FLASH_BANKS_DETECT 2 +#define CFG_FLASH_QUIET_TEST 1 +#define CFG_FLASH_INCREMENT 0x01000000 +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#define CFG_FLASH_AUTOPROTECT_LIST { \ + {0xfe000000, 0x500000}, \ + {0xffe80000, 0x180000} \ + } +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_BANKS_LIST { \ + CFG_FLASH_BASE, \ + CFG_FLASH_BASE + CFG_FLASH_INCREMENT \ + } +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/*----------------------------------------------------------------------- +/* * Environment Variable setup */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the */ + /* beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ +#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting vendor vars */ -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ -/*----------------------------------------------------------------------- +/* * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- +/* * External Bus Controller (EBC) Setup */ -#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define PS2_BA 0xF0000600 /* PS/2 Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ -#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */ -#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */ -#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */ -#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */ -#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ - -#define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ +#define FLASH0_BA (CFG_FLASH_BASE + CFG_FLASH_INCREMENT) /* FLASH 0 BA */ +#define FLASH1_BA CFG_FLASH_BASE /* FLASH 1 Base Address */ +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define DUART0_BA 0xF0000400 /* DUART Base Address */ +#define DUART1_BA 0xF0000408 /* DUART Base Address */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ +#define PS2_BA 0xF0000600 /* PS/2 Base Address */ +#define CF_BA 0xF0100000 /* CompactFlash Base Address */ +#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */ +#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */ +#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */ +#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */ +#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ + +#define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ #define CFG_EBC_PB0AP 0x92015480 #define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ +#define CFG_EBC_PB0AP_HWREV8 CFG_EBC_PB0AP +#define CFG_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */ -/* Memory Bank 1 (Flash Bank 1) initialization */ +/* Memory Bank 1 (Flash Bank 1) initialization */ #define CFG_EBC_PB1AP 0x92015480 #define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ @@ -328,7 +360,7 @@ #define CFG_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ #define CFG_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/ -/*----------------------------------------------------------------------- +/* * FPGA stuff */ @@ -351,48 +383,56 @@ #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ -/*----------------------------------------------------------------------- +/* * LCD Setup */ +#define CFG_LCD_BIG_MEM (VGA_BA + 0x200000) /* S1D13806 Mem Base */ +#define CFG_LCD_BIG_REG VGA_BA /* S1D13806 Reg Base */ -#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ -#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ - -#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */ +#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */ /* Image information... */ -#define CONFIG_LCD_USED CONFIG_LCD_BIG -#define CFG_LCD_HEADER_NAME "../common/s1d13806_640_480_16bpp.h" -#define CFG_LCD_LOGO_NAME "logo_640_480_24bpp.c" +#define CONFIG_LCD_USED CONFIG_LCD_BIG -#define CFG_LCD_MEM CFG_LCD_BIG_MEM -#define CFG_LCD_REG CFG_LCD_BIG_REG +#define CFG_LCD_MEM CFG_LCD_BIG_MEM +#define CFG_LCD_REG CFG_LCD_BIG_REG #define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20) -/*----------------------------------------------------------------------- +/* * Definitions for initial stack pointer and data area (in data cache) */ /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 +#define CFG_TEMP_STACK_OCM 1 /* On Chip Memory location */ #define CFG_OCM_DATA_ADDR 0xF8000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* reserved bytes for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /* * Internal Definitions * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#endif /* __CONFIG_H */ +/* + * PCI OHCI controller + */ +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_PCI_OHCI 1 +#define CFG_OHCI_SWAP_REG_ACCESS 1 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 +#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" +#define CONFIG_USB_STORAGE 1 +#define CFG_USB_OHCI_BOARD_INIT 1 + +#endif /* __CONFIG_H */ -- 1.5.3

2 1

[U-Boot-Users] [PATCH 3/5] 4xx: Update APC405 board support
by Matthias Fuchs 22 Apr '08

22 Apr '08

- enable esd's auto_update mechanism - fix LCD support on latest hardware revision (uses other LCD controller) - support alternative flash layout on rev. 1.8 boards - coding style cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- board/esd/apc405/Makefile | 4 +- board/esd/apc405/apc405.c | 360 ++++++++++++++++++++++++++++++--------------- 2 files changed, 241 insertions(+), 123 deletions(-) diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile index 024997e..c57cd6b 100644 --- a/board/esd/apc405/Makefile +++ b/board/esd/apc405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o strataflash.o ../common/misc.o +COBJS = $(BOARD).o \ + ../common/misc.o \ + ../common/auto_update.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 078df00..b663184 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2005-2008 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs(a)esd-electronics.com + * * (C) Copyright 2001-2003 * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com * @@ -23,17 +26,22 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> #include <malloc.h> +#include <flash.h> +#include <asm/4xx_pci.h> +#include <pci.h> DECLARE_GLOBAL_DATA_PTR; -#if 0 -#define FPGA_DEBUG -#endif +#undef FPGA_DEBUG extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern void lxt971_no_sleep(void); +extern ulong flash_get_size (ulong base, int banknum); + +int flash_banks = CFG_MAX_FLASH_BANKS_DETECT; /* fpga configuration data - gzip compressed and generated by bin2c */ const unsigned char fpgadata[] = @@ -46,82 +54,94 @@ const unsigned char fpgadata[] = */ #include "../common/fpga.c" - /* Prototypes */ int gunzip(void *, int, unsigned char *, unsigned long *); - #ifdef CONFIG_LCD_USED /* logo bitmap data - gzip compressed and generated by bin2c */ unsigned char logo_bmp[] = { -#include CFG_LCD_LOGO_NAME +#include "logo_640_480_24bpp.c" }; /* * include common lcd code (for esd boards) */ #include "../common/lcd.c" - -#include CFG_LCD_HEADER_NAME +#include "../common/s1d13505_640_480_16bpp.h" +#include "../common/s1d13806_640_480_16bpp.h" #endif /* CONFIG_LCD_USED */ +/* + * include common auto-update code (for esd boards) + */ +#include "../common/auto_update.h" + +au_image_t au_image[] = { + {"preinst.img", 0, -1, AU_SCRIPT}, + {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT}, + {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT}, + {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT}, + {"work.img", 0xfe500000, 0x01400000, AU_NOR}, + {"data.img", 0xff900000, 0x00580000, AU_NOR}, + {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT}, + {"postinst.img", 0, 0, AU_SCRIPT}, +}; + +int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); int board_revision(void) { unsigned long cntrl0Reg; - unsigned long value; + volatile unsigned long value; /* * Get version of APC405 board from GPIO's */ - /* - * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) - */ + /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */ cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ + mtdcr(cntrl0, cntrl0Reg | 0x03800000); + out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000); + + /* wait some time before reading input */ + udelay(1000); + /* get config bits */ + value = in_be32((void*)GPIO0_IR) & 0x001c0000; /* * Restore GPIO settings */ mtdcr(cntrl0, cntrl0Reg); switch (value) { - case 0x00180000: - /* CS2==1 && CS3==1 -> version <= 1.2 */ + case 0x001c0000: + /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */ return 2; - case 0x00080000: - /* CS2==0 && CS3==1 -> version 1.3 */ + case 0x000c0000: + /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */ return 3; -#if 0 /* not yet manufactured ! */ - case 0x00100000: - /* CS2==1 && CS3==0 -> version 1.4 */ - return 4; - case 0x00000000: - /* CS2==0 && CS3==0 -> version 1.5 */ - return 5; -#endif + case 0x00180000: + /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */ + return 6; + case 0x00140000: + /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */ + return 8; default: /* should not be reached! */ return 0; } } - int board_early_init_f (void) { /* - * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) + * First pull fpga-prg pin low, to disable fpga logic */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ - out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ - out32(GPIO0_OR, 0); /* pull prg low */ + out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ + out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out_be32((void*)GPIO0_OR, 0); /* pull prg low */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -140,48 +160,61 @@ int board_early_init_f (void) mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicvcr, 0x00000001); /* set vect base=0 */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + * EBC Configuration Register: set ready timeout to 512 ebc-clks + */ + mtebc(epcr, 0xa8400000); /* ebc always driven */ + + /* + * New boards have a single 32MB flash connected to CS0 + * instead of two 16MB flashes on CS0+1. */ -#if 1 /* test-only */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ -#else - mtebc (epcr, 0x28400000); /* ebc in high-z */ -#endif + if (board_revision() >= 8) { + /* disable CS1 */ + mtebc(pb1ap, 0); + mtebc(pb1cr, 0); + + /* resize CS0 to 32MB */ + mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8); + mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8); + } return 0; } - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) +int board_early_init_r(void) { - return 0; /* dummy implementation */ + if (gd->board_type >= 8) + flash_banks = 1; + + return 0; } +#define FUJI_BASE 0xf0100200 +#define LCDBL_PWM 0xa0 +#define LCDBL_PWMMIN 0xa4 +#define LCDBL_PWMMAX 0xa8 -int misc_init_r (void) +int misc_init_r(void) { - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - volatile unsigned short *fpga_ctrl2 = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); - volatile unsigned char *duart0_mcr = - (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = - (unsigned char *)((ulong)DUART1_BA + 4); - volatile unsigned short *fuji_lcdbl_pwm = - (unsigned short *)((ulong)0xf0100200 + 0xa0); + u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); + u8 *duart0_mcr = (u8 *)(DUART0_BA + 4); + u8 *duart1_mcr = (u8 *)(DUART1_BA + 4); unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; unsigned long cntrl0Reg; + char *str; + uchar *logo_addr; + ulong logo_size; + ushort minb, maxb; + int result; /* * Setup GPIO pins (CS6+CS7 as GPIO) @@ -190,9 +223,9 @@ int misc_init_r (void) mtdcr(cntrl0, cntrl0Reg | 0x00300000); dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); + if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf("GUNZIP ERROR - must RESET board to recover\n"); + do_reset(NULL, 0, 0, NULL); } status = fpga_boot(dst, len); @@ -200,31 +233,34 @@ int misc_init_r (void) printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + printf("(Timeout: " + "INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + printf("(Timeout: " + "INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); + printf("(Timeout: " + "DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; + index += len + 3; } - putc ('\n'); + putc('\n'); /* delayed reboot */ - for (i=20; i>0; i--) { + for (i = 20; i > 0; i--) { printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) + for (index = 0; index < 1000; index++) udelay(1000); } - putc ('\n'); + putc('\n'); do_reset(NULL, 0, 0, NULL); } @@ -235,12 +271,12 @@ int misc_init_r (void) /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; + printf("%s ", &(dst[index + 1])); + index += len + 3; } - putc ('\n'); + putc('\n'); free(dst); @@ -255,51 +291,117 @@ int misc_init_r (void) /* * Write board revision in FPGA */ - *fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f); + out_be16(fpga_ctrl2, + (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f)); /* * Enable power on PS/2 interface (with reset) */ - *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET; + out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET); for (i=0;i<100;i++) udelay(1000); udelay(1000); - *fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET; + out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET); /* * Enable interrupts in exar duart mcr[3] */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; + out_8(duart0_mcr, 0x08); + out_8(duart1_mcr, 0x08); /* * Init lcd interface and display logo */ - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), - logo_bmp, sizeof(logo_bmp)); + str = getenv("splashimage"); + if (str) { + logo_addr = (uchar *)simple_strtoul(str, NULL, 16); + logo_size = CFG_VIDEO_LOGO_MAX_SIZE; + } else { + logo_addr = logo_bmp; + logo_size = sizeof(logo_bmp); + } + + if (gd->board_type >= 6) { + result = lcd_init((uchar *)CFG_LCD_BIG_REG, + (uchar *)CFG_LCD_BIG_MEM, + regs_13505_640_480_16bpp, + sizeof(regs_13505_640_480_16bpp) / + sizeof(regs_13505_640_480_16bpp[0]), + logo_addr, logo_size); + if (result && str) { + /* retry with internal image */ + logo_addr = logo_bmp; + logo_size = sizeof(logo_bmp); + lcd_init((uchar *)CFG_LCD_BIG_REG, + (uchar *)CFG_LCD_BIG_MEM, + regs_13505_640_480_16bpp, + sizeof(regs_13505_640_480_16bpp) / + sizeof(regs_13505_640_480_16bpp[0]), + logo_addr, logo_size); + } + } else { + result = lcd_init((uchar *)CFG_LCD_BIG_REG, + (uchar *)CFG_LCD_BIG_MEM, + regs_13806_640_480_16bpp, + sizeof(regs_13806_640_480_16bpp) / + sizeof(regs_13806_640_480_16bpp[0]), + logo_addr, logo_size); + if (result && str) { + /* retry with internal image */ + logo_addr = logo_bmp; + logo_size = sizeof(logo_bmp); + lcd_init((uchar *)CFG_LCD_BIG_REG, + (uchar *)CFG_LCD_BIG_MEM, + regs_13806_640_480_16bpp, + sizeof(regs_13806_640_480_16bpp) / + sizeof(regs_13806_640_480_16bpp[0]), + logo_addr, logo_size); + } + } /* * Reset microcontroller and setup backlight PWM controller */ - *fpga_mode |= 0x0014; + out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014); for (i=0;i<10;i++) udelay(1000); - *fpga_mode |= 0x001c; - *fuji_lcdbl_pwm = 0x00ff; + out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c); + + minb = 0; + maxb = 0xff; + str = getenv("lcdbl"); + if (str) { + minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff; + if (str && (*str=',')) { + str++; + maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff; + } else + minb = 0; + + out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb); + out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb); + + printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb); + } + out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff); + + if (getenv("usb_self") == NULL) { + setenv("usb_load", CFG_USB_LOAD_COMMAND); + setenv("usbargs", CFG_USB_ARGS); + setenv("bootcmd", CONFIG_BOOTCOMMAND); + setenv("usb_self", CFG_USB_SELF_COMMAND); + saveenv(); + } return (0); } - /* * Check Board Identity: */ - int checkboard (void) { - unsigned char str[64]; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); puts ("Board: "); @@ -311,18 +413,11 @@ int checkboard (void) } gd->board_type = board_revision(); - printf(", Rev 1.%ld\n", gd->board_type); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); + printf(", Rev. 1.%ld\n", gd->board_type); return 0; } -/* ------------------------------------------------------------------------- */ - long int initdram (int board_type) { unsigned long val; @@ -330,43 +425,64 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -/* ------------------------------------------------------------------------- */ - -int testdram (void) +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); + u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - return (0); + /* + * Assert or deassert CompactFlash Reset Pin + */ + if (on) { + out_be16(fpga_mode, + in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET); + } else { + out_be16(fpga_mode, + in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET); + } } +#endif /* CONFIG_IDE_RESET */ -/* ------------------------------------------------------------------------- */ +void reset_phy(void) +{ + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +} -#ifdef CONFIG_IDE_RESET +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) +int usb_board_init(void) +{ + return 0; +} -void ide_set_reset(int on) +int usb_board_stop(void) { - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + unsigned short tmp; + int i; /* - * Assert or deassert CompactFlash Reset Pin + * reset PCI bus + * This is required to make some very old Linux OHCI driver + * work after U-Boot has used the OHCI controller. */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; - } -} + pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp); + pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000)); -#endif /* CONFIG_IDE_RESET */ + for (i = 0; i < 100; i++) + udelay(1000); -/* ------------------------------------------------------------------------- */ + pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp); + return 0; +} + +int usb_board_init_fail(void) +{ + usb_board_stop(); + return 0; +} +#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ -- 1.5.3

2 1

[U-Boot-Users] [PATCH 2/5] 4xx: update esd's common auto_update code for 405 boards
by Matthias Fuchs 22 Apr '08

22 Apr '08

- Coding style cleanup (long lines) - improve handling of protected flash regions - remove dead code Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- board/esd/common/auto_update.c | 208 ++++++++++++++++++--------------------- board/esd/common/auto_update.h | 15 ++- 2 files changed, 106 insertions(+), 117 deletions(-) diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 1bf81c6..7e6eea0 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -44,29 +44,16 @@ extern au_image_t au_image[]; extern int N_AU_IMAGES; -#define AU_DEBUG -#undef AU_DEBUG - -#undef debug -#ifdef AU_DEBUG -#define debug(fmt,args...) printf (fmt ,##args) -#else -#define debug(fmt,args...) -#endif /* AU_DEBUG */ - - -#define LOAD_ADDR ((unsigned char *)0x100000) /* where to load files into memory */ -#define MAX_LOADSZ 0x1e00000 +/* where to load files into memory */ +#define LOAD_ADDR ((unsigned char *)0x100000) +#define MAX_LOADSZ 0x1c00000 /* externals */ extern int fat_register_device(block_dev_desc_t *, int); extern int file_fat_detectfs(void); extern long file_fat_read(const char *, void *, unsigned long); -long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, int dols); -#ifdef CONFIG_VFD -extern int trab_vfd (ulong); -extern int transfer_pic(unsigned char, unsigned char *, int, int); -#endif +long do_fat_read (const char *filename, void *buffer, + unsigned long maxsize, int dols); extern int flash_sect_erase(ulong, ulong); extern int flash_sect_protect (int, ulong, ulong); extern int flash_write (char *, ulong, ulong); @@ -78,14 +65,15 @@ extern int flash_write (char *, ulong, ulong); #define NANDRW_JFFS2 0x02 #define NANDRW_JFFS2_SKIP 0x04 extern struct nand_chip nand_dev_desc[]; -extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, - size_t * retlen, u_char * buf); -extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); +extern int nand_legacy_rw(struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf); +extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, + size_t len, int clean); #endif extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; - int au_check_cksum_valid(int i, long nbytes) { image_header_t *hdr; @@ -117,7 +105,6 @@ int au_check_cksum_valid(int i, long nbytes) return 0; } - int au_check_header_valid(int i, long nbytes) { image_header_t *hdr; @@ -132,20 +119,11 @@ int au_check_header_valid(int i, long nbytes) #endif /* check the easy ones first */ -#undef CHECK_VALID_DEBUG -#ifdef CHECK_VALID_DEBUG - printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC); - printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_PPC); - printf("size %#x %#lx ", image_get_data_size (hdr), nbytes); - printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL); -#endif - if (nbytes < image_get_header_size ()) - { + if (nbytes < image_get_header_size ()) { printf ("Image %s bad header SIZE\n", au_image[i].name); return -1; } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) - { + if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) { printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name); return -1; } @@ -155,11 +133,13 @@ int au_check_header_valid(int i, long nbytes) } /* check the type - could do this all in one gigantic if() */ - if ((au_image[i].type == AU_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) { + if (((au_image[i].type & AU_TYPEMASK) == AU_FIRMWARE) && + !image_check_type (hdr, IH_TYPE_FIRMWARE)) { printf ("Image %s wrong type\n", au_image[i].name); return -1; } - if ((au_image[i].type == AU_SCRIPT) && !image_check_type (hdr, IH_TYPE_SCRIPT)) { + if (((au_image[i].type & AU_TYPEMASK) == AU_SCRIPT) && + !image_check_type (hdr, IH_TYPE_SCRIPT)) { printf ("Image %s wrong type\n", au_image[i].name); return -1; } @@ -167,22 +147,9 @@ int au_check_header_valid(int i, long nbytes) /* recycle checksum */ checksum = image_get_data_size (hdr); -#if 0 /* test-only */ - /* for kernel and app the image header must also fit into flash */ - if (idx != IDX_DISK) - checksum += image_get_header_size (); - /* check the size does not exceed space in flash. HUSH scripts */ - /* all have ausize[] set to 0 */ - if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { - printf ("Image %s is bigger than FLASH\n", au_image[i].name); - return -1; - } -#endif - return 0; } - int au_do_update(int i, long sz) { image_header_t *hdr; @@ -203,7 +170,7 @@ int au_do_update(int i, long sz) } #endif - switch (au_image[i].type) { + switch (au_image[i].type & AU_TYPEMASK) { case AU_SCRIPT: printf("Executing script %s\n", au_image[i].name); @@ -243,38 +210,43 @@ int au_do_update(int i, long sz) */ if (au_image[i].type == AU_FIRMWARE) { char *orig = (char*)start; - char *new = (char *)((char *)hdr + image_get_header_size ()); + char *new = (char *)((char *)hdr + + image_get_header_size ()); nbytes = image_get_data_size (hdr); - while(--nbytes) { + while (--nbytes) { if (*orig++ != *new++) { break; } } if (!nbytes) { - printf("Skipping firmware update - images are identical\n"); + printf ("Skipping firmware update - " + "images are identical\n"); break; } } /* unprotect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (au_image[i].type == AU_FIRMWARE) { - flash_sect_protect(0, start, end); + if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) || + (au_image[i].type == AU_FIRMWARE)) { + flash_sect_protect (0, start, end); } /* * erase the address range. */ if (au_image[i].type != AU_NAND) { - printf("Updating NOR FLASH with image %s\n", au_image[i].name); + printf ("Updating NOR FLASH with image %s\n", + au_image[i].name); debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase(start, end); + flash_sect_erase (start, end); } else { #if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) - printf("Updating NAND FLASH with image %s\n", au_image[i].name); + printf ("Updating NAND FLASH with image %s\n", + au_image[i].name); debug ("nand_legacy_erase(%lx, %lx);\n", start, end); - rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0); + rc = nand_legacy_erase (nand_dev_desc, start, + end - start + 1, 0); debug ("nand_legacy_erase returned %x\n", rc); #endif } @@ -296,20 +268,26 @@ int au_do_update(int i, long sz) * copy the data from RAM to FLASH */ if (au_image[i].type != AU_NAND) { - debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write((char *)addr, start, nbytes); + debug ("flash_write(%p, %lx, %x)\n", + addr, start, nbytes); + rc = flash_write ((char *)addr, start, + (nbytes + 1) & ~1); } else { #if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) - debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes); - rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, - start, nbytes, (size_t *)&total, (uchar *)addr); - debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); + debug ("nand_legacy_rw(%p, %lx, %x)\n", + addr, start, nbytes); + rc = nand_legacy_rw (nand_dev_desc, + NANDRW_WRITE | NANDRW_JFFS2, + start, nbytes, (size_t *)&total, + (uchar *)addr); + debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", + rc, total, nbytes); #else rc = -1; #endif } if (rc != 0) { - printf("Flashing failed due to error %d\n", rc); + printf ("Flashing failed due to error %d\n", rc); return -1; } @@ -317,23 +295,30 @@ int au_do_update(int i, long sz) * check the dcrc of the copy */ if (au_image[i].type != AU_NAND) { - rc = crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)); + rc = crc32 (0, (uchar *)(start + off), + image_get_data_size (hdr)); } else { #if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) - rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, - start, nbytes, (size_t *)&total, (uchar *)addr); - rc = crc32 (0, (uchar *)(addr + off), image_get_data_size (hdr)); + rc = nand_legacy_rw (nand_dev_desc, + NANDRW_READ | NANDRW_JFFS2 | + NANDRW_JFFS2_SKIP, + start, nbytes, (size_t *)&total, + (uchar *)addr); + rc = crc32 (0, (uchar *)(addr + off), + image_get_data_size (hdr)); #endif } if (rc != image_get_dcrc (hdr)) { - printf ("Image %s Bad Data Checksum After COPY\n", au_image[i].name); + printf ("Image %s Bad Data Checksum After COPY\n", + au_image[i].name); return -1; } /* protect the address range */ /* this assumes that ONLY the firmware is protected! */ - if (au_image[i].type == AU_FIRMWARE) { - flash_sect_protect(1, start, end); + if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) || + (au_image[i].type == AU_FIRMWARE)) { + flash_sect_protect (1, start, end); } break; @@ -345,7 +330,6 @@ int au_do_update(int i, long sz) return 0; } - static void process_macros (const char *input, char *output) { char c, prev; @@ -359,16 +343,17 @@ static void process_macros (const char *input, char *output) #ifdef DEBUG_PARSER char *output_start = output; - printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen(input), input); + printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", + strlen(input), input); #endif - prev = '\0'; /* previous character */ + prev = '\0'; /* previous character */ while (inputcnt && outputcnt) { c = *input++; inputcnt--; - if (state!=3) { + if (state != 3) { /* remove one level of escape characters */ if ((c == '\\') && (prev != '\\')) { if (inputcnt-- == 0) @@ -379,7 +364,7 @@ static void process_macros (const char *input, char *output) } switch (state) { - case 0: /* Waiting for (unescaped) $ */ + case 0: /* Waiting for (unescaped) $ */ if ((c == '\'') && (prev != '\\')) { state = 3; break; @@ -391,7 +376,7 @@ static void process_macros (const char *input, char *output) outputcnt--; } break; - case 1: /* Waiting for ( */ + case 1: /* Waiting for ( */ if (c == '(' || c == '{') { state++; varname_start = input; @@ -410,7 +395,8 @@ static void process_macros (const char *input, char *output) if (c == ')' || c == '}') { int i; char envname[CFG_CBSIZE], *envval; - int envcnt = input-varname_start-1; /* Varname # of chars */ + /* Varname # of chars */ + int envcnt = input - varname_start - 1; /* Get the varname */ for (i = 0; i < envcnt; i++) { @@ -448,11 +434,10 @@ static void process_macros (const char *input, char *output) #ifdef DEBUG_PARSER printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", - strlen(output_start), output_start); + strlen (output_start), output_start); #endif } - /* * this is called from board_init() after the hardware has been set up * and is usable. That seems like a good time to do this. @@ -460,84 +445,84 @@ static void process_macros (const char *input, char *output) */ int do_auto_update(void) { - block_dev_desc_t *stor_dev; + block_dev_desc_t *stor_dev = NULL; long sz; int i, res, cnt, old_ctrlc, got_ctrlc; char buffer[32]; char str[80]; + int n; - /* - * Check whether a CompactFlash is inserted - */ - if (ide_dev_desc[0].type == DEV_TYPE_UNKNOWN) { - return -1; /* no disk detected! */ + if (ide_dev_desc[0].type != DEV_TYPE_UNKNOWN) { + stor_dev = get_dev ("ide", 0); + if (stor_dev == NULL) { + debug ("ide: unknown device\n"); + return -1; + } } - /* check whether it has a partition table */ - stor_dev = get_dev("ide", 0); - if (stor_dev == NULL) { - debug ("Uknown device type\n"); - return -1; - } - if (fat_register_device(stor_dev, 1) != 0) { - debug ("Unable to register ide disk 0:1 for fatls\n"); + if (fat_register_device (stor_dev, 1) != 0) { + debug ("Unable to register ide disk 0:1\n"); return -1; } /* * Check if magic file is present */ - if (do_fat_read(AU_MAGIC_FILE, buffer, sizeof(buffer), LS_NO) <= 0) { + if ((n = do_fat_read (AU_MAGIC_FILE, buffer, + sizeof(buffer), LS_NO)) <= 0) { + debug ("No auto_update magic file (n=%d)\n", n); return -1; } #ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show(1); + board_auto_update_show (1); #endif puts("\nAutoUpdate Disk detected! Trying to update system...\n"); /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc(0); + old_ctrlc = disable_ctrlc (0); /* just loop thru all the possible files */ for (i = 0; i < N_AU_IMAGES; i++) { /* * Try to expand the environment var in the fname */ - process_macros(au_image[i].name, str); - strcpy(au_image[i].name, str); + process_macros (au_image[i].name, str); + strcpy (au_image[i].name, str); printf("Reading %s ...", au_image[i].name); /* just read the header */ - sz = do_fat_read(au_image[i].name, LOAD_ADDR, image_get_header_size (), LS_NO); + sz = do_fat_read (au_image[i].name, LOAD_ADDR, + image_get_header_size (), LS_NO); debug ("read %s sz %ld hdr %d\n", au_image[i].name, sz, image_get_header_size ()); if (sz <= 0 || sz < image_get_header_size ()) { puts(" not found\n"); continue; } - if (au_check_header_valid(i, sz) < 0) { + if (au_check_header_valid (i, sz) < 0) { puts(" header not valid\n"); continue; } - sz = do_fat_read(au_image[i].name, LOAD_ADDR, MAX_LOADSZ, LS_NO); + sz = do_fat_read (au_image[i].name, LOAD_ADDR, + MAX_LOADSZ, LS_NO); debug ("read %s sz %ld hdr %d\n", au_image[i].name, sz, image_get_header_size ()); if (sz <= 0 || sz <= image_get_header_size ()) { puts(" not found\n"); continue; } - if (au_check_cksum_valid(i, sz) < 0) { + if (au_check_cksum_valid (i, sz) < 0) { puts(" checksum not valid\n"); continue; } puts(" done\n"); do { - res = au_do_update(i, sz); + res = au_do_update (i, sz); /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc()) { - clear_ctrlc(); + if (ctrlc() || had_ctrlc ()) { + clear_ctrlc (); if (res < 0) got_ctrlc = 1; break; @@ -547,17 +532,16 @@ int do_auto_update(void) } /* restore the old state */ - disable_ctrlc(old_ctrlc); + disable_ctrlc (old_ctrlc); puts("AutoUpdate finished\n\n"); #ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show(0); + board_auto_update_show (0); #endif return 0; } - int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { do_auto_update(); diff --git a/board/esd/common/auto_update.h b/board/esd/common/auto_update.h index e2af3c7..3ed0e16 100644 --- a/board/esd/common/auto_update.h +++ b/board/esd/common/auto_update.h @@ -29,16 +29,21 @@ #define AU_MAGIC_FILE "__auto_update" -#define AU_SCRIPT 1 -#define AU_FIRMWARE 2 -#define AU_NOR 3 -#define AU_NAND 4 +#define AU_TYPEMASK 0x000000ff +#define AU_FLAGMASK 0xffff0000 + +#define AU_PROTECT 0x80000000 + +#define AU_SCRIPT 0x01 +#define AU_FIRMWARE (0x02 | AU_PROTECT) +#define AU_NOR 0x03 +#define AU_NAND 0x04 struct au_image_s { char name[80]; ulong start; ulong size; - int type; + ulong type; }; typedef struct au_image_s au_image_t; -- 1.5.3

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[U-Boot-Users] [PATCH 1/5] 4xx: Update esd's common LCD code for 405 boards
by Matthias Fuchs 22 Apr '08

22 Apr '08

- Coding style cleanup (long lines) - Add s1d13505 support - Make some functions return a result code instead of void Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- board/esd/common/lcd.c | 123 ++++++++++++++++++++--------- board/esd/common/s1d13505_640_480_16bpp.h | 66 +++++++++++++++ 2 files changed, 151 insertions(+), 38 deletions(-) create mode 100644 board/esd/common/s1d13505_640_480_16bpp.h diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index ed50def..c23dc81 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -44,37 +44,57 @@ void lcd_setup(int lcd, int config) /* * Set endianess and reset lcd controller 0 (small) */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */ + + /* set reset to low */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); udelay(10); /* wait 10us */ - if (config == 1) - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ - else - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ + if (config == 1) { + /* big-endian */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + } else { + /* little-endian */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); + } udelay(10); /* wait 10us */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */ + /* set reset to high */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); } else { /* * Set endianess and reset lcd controller 1 (big) */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */ + + /* set reset to low */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); udelay(10); /* wait 10us */ - if (config == 1) - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ - else - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ + if (config == 1) { + /* big-endian */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + } else { + /* little-endian */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); + } udelay(10); /* wait 10us */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */ + /* set reset to high */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); } /* * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); } #endif /* CFG_LCD_ENDIAN */ -void lcd_bmp(uchar *logo_bmp) +int lcd_bmp(uchar *logo_bmp) { int i; uchar *ptr; @@ -99,13 +119,18 @@ void lcd_bmp(uchar *logo_bmp) len = CFG_VIDEO_LOGO_MAX_SIZE; dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); if (dst == NULL) { - printf("Error: malloc in gunzip failed!\n"); - return; + printf("Error: malloc for gunzip failed!\n"); + return 1; + } + if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, + (uchar *)logo_bmp, &len) != 0) { + free(dst); + return 1; + } + if (len == CFG_VIDEO_LOGO_MAX_SIZE) { + printf("Image could be truncated" + " (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); } - if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) - return; - if (len == CFG_VIDEO_LOGO_MAX_SIZE) - printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); /* * Check for bmp mark 'BM' @@ -113,7 +138,7 @@ void lcd_bmp(uchar *logo_bmp) if (*(ushort *)dst != 0x424d) { printf("LCD: Unknown image format!\n"); free(dst); - return; + return 1; } } else { /* @@ -150,7 +175,7 @@ void lcd_bmp(uchar *logo_bmp) printf("LCD: Unknown bpp (%d) im image!\n", bpp); if ((dst != NULL) && (dst != (uchar *)logo_bmp)) free(dst); - return; + return 1; } printf(" (%d*%d, %dbpp)\n", width, height, bpp); @@ -180,23 +205,28 @@ void lcd_bmp(uchar *logo_bmp) if (bpp == 24) { for (x = 0; x < width; x++) { /* - * Generate epson 16bpp fb-format from 24bpp image + * Generate epson 16bpp fb-format + * from 24bpp image */ b = *bmp++ >> 3; g = *bmp++ >> 2; r = *bmp++ >> 3; - val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); + val = ((r & 0x1f) << 11) | + ((g & 0x3f) << 5) | + (b & 0x1f); *ptr2++ = val; } } else if (bpp == 8) { for (x = 0; x < line_size; x++) { /* query rgb value from palette */ - ptr = (unsigned char *)(dst + 14 + 40) ; + ptr = (unsigned char *)(dst + 14 + 40); ptr += (*bmp++) << 2; b = *ptr++ >> 3; g = *ptr++ >> 2; r = *ptr++ >> 3; - val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); + val = ((r & 0x1f) << 11) | + ((g & 0x3f) << 5) | + (b & 0x1f); *ptr2++ = val; } } @@ -208,11 +238,12 @@ void lcd_bmp(uchar *logo_bmp) if ((dst != NULL) && (dst != (uchar *)logo_bmp)) free(dst); + return 0; } -void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, - uchar *logo_bmp, ulong len) +int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, + uchar *logo_bmp, ulong len) { int i; ushort s1dReg; @@ -263,8 +294,22 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, lcd_reg += 0x10000; /* add offset for 705 regs */ puts("LCD: S1D13705"); } else { - puts("LCD: No controller detected!\n"); - return; + out_8(&lcd_reg[0x1a], 0x00); + udelay(1000); + if (in_8(&lcd_reg[1]) == 0x0c) { + /* + * S1D13505 detected + */ + reg_byte_swap = TRUE; + palette_index = 0x25; + palette_value = 0x27; + lcd_depth = 16; + + puts("LCD: S1D13505"); + } else { + puts("LCD: No controller detected!\n"); + return 1; + } } /* @@ -279,7 +324,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, s1dReg &= ~0x0001; } s1dValue = regs[i].Value; - lcd_reg[s1dReg] = s1dValue; + out_8(&lcd_reg[s1dReg], s1dValue); } /* @@ -291,15 +336,15 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Display bmp image */ - lcd_bmp(logo_bmp); + return lcd_bmp(logo_bmp); } -#if defined(CONFIG_VIDEO_SM501) int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong addr; +#ifdef CONFIG_VIDEO_SM501 char *str; - +#endif if (argc != 2) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; @@ -307,19 +352,22 @@ int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr = simple_strtoul(argv[1], NULL, 16); +#ifdef CONFIG_VIDEO_SM501 str = getenv("bd_type"); if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) { /* * SM501 available, use standard bmp command */ - return (video_display_bitmap(addr, 0, 0)); + return video_display_bitmap(addr, 0, 0); } else { /* * No SM501 available, use esd epson bmp command */ - lcd_bmp((uchar *)addr); - return 0; + return lcd_bmp((uchar *)addr); } +#else + return lcd_bmp((uchar *)addr); +#endif } U_BOOT_CMD( @@ -327,4 +375,3 @@ U_BOOT_CMD( "esdbmp - display BMP image\n", "<imageAddr> - display image\n" ); -#endif diff --git a/board/esd/common/s1d13505_640_480_16bpp.h b/board/esd/common/s1d13505_640_480_16bpp.h new file mode 100644 index 0000000..19b3e0a --- /dev/null +++ b/board/esd/common/s1d13505_640_480_16bpp.h @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2008 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs(a)esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz) + * Memory: DRAM (MCLK=40.000 MHz) + */ +static S1D_REGS regs_13505_640_480_16bpp[] = +{ + {0x1B,0x00}, /* Miscellaneous Register */ + {0x23,0x20}, /* Performance Enhancement Register 1 */ + {0x01,0x30}, /* Memory Configuration Register */ + {0x22,0x24}, /* Performance Enhancement Register 0 */ + {0x02,0x25}, /* Panel Type Register */ + {0x03,0x00}, /* MOD Rate Register */ + {0x04,0x4F}, /* Horizontal Display Width Register */ + {0x05,0x0c}, /* Horizontal Non-Display Period Register */ + {0x06,0x00}, /* HRTC/FPLINE Start Position Register */ + {0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */ + {0x08,0xDF}, /* Vertical Display Height Register 0 */ + {0x09,0x01}, /* Vertical Display Height Register 1 */ + {0x0A,0x3E}, /* Vertical Non-Display Period Register */ + {0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */ + {0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */ + {0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */ + {0x0F,0x03}, /* Screen 1 Line Compare Register 1 */ + {0x10,0x00}, /* Screen 1 Display Start Address Register 0 */ + {0x11,0x00}, /* Screen 1 Display Start Address Register 1 */ + {0x12,0x00}, /* Screen 1 Display Start Address Register 2 */ + {0x13,0x00}, /* Screen 2 Display Start Address Register 0 */ + {0x14,0x00}, /* Screen 2 Display Start Address Register 1 */ + {0x15,0x00}, /* Screen 2 Display Start Address Register 2 */ + {0x16,0x80}, /* Memory Address Offset Register 0 */ + {0x17,0x02}, /* Memory Address Offset Register 1 */ + {0x18,0x00}, /* Pixel Panning Register */ + {0x19,0x01}, /* Clock Configuration Register */ + {0x1A,0x00}, /* Power Save Configuration Register */ + {0x1C,0x00}, /* MD Configuration Readback Register 0 */ + {0x1E,0x06}, /* General IO Pins Configuration Register 0 */ + {0x1F,0x00}, /* General IO Pins Configuration Register 1 */ + {0x20,0x00}, /* General IO Pins Control Register 0 */ + {0x21,0x00}, /* General IO Pins Control Register 1 */ + {0x23,0x20}, /* Performance Enhancement Register 1 */ + {0x0D,0x15}, /* Display Mode Register */ +}; + -- 1.5.3

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[U-Boot-Users] [PATCH] 4xx: Update FPGA image for APC405 boards
by Matthias Fuchs 22 Apr '08

22 Apr '08

Hi, because of the lists size limit and because I did not find any other suitable way to submit this patch, I am posting a link to the patch file: http://www.esd-electronics.com/Customer/mf/0002-4xx-Update-FPGA-image-for-A… Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- board/esd/apc405/fpgadata.c | 4284 ++++++++++++++++++++----------------------- 1 files changed, 2004 insertions(+), 2280 deletions(-)

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Re: [U-Boot-Users] ubi and u-boot
by Ricard Wanderlof 22 Apr '08

22 Apr '08

On Mon, 21 Apr 2008, Artem Bityutskiy wrote: > On Mon, 2008-04-21 at 08:44 -0500, Josh Boyer wrote: >> I think there was only 1 time the on-flash format changed, and that was >> before UBI was merged upstream. New features can be introduced with >> additional flags, however older versions should be able to ignore those. >> >> Artem, is that right? My memory is fuzzy here. > > [...] We never changed the media format since UBI was merged. Ok, that sounds reassuring. I think I've been confusing UBI with UBIFS in this respect. /Ricard -- Ricard Wolf Wanderlöf ricardw(at)axis.com Axis Communications AB, Lund, Sweden www.axis.com Phone +46 46 272 2016 Fax +46 46 13 61 30

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[U-Boot-Users] [PATCH] ppc4xx: Pass PCIe root-complex/endpoint configuration to Linux via the fdt
by Stefan Roese 22 Apr '08

22 Apr '08

The PCIe root-complex/endpoint setup as configured via the "pcie_mode" environment variable will now get passed to the Linux kernel by setting the device_type property of the PCIe device tree node. For normal root- complex configuration it will keep its defaults value of "pci" and for endpoint configuration it will get changed to "pci-endpoint". Signed-off-by: Stefan Roese <sr(a)denx.de> --- cpu/ppc4xx/fdt.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/4xx_pcie.h | 5 ++++- 2 files changed, 46 insertions(+), 1 deletions(-) diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index afcb974..1f4d6f2 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -31,9 +31,46 @@ #include <libfdt.h> #include <libfdt_env.h> #include <fdt_support.h> +#include <asm/4xx_pcie.h> DECLARE_GLOBAL_DATA_PTR; +/* + * Fixup all PCIe nodes by setting the device_type property + * to "pci-endpoint" instead is "pci" for endpoint ports. + * This property will get checked later by the Linux driver + * to properly configure the PCIe port in Linux (again). + */ +void fdt_pcie_setup(void *blob) +{ + const char *compat = "ibm,plb-pciex"; + const char *prop = "device_type"; + const char *prop_val = "pci-endpoint"; + const u32 *port; + int no; + int rc; + + /* Search first PCIe node */ + no = fdt_node_offset_by_compatible(blob, -1, compat); + while (no != -FDT_ERR_NOTFOUND) { + port = fdt_getprop(blob, no, "port", NULL); + if (port == NULL) { + printf("WARNING: could not find port property\n"); + } else { + if (is_end_point(*port)) { + rc = fdt_setprop(blob, no, prop, prop_val, + strlen(prop_val) + 1); + if (rc < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop, compat, fdt_strerror(rc)); + } + } + + /* Jump to next PCIe node */ + no = fdt_node_offset_by_compatible(blob, no, compat); + } +} + void ft_cpu_setup(void *blob, bd_t *bd) { sys_info_t sys_info; @@ -60,5 +97,10 @@ void ft_cpu_setup(void *blob, bd_t *bd) * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob, bd); + + /* + * Fixup all available PCIe nodes by setting the device_type property + */ + fdt_pcie_setup(blob); } #endif /* CONFIG_OF_LIBFDT */ diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index d27d2a9..5398696 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -8,10 +8,11 @@ * option) any later version. */ -#include <ppc4xx.h> #ifndef __4XX_PCIE_H #define __4XX_PCIE_H +#include <ppc4xx.h> + #define DCRN_SDR0_CFGADDR 0x00e #define DCRN_SDR0_CFGDATA 0x00f @@ -395,6 +396,7 @@ static inline void mdelay(int n) udelay(1000); } +#if defined(PCIE0_SDR) static inline u32 sdr_base(int port) { switch (port) { @@ -409,5 +411,6 @@ static inline u32 sdr_base(int port) #endif } } +#endif /* defined(PCIE0_SDR) */ #endif /* __4XX_PCIE_H */ -- 1.5.5.1

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