April 2008 - U-Boot

[U-Boot-Users] minimum bdi config to read flash on 85xx
by robert lazarski 28 May '13

28 May '13

Hi all, On our custom 8548 board, we can't read our flash correctly. We have one 1Gb bank of spansion S29GL01GP flash and we get: atum>mdh 0xf8000000 0_f8000000 : f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 The big problem we have now: is this a hardware issue or a bdi config issue? Aside from the flash we have 1GigaByte of DDR ram. Can anyone help us track our flash issues down to be hardware, config file, or some combination? The hardware guys think the board is fine. We've been deep into the manuals of both the 8548 and the bdi and can't find anything wrong. Here's the config, thanks for any help! ;bdiGDB configuration file for ATUM 8548 ;--------------------------------------------------- ; [INIT] ; ; ; use the following two lines for STARTUP HALT WSPR 63 0xffff0000 ;IVPR to boot core WSPR 415 0x0000f000 ;IVOR15 : Debug exception ; ; ;================= setup for flash programming =============== ; Move CCSRBAR to 0xe0000000 WM32 0xff700000 0x000e0000 ;CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's WM32 0xe0000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0xe0000C10 0x80f0001d ;LAWAR0 : DDR 1GB WM32 0xe0000C28 0xf8000000 ;LAWBAR1 : @0xf8000000 WM32 0xe0000C30 0x8040001a ;LAWAR1 : Local Bus 128MB for S29GL01GP ; ; Setup Flash chip select WM32 0xe0005000 0xf8001001 ;BR0 WM32 0xe0005004 0xf8000E65 ;OR0 ; CS0_BNDS WM32 0xe0002000 0x0000000f ; DDR CS0 ; CS0_CONFIG WM32 0xe0002080 0x80000102 ; TIMING_CFG_0 WM32 0xe0002104 0x00260802 ; TIMING_CFG_1 WM32 0xe0002108 0x38355322 ; TIMING_CFG_2 WM32 0xe000210C 0x039048c7 ; DDR_SDRAM_MODE WM32 0xe0002118 0x00000432 ; DDR_SDRAM_INTERVAL WM32 0xe0002124 0x05150100 ; DDR_SDRAM_CFG2 WM32 0xe0002114 0x24000000 ; DDR_SDRAM_CLK_CNTL WM32 0xe0002130 0x03000000 DELAY 200 ; enable the memory interface ; DDR_SDRAM_CFG ; enable the memory interface WM32 0xe0002110 0xc3000000 ;================= end flash programming ===================== ; [TARGET] CPUTYPE 8548 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock ;STARTUP STOP 5000 ;let U-boot code setup the system STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 500 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms [REGS] FILE $reg8548.def [HOST] IP 10.101.43.10 FILE vmlinux.8548 FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP e500.bin PROMPT atum> [FLASH] CHIPTYPE MIRRORX16 ;S29GL01GP CHIPSIZE 0x8000000 ;The size of one flash chip in bytes - 1Gb BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE u-boot.bin FORMAT BIN 0xF8000000 ERASE 0xF8000000 ;erase sector 0 [REGS] FILE $reg8548.def

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[U-Boot-Users] U boot modification...
by Kiran Jammula 23 May '12

23 May '12

Hi, I am using U boot for my project. I need to configure the console while booting by prompting the user from target board LCD and Keypad. So please let me know which file of the U-boot I have to modify to achieve this. Kiran _________________________________________________________________ Special offer for NRIs! http://creative.mediaturf.net/creatives/citibankrca/rca_msntagofline.htm Get a zero balance account for next 20 years. From Citibank

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[U-Boot-Users] Ethernet loopback command
by Thomas Schäfer 17 Apr '12

17 Apr '12

Hi, The patch attached provides a command called 'ethloop' which allows to perform loopback testing on the current eth device. To achieve this, a new ethernet packet type (PROT_TEST, 0x0808, AFAIK this is not used otherwise) is introduced in net/net.c. The patch is against SF CVS from 20050307. The functions EthLoopStart, EthLoopSend and EthLoopHandler generate a simple ethernet frame with NetOurEther as destination address and packet type PROT_TEST. The looped back package is compared with the original one and a message is displayed. It is necessary to set the ethernet line into loopback mode either by programming the PHY or using a loopback plug. I've tested this on our PPC405 custom board, but it should also work on all other systems because packet generation is independent of the underlying ethernet hardware. Example usage: => mii w 0 0 7100 <-- sets PHY into loopback mode => ethloop Using ppc_405x_eth0 device Got ethernet loopback frame, len=64 loopback test successfully completed => mii w 0 0 8000 <-- PHY reset after test is completed Maybe this is also useful for others.. Best regards, Thomas Schäfer ____________________________________ Kontron Modular Computers GmbH Konrad-Zuse-Str. 9 66115 Saarbrücken Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: thomas.schaefer(a)kontron.com

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[U-Boot-Users] Add a new command to U-Boot
by Carlos Filipe Silva 20 May '09

20 May '09

Hi all! I have one doubt. How can I add a new command to U-Boot? Do I have to use only the macro U_BOOT_CMD() like files .../common/cmd_* or do I have to do more things, like defines, etc.? And after this is compliled with no error, if I type help in U-Boot's shell, do I see this command like the others? Best regards, Carlos Silva

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Re: [U-Boot-Users] NAND boot from file
by Charles Krinke 06 Mar '09

06 Mar '09

Dear Wolfgang: >Um... if this is JFFS2, then why not simply "fsload" + "bootm" ? Although I can format the flash in Linux and run fsinfo, ls or fsload in u-boot, there is a time of several minutes after Scanning JFFS2 FS Before ls can find the directory or fsload can attempt to load the uImage file. I am thinking that the 'flash_eraseall -j' command I am using may not be quite setup correctly with the u-boot environment. It should not take several minutes to pull a directory off a formatted flash. Here is what I do: Linux# flash_eraseall -j /dev/mtd0 Linux# mount -t jffs2 /dev/mtdblock0 /mnt/flash1 Linux# cp /uImage /mnt/flash1 Linux# ls /mnt/flash1 uImage is here, now reboot uboot> ls uImage is here, but it takes several minutes to get the listing. Fsload takes several minutes also. Can you think of what other assumptions I may be making that may be invalid? Charles

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[U-Boot-Users] [PATCH] part 2. Embedded PlanetBoards
by Jeff Mann 29 Nov '08

29 Nov '08

*CHANGELOG Added Support for Embedded Planet Boards EP852 EP866 and EP85xxm. See respective board config file for original author information. Merged from internal company port and QUICCstart kit into the most recent u-boot git by J. Mann, Embedded Planet, 2006-JUL-27. (this is part 2 of 2 split in half for size reasons.) (the first attempt to send this e-mail resulted in a message too big error. Sorry if you get two on acident)

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[U-Boot-Users] [PATCH] Add AT2440 (S3C2440) board support
by roger.esoft＠msa.hinet.net 29 Nov '08

29 Nov '08

3 2

[U-Boot-Users] how to support usbtty
by zhuzhenhua 31 Aug '08

31 Aug '08

becides set CONFIG_USB_TTY, what other modification need to do for the usbtty support? thanks for any hints

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[U-Boot-Users] [PATCH][resubmit] QE IO: Add initial data to pin configuration + read/write functions
by David Saada 16 Jul '08

16 Jul '08

On the MPC83xx & MPC85xx architectures that have QE, add initial data to the pin configuration table (qe_iop_conf_tab). This is relevant for GPIO pins defined as output. One can setup a value of -1 to leave the value unchanged. QE initialization tables in all relevant boards were also replaced. In addition, add IO pin read & write functions. This patch also includes commands for reading and writing parallel I/O ports (pario command). Signed-off-by: David Saada <david.saada(a)ecitele.com> b/common/cmd_pario.c | 85 +++++++++ board/freescale/mpc8323erdb/mpc8323erdb.c | 74 +++---- board/freescale/mpc832xemds/mpc832xemds.c | 74 +++---- board/freescale/mpc8360emds/mpc8360emds.c | 110 +++++------ board/freescale/mpc8360erdk/mpc8360erdk.c | 280 +++++++++++++++--------------- board/freescale/mpc8568mds/mpc8568mds.c | 106 +++++------ common/Makefile | 1 cpu/mpc83xx/cpu_init.c | 7 cpu/mpc83xx/qe_io.c | 59 +++++- cpu/mpc85xx/cpu_init.c | 7 cpu/mpc85xx/qe_io.c | 58 +++++- include/ioports.h | 8 12 files changed, 526 insertions(+), 343 deletions(-) --- a/include/ioports.h 2008-03-28 01:49:12.000000000 +0200 +++ b/include/ioports.h 2008-03-30 16:11:09.514274000 +0300 @@ -60,6 +60,14 @@ typedef struct { int dir; int open_drain; int assign; + int data; } qe_iop_conf_t; #define QE_IOP_TAB_END (-1) + +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign, + int data); +void qe_read_iopin(u8 port, u8 pin, int *data); +void qe_write_iopin(u8 port, u8 pin, int data); + + --- a/cpu/mpc85xx/cpu_init.c 2008-03-28 01:49:12.000000000 +0200 +++ b/cpu/mpc85xx/cpu_init.c 2008-03-30 15:42:32.913152000 +0300 @@ -39,15 +39,13 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; -extern void qe_config_iopin(u8 port, u8 pin, int dir, - int open_drain, int assign); extern void qe_init(uint qe_base); extern void qe_reset(void); static void config_qe_ioports(void) { u8 port, pin; - int dir, open_drain, assign; + int dir, open_drain, assign, data; int i; for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { @@ -56,7 +54,8 @@ static void config_qe_ioports(void) dir = qe_iop_conf_tab[i].dir; open_drain = qe_iop_conf_tab[i].open_drain; assign = qe_iop_conf_tab[i].assign; - qe_config_iopin(port, pin, dir, open_drain, assign); + data = qe_iop_conf_tab[i].data; + qe_config_iopin(port, pin, dir, open_drain, assign, data); } } #endif --- a/cpu/mpc85xx/qe_io.c 2008-03-28 01:49:12.000000000 +0200 +++ b/cpu/mpc85xx/qe_io.c 2008-03-30 15:44:56.961332000 +0300 @@ -27,16 +27,30 @@ #if defined(CONFIG_QE) #define NUM_OF_PINS 32 -void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign, + int data) { u32 pin_2bit_mask; u32 pin_2bit_dir; u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile par_io_t *par_io = (volatile par_io_t *) - &(gur->qe_par_io); + ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the data */ + if ((data != -1) && /* Don't leave unchanged */ + (assign == 0) && /* GPIO */ + (dir & 1)) { /* Has output */ + tmp_val = in_be32(&par_io[port].cpdat); + if (data) + out_be32(&par_io[port].cpdat, pin_1bit_mask | tmp_val); + else + out_be32(&par_io[port].cpdat, ~pin_1bit_mask & tmp_val); + } /* Caculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); @@ -55,9 +69,6 @@ void qe_config_iopin(u8 port, u8 pin, in out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val); } - /* Calculate pin location for 1bit mask */ - pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); - /* Setup the open drain */ tmp_val = in_be32(&par_io[port].cpodr); if (open_drain) @@ -82,4 +93,37 @@ void qe_config_iopin(u8 port, u8 pin, in } } +void qe_read_iopin(u8 port, u8 pin, int *data) +{ + u32 pin_1bit_mask; + u32 tmp_val; + ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Read the data */ + tmp_val = in_be32(&par_io[port].cpdat); + *data = (tmp_val >> (NUM_OF_PINS - (pin+1))) & 0x1; +} + +void qe_write_iopin(u8 port, u8 pin, int data) +{ + u32 pin_1bit_mask; + u32 tmp_val; + ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Write the data */ + tmp_val = in_be32(&par_io[port].cpdat); + if (data) + out_be32(&par_io[port].cpdat, pin_1bit_mask | tmp_val); + else + out_be32(&par_io[port].cpdat, ~pin_1bit_mask & tmp_val); +} + #endif /* CONFIG_QE */ --- a/cpu/mpc83xx/cpu_init.c 2008-03-28 01:49:12.000000000 +0200 +++ b/cpu/mpc83xx/cpu_init.c 2008-03-30 15:45:53.227362000 +0300 @@ -28,15 +28,13 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; -extern void qe_config_iopin(u8 port, u8 pin, int dir, - int open_drain, int assign); extern void qe_init(uint qe_base); extern void qe_reset(void); static void config_qe_ioports(void) { u8 port, pin; - int dir, open_drain, assign; + int dir, open_drain, assign, data; int i; for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { @@ -45,7 +43,8 @@ static void config_qe_ioports(void) dir = qe_iop_conf_tab[i].dir; open_drain = qe_iop_conf_tab[i].open_drain; assign = qe_iop_conf_tab[i].assign; - qe_config_iopin(port, pin, dir, open_drain, assign); + data = qe_iop_conf_tab[i].data; + qe_config_iopin(port, pin, dir, open_drain, assign, data); } } #endif --- a/cpu/mpc83xx/qe_io.c 2008-03-28 01:49:12.000000000 +0200 +++ b/cpu/mpc83xx/qe_io.c 2008-03-30 15:53:43.620970000 +0300 @@ -26,15 +26,30 @@ #include "asm/immap_83xx.h" #define NUM_OF_PINS 32 -void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign, + int data) { u32 pin_2bit_mask; u32 pin_2bit_dir; u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; + immap_t *im = (immap_t *)CFG_IMMR; + qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio; + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the data */ + if ((data != -1) && /* Don't leave unchanged */ + (assign == 0) && /* GPIO */ + (dir & 1)) { /* Has output */ + tmp_val = in_be32(&par_io->ioport[port].pdat); + if (data) + out_be32(&par_io->ioport[port].pdat, pin_1bit_mask | tmp_val); + else + out_be32(&par_io->ioport[port].pdat, ~pin_1bit_mask & tmp_val); + } /* Caculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); @@ -53,9 +68,6 @@ void qe_config_iopin(u8 port, u8 pin, in out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val); } - /* Calculate pin location for 1bit mask */ - pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); - /* Setup the open drain */ tmp_val = in_be32(&par_io->ioport[port].podr); if (open_drain) { @@ -80,3 +92,38 @@ void qe_config_iopin(u8 port, u8 pin, in out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val); } } + +void qe_read_iopin(u8 port, u8 pin, int *data) +{ + u32 pin_1bit_mask; + u32 tmp_val; + immap_t *im = (immap_t *)CFG_IMMR; + qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio; + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Read the data */ + tmp_val = in_be32(&par_io->ioport[port].pdat); + *data = (tmp_val >> (NUM_OF_PINS - (pin+1))) & 0x1; +} + +void qe_write_iopin(u8 port, u8 pin, int data) +{ + u32 pin_1bit_mask; + u32 tmp_val; + immap_t *im = (immap_t *)CFG_IMMR; + qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio; + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the data */ + tmp_val = in_be32(&par_io->ioport[port].pdat); + if (data) { + out_be32(&par_io->ioport[port].pdat, pin_1bit_mask | tmp_val); + } else { + out_be32(&par_io->ioport[port].pdat, ~pin_1bit_mask & tmp_val); + } +} + --- a/board/freescale/mpc8323erdb/mpc8323erdb.c 2008-03-28 01:49:12.000000000 +0200 +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c 2008-03-30 15:54:25.959133000 +0300 @@ -23,47 +23,47 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* UCC3 */ - {1, 0, 1, 0, 1}, /* TxD0 */ - {1, 1, 1, 0, 1}, /* TxD1 */ - {1, 2, 1, 0, 1}, /* TxD2 */ - {1, 3, 1, 0, 1}, /* TxD3 */ - {1, 9, 1, 0, 1}, /* TxER */ - {1, 12, 1, 0, 1}, /* TxEN */ - {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ - - {1, 4, 2, 0, 1}, /* RxD0 */ - {1, 5, 2, 0, 1}, /* RxD1 */ - {1, 6, 2, 0, 1}, /* RxD2 */ - {1, 7, 2, 0, 1}, /* RxD3 */ - {1, 8, 2, 0, 1}, /* RxER */ - {1, 10, 2, 0, 1}, /* RxDV */ - {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ - {1, 11, 2, 0, 1}, /* COL */ - {1, 13, 2, 0, 1}, /* CRS */ + {1, 0, 1, 0, 1, -1}, /* TxD0 */ + {1, 1, 1, 0, 1, -1}, /* TxD1 */ + {1, 2, 1, 0, 1, -1}, /* TxD2 */ + {1, 3, 1, 0, 1, -1}, /* TxD3 */ + {1, 9, 1, 0, 1, -1}, /* TxER */ + {1, 12, 1, 0, 1, -1}, /* TxEN */ + {3, 24, 2, 0, 1, -1}, /* TxCLK->CLK10 */ + + {1, 4, 2, 0, 1, -1}, /* RxD0 */ + {1, 5, 2, 0, 1, -1}, /* RxD1 */ + {1, 6, 2, 0, 1, -1}, /* RxD2 */ + {1, 7, 2, 0, 1, -1}, /* RxD3 */ + {1, 8, 2, 0, 1, -1}, /* RxER */ + {1, 10, 2, 0, 1, -1}, /* RxDV */ + {0, 13, 2, 0, 1, -1}, /* RxCLK->CLK9 */ + {1, 11, 2, 0, 1, -1}, /* COL */ + {1, 13, 2, 0, 1, -1}, /* CRS */ /* UCC2 */ - {0, 18, 1, 0, 1}, /* TxD0 */ - {0, 19, 1, 0, 1}, /* TxD1 */ - {0, 20, 1, 0, 1}, /* TxD2 */ - {0, 21, 1, 0, 1}, /* TxD3 */ - {0, 27, 1, 0, 1}, /* TxER */ - {0, 30, 1, 0, 1}, /* TxEN */ - {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */ - - {0, 22, 2, 0, 1}, /* RxD0 */ - {0, 23, 2, 0, 1}, /* RxD1 */ - {0, 24, 2, 0, 1}, /* RxD2 */ - {0, 25, 2, 0, 1}, /* RxD3 */ - {0, 26, 1, 0, 1}, /* RxER */ - {0, 28, 2, 0, 1}, /* Rx_DV */ - {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */ - {0, 29, 2, 0, 1}, /* COL */ - {0, 31, 2, 0, 1}, /* CRS */ + {0, 18, 1, 0, 1, -1}, /* TxD0 */ + {0, 19, 1, 0, 1, -1}, /* TxD1 */ + {0, 20, 1, 0, 1, -1}, /* TxD2 */ + {0, 21, 1, 0, 1, -1}, /* TxD3 */ + {0, 27, 1, 0, 1, -1}, /* TxER */ + {0, 30, 1, 0, 1, -1}, /* TxEN */ + {3, 23, 2, 0, 1, -1}, /* TxCLK->CLK3 */ + + {0, 22, 2, 0, 1, -1}, /* RxD0 */ + {0, 23, 2, 0, 1, -1}, /* RxD1 */ + {0, 24, 2, 0, 1, -1}, /* RxD2 */ + {0, 25, 2, 0, 1, -1}, /* RxD3 */ + {0, 26, 1, 0, 1, -1}, /* RxER */ + {0, 28, 2, 0, 1, -1}, /* Rx_DV */ + {3, 21, 2, 0, 1, -1}, /* RxCLK->CLK16 */ + {0, 29, 2, 0, 1, -1}, /* COL */ + {0, 31, 2, 0, 1, -1}, /* CRS */ - {3, 4, 3, 0, 2}, /* MDIO */ - {3, 5, 1, 0, 2}, /* MDC */ + {3, 4, 3, 0, 2, -1}, /* MDIO */ + {3, 5, 1, 0, 2, -1}, /* MDC */ - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END, -1}, /* END of table */ }; int board_early_init_f(void) --- a/board/freescale/mpc832xemds/mpc832xemds.c 2008-03-28 01:49:12.000000000 +0200 +++ b/board/freescale/mpc832xemds/mpc832xemds.c 2008-03-30 15:57:01.040395000 +0300 @@ -31,47 +31,47 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* ETH3 */ - {1, 0, 1, 0, 1}, /* TxD0 */ - {1, 1, 1, 0, 1}, /* TxD1 */ - {1, 2, 1, 0, 1}, /* TxD2 */ - {1, 3, 1, 0, 1}, /* TxD3 */ - {1, 9, 1, 0, 1}, /* TxER */ - {1, 12, 1, 0, 1}, /* TxEN */ - {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ - - {1, 4, 2, 0, 1}, /* RxD0 */ - {1, 5, 2, 0, 1}, /* RxD1 */ - {1, 6, 2, 0, 1}, /* RxD2 */ - {1, 7, 2, 0, 1}, /* RxD3 */ - {1, 8, 2, 0, 1}, /* RxER */ - {1, 10, 2, 0, 1}, /* RxDV */ - {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ - {1, 11, 2, 0, 1}, /* COL */ - {1, 13, 2, 0, 1}, /* CRS */ + {1, 0, 1, 0, 1, -1}, /* TxD0 */ + {1, 1, 1, 0, 1, -1}, /* TxD1 */ + {1, 2, 1, 0, 1, -1}, /* TxD2 */ + {1, 3, 1, 0, 1, -1}, /* TxD3 */ + {1, 9, 1, 0, 1, -1}, /* TxER */ + {1, 12, 1, 0, 1, -1}, /* TxEN */ + {3, 24, 2, 0, 1, -1}, /* TxCLK->CLK10 */ + + {1, 4, 2, 0, 1, -1}, /* RxD0 */ + {1, 5, 2, 0, 1, -1}, /* RxD1 */ + {1, 6, 2, 0, 1, -1}, /* RxD2 */ + {1, 7, 2, 0, 1, -1}, /* RxD3 */ + {1, 8, 2, 0, 1, -1}, /* RxER */ + {1, 10, 2, 0, 1, -1}, /* RxDV */ + {0, 13, 2, 0, 1, -1}, /* RxCLK->CLK9 */ + {1, 11, 2, 0, 1, -1}, /* COL */ + {1, 13, 2, 0, 1, -1}, /* CRS */ /* ETH4 */ - {1, 18, 1, 0, 1}, /* TxD0 */ - {1, 19, 1, 0, 1}, /* TxD1 */ - {1, 20, 1, 0, 1}, /* TxD2 */ - {1, 21, 1, 0, 1}, /* TxD3 */ - {1, 27, 1, 0, 1}, /* TxER */ - {1, 30, 1, 0, 1}, /* TxEN */ - {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ - - {1, 22, 2, 0, 1}, /* RxD0 */ - {1, 23, 2, 0, 1}, /* RxD1 */ - {1, 24, 2, 0, 1}, /* RxD2 */ - {1, 25, 2, 0, 1}, /* RxD3 */ - {1, 26, 1, 0, 1}, /* RxER */ - {1, 28, 2, 0, 1}, /* Rx_DV */ - {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ - {1, 29, 2, 0, 1}, /* COL */ - {1, 31, 2, 0, 1}, /* CRS */ + {1, 18, 1, 0, 1, -1}, /* TxD0 */ + {1, 19, 1, 0, 1, -1}, /* TxD1 */ + {1, 20, 1, 0, 1, -1}, /* TxD2 */ + {1, 21, 1, 0, 1, -1}, /* TxD3 */ + {1, 27, 1, 0, 1, -1}, /* TxER */ + {1, 30, 1, 0, 1, -1}, /* TxEN */ + {3, 6, 2, 0, 1, -1}, /* TxCLK->CLK8 */ + + {1, 22, 2, 0, 1, -1}, /* RxD0 */ + {1, 23, 2, 0, 1, -1}, /* RxD1 */ + {1, 24, 2, 0, 1, -1}, /* RxD2 */ + {1, 25, 2, 0, 1, -1}, /* RxD3 */ + {1, 26, 1, 0, 1, -1}, /* RxER */ + {1, 28, 2, 0, 1, -1}, /* Rx_DV */ + {3, 31, 2, 0, 1, -1}, /* RxCLK->CLK7 */ + {1, 29, 2, 0, 1, -1}, /* COL */ + {1, 31, 2, 0, 1, -1}, /* CRS */ - {3, 4, 3, 0, 2}, /* MDIO */ - {3, 5, 1, 0, 2}, /* MDC */ + {3, 4, 3, 0, 2, -1}, /* MDIO */ + {3, 5, 1, 0, 2, -1}, /* MDC */ - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END, -1}, /* END of table */ }; int board_early_init_f(void) --- a/board/freescale/mpc8360emds/mpc8360emds.c 2008-03-28 01:49:12.000000000 +0200 +++ b/board/freescale/mpc8360emds/mpc8360emds.c 2008-03-30 15:57:20.682650000 +0300 @@ -30,63 +30,63 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ - {0, 3, 1, 0, 1}, /* TxD0 */ - {0, 4, 1, 0, 1}, /* TxD1 */ - {0, 5, 1, 0, 1}, /* TxD2 */ - {0, 6, 1, 0, 1}, /* TxD3 */ - {1, 6, 1, 0, 3}, /* TxD4 */ - {1, 7, 1, 0, 1}, /* TxD5 */ - {1, 9, 1, 0, 2}, /* TxD6 */ - {1, 10, 1, 0, 2}, /* TxD7 */ - {0, 9, 2, 0, 1}, /* RxD0 */ - {0, 10, 2, 0, 1}, /* RxD1 */ - {0, 11, 2, 0, 1}, /* RxD2 */ - {0, 12, 2, 0, 1}, /* RxD3 */ - {0, 13, 2, 0, 1}, /* RxD4 */ - {1, 1, 2, 0, 2}, /* RxD5 */ - {1, 0, 2, 0, 2}, /* RxD6 */ - {1, 4, 2, 0, 2}, /* RxD7 */ - {0, 7, 1, 0, 1}, /* TX_EN */ - {0, 8, 1, 0, 1}, /* TX_ER */ - {0, 15, 2, 0, 1}, /* RX_DV */ - {0, 16, 2, 0, 1}, /* RX_ER */ - {0, 0, 2, 0, 1}, /* RX_CLK */ - {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ - {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ + {0, 3, 1, 0, 1, -1}, /* TxD0 */ + {0, 4, 1, 0, 1, -1}, /* TxD1 */ + {0, 5, 1, 0, 1, -1}, /* TxD2 */ + {0, 6, 1, 0, 1, -1}, /* TxD3 */ + {1, 6, 1, 0, 3, -1}, /* TxD4 */ + {1, 7, 1, 0, 1, -1}, /* TxD5 */ + {1, 9, 1, 0, 2, -1}, /* TxD6 */ + {1, 10, 1, 0, 2, -1}, /* TxD7 */ + {0, 9, 2, 0, 1, -1}, /* RxD0 */ + {0, 10, 2, 0, 1, -1}, /* RxD1 */ + {0, 11, 2, 0, 1, -1}, /* RxD2 */ + {0, 12, 2, 0, 1, -1}, /* RxD3 */ + {0, 13, 2, 0, 1, -1}, /* RxD4 */ + {1, 1, 2, 0, 2, -1}, /* RxD5 */ + {1, 0, 2, 0, 2, -1}, /* RxD6 */ + {1, 4, 2, 0, 2, -1}, /* RxD7 */ + {0, 7, 1, 0, 1, -1}, /* TX_EN */ + {0, 8, 1, 0, 1, -1}, /* TX_ER */ + {0, 15, 2, 0, 1, -1}, /* RX_DV */ + {0, 16, 2, 0, 1, -1}, /* RX_ER */ + {0, 0, 2, 0, 1, -1}, /* RX_CLK */ + {2, 9, 1, 0, 3, -1}, /* GTX_CLK - CLK10 */ + {2, 8, 2, 0, 1, -1}, /* GTX125 - CLK9 */ /* GETH2 */ - {0, 17, 1, 0, 1}, /* TxD0 */ - {0, 18, 1, 0, 1}, /* TxD1 */ - {0, 19, 1, 0, 1}, /* TxD2 */ - {0, 20, 1, 0, 1}, /* TxD3 */ - {1, 2, 1, 0, 1}, /* TxD4 */ - {1, 3, 1, 0, 2}, /* TxD5 */ - {1, 5, 1, 0, 3}, /* TxD6 */ - {1, 8, 1, 0, 3}, /* TxD7 */ - {0, 23, 2, 0, 1}, /* RxD0 */ - {0, 24, 2, 0, 1}, /* RxD1 */ - {0, 25, 2, 0, 1}, /* RxD2 */ - {0, 26, 2, 0, 1}, /* RxD3 */ - {0, 27, 2, 0, 1}, /* RxD4 */ - {1, 12, 2, 0, 2}, /* RxD5 */ - {1, 13, 2, 0, 3}, /* RxD6 */ - {1, 11, 2, 0, 2}, /* RxD7 */ - {0, 21, 1, 0, 1}, /* TX_EN */ - {0, 22, 1, 0, 1}, /* TX_ER */ - {0, 29, 2, 0, 1}, /* RX_DV */ - {0, 30, 2, 0, 1}, /* RX_ER */ - {0, 31, 2, 0, 1}, /* RX_CLK */ - {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ - {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ - - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ - - {5, 0, 1, 0, 2}, /* UART2_SOUT */ - {5, 1, 2, 0, 3}, /* UART2_CTS */ - {5, 2, 1, 0, 1}, /* UART2_RTS */ - {5, 3, 2, 0, 2}, /* UART2_SIN */ + {0, 17, 1, 0, 1, -1}, /* TxD0 */ + {0, 18, 1, 0, 1, -1}, /* TxD1 */ + {0, 19, 1, 0, 1, -1}, /* TxD2 */ + {0, 20, 1, 0, 1, -1}, /* TxD3 */ + {1, 2, 1, 0, 1, -1}, /* TxD4 */ + {1, 3, 1, 0, 2, -1}, /* TxD5 */ + {1, 5, 1, 0, 3, -1}, /* TxD6 */ + {1, 8, 1, 0, 3, -1}, /* TxD7 */ + {0, 23, 2, 0, 1, -1}, /* RxD0 */ + {0, 24, 2, 0, 1, -1}, /* RxD1 */ + {0, 25, 2, 0, 1, -1}, /* RxD2 */ + {0, 26, 2, 0, 1, -1}, /* RxD3 */ + {0, 27, 2, 0, 1, -1}, /* RxD4 */ + {1, 12, 2, 0, 2, -1}, /* RxD5 */ + {1, 13, 2, 0, 3, -1}, /* RxD6 */ + {1, 11, 2, 0, 2, -1}, /* RxD7 */ + {0, 21, 1, 0, 1, -1}, /* TX_EN */ + {0, 22, 1, 0, 1, -1}, /* TX_ER */ + {0, 29, 2, 0, 1, -1}, /* RX_DV */ + {0, 30, 2, 0, 1, -1}, /* RX_ER */ + {0, 31, 2, 0, 1, -1}, /* RX_CLK */ + {2, 2, 1, 0, 2, -1}, /* GTX_CLK = CLK10 */ + {2, 3, 2, 0, 1, -1}, /* GTX125 - CLK4 */ + + {0, 1, 3, 0, 2, -1}, /* MDIO */ + {0, 2, 1, 0, 1, -1}, /* MDC */ + + {5, 0, 1, 0, 2, -1}, /* UART2_SOUT */ + {5, 1, 2, 0, 3, -1}, /* UART2_CTS */ + {5, 2, 1, 0, 1, -1}, /* UART2_RTS */ + {5, 3, 2, 0, 2, -1}, /* UART2_SIN */ - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END, -1}, /* END of table */ }; int board_early_init_f(void) --- a/board/freescale/mpc8360erdk/mpc8360erdk.c 2008-03-28 01:49:12.000000000 +0200 +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c 2008-03-30 15:57:40.425878000 +0300 @@ -26,165 +26,165 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* MDIO */ - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ + {0, 1, 3, 0, 2, -1}, /* MDIO */ + {0, 2, 1, 0, 1, -1}, /* MDC */ /* UCC1 - UEC (Gigabit) */ - {0, 3, 1, 0, 1}, /* TxD0 */ - {0, 4, 1, 0, 1}, /* TxD1 */ - {0, 5, 1, 0, 1}, /* TxD2 */ - {0, 6, 1, 0, 1}, /* TxD3 */ - {0, 9, 2, 0, 1}, /* RxD0 */ - {0, 10, 2, 0, 1}, /* RxD1 */ - {0, 11, 2, 0, 1}, /* RxD2 */ - {0, 12, 2, 0, 1}, /* RxD3 */ - {0, 7, 1, 0, 1}, /* TX_EN */ - {0, 8, 1, 0, 1}, /* TX_ER */ - {0, 15, 2, 0, 1}, /* RX_DV */ - {0, 0, 2, 0, 1}, /* RX_CLK */ - {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ - {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ + {0, 3, 1, 0, 1, -1}, /* TxD0 */ + {0, 4, 1, 0, 1, -1}, /* TxD1 */ + {0, 5, 1, 0, 1, -1}, /* TxD2 */ + {0, 6, 1, 0, 1, -1}, /* TxD3 */ + {0, 9, 2, 0, 1, -1}, /* RxD0 */ + {0, 10, 2, 0, 1, -1}, /* RxD1 */ + {0, 11, 2, 0, 1, -1}, /* RxD2 */ + {0, 12, 2, 0, 1, -1}, /* RxD3 */ + {0, 7, 1, 0, 1, -1}, /* TX_EN */ + {0, 8, 1, 0, 1, -1}, /* TX_ER */ + {0, 15, 2, 0, 1, -1}, /* RX_DV */ + {0, 0, 2, 0, 1, -1}, /* RX_CLK */ + {2, 9, 1, 0, 3, -1}, /* GTX_CLK - CLK10 */ + {2, 8, 2, 0, 1, -1}, /* GTX125 - CLK9 */ /* UCC2 - UEC (Gigabit) */ - {0, 17, 1, 0, 1}, /* TxD0 */ - {0, 18, 1, 0, 1}, /* TxD1 */ - {0, 19, 1, 0, 1}, /* TxD2 */ - {0, 20, 1, 0, 1}, /* TxD3 */ - {0, 23, 2, 0, 1}, /* RxD0 */ - {0, 24, 2, 0, 1}, /* RxD1 */ - {0, 25, 2, 0, 1}, /* RxD2 */ - {0, 26, 2, 0, 1}, /* RxD3 */ - {0, 21, 1, 0, 1}, /* TX_EN */ - {0, 22, 1, 0, 1}, /* TX_ER */ - {0, 29, 2, 0, 1}, /* RX_DV */ - {0, 31, 2, 0, 1}, /* RX_CLK */ - {2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */ - {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ + {0, 17, 1, 0, 1, -1}, /* TxD0 */ + {0, 18, 1, 0, 1, -1}, /* TxD1 */ + {0, 19, 1, 0, 1, -1}, /* TxD2 */ + {0, 20, 1, 0, 1, -1}, /* TxD3 */ + {0, 23, 2, 0, 1, -1}, /* RxD0 */ + {0, 24, 2, 0, 1, -1}, /* RxD1 */ + {0, 25, 2, 0, 1, -1}, /* RxD2 */ + {0, 26, 2, 0, 1, -1}, /* RxD3 */ + {0, 21, 1, 0, 1, -1}, /* TX_EN */ + {0, 22, 1, 0, 1, -1}, /* TX_ER */ + {0, 29, 2, 0, 1, -1}, /* RX_DV */ + {0, 31, 2, 0, 1, -1}, /* RX_CLK */ + {2, 2, 1, 0, 2, -1}, /* GTX_CLK - CLK10 */ + {2, 3, 2, 0, 1, -1}, /* GTX125 - CLK4 */ /* UCC7 - UEC */ - {4, 0, 1, 0, 1}, /* TxD0 */ - {4, 1, 1, 0, 1}, /* TxD1 */ - {4, 2, 1, 0, 1}, /* TxD2 */ - {4, 3, 1, 0, 1}, /* TxD3 */ - {4, 6, 2, 0, 1}, /* RxD0 */ - {4, 7, 2, 0, 1}, /* RxD1 */ - {4, 8, 2, 0, 1}, /* RxD2 */ - {4, 9, 2, 0, 1}, /* RxD3 */ - {4, 4, 1, 0, 1}, /* TX_EN */ - {4, 5, 1, 0, 1}, /* TX_ER */ - {4, 12, 2, 0, 1}, /* RX_DV */ - {4, 13, 2, 0, 1}, /* RX_ER */ - {4, 10, 2, 0, 1}, /* COL */ - {4, 11, 2, 0, 1}, /* CRS */ - {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */ - {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */ + {4, 0, 1, 0, 1, -1}, /* TxD0 */ + {4, 1, 1, 0, 1, -1}, /* TxD1 */ + {4, 2, 1, 0, 1, -1}, /* TxD2 */ + {4, 3, 1, 0, 1, -1}, /* TxD3 */ + {4, 6, 2, 0, 1, -1}, /* RxD0 */ + {4, 7, 2, 0, 1, -1}, /* RxD1 */ + {4, 8, 2, 0, 1, -1}, /* RxD2 */ + {4, 9, 2, 0, 1, -1}, /* RxD3 */ + {4, 4, 1, 0, 1, -1}, /* TX_EN */ + {4, 5, 1, 0, 1, -1}, /* TX_ER */ + {4, 12, 2, 0, 1, -1}, /* RX_DV */ + {4, 13, 2, 0, 1, -1}, /* RX_ER */ + {4, 10, 2, 0, 1, -1}, /* COL */ + {4, 11, 2, 0, 1, -1}, /* CRS */ + {2, 18, 2, 0, 1, -1}, /* TX_CLK - CLK19 */ + {2, 19, 2, 0, 1, -1}, /* RX_CLK - CLK20 */ /* UCC4 - UEC */ - {1, 14, 1, 0, 1}, /* TxD0 */ - {1, 15, 1, 0, 1}, /* TxD1 */ - {1, 16, 1, 0, 1}, /* TxD2 */ - {1, 17, 1, 0, 1}, /* TxD3 */ - {1, 20, 2, 0, 1}, /* RxD0 */ - {1, 21, 2, 0, 1}, /* RxD1 */ - {1, 22, 2, 0, 1}, /* RxD2 */ - {1, 23, 2, 0, 1}, /* RxD3 */ - {1, 18, 1, 0, 1}, /* TX_EN */ - {1, 19, 1, 0, 2}, /* TX_ER */ - {1, 26, 2, 0, 1}, /* RX_DV */ - {1, 27, 2, 0, 1}, /* RX_ER */ - {1, 24, 2, 0, 1}, /* COL */ - {1, 25, 2, 0, 1}, /* CRS */ - {2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */ - {2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */ + {1, 14, 1, 0, 1, -1}, /* TxD0 */ + {1, 15, 1, 0, 1, -1}, /* TxD1 */ + {1, 16, 1, 0, 1, -1}, /* TxD2 */ + {1, 17, 1, 0, 1, -1}, /* TxD3 */ + {1, 20, 2, 0, 1, -1}, /* RxD0 */ + {1, 21, 2, 0, 1, -1}, /* RxD1 */ + {1, 22, 2, 0, 1, -1}, /* RxD2 */ + {1, 23, 2, 0, 1, -1}, /* RxD3 */ + {1, 18, 1, 0, 1, -1}, /* TX_EN */ + {1, 19, 1, 0, 2, -1}, /* TX_ER */ + {1, 26, 2, 0, 1, -1}, /* RX_DV */ + {1, 27, 2, 0, 1, -1}, /* RX_ER */ + {1, 24, 2, 0, 1, -1}, /* COL */ + {1, 25, 2, 0, 1, -1}, /* CRS */ + {2, 6, 2, 0, 1, -1}, /* TX_CLK - CLK7 */ + {2, 7, 2, 0, 1, -1}, /* RX_CLK - CLK8 */ /* PCI1 */ - {5, 4, 2, 0, 3}, /* PCI_M66EN */ - {5, 5, 1, 0, 3}, /* PCI_INTA */ - {5, 6, 1, 0, 3}, /* PCI_RSTO */ - {5, 7, 3, 0, 3}, /* PCI_C_BE0 */ - {5, 8, 3, 0, 3}, /* PCI_C_BE1 */ - {5, 9, 3, 0, 3}, /* PCI_C_BE2 */ - {5, 10, 3, 0, 3}, /* PCI_C_BE3 */ - {5, 11, 3, 0, 3}, /* PCI_PAR */ - {5, 12, 3, 0, 3}, /* PCI_FRAME */ - {5, 13, 3, 0, 3}, /* PCI_TRDY */ - {5, 14, 3, 0, 3}, /* PCI_IRDY */ - {5, 15, 3, 0, 3}, /* PCI_STOP */ - {5, 16, 3, 0, 3}, /* PCI_DEVSEL */ - {5, 17, 0, 0, 0}, /* PCI_IDSEL */ - {5, 18, 3, 0, 3}, /* PCI_SERR */ - {5, 19, 3, 0, 3}, /* PCI_PERR */ - {5, 20, 3, 0, 3}, /* PCI_REQ0 */ - {5, 21, 2, 0, 3}, /* PCI_REQ1 */ - {5, 22, 2, 0, 3}, /* PCI_GNT2 */ - {5, 23, 3, 0, 3}, /* PCI_GNT0 */ - {5, 24, 1, 0, 3}, /* PCI_GNT1 */ - {5, 25, 1, 0, 3}, /* PCI_GNT2 */ - {5, 26, 0, 0, 0}, /* PCI_CLK0 */ - {5, 27, 0, 0, 0}, /* PCI_CLK1 */ - {5, 28, 0, 0, 0}, /* PCI_CLK2 */ - {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */ - {6, 0, 3, 0, 3}, /* PCI_AD0 */ - {6, 1, 3, 0, 3}, /* PCI_AD1 */ - {6, 2, 3, 0, 3}, /* PCI_AD2 */ - {6, 3, 3, 0, 3}, /* PCI_AD3 */ - {6, 4, 3, 0, 3}, /* PCI_AD4 */ - {6, 5, 3, 0, 3}, /* PCI_AD5 */ - {6, 6, 3, 0, 3}, /* PCI_AD6 */ - {6, 7, 3, 0, 3}, /* PCI_AD7 */ - {6, 8, 3, 0, 3}, /* PCI_AD8 */ - {6, 9, 3, 0, 3}, /* PCI_AD9 */ - {6, 10, 3, 0, 3}, /* PCI_AD10 */ - {6, 11, 3, 0, 3}, /* PCI_AD11 */ - {6, 12, 3, 0, 3}, /* PCI_AD12 */ - {6, 13, 3, 0, 3}, /* PCI_AD13 */ - {6, 14, 3, 0, 3}, /* PCI_AD14 */ - {6, 15, 3, 0, 3}, /* PCI_AD15 */ - {6, 16, 3, 0, 3}, /* PCI_AD16 */ - {6, 17, 3, 0, 3}, /* PCI_AD17 */ - {6, 18, 3, 0, 3}, /* PCI_AD18 */ - {6, 19, 3, 0, 3}, /* PCI_AD19 */ - {6, 20, 3, 0, 3}, /* PCI_AD20 */ - {6, 21, 3, 0, 3}, /* PCI_AD21 */ - {6, 22, 3, 0, 3}, /* PCI_AD22 */ - {6, 23, 3, 0, 3}, /* PCI_AD23 */ - {6, 24, 3, 0, 3}, /* PCI_AD24 */ - {6, 25, 3, 0, 3}, /* PCI_AD25 */ - {6, 26, 3, 0, 3}, /* PCI_AD26 */ - {6, 27, 3, 0, 3}, /* PCI_AD27 */ - {6, 28, 3, 0, 3}, /* PCI_AD28 */ - {6, 29, 3, 0, 3}, /* PCI_AD29 */ - {6, 30, 3, 0, 3}, /* PCI_AD30 */ - {6, 31, 3, 0, 3}, /* PCI_AD31 */ + {5, 4, 2, 0, 3, -1}, /* PCI_M66EN */ + {5, 5, 1, 0, 3, -1}, /* PCI_INTA */ + {5, 6, 1, 0, 3, -1}, /* PCI_RSTO */ + {5, 7, 3, 0, 3, -1}, /* PCI_C_BE0 */ + {5, 8, 3, 0, 3, -1}, /* PCI_C_BE1 */ + {5, 9, 3, 0, 3, -1}, /* PCI_C_BE2 */ + {5, 10, 3, 0, 3, -1}, /* PCI_C_BE3 */ + {5, 11, 3, 0, 3, -1}, /* PCI_PAR */ + {5, 12, 3, 0, 3, -1}, /* PCI_FRAME */ + {5, 13, 3, 0, 3, -1}, /* PCI_TRDY */ + {5, 14, 3, 0, 3, -1}, /* PCI_IRDY */ + {5, 15, 3, 0, 3, -1}, /* PCI_STOP */ + {5, 16, 3, 0, 3, -1}, /* PCI_DEVSEL */ + {5, 17, 0, 0, 0, -1}, /* PCI_IDSEL */ + {5, 18, 3, 0, 3, -1}, /* PCI_SERR */ + {5, 19, 3, 0, 3, -1}, /* PCI_PERR */ + {5, 20, 3, 0, 3, -1}, /* PCI_REQ0 */ + {5, 21, 2, 0, 3, -1}, /* PCI_REQ1 */ + {5, 22, 2, 0, 3, -1}, /* PCI_GNT2 */ + {5, 23, 3, 0, 3, -1}, /* PCI_GNT0 */ + {5, 24, 1, 0, 3, -1}, /* PCI_GNT1 */ + {5, 25, 1, 0, 3, -1}, /* PCI_GNT2 */ + {5, 26, 0, 0, 0, -1}, /* PCI_CLK0 */ + {5, 27, 0, 0, 0, -1}, /* PCI_CLK1 */ + {5, 28, 0, 0, 0, -1}, /* PCI_CLK2 */ + {5, 29, 0, 0, 3, -1}, /* PCI_SYNC_OUT */ + {6, 0, 3, 0, 3, -1}, /* PCI_AD0 */ + {6, 1, 3, 0, 3, -1}, /* PCI_AD1 */ + {6, 2, 3, 0, 3, -1}, /* PCI_AD2 */ + {6, 3, 3, 0, 3, -1}, /* PCI_AD3 */ + {6, 4, 3, 0, 3, -1}, /* PCI_AD4 */ + {6, 5, 3, 0, 3, -1}, /* PCI_AD5 */ + {6, 6, 3, 0, 3, -1}, /* PCI_AD6 */ + {6, 7, 3, 0, 3, -1}, /* PCI_AD7 */ + {6, 8, 3, 0, 3, -1}, /* PCI_AD8 */ + {6, 9, 3, 0, 3, -1}, /* PCI_AD9 */ + {6, 10, 3, 0, 3, -1}, /* PCI_AD10 */ + {6, 11, 3, 0, 3, -1}, /* PCI_AD11 */ + {6, 12, 3, 0, 3, -1}, /* PCI_AD12 */ + {6, 13, 3, 0, 3, -1}, /* PCI_AD13 */ + {6, 14, 3, 0, 3, -1}, /* PCI_AD14 */ + {6, 15, 3, 0, 3, -1}, /* PCI_AD15 */ + {6, 16, 3, 0, 3, -1}, /* PCI_AD16 */ + {6, 17, 3, 0, 3, -1}, /* PCI_AD17 */ + {6, 18, 3, 0, 3, -1}, /* PCI_AD18 */ + {6, 19, 3, 0, 3, -1}, /* PCI_AD19 */ + {6, 20, 3, 0, 3, -1}, /* PCI_AD20 */ + {6, 21, 3, 0, 3, -1}, /* PCI_AD21 */ + {6, 22, 3, 0, 3, -1}, /* PCI_AD22 */ + {6, 23, 3, 0, 3, -1}, /* PCI_AD23 */ + {6, 24, 3, 0, 3, -1}, /* PCI_AD24 */ + {6, 25, 3, 0, 3, -1}, /* PCI_AD25 */ + {6, 26, 3, 0, 3, -1}, /* PCI_AD26 */ + {6, 27, 3, 0, 3, -1}, /* PCI_AD27 */ + {6, 28, 3, 0, 3, -1}, /* PCI_AD28 */ + {6, 29, 3, 0, 3, -1}, /* PCI_AD29 */ + {6, 30, 3, 0, 3, -1}, /* PCI_AD30 */ + {6, 31, 3, 0, 3, -1}, /* PCI_AD31 */ /* NAND */ - {4, 18, 2, 0, 0}, /* NAND_RYnBY */ + {4, 18, 2, 0, 0, -1}, /* NAND_RYnBY */ /* DUART - UART2 */ - {5, 0, 1, 0, 2}, /* UART2_SOUT */ - {5, 2, 1, 0, 1}, /* UART2_RTS */ - {5, 3, 2, 0, 2}, /* UART2_SIN */ - {5, 1, 2, 0, 3}, /* UART2_CTS */ + {5, 0, 1, 0, 2, -1}, /* UART2_SOUT */ + {5, 2, 1, 0, 1, -1}, /* UART2_RTS */ + {5, 3, 2, 0, 2, -1}, /* UART2_SIN */ + {5, 1, 2, 0, 3, -1}, /* UART2_CTS */ /* UCC5 - UART3 */ - {3, 0, 1, 0, 1}, /* UART3_TX */ - {3, 4, 1, 0, 1}, /* UART3_RTS */ - {3, 6, 2, 0, 1}, /* UART3_RX */ - {3, 12, 2, 0, 0}, /* UART3_CTS */ - {3, 13, 2, 0, 0}, /* UCC5_CD */ + {3, 0, 1, 0, 1, -1}, /* UART3_TX */ + {3, 4, 1, 0, 1, -1}, /* UART3_RTS */ + {3, 6, 2, 0, 1, -1}, /* UART3_RX */ + {3, 12, 2, 0, 0, -1}, /* UART3_CTS */ + {3, 13, 2, 0, 0, -1}, /* UCC5_CD */ /* UCC6 - UART4 */ - {3, 14, 1, 0, 1}, /* UART4_TX */ - {3, 18, 1, 0, 1}, /* UART4_RTS */ - {3, 20, 2, 0, 1}, /* UART4_RX */ - {3, 26, 2, 0, 0}, /* UART4_CTS */ - {3, 27, 2, 0, 0}, /* UCC6_CD */ + {3, 14, 1, 0, 1, -1}, /* UART4_TX */ + {3, 18, 1, 0, 1, -1}, /* UART4_RTS */ + {3, 20, 2, 0, 1, -1}, /* UART4_RX */ + {3, 26, 2, 0, 0, -1}, /* UART4_CTS */ + {3, 27, 2, 0, 0, -1}, /* UCC6_CD */ /* Fujitsu MB86277 (MINT) graphics controller */ - {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */ - {1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */ - {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */ - {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */ + {0, 30, 1, 0, 0, -1}, /* nSRESET_GRAPHICS */ + {1, 5, 1, 0, 0, -1}, /* nXRST_GRAPHICS */ + {1, 7, 1, 0, 0, -1}, /* LVDS_BKLT_CTR */ + {2, 16, 1, 0, 0, -1}, /* LVDS_BKLT_EN */ /* AD7843 ADC/Touchscreen controller */ {4, 14, 1, 0, 0}, /* SPI_nCS0 */ @@ -204,7 +204,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {4, 21, 1, 0, 0}, /* SUSPND */ /* END of table */ - {0, 0, 0, 0, QE_IOP_TAB_END}, + {0, 0, 0, 0, QE_IOP_TAB_END, -1}, }; int board_early_init_f(void) --- a/board/freescale/mpc8568mds/mpc8568mds.c 2008-03-28 01:49:12.000000000 +0200 +++ b/board/freescale/mpc8568mds/mpc8568mds.c 2008-03-30 15:57:57.592361000 +0300 @@ -37,64 +37,64 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ - {4, 10, 1, 0, 2}, /* TxD0 */ - {4, 9, 1, 0, 2}, /* TxD1 */ - {4, 8, 1, 0, 2}, /* TxD2 */ - {4, 7, 1, 0, 2}, /* TxD3 */ - {4, 23, 1, 0, 2}, /* TxD4 */ - {4, 22, 1, 0, 2}, /* TxD5 */ - {4, 21, 1, 0, 2}, /* TxD6 */ - {4, 20, 1, 0, 2}, /* TxD7 */ - {4, 15, 2, 0, 2}, /* RxD0 */ - {4, 14, 2, 0, 2}, /* RxD1 */ - {4, 13, 2, 0, 2}, /* RxD2 */ - {4, 12, 2, 0, 2}, /* RxD3 */ - {4, 29, 2, 0, 2}, /* RxD4 */ - {4, 28, 2, 0, 2}, /* RxD5 */ - {4, 27, 2, 0, 2}, /* RxD6 */ - {4, 26, 2, 0, 2}, /* RxD7 */ - {4, 11, 1, 0, 2}, /* TX_EN */ - {4, 24, 1, 0, 2}, /* TX_ER */ - {4, 16, 2, 0, 2}, /* RX_DV */ - {4, 30, 2, 0, 2}, /* RX_ER */ - {4, 17, 2, 0, 2}, /* RX_CLK */ - {4, 19, 1, 0, 2}, /* GTX_CLK */ - {1, 31, 2, 0, 3}, /* GTX125 */ + {4, 10, 1, 0, 2, -1}, /* TxD0 */ + {4, 9, 1, 0, 2, -1}, /* TxD1 */ + {4, 8, 1, 0, 2, -1}, /* TxD2 */ + {4, 7, 1, 0, 2, -1}, /* TxD3 */ + {4, 23, 1, 0, 2, -1}, /* TxD4 */ + {4, 22, 1, 0, 2, -1}, /* TxD5 */ + {4, 21, 1, 0, 2, -1}, /* TxD6 */ + {4, 20, 1, 0, 2, -1}, /* TxD7 */ + {4, 15, 2, 0, 2, -1}, /* RxD0 */ + {4, 14, 2, 0, 2, -1}, /* RxD1 */ + {4, 13, 2, 0, 2, -1}, /* RxD2 */ + {4, 12, 2, 0, 2, -1}, /* RxD3 */ + {4, 29, 2, 0, 2, -1}, /* RxD4 */ + {4, 28, 2, 0, 2, -1}, /* RxD5 */ + {4, 27, 2, 0, 2, -1}, /* RxD6 */ + {4, 26, 2, 0, 2, -1}, /* RxD7 */ + {4, 11, 1, 0, 2, -1}, /* TX_EN */ + {4, 24, 1, 0, 2, -1}, /* TX_ER */ + {4, 16, 2, 0, 2, -1}, /* RX_DV */ + {4, 30, 2, 0, 2, -1}, /* RX_ER */ + {4, 17, 2, 0, 2, -1}, /* RX_CLK */ + {4, 19, 1, 0, 2, -1}, /* GTX_CLK */ + {1, 31, 2, 0, 3, -1}, /* GTX125 */ /* GETH2 */ - {5, 10, 1, 0, 2}, /* TxD0 */ - {5, 9, 1, 0, 2}, /* TxD1 */ - {5, 8, 1, 0, 2}, /* TxD2 */ - {5, 7, 1, 0, 2}, /* TxD3 */ - {5, 23, 1, 0, 2}, /* TxD4 */ - {5, 22, 1, 0, 2}, /* TxD5 */ - {5, 21, 1, 0, 2}, /* TxD6 */ - {5, 20, 1, 0, 2}, /* TxD7 */ - {5, 15, 2, 0, 2}, /* RxD0 */ - {5, 14, 2, 0, 2}, /* RxD1 */ - {5, 13, 2, 0, 2}, /* RxD2 */ - {5, 12, 2, 0, 2}, /* RxD3 */ - {5, 29, 2, 0, 2}, /* RxD4 */ - {5, 28, 2, 0, 2}, /* RxD5 */ - {5, 27, 2, 0, 3}, /* RxD6 */ - {5, 26, 2, 0, 2}, /* RxD7 */ - {5, 11, 1, 0, 2}, /* TX_EN */ - {5, 24, 1, 0, 2}, /* TX_ER */ - {5, 16, 2, 0, 2}, /* RX_DV */ - {5, 30, 2, 0, 2}, /* RX_ER */ - {5, 17, 2, 0, 2}, /* RX_CLK */ - {5, 19, 1, 0, 2}, /* GTX_CLK */ - {1, 31, 2, 0, 3}, /* GTX125 */ - {4, 6, 3, 0, 2}, /* MDIO */ - {4, 5, 1, 0, 2}, /* MDC */ + {5, 10, 1, 0, 2, -1}, /* TxD0 */ + {5, 9, 1, 0, 2, -1}, /* TxD1 */ + {5, 8, 1, 0, 2, -1}, /* TxD2 */ + {5, 7, 1, 0, 2, -1}, /* TxD3 */ + {5, 23, 1, 0, 2, -1}, /* TxD4 */ + {5, 22, 1, 0, 2, -1}, /* TxD5 */ + {5, 21, 1, 0, 2, -1}, /* TxD6 */ + {5, 20, 1, 0, 2, -1}, /* TxD7 */ + {5, 15, 2, 0, 2, -1}, /* RxD0 */ + {5, 14, 2, 0, 2, -1}, /* RxD1 */ + {5, 13, 2, 0, 2, -1}, /* RxD2 */ + {5, 12, 2, 0, 2, -1}, /* RxD3 */ + {5, 29, 2, 0, 2, -1}, /* RxD4 */ + {5, 28, 2, 0, 2, -1}, /* RxD5 */ + {5, 27, 2, 0, 3, -1}, /* RxD6 */ + {5, 26, 2, 0, 2, -1}, /* RxD7 */ + {5, 11, 1, 0, 2, -1}, /* TX_EN */ + {5, 24, 1, 0, 2, -1}, /* TX_ER */ + {5, 16, 2, 0, 2, -1}, /* RX_DV */ + {5, 30, 2, 0, 2, -1}, /* RX_ER */ + {5, 17, 2, 0, 2, -1}, /* RX_CLK */ + {5, 19, 1, 0, 2, -1}, /* GTX_CLK */ + {1, 31, 2, 0, 3, -1}, /* GTX125 */ + {4, 6, 3, 0, 2, -1}, /* MDIO */ + {4, 5, 1, 0, 2, -1}, /* MDC */ /* UART1 */ - {2, 0, 1, 0, 2}, /* UART_SOUT1 */ - {2, 1, 1, 0, 2}, /* UART_RTS1 */ - {2, 2, 2, 0, 2}, /* UART_CTS1 */ - {2, 3, 2, 0, 2}, /* UART_SIN1 */ + {2, 0, 1, 0, 2, -1}, /* UART_SOUT1 */ + {2, 1, 1, 0, 2, -1}, /* UART_RTS1 */ + {2, 2, 2, 0, 2, -1}, /* UART_CTS1 */ + {2, 3, 2, 0, 2, -1}, /* UART_SIN1 */ - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END, -1}, /* END of table */ }; --- a/common/Makefile 2008-03-28 01:49:12.000000000 +0200 +++ b/common/Makefile 2008-03-30 15:59:57.944754000 +0300 @@ -81,6 +81,7 @@ COBJS-$(CONFIG_CMD_NET) += cmd_net.o COBJS-y += cmd_nvedit.o COBJS-y += cmd_onenand.o COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o +COBJS-$(CONFIG_CMD_PARIO) += cmd_pario.o ifdef CONFIG_PCI COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o endif 0a1,85 --- /dev/null 2008-03-30 10:13:32.378222985 +0300 +++ b/common/cmd_pario.c 2008-03-30 16:00:43.124433000 +0300 @@ -0,0 +1,85 @@ +/* + * Copyright 2008 ECI Telecommunication. + * + * (C) Copyright 2008 David Saada <david.saada(a)ecitele.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <ioports.h> + +int do_pario (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char op; + int port, pin, data; + static char last_op; + static int last_port, last_pin, last_data; + + /* + * We use the last specified parameters, unless new ones are + * entered. + */ + op = last_op; + port = last_port; + pin = last_pin; + data = last_data; + + if ((flag & CMD_FLAG_REPEAT) == 0) { + op = argv[1][0]; + + if (argc >= 3) + port = simple_strtoul (argv[2], NULL, 10); + if (argc >= 4) + pin = simple_strtoul (argv[3], NULL, 10); + if (argc >= 5) + data = simple_strtoul (argv[4], NULL, 10); + } + + if (op == 'r') { + qe_read_iopin(port ,pin ,&data); + printf("%d\n", data); + } else if (op == 'w') { + qe_write_iopin(port ,pin ,data); + } else { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* + * Save the parameters for repeats. + */ + last_op = op; + last_port = port; + last_pin = pin; + last_data = data; + + return 0; +} + +/***************************************************/ + +U_BOOT_CMD( + pario, 5, 1, do_pario, + "pario - Parallel I/O utility commands\n", + "read <port> <pin> - read from port <port> (0-5) pin <pin> (0-31)\n" + "pario write <port> <pin> <data> - write to port <port> (0-5) pin <pin> (0-31)\n" +); + -- View this message in context: http://www.nabble.com/-PATCH--resubmit--QE-IO%3A-Add-initial-data-to-pin-co… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] PCI stopped working on MPC8343
by Andre Schwarz 08 Jul '08

08 Jul '08

Last week my PCI bus has been running fine showing all devices. Right now no devices are shown on the bus. I'm using CONFIG_83XX_GENERIC_PCI with common setup code for PCI. Nothing changed from my side during the last 2 weeks. Did I miss any changes in u-boot ? regards, Andre Schwarz Matrix Vision MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

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