April 2008 - U-Boot

[U-Boot-Users] [PATCH] M18 flash (Sibley) support (attempt 2)
by Vasiliy Leoenenko 03 Jun '08

03 Jun '08

Hi Wolfgang, > Your patch was corrupted by your mailer which wrapped long lines. It > cannot be applied. Thank you very much for your reply. Gmail wrapped long lines. So I changed mail box. This is the second attempt. The patch was verified on different kinds of NOR using Mainstone II platform - no issues are found on u-boot (versions 1.3.0-rc1 and 1.3.0-rc2). Any comments and suggestions are welcome. Thanks, Signed-off-by: Vasiliy Leonenko <vasiliy.leonenko(a)mail.ru> Signed-off-by: Alexey Korolev <akorolex(a)gmail.com> ==================================================== --- u-boot-1.3.0-rc1.base/drivers/cfi_flash.c 2007-09-07 19:43:36.000000000 +0400 +++ u-boot-1.3.0-rc1/drivers/cfi_flash.c 2007-09-24 16:07:10.000000000 +0400 @@ -74,6 +74,7 @@ #define FLASH_CMD_PROTECT_CLEAR 0xD0 #define FLASH_CMD_CLEAR_STATUS 0x50 #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_TO_BUFFER_EXT 0xE9 #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 #define FLASH_STATUS_DONE 0x80 @@ -136,6 +137,7 @@ #define CFI_CMDSET_MITSU_STANDARD 256 #define CFI_CMDSET_MITSU_EXTENDED 257 #define CFI_CMDSET_SST 258 +#define CFI_CMDSET_INTEL_PROG_REGIONS 512 #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ # undef FLASH_CMD_RESET @@ -184,8 +186,8 @@ flash_info_t flash_info[CFG_MAX_FLASH_BA typedef unsigned long flash_sect_t; static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); -static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf); +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, ulong cmd); static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); @@ -474,6 +476,7 @@ int flash_erase (flash_info_t * info, in for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS); @@ -522,6 +525,9 @@ void flash_print_info (flash_info_t * in info->size >> 20, info->sector_count); printf (" "); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: + printf ("Intel Prog Regions"); + break; case CFI_CMDSET_INTEL_STANDARD: printf ("Intel Standard"); break; @@ -771,6 +777,7 @@ static int flash_is_busy (flash_info_t * int retval; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); @@ -825,6 +832,7 @@ static int flash_full_status_check (flas retcode = flash_status_check (info, sector, tout, prompt); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: if ((retcode == ERR_OK) @@ -903,7 +911,7 @@ static void flash_add_byte (flash_info_t /*----------------------------------------------------------------------- * make a proper sized command based on the port and chip widths */ -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf) { int i; uchar *cp = (uchar *) cmdbuf; @@ -913,13 +921,13 @@ static void flash_make_cmd (flash_info_t #else for (i = 1; i <= info->portwidth; i++) #endif - *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; + *cp++ = (i > info->chipwidth) ? '\0' : *((uchar *)&cmd + info->portwidth - i); } /* * Write a proper sized command to the correct address */ -static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, ulong cmd) { volatile cfiptr_t addr; @@ -1090,6 +1098,7 @@ static void flash_read_jedec_ids (flash_ info->device_id2 = 0; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); @@ -1209,6 +1218,7 @@ ulong flash_get_size (ulong base, int ba flash_printqry (info, 0); #endif switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: default: @@ -1289,6 +1299,7 @@ ulong flash_get_size (ulong base, int ba * Only read protection status from supported devices (intel...) */ switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: info->protect[sect_cnt] = @@ -1377,6 +1388,7 @@ static int flash_write_cfiword (flash_in flag = disable_interrupts (); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); @@ -1422,15 +1434,19 @@ static int flash_write_cfibuffer (flash_ int retcode; volatile cfiptr_t src; volatile cfiptr_t dst; + uchar write_cmd; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: src.cp = cp; dst.cp = (uchar *) dest; sector = find_sector (info, dest); + write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? + FLASH_CMD_WRITE_TO_BUFFER_EXT : FLASH_CMD_WRITE_TO_BUFFER; flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + flash_write_cmd (info, sector, 0, write_cmd); if ((retcode = flash_status_check (info, sector, info->buffer_write_tout, "write to buffer")) == ERR_OK) { /* reduce the number of loops by the width of the port */ @@ -1451,7 +1467,7 @@ static int flash_write_cfibuffer (flash_ return ERR_INVAL; break; } - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + flash_write_cmd (info, sector, 0, cnt - 1); while (cnt-- > 0) { switch (info->portwidth) { case FLASH_CFI_8BIT:

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[U-Boot-Users] Setting processor endianess for USB modules
by Christian Eggers 21 May '08

21 May '08

Hello, I've recognized that a lot of USB code in U-Boot uses the macros swap_16() and swap_32() which are defined in usb.h. The behaviour of the macros is controlled by the define LITTLEENDIAN. Is there a good reason NOT to use the macros provided in asm/byteorder.h (as in the appropriate code in Linux-2.4 )? I think that switching to these functions might be useful in order to eliminate the need to use the LITTLEENDIAN define for specifying the byteorder. It seems that LITTLEENDIAN is not used outside the USB code. regards Christian Eggers

3 3

[U-Boot-Users] Loading a kernel on MX31ADS using U-boot
by Fabio Estevam 15 May '08

15 May '08

Hi, I am using U-boot 1.3.2 with the MX31ADS patches posted by Guennadi Liakhovetski. I would like to load the zImage kernel from Freescale Linux BSP via TFTP and mount the rootfs via NFS. Does anyone have an example for doing this? I am not sure what address should I use to load the kernel into RAM. Thanks, Fabio Estevam __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

4 13

[U-Boot-Users] [PATCH] Remove $(VERSION_FILE) from PHONY Target List
by Grant Erickson 09 May '08

09 May '08

When building against non-local, non-disk-backed file systems (e.g. NFS, tmpfs), the u-boot build can iterate forever, attempting to re-generate "include/autoconf.mk". This occurs because $(VERSION_FILE) (aka ${ROOT}/u-boot/build/include/version_autogenerated.h) is always regarded as out-of-date because it is in the .PHONY target list, even though it's a real file and seems to need to be only created once and only once. This patch removes $(VERSION_FILE) from the .PHONY target list and has been verified to work with various flavors and builds of make-3.81 against NFS, ext2fs, ext3fs and tmpfs file systems. More detail at: http://sourceforge.net/mailarchive/message.php?msg_id=C4180895.E556%25gerick son%40nuovations.com Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> --- diff --git a/Makefile b/Makefile index e5b4210..50069b7 100644 --- a/Makefile +++ b/Makefile @@ -247,7 +247,7 LIBS += api/libapi.a LIBS := $(addprefix $(obj),$(LIBS)) -.PHONY : $(LIBS) $(VERSION_FILE) +.PHONY : $(LIBS) # Add GCC lib PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc

3 5

[U-Boot-Users] [PATCH v2 1/3] New i.MX31 SPI driver
by Guennadi Liakhovetski 09 May '08

09 May '08

This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far only implemented and tested on i.MX31, can with a modified register layout and definitions be used for i.MX27, I think, MXC CPUs have similar SPI controllers too. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- Changes since v1: fix a copy-paste error README | 5 + drivers/spi/Makefile | 1 + drivers/spi/mxc_spi.c | 166 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-mx31/mx31-regs.h | 7 +- include/spi.h | 16 +++- 5 files changed, 193 insertions(+), 2 deletions(-) create mode 100644 drivers/spi/mxc_spi.c diff --git a/README b/README index 7c16345..d201b92 100644 --- a/README +++ b/README @@ -1414,6 +1414,11 @@ The following options need to be configured: Currently supported on some MPC8xxx processors. For an example, see include/configs/mpc8349emds.h. + CONFIG_MXC_SPI + + Enables the driver for the SPI controllers on i.MX and MXC + SoCs. Currently only i.MX31 is supported. + - FPGA Support: CONFIG_FPGA Enables FPGA subsystem. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 0b7a2df..bc8a104 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.a COBJS-y += mpc8xxx_spi.o +COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c new file mode 100644 index 0000000..b2e3ab9 --- /dev/null +++ b/drivers/spi/mxc_spi.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <spi.h> +#include <asm/io.h> + +#ifdef CONFIG_MX27 +/* i.MX27 has a completely wrong register layout and register definitions in the + * datasheet, the correct one is in the Freescale's Linux driver */ + +#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ +"See linux mxc_spi driver from Freescale for details." + +#else + +#define MXC_CSPIRXDATA 0x00 +#define MXC_CSPITXDATA 0x04 +#define MXC_CSPICTRL 0x08 +#define MXC_CSPIINT 0x0C +#define MXC_CSPIDMA 0x10 +#define MXC_CSPISTAT 0x14 +#define MXC_CSPIPERIOD 0x18 +#define MXC_CSPITEST 0x1C +#define MXC_CSPIRESET 0x00 + +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) + +static unsigned long spi_bases[] = { + 0x43fa4000, + 0x50010000, + 0x53f84000, +}; + +static unsigned long spi_base; + +#endif + +spi_chipsel_type spi_chipsel[] = { + (spi_chipsel_type)0, + (spi_chipsel_type)1, + (spi_chipsel_type)2, + (spi_chipsel_type)3, +}; +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +static inline u32 reg_read(unsigned long addr) +{ + return *(volatile unsigned long*)addr; +} + +static inline void reg_write(unsigned long addr, u32 val) +{ + *(volatile unsigned long*)addr = val; +} + +static u32 spi_xchg_single(u32 data, int bitlen) +{ + + unsigned int cfg_reg = reg_read(spi_base + MXC_CSPICTRL); + + if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) { + cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) | + MXC_CSPICTRL_BITCOUNT(bitlen - 1); + reg_write(spi_base + MXC_CSPICTRL, cfg_reg); + } + + reg_write(spi_base + MXC_CSPITXDATA, data); + + cfg_reg |= MXC_CSPICTRL_XCH; + + reg_write(spi_base + MXC_CSPICTRL, cfg_reg); + + while (reg_read(spi_base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH) + ; + + return reg_read(spi_base + MXC_CSPIRXDATA); +} + +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +{ + int n_blks = (bitlen + 31) / 32; + u32 *out_l, *in_l; + int i; + + if ((int)dout & 3 || (int)din & 3) { + printf("Error: unaligned buffers in: %p, out: %p\n", din, dout); + return 1; + } + + if (!spi_base) + spi_select(CONFIG_MXC_SPI_IFACE, (int)chipsel, SPI_MODE_2 | SPI_CS_HIGH); + + for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; + i < n_blks; + i++, in_l++, out_l++, bitlen -= 32) + *in_l = spi_xchg_single(*out_l, bitlen); + + return 0; +} + +void spi_init(void) +{ +} + +int spi_select(unsigned int bus, unsigned int dev, unsigned long mode) +{ + unsigned int ctrl_reg; + + if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) || + dev > 3) + return 1; + + spi_base = spi_bases[bus]; + + ctrl_reg = MXC_CSPICTRL_CHIPSELECT(dev) | + MXC_CSPICTRL_BITCOUNT(31) | + MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ + MXC_CSPICTRL_EN | + MXC_CSPICTRL_MODE; + + if (mode & SPI_CPHA) + ctrl_reg |= MXC_CSPICTRL_PHA; + if (!(mode & SPI_CPOL)) + ctrl_reg |= MXC_CSPICTRL_POL; + if (mode & SPI_CS_HIGH) + ctrl_reg |= MXC_CSPICTRL_SSPOL; + + reg_write(spi_base + MXC_CSPIRESET, 1); + udelay(1); + reg_write(spi_base + MXC_CSPICTRL, ctrl_reg); + reg_write(spi_base + MXC_CSPIPERIOD, + MXC_CSPIPERIOD_32KHZ); + reg_write(spi_base + MXC_CSPIINT, 0); + + return 0; +} diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index 380b401..d04072e 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -37,6 +37,9 @@ #define CCM_UPCTL (CCM_BASE + 0x10) #define CCM_SPCTL (CCM_BASE + 0x18) #define CCM_COSR (CCM_BASE + 0x1C) +#define CCM_CGR0 (CCM_BASE + 0x20) +#define CCM_CGR1 (CCM_BASE + 0x24) +#define CCM_CGR2 (CCM_BASE + 0x28) #define CCMR_MDS (1 << 7) #define CCMR_SBYCS (1 << 4) @@ -118,7 +121,9 @@ #define MUX_CTL_RXD1 0x82 #define MUX_CTL_TXD1 0x83 #define MUX_CTL_CSPI2_MISO 0x84 -/* 0x85 .. 0x8a */ +#define MUX_CTL_CSPI2_SS0 0x85 +#define MUX_CTL_CSPI2_SS1 0x86 +#define MUX_CTL_CSPI2_SS2 0x87 #define MUX_CTL_CSPI2_MOSI 0x8b /* The modes a specific pin can be in diff --git a/include/spi.h b/include/spi.h index 03dc5bc..3a55a68 100644 --- a/include/spi.h +++ b/include/spi.h @@ -24,6 +24,18 @@ #ifndef _SPI_H_ #define _SPI_H_ +/* SPI mode flags */ +#define SPI_CPHA 0x01 /* clock phase */ +#define SPI_CPOL 0x02 /* clock polarity */ +#define SPI_MODE_0 (0|0) /* (original MicroWire) */ +#define SPI_MODE_1 (0|SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL|0) +#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_CS_HIGH 0x04 /* chipselect active high? */ +#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ +#define SPI_3WIRE 0x10 /* SI/SO signals shared */ +#define SPI_LOOP 0x20 /* loopback mode */ + /* * The function call pointer type used to drive the chip select. */ @@ -68,6 +80,8 @@ void spi_init(void); * * Returns: 0 on success, not 0 on failure */ -int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din); +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din); + +int spi_select(unsigned int bus, unsigned int dev, unsigned long mode); #endif /* _SPI_H_ */ -- 1.5.4

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Re: [U-Boot-Users] drivers MMCplus for at91sam9x
by Ken.Fuchs＠bench.com 08 May '08

08 May '08

I posted the following patch under a different subject line: Re: [U-Boot-Users] [PATCH] Add eSDHC driver > > --- u-boot_at91sam9260_mmc.patch (AT91 MCI driver) --- Pierre Savary wrote: > Thanks for that... but it's my own patch ;) > > Pierre =========================================================== Pierre, I hope you like this patch better. :) The following MMC v4 patch is for u-boot-1.1.5_atmel_1.2. To the AT91SAM9261 MCI device driver it adds support for MMC v4.x chips (MoviNAND in particular). The u-boot_at91sam9260_mmc.patch, previously send to this thread 23 April 2008 must be applied to u-boot-1.1.5_atmel_1.2, prior to applying the patch below. The patch includes lines "/* Ignore */". These are simply place holders for code that was not relevant to the MCI driver or MMC code. The patch is actually of four individual source files. Please let me know of any serious problems applying the patch. It should apply cleanly, but I didn't verify this. The MCI MMC v4 features contained in this patch work perfectly on our AT91SAM9261 board, except that I never got MMC 4 bit bus working (that code is omitted from this patch). Anyone know why the AT91SAM9261-EK doesn't appear to support 4 bit MMC? This patch may not work on AT91SAM9261-EK, since we modified the AT91SAM9261-EK board definitions rather than creating a new configuration and files for our board. Sincerely, Ken Fuchs u-boot-at91sam9261-mmc-v4.patch =============================== svn diff -r21 cpu/arm926ejs/at91sam926x/atmel_mci.c Index: cpu/arm926ejs/at91sam926x/atmel_mci.c =================================================================== --- cpu/arm926ejs/at91sam926x/atmel_mci.c (revision 21) +++ cpu/arm926ejs/at91sam926x/atmel_mci.c (working copy) @@ -1,4 +1,8 @@ /* + * (C) Copyright 2007-2008 + * Benchmark Electronics, Inc. + * Added MMC v4.x (MoviNAND) support + * * Copyright (C) 2004-2006 Atmel Corporation * * See file CREDITS for list of people who contributed to this @@ -34,21 +38,43 @@ #include <asm/arch/hardware.h> //klk #include "atmel_mci.h" -#undef DEBUG + +/* Ignore */ +/* Ignore */ +/* Ignore */ + +#if 0 +#define DEBUG +#else /* 0 */ +#undef DEBUG /* kf - was #undef */ +#endif /* 0 */ + #ifdef DEBUG #define pr_debug(fmt, args...) printf(fmt, ##args) #else #define pr_debug(...) do { } while(0) #endif +#undef CFG_MMC_CLK_OD +#define CFG_MMC_CLK_OD 375000 + #ifndef CFG_MMC_CLK_OD #define CFG_MMC_CLK_OD 375000 #endif +#undef CFG_MMC_CLK_PP +#define CFG_MMC_CLK_PP 20000000 + #ifndef CFG_MMC_CLK_PP #define CFG_MMC_CLK_PP 20000000 #endif +#undef CFG_MMC_OP_COND +#define CFG_MMC_OP_COND 0x80ff8000 +/* 0x80ff8080 works with 30+ sec. power off req */ +/* 0x00800000 works better, but write forever? */ +/* 0x00100000 works with 30+ sec. power off req */ + #ifndef CFG_MMC_OP_COND #define CFG_MMC_OP_COND 0x00100000 #endif @@ -74,8 +100,13 @@ bus_hz = AT91C_MASTER_CLOCK; clkdiv = (bus_hz / hz) / 2 - 1; +#if 1 + printf("mmc: setting clock %lu Hz, block size %lu\n", + hz, blklen); +#else /* 1 */ pr_debug("mmc: setting clock %lu Hz, block size %lu\n", hz, blklen); +#endif /* 1 */ if (clkdiv & ~255UL) { clkdiv = 255; @@ -84,10 +115,17 @@ } blklen &= 0xfffc; + +#if 1 /* AT91SAM9261 does not have RDPROOF and WRPROOF fields. */ mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv) + | MMCI_BF(BLKLEN, blklen))); +#else /* 1 */ + mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv) | MMCI_BF(BLKLEN, blklen) | MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF))); +#endif /* 1 */ + } #define RESP_NO_CRC 1 @@ -99,6 +137,7 @@ #define NCR MMCI_BF(MAXLAT, 1) #define TRCMD_START MMCI_BF(TRCMD, 1) #define TRDIR_READ MMCI_BF(TRDIR, 1) +#define TRDIR_WRITE MMCI_BF(TRDIR, 0) #define TRTYP_BLOCK MMCI_BF(TRTYP, 0) #define INIT_CMD MMCI_BF(SPCMD, 1) #define OPEN_DRAIN MMCI_BF(OPDCMD, 1) @@ -109,6 +148,20 @@ | MMCI_BIT(RINDE) \ | MMCI_BIT(RTOE)) +#if 0 +#define DEBUG +#else /* 0 */ +#undef DEBUG /* kf - was #undef */ +#endif /* 0 */ + +#undef pr_debug + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args) +#else +#define pr_debug(...) do { } while(0) +#endif + static int mmc_cmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) @@ -117,7 +170,9 @@ int i, response_words = 0; unsigned long error_flags; u32 status; - +#if 1 + pr_debug("mmc_cmd: entry\n"); +#endif /* 1 */ AT91F_MMC_Hardware_Init(); pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n", @@ -161,12 +216,28 @@ return 0; } +#if 0 +#define DEBUG +#else /* 0 */ +#undef DEBUG /* kf - was #undef */ +#endif /* 0 */ + +#undef pr_debug + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args) +#else +#define pr_debug(...) do { } while(0) +#endif + static int mmc_acmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) { unsigned long aresp[4]; int ret; + pr_debug("mmc_acmd: entry\n"); + /* * Seems like the APP_CMD part of an ACMD has 64 cycles max * latency even though the ACMD part doesn't. This isn't @@ -184,7 +255,16 @@ return ret; } -static unsigned long +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + +unsigned long mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, unsigned long *buffer) { @@ -193,7 +273,14 @@ unsigned long card_status, data; unsigned long wordcount; u32 status; + unsigned long *bufaddr; + pr_debug("mmc_bread: entry\n"); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("mmc: bread ret = %d, card status = %08x\n", ret, card_status); + + bufaddr = buffer; + if (blkcnt == 0) return 0; @@ -202,10 +289,16 @@ /* Put the device into Transfer state */ ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("mmc: bread ret = %d, card status = %08x\n", + ret, card_status); if (ret) goto fail; /* Set block length */ ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("mmc: bread ret = %d, card status = %08x\n", + ret, card_status); if (ret) goto fail; pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); @@ -228,7 +321,6 @@ if (status & MMCI_BIT(RXRDY)) { data = mmci_readl(RDR); - /* pr_debug("%x\n", data); */ *buffer++ = data; wordcount++; } @@ -240,12 +332,68 @@ status = mmci_readl(SR); } while (!(status & MMCI_BIT(BLKE))); - putc('.'); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, + &card_status, R1 | NCR); + pr_debug("mmc: bread ret = %d, card status = %08x\n", + ret, card_status); + + if (i % 0x800 == 0x7ff) { + putc('.'); /* Display '.', after each MB xfer'ed */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + } + +#if 0 + buffer = bufaddr; + wordcount = 0; + do { + if (wordcount % 8 == 0) { + pr_debug("\n%06lx:", 4 * wordcount); + } + pr_debug(" %08lx", *buffer++); + wordcount++; + } while (4 * wordcount < mmc_blkdev.blksz); + pr_debug("\n"); +#endif /* 0 */ + } out: /* Put the device back into Standby state */ mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("mmc: bread ret = %d, card status = %08x\n", ret, card_status); + if (i >= 0x7ff) { + putc('\n'); + } return i; fail: @@ -254,8 +402,329 @@ goto out; } +unsigned long +mmc_bwrite(int dev, unsigned long start, lbaint_t blkcnt, + unsigned long *buffer) +{ + int ret, i = 0; + unsigned long resp[4]; + unsigned long card_status, data; + unsigned long wordcount; + u32 status; + unsigned long *bufaddr; + + pr_debug("mmc_bwrite: entry\n"); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("en mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + + bufaddr = buffer; + + if (blkcnt == 0) + return 0; + + pr_debug("mmc_bwrite: dev %d, start %lx, blkcnt %lx\n", + dev, start, blkcnt); + + /* Put the device into Transfer state */ + ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("sc mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; + + /* Set block length */ + ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("bl mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; + + pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); + + for (i = 0; i < blkcnt; i++, start++) { + ret = mmc_cmd(MMC_CMD_WRITE_BLOCK, + start * mmc_blkdev.blksz, resp, + (R1 | NCR | TRCMD_START | TRDIR_WRITE + | TRTYP_BLOCK)); + if (ret) goto fail; + + ret = -EIO; + wordcount = 0; + do { + do { + status = mmci_readl(SR); + if (status & (ERROR_FLAGS | MMCI_BIT(UNRE))) + goto fail; + } while (!(status & MMCI_BIT(TXRDY))); + + if (status & MMCI_BIT(TXRDY)) { + data = *buffer++; + mmci_writel(TDR, data); + wordcount++; + } + } while(wordcount < (mmc_blkdev.blksz / 4)); + + pr_debug("mmc: write %u words, waiting for BLKE\n", wordcount); + + do { + status = mmci_readl(SR); + } while (!(status & MMCI_BIT(BLKE))); + + do { + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, + &card_status, R1 | NCR); + if ((card_status & 0x00000100) != 0x00000100) { +#if 0 + printf("lp mmc: bwrite ret = %d, ", ret); + printf("card status = %08x\n", card_status); +#endif /* 0 */ + } else { + pr_debug("lp mmc: bwrite ret = %d, ", ret); + pr_debug("card status = %08x\n", card_status); + } + } while ((card_status & 0x00000100) != 0x00000100); + + if (i % 0x800 == 0x7ff) { + putc('.'); /* Display '.', after each MB xfer'ed */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + } + +#if 0 + ret = mmc_cmd(MMC_CMD_STOP_TRANSMISSION, + 0, resp, + R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, + &card_status, R1 | NCR); + pr_debug("st mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; +#endif /* 0 */ + + } + +out: +#if 0 + ret = mmc_cmd(MMC_CMD_STOP_TRANSMISSION, + 0, resp, + R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("st mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; +#endif /* 0 */ + + /* Put the device back into Standby state */ + mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("dc mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + if (i >= 0x7ff) { + putc('\n'); + } + return i; + +fail: + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("fa mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + goto out; +} + + /* Hangs - did not attempt to debug */ +/* MMC Multiple Block Write - mmc_mbwrite() */ +unsigned long +mmc_mbwrite(int dev, unsigned long start, lbaint_t blkcnt, + unsigned long *buffer) +{ + int ret, i = 0; + unsigned long resp[4]; + unsigned long card_status, data; + unsigned long wordcount; + u32 status; + unsigned long *bufaddr; + + pr_debug("mmc_bwrite: entry\n"); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("en mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + + bufaddr = buffer; + + if (blkcnt == 0) + return 0; + + if (blkcnt > 0xffff) { /* Exceeds length supported by MoviNAND. */ + return -1; + } + + pr_debug("mmc_mbwrite: dev %d, start %lx, blkcnt %lx\n", + dev, start, blkcnt); + + /* Put the device into Transfer state */ + ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("sc mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; + + /* Set block length */ + ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("bl mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; + + pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); + + ret = mmc_cmd(MMC_CMD_SET_BLOCK_COUNT, + blkcnt, resp, + R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("bc mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; + + ret = mmc_cmd(MMC_CMD_WRITE_MULTIPLE_BLOCK, + start * mmc_blkdev.blksz, resp, + (R1 | NCR | TRCMD_START | TRDIR_WRITE | TRTYP_BLOCK)); + if (ret) goto fail; + + for (i = 0; i < blkcnt; i++, start++) { + + ret = -EIO; + wordcount = 0; + do { + do { + status = mmci_readl(SR); + if (status & (ERROR_FLAGS | MMCI_BIT(UNRE))) + goto fail; + } while (!(status & MMCI_BIT(TXRDY))); + + if (status & MMCI_BIT(TXRDY)) { + data = *buffer++; + mmci_writel(TDR, data); + wordcount++; + } + } while(wordcount < (mmc_blkdev.blksz / 4)); + +#if 1 + pr_debug("mmc: write %u words, waiting for BLKE\n", wordcount); + + do { + status = mmci_readl(SR); + } while (!(status & MMCI_BIT(BLKE))); +#endif /* 0 */ + + do { + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, + &card_status, R1 | NCR); + if ((card_status & 0x00000100) != 0x00000100) { +#if 0 + printf("lp mmc: mbwrite ret = %d, ", ret); + printf("card status = %08x\n", card_status); +#endif /* 0 */ + } else { + pr_debug("lp mmc: mbwrite ret = %d, ", ret); + pr_debug("card status = %08x\n", card_status); + } + } while ((card_status & 0x00000100) != 0x00000100); + + if (i % 0x800 == 0x7ff) { + putc('.'); /* Display '.', after each MB xfer'ed */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + } + } + +out: +#if 0 + ret = mmc_cmd(MMC_CMD_STOP_TRANSMISSION, + 0, resp, + R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("st mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; +#endif /* 0 */ + + /* Put the device back into Standby state */ + mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("dc mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + if (i >= 0x7ff) { + putc('\n'); + } + return i; + +fail: + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("fa mmc: mbwrite failed, card status = %08x\n", card_status); + goto out; +} + static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp) { + pr_debug("mmc_parse_cid: entry\n"); + cid->mid = resp[0] >> 24; cid->oid = (resp[0] >> 8) & 0xffff; cid->pnm[0] = resp[0]; @@ -272,6 +741,8 @@ static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) { + pr_debug("sd_parse_cid: entry\n"); + cid->mid = resp[0] >> 24; cid->oid = (resp[0] >> 8) & 0xffff; cid->pnm[0] = resp[0]; @@ -288,6 +759,8 @@ static void mmc_dump_cid(const struct mmc_cid *cid) { + pr_debug("mmc_dump_cid: entry\n"); + printf("Manufacturer ID: %02lX\n", cid->mid); printf("OEM/Application ID: %04lX\n", cid->oid); printf("Product name: %s\n", cid->pnm); @@ -301,6 +774,9 @@ static void mmc_dump_csd(const struct mmc_csd *csd) { unsigned long *csd_raw = (unsigned long *)csd; + + pr_debug("mmc_dump_csd: entry\n"); + pr_debug("CSD data: %08lx %08lx %08lx %08lx\n", csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]); pr_debug("CSD structure version: 1.%u\n", csd->csd_structure); @@ -337,6 +813,8 @@ { int ret; + pr_debug("mmc_idle_cards: entry\n"); + /* Reset and initialize all cards */ ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); @@ -352,6 +830,8 @@ unsigned long resp[4]; int i, ret = 0; + pr_debug("sd_init_card: entry\n"); + mmc_idle_cards(); for (i = 0; i < 1000; i++) { ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND, @@ -387,10 +867,40 @@ { unsigned long resp[4]; int i, ret = 0; + u32 status; + pr_debug("mmc_init_card: entry\n"); + mmc_idle_cards(); + /* MoviNAND initialization */ for (i = 0; i < 1000; i++) { + mmci_writel(ARGR, 0xFFFFFFFF); + mmci_writel(CMDR, 0x0018113F); + do { + status = mmci_readl(SR); + } while (!(status & MMCI_BIT(CMDRDY))); + } + /* Getting the OCR value seems to prevent marginal chips from */ + /* working at all, whereas they would work fine after waiting */ + /* a full minute or more with the power off prior to booting. */ + /* Our marginal chips have date codes 0716 and 0728. */ +#if 0 + for (i = 0; i < 1000; i++) { + /* Request OCR value to determine chip's supported volt. */ + ret = mmc_cmd(MMC_CMD_SEND_OP_COND, 0, resp, + R3 | NID | OPEN_DRAIN); + if (ret || (resp[0] & 0x80000000)) + { + break; + } + ret = -ETIMEDOUT; + } + if (ret) { + return ret; + } +#endif /* 0 */ + for (i = 0; i < 1000; i++) { ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp, R3 | NID | OPEN_DRAIN); if (ret || (resp[0] & 0x80000000)) @@ -399,13 +909,35 @@ } ret = -ETIMEDOUT; } + pr_debug("Step 4: ret = 0x%lx\n", ret); + pr_debug("MMC_CMD_SEND_OP_COND = 0x%lx\n", MMC_CMD_SEND_OP_COND); + pr_debug("CFG_MMC_OP_COND = 0x%lx\n", CFG_MMC_OP_COND); + pr_debug("resp[0] = 0x%lx\n", resp[0]); + pr_debug("resp[1] = 0x%lx\n", resp[1]); + pr_debug("resp[2] = 0x%lx\n", resp[2]); + pr_debug("resp[3] = 0x%lx\n", resp[3]); + pr_debug("R3 = 0x%lx\n", R3); + pr_debug("NID = 0x%lx\n", NID); + pr_debug("OPEN_DRAIN = 0x%lx\n", OPEN_DRAIN); + pr_debug("4\n"); pr_debug("ret : %i\n",ret); + + pr_debug("MCI_MR = 0x%08lx\n", mmci_readl(MR)); + pr_debug("MCI_DTOR = 0x%08lx\n", mmci_readl(DTOR)); + pr_debug("MCI_SDCR = 0x%08lx\n", mmci_readl(SDCR)); + pr_debug("MCI_ARGR = 0x%08lx\n", mmci_readl(ARGR)); + /* RSPR */ + /* RDR */ + pr_debug("MCI_SR = 0x%08lx\n", mmci_readl(SR)); + pr_debug("MCI_IMR = 0x%08lx\n", mmci_readl(IMR)); + if (ret) return ret; pr_debug("5\n"); /* Get CID of all cards. FIXME: Support more than one card */ ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN); + pr_debug("ALL_SEND_CID ret: 0x%08lx\n", ret); if (ret) return ret; mmc_parse_cid(cid, resp); @@ -415,6 +947,7 @@ /* Set Relative Address of the card that responded */ ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp, R1 | NCR | OPEN_DRAIN); + pr_debug("SET_RELATIVE_ADDR ret: 0x%08lx\n", ret); return ret; } @@ -471,23 +1004,42 @@ dtocyc << shift, dtor); } +#define DEFAULT_SECTOR_SIZE 512 + int mmc_init(int verbose) { struct mmc_cid cid; struct mmc_csd csd; unsigned int max_blksz; int ret,aux; + unsigned char buffer[DEFAULT_SECTOR_SIZE]; + pr_debug("mmc_init: entry\n"); + pr_debug("mmc_init: verbose = 0x%08lx\n", verbose); + AT91F_MMC_Hardware_Init(); pr_debug("0\n"); /* Initialize controller */ mmci_writel(CR, MMCI_BIT(SWRST)); mmci_writel(CR, MMCI_BIT(MCIEN)); + + pr_debug("MCI_MR = 0x%08lx\n", mmci_readl(MR)); + pr_debug("MCI_DTOR = 0x%08lx\n", mmci_readl(DTOR)); + pr_debug("MCI_SDCR = 0x%08lx\n", mmci_readl(SDCR)); + pr_debug("MCI_ARGR = 0x%08lx\n", mmci_readl(ARGR)); + /* RSPR */ + /* RDR */ + pr_debug("MCI_SR = 0x%08lx\n", mmci_readl(SR)); + pr_debug("MCI_IMR = 0x%08lx\n", mmci_readl(IMR)); + mmci_writel(DTOR, 0x5f); mmci_writel(IDR, ~0UL); mmci_writel(SDCR, 0x1); mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); +#if 0 + mmci_writel(MR, 0x02009B4A); +#endif /* 0 */ /* //mmci_writel(CR, MMCI_BIT(SWRST)); mmci_writel(CR, 0x00000001); mmci_writel(DTOR, 0x0000007F); @@ -502,6 +1054,7 @@ ret = sd_init_card(&cid, verbose); if (ret) { + pr_debug("Not SDCard, try MMC\n"); mmc_rca = MMC_DEFAULT_RCA; ret = mmc_init_card(&cid, verbose); } @@ -545,6 +1098,20 @@ mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz); #if 0 + mmc_bread(mmc_blkdev.dev, 1024, 1, (ulong *)buffer); + buffer[0] = 0x00; buffer[1] = 0x11; + buffer[2] = 0x22; buffer[3] = 0x33; + buffer[4] = 0x44; buffer[5] = 0x55; + buffer[6] = 0x66; buffer[7] = 0x77; + buffer[504] = 0x88; buffer[505] = 0x99; + buffer[506] = 0xaa; buffer[507] = 0xbb; + buffer[508] = 0xcc; buffer[509] = 0xdd; + buffer[510] = 0xee; buffer[511] = 0xff; + mmc_bwrite(mmc_blkdev.dev, 1024, 1, (ulong *)buffer); + mmc_bread(mmc_blkdev.dev, 1024, 1, (ulong *)buffer); +#endif /* 0 */ + +#if 0 if (fat_register_device(&mmc_blkdev, 1)) pr_debug("Could not register MMC fat device\n"); #else @@ -556,16 +1123,22 @@ int mmc_read(ulong src, uchar *dst, int size) { + pr_debug("mmc_read: entry\n"); + return -ENOSYS; } int mmc_write(uchar *src, ulong dst, int size) { + pr_debug("mmc_write: entry\n"); + return -ENOSYS; } int mmc2info(ulong addr) { + pr_debug("mmc2info: entry\n"); + return 0; } svn diff -r21 include/asm-arm/arch-at91sam926x/mmc.h Index: include/asm-arm/arch-at91sam926x/mmc.h =================================================================== --- include/asm-arm/arch-at91sam926x/mmc.h (revision 0) +++ include/asm-arm/arch-at91sam926x/mmc.h (revision 50) @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2007 + * Benchmark Electronics, Inc. + * Added MMC v4.x (MoviNAND) support + * + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AT91SAM926X_MMC_H +#define __ASM_AT91SAM926X_MMC_H + +struct mmc_cid { + unsigned long psn; + unsigned short oid; + unsigned char mid; + unsigned char prv; + unsigned char mdt; + char pnm[7]; +}; + +struct mmc_csd +{ + u8 csd_structure:2, + spec_vers:4, + rsvd1:2; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc:12, + read_bl_len:4; + u64 read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + sector_size:5, + erase_grp_size:5, + wp_grp_size:5, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:5; + u8 file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; + u8 crc:7; + u8 one:1; +}; + +/* MMC Command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_STOP_TRANSMISSION 12 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_SET_BLOCK_COUNT 23 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 +#define MMC_CMD_APP_CMD 55 + +#define MMC_ACMD_SD_SEND_OP_COND 41 + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#endif /* __ASM_AT91SAM926X_MMC_H */ svn diff -r21 include/configs/at91sam9261ek.h Index: include/configs/at91sam9261ek.h =================================================================== --- include/configs/at91sam9261ek.h (revision 21) +++ include/configs/at91sam9261ek.h (working copy) @@ -1,4 +1,8 @@ /* + * (C) Copyright 2007-2008 + * Benchmark Electronics, Inc. + * Added MMC v4.x (MoviNAND) support + * * (C) Copyright 2005 * M. Amine SAYA ATMEL Rousset, France. * @@ -95,18 +99,24 @@ /* SPI */ #define CONFIG_SPI +/* kf - define hush (from busy box) command line interface & options */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + #define CONFIG_COMMANDS \ ((CONFIG_CMD_DFL | \ CFG_CMD_NET | \ CFG_CMD_ENV | \ CFG_CMD_USB | \ CFG_CMD_FLASH | \ - CFG_CMD_NAND | \ + CFG_CMD_MMC | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FAT | \ CFG_CMD_NFS | \ CFG_CMD_SPI | \ - CFG_CMD_U | \ CFG_CMD_IMI | \ CFG_CMD_PING ) & \ ~(CFG_CMD_BDI | \ @@ -296,8 +306,12 @@ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ +#undef CFG_ENV_IS_IN_FLASH #define CFG_ENV_IS_IN_DATAFLASH 1 -#undef CFG_ENV_IS_IN_FLASH +#if 0 +#undef CFG_ENV_IS_IN_NAND +#endif /* 0 - kf */ +#undef CFG_ENV_IS_NOWHERE #ifdef CFG_ENV_IS_IN_DATAFLASH #define CFG_ENV_OFFSET 0x4000 @@ -305,6 +319,10 @@ #define CFG_ENV_SIZE 0x4000 /* 0x8000 */ #endif +#ifdef CFG_ENV_IS_NOWHERE +#define CFG_ENV_SIZE 0x4000 +#endif + #ifdef CFG_ENV_IS_IN_FLASH #ifdef CONFIG_BOOTBINFUNC #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ @@ -316,6 +334,9 @@ #endif /* Add LCD stuff */ +/* Ignore */ +/* Ignore */ + #if 0 /* No LCD */ #define CONFIG_LCD /* #undef CONFIG_LCD_LOGO */ @@ -333,8 +354,21 @@ #define CONFIG_DOS_PARTITION 1 #define LITTLEENDIAN 1 -#define CFG_LOAD_ADDR 0x23f00000 /* default load address */ +/* Add FAT filesystem configuration, other than CFG_CMD_FAT */ +#define CONFIG_SUPPORT_VFAT +/* MMC */ +#define CONFIG_MMC 1 +#define MMCI_BASE 0xFFFA8000 /* (void *)AT91C_BASE_MCI */ +/* MMC - kf - slow down speed for debug from 20000000 Hz down to ... */ +/* However, tweaking this value here causes all code to be compiled, */ +/* so we shall change the value only where needed - in atmel_mci.c. */ +#define CFG_MMC_CLK_PP 20000000 + +#define CFG_LOAD_ADDR 0x23f00000 /* default load address */ + +#define CFG_BOOTM_LEN 0x02100000 /* 33MB uncompressed max. */ + #ifdef CONFIG_BOOTBINFUNC #define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ #define CFG_U_BOOT_BASE PHYS_FLASH_1 svn diff -r21 board/at91sam9261ek/at91sam9261ek.c Index: board/at91sam9261ek/at91sam9261ek.c =================================================================== --- board/at91sam9261ek/at91sam9261ek.c (revision 21) +++ board/at91sam9261ek/at91sam9261ek.c (working copy) @@ -1,4 +1,8 @@ /* + * (C) Copyright 2007-2008 + * Benchmark Electronics, Inc. + * Added specific AT91SAM9261 board support + * * (C) Copyright 2005 * M. Amine SAYA ATMEL Rousset, France. * Added AT91SAM9261EK support. @@ -28,12 +32,19 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch-at91sam926x/at91sam9261.h> #include <net.h> extern void AT91F_Spi1Init (void); extern void gpio_init(void); +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + /* ------------------------------------------------------------------------ - */ /* * Miscelaneous platform dependent initialisations @@ -107,7 +118,8 @@ *AT91C_PMC_PCER |= 1 << AT91C_ID_US0; /* enable clock */ #endif -#ifdef CONFIG_USART1 +#if 1 + /* #ifdef CONFIG_USART1 */ *AT91C_PIOB_PDR = AT91C_PC12_TXD1 | AT91C_PC13_RXD1; *AT91C_PMC_PCER |= 1 << AT91C_ID_US1; /* enable clock */ #endif @@ -118,6 +130,41 @@ #endif } +#ifdef CONFIG_MMC +#if (CONFIG_COMMANDS & CFG_CMD_MMC) +int AT91F_MMC_Hardware_Init(void) +{ +#if 0 + printf("AT91F_MMC_Hardware_Init: entry\n"); +#endif /* 0 */ + + AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, + 0, /* <- Peripheral A */ + (AT91C_PA0_MCDA0 | /* MMC NAND MCDA0 */ + AT91C_PA1_MCCDA | /* MMC NAND MCCDA */ + AT91C_PA2_MCCK | /* MMC NAND MCCK */ + AT91C_PA4_MCDA1 | /* MMC NAND MCDA1 */ + AT91C_PA5_MCDA2 | /* MMC NAND MCDA2 */ + AT91C_PA6_MCDA3 | /* MMC NAND MCDA3 */ + 0)); /* <- Peripheral B */ + +#if 1 + /* Pull up disable register */ + AT91C_BASE_PIOA->PIO_PPUDR |= + AT91C_PA0_MCDA0 | /* MMC NAND MCDA0 */ + AT91C_PA1_MCCDA | /* MMC NAND MCCDA */ + AT91C_PA2_MCCK | /* MMC NAND MCCK */ + AT91C_PA4_MCDA1 | /* MMC NAND MCDA1 */ + AT91C_PA5_MCDA2 | /* MMC NAND MCDA2 */ + AT91C_PA6_MCDA3; /* MMC NAND MCDA3 */ +#endif /* 0 */ + + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_MCI); +} +#endif /* CONFIG_COMMANDS & CFG_CMD_MMC */ +#endif /* CONFIG_MMC */ + + int dram_init (void) { DECLARE_GLOBAL_DATA_PTR; @@ -148,5 +195,35 @@ gpio_init(); +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + return 0; }

6 8

[U-Boot-Users] [PATCH] ColdFire: Get information from the correct GCC
by Tsi-Chung Liew 06 May '08

06 May '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: Kurt Mahan <kmahan(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- cpu/mcf5227x/config.mk | 2 +- cpu/mcf523x/config.mk | 2 +- cpu/mcf52x2/config.mk | 2 +- cpu/mcf532x/config.mk | 2 +- cpu/mcf5445x/config.mk | 2 +- cpu/mcf547x_8x/config.mk | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cpu/mcf5227x/config.mk b/cpu/mcf5227x/config.mk index 8d60fd6..2e50696 100644 --- a/cpu/mcf5227x/config.mk +++ b/cpu/mcf5227x/config.mk @@ -24,7 +24,7 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifeq ($(findstring 4.2,$(shell $(CROSS_COMPILE)gcc --version)),4.2) PLATFORM_CPPFLAGS += -mcpu=5208 -fPIC else PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/cpu/mcf523x/config.mk b/cpu/mcf523x/config.mk index 93645a3..73fb08d 100644 --- a/cpu/mcf523x/config.mk +++ b/cpu/mcf523x/config.mk @@ -24,7 +24,7 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifeq ($(findstring 4.2,$(shell $(CROSS_COMPILE)gcc --version)),4.2) PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC else PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk index 650e340..be360f8 100644 --- a/cpu/mcf52x2/config.mk +++ b/cpu/mcf52x2/config.mk @@ -34,7 +34,7 @@ is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg)) is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg)) -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifeq ($(findstring 4.2,$(shell $(CROSS_COMPILE)gcc --version)),4.2) ifneq (,$(findstring CONFIG_M5249,$(is5249))) PLATFORM_CPPFLAGS += -mcpu=5249 diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk index 16a0bc3..e4a3cf9 100644 --- a/cpu/mcf532x/config.mk +++ b/cpu/mcf532x/config.mk @@ -24,7 +24,7 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifeq ($(findstring 4.2,$(shell $(CROSS_COMPILE)gcc --version)),4.2) PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC else PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/cpu/mcf5445x/config.mk b/cpu/mcf5445x/config.mk index 88433f2..a85d0f9 100644 --- a/cpu/mcf5445x/config.mk +++ b/cpu/mcf5445x/config.mk @@ -24,7 +24,7 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifeq ($(findstring 4.2,$(shell $(CROSS_COMPILE)gcc --version)),4.2) PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC else PLATFORM_CPPFLAGS += -m5407 -fPIC diff --git a/cpu/mcf547x_8x/config.mk b/cpu/mcf547x_8x/config.mk index e5f4385..eb6b50b 100644 --- a/cpu/mcf547x_8x/config.mk +++ b/cpu/mcf547x_8x/config.mk @@ -24,7 +24,7 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifeq ($(findstring 4.2,$(shell $(CROSS_COMPILE)gcc --version)),4.2) PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC else PLATFORM_CPPFLAGS += -m5407 -fPIC -- 1.5.4.1

5 20

[U-Boot-Users] [PATCH] add config options for VSC8601 RGMII PHY - 2nd try
by Andre Schwarz 05 May '08

05 May '08

The Vitesse VSC8601 RGMII PHY has internal delay for both Rx and Tx clock lines. They are configured using 2 bits in extended register 0x17. Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay. Signed-off-by: Andre Schwarz <andre.schwarz(a)matrix-vision.de> -- drivers/net/tsec.c | 6 ++++++ drivers/net/tsec.h | 3 +++ 2 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9d22aa3..06250ae 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1277,6 +1277,12 @@ struct phy_info phy_info_VSC8601 = { {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, #ifdef CFG_VSC8601_SKEWFIX {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, +#if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX) + {MIIM_EXT_PAGE_ACCESS,1,NULL}, +#define VSC8101_SKEW (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12) + {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, + {MIIM_EXT_PAGE_ACCESS,0,NULL}, +#endif #endif {miim_end,} }, diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h index cfa7d1a..213a809 100644 --- a/drivers/net/tsec.h +++ b/drivers/net/tsec.h @@ -112,6 +112,8 @@ #define MIIM_GBIT_CONTROL 0x9 #define MIIM_GBIT_CONTROL_INIT 0xe00 +#define MIIM_EXT_PAGE_ACCESS 0x1f + /* Broadcom BCM54xx -- taken from linux sungem_phy */ #define MIIM_BCM54xx_AUXSTATUS 0x19 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 @@ -163,6 +165,7 @@ /* Vitesse VSC8601 Extended PHY Control Register 1 */ #define MIIM_VSC8601_EPHY_CON 0x17 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120 +#define MIIM_VSC8601_SKEW_CTRL 0x1c /* 88E1011 PHY Status Register */ #define MIIM_88E1011_PHY_STATUS 0x11 MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

6 5

[U-Boot-Users] ppc4xx: Unable to clone git repository from denx
by Niklaus Giger 05 May '08

05 May '08

Hi I wanted to get Stefan's git and got the following error: > $ git clone http://www.denx.de/git/u-boot-ppc4xx.git/ work <...> > Getting pack list for http://www.denx.de/u-boot.git/ > error: Unable to find f616ab96cc773d1719761d511a8649c9aa6eb473 under > http://www.denx.de/git/u-boot-ppc4xx.git Cannot obtain needed blob > f616ab96cc773d1719761d511a8649c9aa6eb473 while processing commit > 60bbcad0e2e7007a36a1cb42c664b0662ae0c9f1. It would be nice if this error could be fixed. But I will go home for the weekend in a few minutes. Best regards Niklaus

2 3

[U-Boot-Users] 1.3.3-rc2 - release status
by Wolfgang Denk 03 May '08

03 May '08

Hello, U-Boot v1.3.3-rc2 has just been released. PowerPC seems to be in a pretty good state now; other architectures still need a lot of testing / fixing. For example, on ARM we see the following conflicts: Configuring for kb9202 board... start.S: Assembler messages: start.S:205: Error: invalid constant -- `sub r0,r0,#(0x0200+128*1024)' start.S:378: Error: invalid constant -- `sub r13,r13,#((32*1024)+(0x0200+128*1024))' start.S:379: Error: invalid constant -- `sub r2,r2,#((32*1024)+(0x0200+128*1024))' start.S:384: Error: invalid constant -- `sub r13,r13,#((32*1024)+(0x0200+128*1024))' start.S:385: Error: invalid constant -- `sub r2,r2,#((32*1024)+(0x0200+128*1024))' start.S:390: Error: invalid constant -- `sub r13,r13,#((32*1024)+(0x0200+128*1024))' start.S:391: Error: invalid constant -- `sub r2,r2,#((32*1024)+(0x0200+128*1024))' start.S:396: Error: invalid constant -- `sub r13,r13,#((32*1024)+(0x0200+128*1024))' start.S:397: Error: invalid constant -- `sub r2,r2,#((32*1024)+(0x0200+128*1024))' start.S:402: Error: invalid constant -- `sub r13,r13,#((32*1024)+(0x0200+128*1024))' start.S:403: Error: invalid constant -- `sub r2,r2,#((32*1024)+(0x0200+128*1024))' start.S:427: Error: invalid constant -- `sub r13,r13,#((32*1024)+(0x0200+128*1024))' start.S:428: Error: invalid constant -- `sub r2,r2,#((32*1024)+(0x0200+128*1024))' start.S:433: Error: invalid constant -- `sub r13,r13,#((32*1024)+(0x0200+128*1024))' start.S:434: Error: invalid constant -- `sub r2,r2,#((32*1024)+(0x0200+128*1024))' make[1]: *** [start.o] Error 1 Configuring for netstar board... arm-linux-ld: cannot find -lgeneric make[1]: *** [eeprom.srec] Error 1 Configuring for voiceblue board... arm-linux-ld: cannot find -lgeneric make[1]: *** [eeprom.srec] Error 1 Configuring for apollon board... onenand_base.c:25: error: static declaration of 'memcpy' follows non-static declaration /home/wd/git/u-boot/master/include/linux/string.h:70: error: previous declaration of 'memcpy' was here make[1]: *** [onenand_base.o] Error 1 Configuring for adsvix board... start.S:183:1: warning: "ICMR" redefined In file included from start.S:33: /home/wd/git/u-boot/master/include/asm/arch/pxa-regs.h:935:1: warning: this is the location of the previous definition start.S:187:1: warning: "RCSR" redefined /home/wd/git/u-boot/master/include/asm/arch/pxa-regs.h:1602:1: warning: this is the location of the previous definition start.S:191:1: warning: "OSMR3" redefined /home/wd/git/u-boot/master/include/asm/arch/pxa-regs.h:869:1: warning: this is the location of the previous definition start.S:192:1: warning: "OSCR" redefined /home/wd/git/u-boot/master/include/asm/arch/pxa-regs.h:870:1: warning: this is the location of the previous definition start.S:193:1: warning: "OWER" redefined /home/wd/git/u-boot/master/include/asm/arch/pxa-regs.h:872:1: warning: this is the location of the previous definition start.S:194:1: warning: "OIER" redefined /home/wd/git/u-boot/master/include/asm/arch/pxa-regs.h:873:1: warning: this is the location of the previous definition start.S:207:1: warning: "CCCR" redefined /home/wd/git/u-boot/master/include/asm/arch/pxa-regs.h:1770:1: warning: this is the location of the previous definition pcmcia.c:39:2: warning: #warning "Board will only supply 5V, wait for next HW spin for selectable power" pxa_pcmcia.c: In function 'pcmcia_on': pxa_pcmcia.c:39: warning: operation on 'i' may be undefined cmd_ide.c: In function '__ide_outb': cmd_ide.c:828: warning: implicit declaration of function 'outb' cmd_ide.c: In function '__ide_inb': cmd_ide.c:837: warning: implicit declaration of function 'inb' common/libcommon.a(cmd_ide.o): In function `__ide_outb': /home/wd/git/u-boot/master/common/cmd_ide.c:828: undefined reference to `outb' common/libcommon.a(cmd_ide.o): In function `__ide_inb': /home/wd/git/u-boot/master/common/cmd_ide.c:837: undefined reference to `inb' make: *** [u-boot] Error 1 Configuring for actux4 board... actux4.c: In function 'board_init': actux4.c:83: warning: left shift count >= width of type actux4.c:83: warning: left shift count >= width of type Configuring for davinci_schmoogie board... env_nand.c: In function 'saveenv': env_nand.c:200: warning: passing argument 3 of 'nand_write' from incompatible pointer type env_nand.c: In function 'env_relocate_spec': env_nand.c:275: warning: passing argument 3 of 'nand_read' from incompatible pointer type Board maintainers / custodians - please help! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de If programming was easy, they wouldn't need something as complicated as a human being to do it, now would they? - L. Wall & R. L. Schwartz, _Programming Perl_

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