March 2008 - U-Boot

[U-Boot-Users] MPC83xx HRCW
by Andre Schwarz 28 Mar '08

28 Mar '08

In "cpu/mpc83xx/start.S" there is a comment : /* * The Hard Reset Configuration Word (HRCW) table is in the first 64 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 * times so the processor can fetch it out of flash whether the flash * is 8, 16, 32, or 64 bits wide (hardware trickery). */ This does _not_ hold true for all configurations. Flash is simply one of many options ... Maybe it's true for the Freescale boards. Other sources of the HRCW can be hard-coded strapping pins or an I2C EEPROM. Why is there a need to define the HRCW ? regards, Andre Schwarz Matrix Vision MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

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[U-Boot-Users] [Fwd: Re: LZMA support (patch)]
by Luigi 'Comio' Mantellini 28 Mar '08

28 Mar '08

Hi Wolfgang, > In message <1206724722.23627.28.camel@localhost> you wrote: >> >> this patch adds the lzma support with the following >> constraints: >> >> - it doesn't install the LZMA SDK files. I provide the >> import_lzma.sh >> script to import the needs file from a lzma sdk release > > Sorry, but I will not accept this. > > U-Boot has always been self-contained, and I don't intend to > change > this. Running the contained script the directory will be populated with all need files (LzmaTypes.h, LzmaDecode.*). Anyway, I can resubmit the patch including all files. The LZMA SDK is released under LGPL with exceptions but I don't understand if the license is compatible with the u-boot's license. For this reason I omitted the sources from the SDK. > > Please make sure that a patch contains all files that belong to > it. > > Also, please explain what this new code is useful for. So far I > don;t > see any real-life use cases ? > > LMZA performs better than LZ on binary files. I will switch to LZMA to save flash memory space on my appliance. Of course, the LZMA is slower than LZ. Anyway, if the LZMA SDK license is compatible with U-boot , I think that LZMA should be chosen by firmware developer when the flash memory space is a critical resource. My 2 Cents, luigi > Best regards, > > Wolfgang Denk > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev > Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, > Germany > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: > wd(a)denx.de > "I like your game but we have to change the rules." >

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[U-Boot-Users] [PATCH 3/3] mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) code
by Kim Phillips 28 Mar '08

28 Mar '08

in the spirit of commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6, 85xx's "Update SVR numbers to expand support", simplify SPRIDR processing and processor ID display. Add REVID_{MAJ,MIN}OR macros to make REVID dependent code simpler. Also added PARTID_NO_E and IS_E_PROCESSOR convenience macros. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- board/freescale/mpc8360emds/mpc8360emds.c | 11 +-- board/freescale/mpc837xerdb/mpc837xerdb.c | 15 +-- cpu/mpc83xx/cpu.c | 169 ++++++++--------------------- include/mpc83xx.h | 91 +++++----------- 4 files changed, 84 insertions(+), 202 deletions(-) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index d90cdb3..2119320 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -98,11 +98,8 @@ int board_early_init_f(void) /* Enable flash write */ bcsr[0xa] &= ~0x04; - /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */ - if (immr->sysconf.spridr == SPR_8360_REV20 || - immr->sysconf.spridr == SPR_8360E_REV20 || - immr->sysconf.spridr == SPR_8360_REV21 || - immr->sysconf.spridr == SPR_8360E_REV21) + /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */ + if (REVID_MAJOR(immr->sysconf.spridr) == 2) bcsr[0xe] = 0x30; /* Enable second UART */ @@ -308,8 +305,8 @@ void ft_board_setup(void *blob, bd_t *bd) * if on mpc8360ea rev. 2.1, * change both ucc phy-connection-types from rgmii-id to rgmii-rxid */ - if (immr->sysconf.spridr == SPR_8360_REV21 || - immr->sysconf.spridr == SPR_8360E_REV21) { + if ((REVID_MAJOR(immr->sysconf.spridr) == 2) && + (REVID_MINOR(immr->sysconf.spridr) == 1)) { int nodeoffset; const char *prop; int path; diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 83fb60d..e054f4e 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -140,24 +140,21 @@ int board_early_init_f(void) u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ - switch (spridr >> 16) { - case SPR_8379E_REV10 >> 16: - case SPR_8379_REV10 >> 16: + switch (PARTID_NO_E(spridr)) { + case SPR_8377: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; - case SPR_8378E_REV10 >> 16: - case SPR_8378_REV10 >> 16: + case SPR_8378: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; - case SPR_8377E_REV10 >> 16: - case SPR_8377_REV10 >> 16: + case SPR_8379: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; default: diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index bff3cef..c878268 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -35,6 +35,32 @@ DECLARE_GLOBAL_DATA_PTR; +struct cpu_type { + char name[15]; + u32 partid; +}; + +#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} + +struct cpu_type cpu_type_list [] = { + CPU_TYPE_ENTRY(8311), + CPU_TYPE_ENTRY(8313), + CPU_TYPE_ENTRY(8314), + CPU_TYPE_ENTRY(8315), + CPU_TYPE_ENTRY(8321), + CPU_TYPE_ENTRY(8323), + CPU_TYPE_ENTRY(8343), + CPU_TYPE_ENTRY(8347_TBGA_), + CPU_TYPE_ENTRY(8347_PBGA_), + CPU_TYPE_ENTRY(8349), + CPU_TYPE_ENTRY(8358_TBGA_), + CPU_TYPE_ENTRY(8358_PBGA_), + CPU_TYPE_ENTRY(8360), + CPU_TYPE_ENTRY(8377), + CPU_TYPE_ENTRY(8378), + CPU_TYPE_ENTRY(8379), +}; + int checkcpu(void) { volatile immap_t *immr; @@ -42,6 +68,7 @@ int checkcpu(void) u32 pvr = get_pvr(); u32 spridr; char buf[32]; + int i; immr = (immap_t *)CFG_IMMR; @@ -69,130 +96,26 @@ int checkcpu(void) } spridr = immr->sysconf.spridr; - switch(spridr) { - case SPR_8349E_REV10: - case SPR_8349E_REV11: - case SPR_8349E_REV31: - puts("MPC8349E, "); - break; - case SPR_8349_REV10: - case SPR_8349_REV11: - case SPR_8349_REV31: - puts("MPC8349, "); - break; - case SPR_8347E_REV10_TBGA: - case SPR_8347E_REV11_TBGA: - case SPR_8347E_REV31_TBGA: - case SPR_8347E_REV10_PBGA: - case SPR_8347E_REV11_PBGA: - case SPR_8347E_REV31_PBGA: - puts("MPC8347E, "); - break; - case SPR_8347_REV10_TBGA: - case SPR_8347_REV11_TBGA: - case SPR_8347_REV31_TBGA: - case SPR_8347_REV10_PBGA: - case SPR_8347_REV11_PBGA: - case SPR_8347_REV31_PBGA: - puts("MPC8347, "); - break; - case SPR_8343E_REV10: - case SPR_8343E_REV11: - case SPR_8343E_REV31: - puts("MPC8343E, "); - break; - case SPR_8343_REV10: - case SPR_8343_REV11: - case SPR_8343_REV31: - puts("MPC8343, "); - break; - case SPR_8360E_REV10: - case SPR_8360E_REV11: - case SPR_8360E_REV12: - case SPR_8360E_REV20: - case SPR_8360E_REV21: - puts("MPC8360E, "); - break; - case SPR_8360_REV10: - case SPR_8360_REV11: - case SPR_8360_REV12: - case SPR_8360_REV20: - case SPR_8360_REV21: - puts("MPC8360, "); - break; - case SPR_8323E_REV10: - case SPR_8323E_REV11: - puts("MPC8323E, "); - break; - case SPR_8323_REV10: - case SPR_8323_REV11: - puts("MPC8323, "); - break; - case SPR_8321E_REV10: - case SPR_8321E_REV11: - puts("MPC8321E, "); - break; - case SPR_8321_REV10: - case SPR_8321_REV11: - puts("MPC8321, "); - break; - case SPR_8311_REV10: - puts("MPC8311, "); - break; - case SPR_8311E_REV10: - puts("MPC8311E, "); - break; - case SPR_8313_REV10: - puts("MPC8313, "); - break; - case SPR_8313E_REV10: - puts("MPC8313E, "); - break; - case SPR_8315E_REV10: - puts("MPC8315E, "); - break; - case SPR_8315_REV10: - puts("MPC8315, "); - break; - case SPR_8314E_REV10: - puts("MPC8314E, "); - break; - case SPR_8314_REV10: - puts("MPC8314, "); - break; - case SPR_8379E_REV10: - puts("MPC8379E, "); - break; - case SPR_8379_REV10: - puts("MPC8379, "); - break; - case SPR_8378E_REV10: - puts("MPC8378E, "); - break; - case SPR_8378_REV10: - puts("MPC8378, "); - break; - case SPR_8377E_REV10: - puts("MPC8377E, "); - break; - case SPR_8377_REV10: - puts("MPC8377, "); - break; - default: - printf("Rev: Unknown revision number:%08x\n" - "Warning: Unsupported cpu revision!\n",spridr); - return 0; - } -#if defined(CONFIG_MPC834X) - /* Multiple revisons of 834x processors may have the same SPRIDR value. - * So use PVR to identify the revision number. - */ - printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock)); -#else - printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock)); -#endif - printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000); + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { + puts("MPC"); + puts(cpu_type_list[i].name); + if (IS_E_PROCESSOR(spridr)) + puts("E"); + if (REVID_MAJOR(spridr) >= 2) + puts("A"); + printf(", Rev: %d.%d", REVID_MAJOR(spridr), + REVID_MINOR(spridr)); + break; + } + + if (i == ARRAY_SIZE(cpu_type_list)) + printf("(SPRIDR %08x unknown), ", spridr); + + printf(" at %s MHz, ", strmhz(buf, clock)); + + printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk)); return 0; } diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 4ee38aa..d2e1e2b 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -48,71 +48,36 @@ /* SPRIDR - System Part and Revision ID Register */ -#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ -#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ - -#define SPR_8349E_REV10 0x80300100 -#define SPR_8349_REV10 0x80310100 -#define SPR_8347E_REV10_TBGA 0x80320100 -#define SPR_8347_REV10_TBGA 0x80330100 -#define SPR_8347E_REV10_PBGA 0x80340100 -#define SPR_8347_REV10_PBGA 0x80350100 -#define SPR_8343E_REV10 0x80360100 -#define SPR_8343_REV10 0x80370100 - -#define SPR_8349E_REV11 0x80300101 -#define SPR_8349_REV11 0x80310101 -#define SPR_8347E_REV11_TBGA 0x80320101 -#define SPR_8347_REV11_TBGA 0x80330101 -#define SPR_8347E_REV11_PBGA 0x80340101 -#define SPR_8347_REV11_PBGA 0x80350101 -#define SPR_8343E_REV11 0x80360101 -#define SPR_8343_REV11 0x80370101 - -#define SPR_8349E_REV31 0x80300300 -#define SPR_8349_REV31 0x80310300 -#define SPR_8347E_REV31_TBGA 0x80320300 -#define SPR_8347_REV31_TBGA 0x80330300 -#define SPR_8347E_REV31_PBGA 0x80340300 -#define SPR_8347_REV31_PBGA 0x80350300 -#define SPR_8343E_REV31 0x80360300 -#define SPR_8343_REV31 0x80370300 - -#define SPR_8360E_REV10 0x80480010 -#define SPR_8360_REV10 0x80490010 -#define SPR_8360E_REV11 0x80480011 -#define SPR_8360_REV11 0x80490011 -#define SPR_8360E_REV12 0x80480012 -#define SPR_8360_REV12 0x80490012 -#define SPR_8360E_REV20 0x80480020 -#define SPR_8360_REV20 0x80490020 -#define SPR_8360E_REV21 0x80480021 -#define SPR_8360_REV21 0x80490021 - -#define SPR_8323E_REV10 0x80620010 -#define SPR_8323_REV10 0x80630010 -#define SPR_8321E_REV10 0x80660010 -#define SPR_8321_REV10 0x80670010 -#define SPR_8323E_REV11 0x80620011 -#define SPR_8323_REV11 0x80630011 -#define SPR_8321E_REV11 0x80660011 -#define SPR_8321_REV11 0x80670011 - -#define SPR_8313E_REV10 0x80B00010 -#define SPR_8313_REV10 0x80B10010 -#define SPR_8311E_REV10 0x80B20010 -#define SPR_8311_REV10 0x80B30010 -#define SPR_8315E_REV10 0x80B40010 -#define SPR_8315_REV10 0x80B50010 -#define SPR_8314E_REV10 0x80B60010 -#define SPR_8314_REV10 0x80B70010 - -#define SPR_8379E_REV10 0x80C20010 -#define SPR_8379_REV10 0x80C30010 -#define SPR_8378E_REV10 0x80C40010 -#define SPR_8378_REV10 0x80C50010 -#define SPR_8377E_REV10 0x80C60010 -#define SPR_8377_REV10 0x80C70010 +#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Id */ + +#if defined(CONFIG_MPC834X) +#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) +#define REVID_MINOR(spridr) (spridr & 0x000000FF) +#else +#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) +#define REVID_MINOR(spridr) (spridr & 0x0000000F) +#endif + +#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) +#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) /* has SEC */ + +#define SPR_8311 0x80B2 +#define SPR_8313 0x80B0 +#define SPR_8314 0x80B6 +#define SPR_8315 0x80B4 +#define SPR_8321 0x8066 +#define SPR_8323 0x8062 +#define SPR_8343 0x8036 +#define SPR_8347_TBGA_ 0x8032 +#define SPR_8347_PBGA_ 0x8034 +#define SPR_8349 0x8030 +#define SPR_8358_TBGA_ 0x804A +#define SPR_8358_PBGA_ 0x804E +#define SPR_8360 0x8048 +#define SPR_8377 0x80C6 +#define SPR_8378 0x80C4 +#define SPR_8379 0x80C2 /* SPCR - System Priority Configuration Register */ -- 1.5.4.4.481.g5075

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[U-Boot-Users] [PATCH] mpc8323erdb: define CONFIG_PCI_SKIP_HOST_BRIDGE
by Michael Barkowski 28 Mar '08

28 Mar '08

Commit 55774b512fdf63c0516d441cc5da7c54bbffb7f2 broke the onboard USB controller on the PCI bus in Linux on the MPC8323ERDB. This fixes it by defining CONFIG_PCI_SKIP_HOST_BRIDGE in the board's config file. Signed-off-by: Michael Barkowski <michael.barkowski(a)freescale.com> --- Kim, please consider this for 1.3.3, as well as the previously posted "mpc8323erdb: fix EEPROM page size and get MAC from EEPROM". regards, Michael include/configs/MPC8323ERDB.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 3775465..92d7aa4 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -344,7 +344,7 @@ #define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */ #ifdef CONFIG_PCI - +#define CONFIG_PCI_SKIP_HOST_BRIDGE #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -- 1.5.3.6

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[U-Boot-Users] Is any i.MX21 board supported?
by Leon Woestenberg 28 Mar '08

28 Mar '08

Hello, I wonder if u-boot supports any i.MX21 board? http://www.denx.de/wiki/UBoot/PatchStatus mentions that "PATCH] Support for csb535fs / i.MX21 LiteKit." has been merged in the main tree, but I could not find it. Regards, -- Leon

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[U-Boot-Users] [PATCH v4] ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"
by Stefan Roese 28 Mar '08

28 Mar '08

If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of ram and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux board ports in arch/powerpc with bootwrapper support, that recalculate the memory size from the SDRAM controller setup will have to get fixed. This patch enables this config option on some PPC440EPx boards as a workaround for the CHIP 11 errata. Here the description from the AMCC documentation: CHIP_11: End of memory range area restricted access. Category: 3 Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus. Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU. Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux. This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: lwmon5, korat, sequoia The other remaining 440EPx board were intentionally not included since it is not clear to me, if they use the end of ram for some other purpose. This is unclear, since these boards have CONFIG_PRAM defined and even comments like this: PMC440.h: /* esd expects pram at end of physical memory. * So no logbuffer at the moment. */ It is strongly recommendet to not use the last 256 bytes on those boards too. Patches from the board maintainers are welcome. Signed-off-by: Stefan Roese <sr(a)denx.de> --- Changes in this version v4: - Add CFG_MEM_TOP_HIDE decription to README Changes in this version v3: - Changed value of CFG_MEM_TOP_HIDE from 256 to 4k so that memory end location is on a page boundary - Rebased on current git version Changes in this version v2: - Changed name of define to CFG_MEM_TOP_HIDE README | 21 +++++++++++++++++++++ include/configs/korat.h | 2 ++ include/configs/lwmon5.h | 2 ++ include/configs/sequoia.h | 4 +++- lib_ppc/board.c | 13 +++++++++++++ 5 files changed, 41 insertions(+), 1 deletions(-) diff --git a/README b/README index 0e37b8b..4c7bf95 100644 --- a/README +++ b/README @@ -1854,6 +1854,27 @@ Configuration Settings: Scratch address used by the alternate memory test You only need to set this if address zero isn't writeable +- CFG_MEM_TOP_HIDE (PPC only): + If CFG_MEM_TOP_HIDE is defined in the board config header, + this specified memory area will get subtracted from the top + (end) of ram and won't get "touched" at all by U-Boot. By + fixing up gd->ram_size the Linux kernel should gets passed + the now "corrected" memory size and won't touch it either. + This should work for arch/ppc and arch/powerpc. Only Linux + board ports in arch/powerpc with bootwrapper support, that + recalculate the memory size from the SDRAM controller setup + will have to get fixed. + + This option can be used as a workaround for the 440EPx/GRx + CHIP 11 errata where the last 256 bytes in SDRAM shouldn't + be touched. + + WARNING: Please make sure that this value is a multiple of + the Linux page size (normally 4k). If this is not the case, + then the end address of the Linux memory will be located at a + non page size aligned address and this could cause mayor + problems. + - CFG_TFTP_LOADADDR: Default load address for network file downloads diff --git a/include/configs/korat.h b/include/configs/korat.h index dcec9b0..de672ea 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -144,6 +144,8 @@ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB #define CFG_DRAM_TEST +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /* * I2C diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index ced7ba6..3056cb0 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -86,6 +86,8 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) /* unused GPT0 COMP reg */ +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /* Additional registers for watchdog timer post test */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index dfa8779..555316f 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -221,6 +221,8 @@ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /* * I2C @@ -275,7 +277,7 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ "flash_nfs=run nfsargs addip addtty addmisc;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty addmisc;" \ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 3ab22f8..f0a2c87 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -425,6 +425,7 @@ void board_init_f (ulong bootflag) * relocate the code and continue running from DRAM. * * Reserve memory at end of RAM for (top down in that order): + * - area that won't get touched by U-Boot and Linux (optional) * - kernel log buffer * - protected RAM * - LCD framebuffer @@ -433,6 +434,18 @@ void board_init_f (ulong bootflag) */ len = (ulong)&_end - CFG_MONITOR_BASE; + /* + * Subtract specified amount of memory to hide so that it won't + * get "touched" at all by U-Boot. By fixing up gd->ram_size + * the Linux kernel should now get passed the now "corrected" + * memory size and won't touch it either. This should work + * for arch/ppc and arch/powerpc. Only Linux board ports in + * arch/powerpc with bootwrapper support, that recalculate the + * memory size from the SDRAM controller setup will have to + * get fixed. + */ + gd->ram_size -= CFG_MEM_TOP_HIDE; + #ifndef CONFIG_MAX_MEM_MAPPED #define CONFIG_MAX_MEM_MAPPED (256 << 20) #endif -- 1.5.4.4

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[U-Boot-Users] PPC4xx: Build problem in u-boot-ppc4xx
by Larry Johnson 28 Mar '08

28 Mar '08

Hi Stefan, You may have found this already, but as of 1600 UTC 28 March, the tip of the u-boot-pcc4xx fork breaks when building U-Boot for the Korat board on my system (Kubuntu 7.10, ELDK 4.1). The tip of the u-boot main repository builds OK. Replacing the file "include/libfdt_env.h in the u-boot-ppc4xx code with the version from the main repository appears to fix the problem. Best regards, Larry

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[U-Boot-Users] [PATCH][resend] ColdFire: Fix alignment issue after CONFIG_IDENT_STRING in start.S
by Tsi-Chung Liew 28 Mar '08

28 Mar '08

When the version_string function in start.S is not 4-byte align, it will cause the compiler generates "unaligned opcodes detected in executable segment". This issue affects all ColdFire CPUs. By adding .align 4 after CONFIG_IDENT_STRING, it will pad 0's if it is not aligned. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- cpu/mcf5227x/start.S | 1 + cpu/mcf523x/start.S | 1 + cpu/mcf52x2/start.S | 1 + cpu/mcf532x/start.S | 1 + cpu/mcf5445x/start.S | 1 + cpu/mcf547x_8x/start.S | 1 + 6 files changed, 6 insertions(+), 0 deletions(-) diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S index 0e2db12..1b47c97 100644 --- a/cpu/mcf5227x/start.S +++ b/cpu/mcf5227x/start.S @@ -354,3 +354,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S index 2bd603d..ad04c09 100644 --- a/cpu/mcf523x/start.S +++ b/cpu/mcf523x/start.S @@ -338,3 +338,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 9e496a4..2bc0df3 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -476,3 +476,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index 61be2ea..a524f70 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -333,3 +333,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index d64c5af..0c5194a 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -379,3 +379,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S index 442665f..c12d7a0 100644 --- a/cpu/mcf547x_8x/start.S +++ b/cpu/mcf547x_8x/start.S @@ -359,3 +359,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 -- 1.5.4.1

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[U-Boot-Users] CS8900 Problem on an ARM system
by Guennadi Liakhovetski 28 Mar '08

28 Mar '08

Hi all yet another problem from me. This time with the cs8900 driver. Macroscopic error description: immediately after booting, the first (typically) 2 packets are not received. E.g., if a ping is issued, two ARP requests go out, can be seen on the network, are replied, but the driver doesn't receive anything - rx status register still returns "no data". The next and all following pings work fine. In case of tftp similarly replies to the first two ARP packets are not received, after further repeats it works. If after power on I just wait for one minute without doing anything (network inactive too), then the network works from the very first packet. If at the time, when the first ping is issued I put some traffic on the network, e.g., some broadcasts, the driver starts receiving data immediately too. I tried putting the chip in promiscuous mode to see whether the problem is, that the chip doesn't identify packets as matching its ethernet address, but the board is on a switch. Any ideas? Thanks Guennadi --- Guennadi Liakhovetski, Ph.D. DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de

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[U-Boot-Users] Ayssa votre voyante : vous dévoile les secrets D'amour, Chance, Argent et Santé
by Cabinet.Alyssa＠topnet.tn 28 Mar '08

28 Mar '08

Alyssa vient d'avoir un flash intéressant pour vous. l'intonation de votre voix est nécéssaire . Contactez moi au : 08 92 35 01 06 (France) 0901 901 900 (Suisse) Je vous dévoile les secrets et les surprises. Contactez Alyssa au : 08 92 35 01 06 (France) 0901 901 900 (Suisse) *********************************************************** C'est un message Automatique. En cas de réponse veuiller repondre sur cette adresse : Alyssa.Voyante(a)gmail.com

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