November 2008 - U-Boot

[U-Boot] program exception trap 700
by raj shekar 24 Nov '08

24 Nov '08

I am working on mpc8548cds board … Feature : POST DIAGNOSTICS; In u-boot : post/memory.c,cpu.c..etc.. Need your suggestion… There is function pointers in post.c which calls the respective function to perform diag test ( example ram , cpu, ether ..etc ) which will be picked from tests.c ( This is the structure which defines all the fileds of the tests) Function pointer defined in post.c static int post_run_single (struct post_test *test, int test_flags, int flags, unsigned int i) { … .. if ((*test->test) (flags) != 0) { ( This function pointers will call cpu tests from post/cpu.c defined below based tested entered from u-boot promt ) post_log ("FAILED\n") } else { post_log ("PASSED\n") } ------------------------------------------------------------------------------------------------------------ CASE 1 Experiment : Post/cpu.c int cpu_post_test (int flags) { int ic = icache_status (); int ret = 0; int c; post_result_cpu = 0; cpu_dbg = 0; boot_flag_post = 0; printf( “ Testing cpu diag \n”); à TRAP IS Generated and box got rebooted. Other part of code exits.. } >From u-boot prompt. =>diag run cpu By log I verfied that this TRAP is generated from the post/cpu.c because of printf NIP: 00000000 XER: 00000000 LR: FFF25C40 REGS: 3feed878 TRAP: 0700 DAR: 00000004 MSR: 00029200 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 00000004 3FEED968 00000200 3FEEDA18 3FEEDA18 3FEEDA08 FFFFFFF4 00000007 GPR08: 00000000 00000000 FFFFFFFF 3FEED918 44028042 00000000 3FFBBC00 00000000 GPR16: 00000000 00000000 00000000 00000000 00000000 3FEF0378 00000003 0000000C GPR24: 3FEF0350 00000600 00000002 00000600 3FEEDA18 3FEEDF90 FFF4D3BC 00000000 ** Illegal Instruction ** Call backtrace: 3FF73310 FFF25DB8 FFF25E38 FFF338A0 3FFA2FAC 3FFA3564 3FF8D620 3FF98820 3FF98E98 3FF99000 3FF8AE44 3FF81DA8 3FF72628 Program Check Exception NIPÞ CASE 2 Experiment: Post/cpu.c int cpu_post_test (int flags) { int ic = icache_status (); int ret = 0; int c; post_result_cpu = 0; cpu_dbg = 0; boot_flag_post = 0; < Removed or commented the printf statement > return 0; NO TRAP is Generated. . } Another approach to validate the post/cpu.c fuction. Is working correctly or not. In file post.c Declared this API and directly called cpu_post_test(flags) before the function pointers. This API executed correctly with out a TRAP and results were displayed correctly. extern int cpu_post_test (int flags); static int post_run_single (struct post_test *test, int test_flags, int flags, unsigned int i) { ret = cpu_post_test(flags); #if 0 if ((*test->test) (flags) != 0) { post_log ("FAILED\n") } else { post_log ("PASSED\n") } #iendif Could u please let me know how do I avoid this TRAP when I am using the function pointers.. CASE 1 Experiment: Regards, Rajshekar

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[U-Boot] ppc405ep boot freeze with u-boot 1.3.4
by Reto Stalder 23 Nov '08

23 Nov '08

Hi I have a custom ppc405ep board with 128MB SDRAM, very similar to the AMCC Taihu board. U-Boot 1.1.4 works perfectly fine. But version 1.3.4 freezes after saying "Relocating now" in debug mode. Additionally, I've observed a strange effect concerning memory size: When a BDI2000 emulator is connected and the SDRAM size is set to 64MB or less, the board starts to the prompt. When a BDI2000 emulator is connected and the SDRAM size is set to 128MB, it freezes as well. Has somebody any ideas, where the problem could reside, or what else to do, to isolate the problem? Every comment is welcome ;-), Reto

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[U-Boot] program exception trap 700
by raj shekar 23 Nov '08

23 Nov '08

I am working on mpc8548cds board … Feature : POST DIAGNOSTICS; In u-boot : post/memory.c,cpu.c..etc.. Need your suggestion… There is function pointers in post.c which calls the respective function to perform diag test ( example ram , cpu, ether ..etc ) which will be picked from tests.c ( This is the structure which defines all the fileds of the tests) Function pointer defined in post.c static int post_run_single (struct post_test *test, int test_flags, int flags, unsigned int i) { … .. if ((*test->test) (flags) != 0) { ( This function pointers will call cpu tests from post/cpu.c defined below based tested entered from u-boot promt ) post_log ("FAILED\n") } else { post_log ("PASSED\n") } ------------------------------------------------------------------------------------------------------------ CASE 1 Experiment : Post/cpu.c int cpu_post_test (int flags) { int ic = icache_status (); int ret = 0; int c; post_result_cpu = 0; cpu_dbg = 0; boot_flag_post = 0; printf( “ Testing cpu diag \n”); à TRAP IS Generated and box got rebooted. Other part of code exits.. } >From u-boot prompt. =>diag run cpu By log I verfied that this TRAP is generated from the post/cpu.c because of printf NIP: 00000000 XER: 00000000 LR: FFF25C40 REGS: 3feed878 TRAP: 0700 DAR: 00000004 MSR: 00029200 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 00000004 3FEED968 00000200 3FEEDA18 3FEEDA18 3FEEDA08 FFFFFFF4 00000007 GPR08: 00000000 00000000 FFFFFFFF 3FEED918 44028042 00000000 3FFBBC00 00000000 GPR16: 00000000 00000000 00000000 00000000 00000000 3FEF0378 00000003 0000000C GPR24: 3FEF0350 00000600 00000002 00000600 3FEEDA18 3FEEDF90 FFF4D3BC 00000000 ** Illegal Instruction ** Call backtrace: 3FF73310 FFF25DB8 FFF25E38 FFF338A0 3FFA2FAC 3FFA3564 3FF8D620 3FF98820 3FF98E98 3FF99000 3FF8AE44 3FF81DA8 3FF72628 Program Check Exception NIPÞ CASE 2 Experiment: Post/cpu.c int cpu_post_test (int flags) { int ic = icache_status (); int ret = 0; int c; post_result_cpu = 0; cpu_dbg = 0; boot_flag_post = 0; < Removed or commented the printf statement > return 0; NO TRAP is Generated. . } Another approach to validate the post/cpu.c fuction. Is working correctly or not. In file post.c Declared this API and directly called cpu_post_test(flags) before the function pointers. This API executed correctly with out a TRAP and results were displayed correctly. extern int cpu_post_test (int flags); static int post_run_single (struct post_test *test, int test_flags, int flags, unsigned int i) { ret = cpu_post_test(flags); #if 0 if ((*test->test) (flags) != 0) { post_log ("FAILED\n") } else { post_log ("PASSED\n") } #iendif Could u please let me know how do I avoid this TRAP when I am using the function pointers.. CASE 1 Experiment: Regards, Rajshekar

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[U-Boot] TRAP 700 to understand
by raj shekar 23 Nov '08

23 Nov '08

Hi Could u pelease help in understanding thsi trap. NIP: 00000000 XER: 00000000 LR: FFF25C40 REGS: 3feed878 TRAP: 0700 DAR: 00000004 MSR: 00029200 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 00000004 3FEED968 00000200 3FEEDA18 3FEEDA18 3FEEDA08 FFFFFFF4 00000007 GPR08: 00000000 00000000 FFFFFFFF 3FEED918 44028042 00000000 3FFBBC00 00000000 GPR16: 00000000 00000000 00000000 00000000 00000000 3FEF0378 00000003 0000000C GPR24: 3FEF0350 00000600 00000002 00000600 3FEEDA18 3FEEDF90 FFF4D3BC 00000000 ** Illegal Instruction ** Call backtrace: 3FF73310 FFF25DB8 FFF25E38 FFF338A0 3FFA2FAC 3FFA3564 3FF8D620 3FF98820 3FF98E98 3FF99000 3FF8AE44 3FF81DA8 3FF72628 Program Check Exception NIPÞ

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[U-Boot] [PATCH-OMAP3] OMAP3: Fix merge error in omap3 header
by Dirk Behme 22 Nov '08

22 Nov '08

Fix merge error. Signed-off-by: Dirk Behme <dirk.behme(a)googlemail.com> --- Jean-Christophe: Regarding http://lists.denx.de/pipermail/u-boot/2008-November/043711.html this is the only issue I can find in omap3.h. It doesn't seem to me that you removed anything (??) Current u-boot-arm/omap3 head (b8220c34487428dc523433f79c7d9df5cd20921e) with this patch boot tested at BeagleBoard. include/asm-arm/arch-omap3/omap3.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/omap3.h +++ u-boot-arm/include/asm-arm/arch-omap3/omap3.h @@ -77,7 +77,7 @@ #define SYNC_32KTIMER_BASE 0x48320000 #define S32K_CR (SYNC_32KTIMER_BASE + 0x10) -+/* OMAP3 GPIO registers */ +/* OMAP3 GPIO registers */ #define OMAP34XX_GPIO1_BASE 0x48310000 #define OMAP34XX_GPIO2_BASE 0x49050000 #define OMAP34XX_GPIO3_BASE 0x49052000

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[U-Boot] [PATCH 1/1] ARM DaVinci: Add common peripherals and modules enable functions.
by Hugo Villeneuve 21 Nov '08

21 Nov '08

Taken all the duplicated code for enabling common modules and apply software workarounds from the board specific code into common functions. Also added comments explaining the workarounds (from TI errata documents) and replaced some numerical bit numbers with more meaningful defines. Signed-off-by: Hugo Villeneuve <hugo.villeneuve(a)lyrtech.com> --- board/davinci/common/psc.c | 65 +++++++++++++++++++++++++++++++++++ board/davinci/common/psc.h | 3 ++ board/davinci/dvevm/dvevm.c | 35 +++++-------------- board/davinci/schmoogie/schmoogie.c | 37 +++++-------------- board/davinci/sffsdr/sffsdr.c | 31 +++-------------- board/davinci/sonata/sonata.c | 35 +++++-------------- 6 files changed, 101 insertions(+), 105 deletions(-) diff --git a/board/davinci/common/psc.c b/board/davinci/common/psc.c index d538d51..28e2a4b 100644 --- a/board/davinci/common/psc.c +++ b/board/davinci/common/psc.c @@ -26,6 +26,14 @@ #include <common.h> #include <asm/arch/hardware.h> +#define PINMUX0_EMACEN (1 << 31) +#define PINMUX0_AECS5 (1 << 11) +#define PINMUX0_AECS4 (1 << 10) + +#define PINMUX1_I2C (1 << 7) +#define PINMUX1_UART1 (1 << 1) +#define PINMUX1_UART0 (1 << 0) + /* * The DM6446 includes two separate power domains: "Always On" and "DSP". The * "Always On" power domain is always on when the chip is on. The "Always On" @@ -115,3 +123,60 @@ void dsp_on(void) REG(PSC_GBLCTL) &= ~0x1f; } #endif /* CONFIG_SYS_USE_DSPLINK */ + +void davinci_enable_uart0(void) +{ + lpsc_on(DAVINCI_LPSC_UART0); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= PINMUX1_UART0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +void davinci_enable_emac(void) +{ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable EMAC. */ + REG(PINMUX0) |= PINMUX0_EMACEN; +} +#endif + +void davinci_enable_i2c(void) +{ + lpsc_on(DAVINCI_LPSC_I2C); + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= PINMUX1_I2C; +} + +void davinci_errata_workarounds(void) +{ + /* + * Workaround for TMS320DM6446 errata 1.3.22: + * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset + * Revision(s) Affected: 1.3 and earlier + */ + REG(PSC_SILVER_BULLET) = 0; + + /* + * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) + * as suggested in TMS320DM6446 errata 2.1.2: + * + * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions + * low priority modules can occupy the bus and prevent high priority + * modules like the VPSS from getting the required DDR2 throughput. + * A hex value of 0x20 should provide a good ARM (cache enabled) + * performance and still allow good utilization by the VPSS or other + * modules. + */ + REG(VBPR) = 0x20; +} diff --git a/board/davinci/common/psc.h b/board/davinci/common/psc.h index 6ab2575..b18a185 100644 --- a/board/davinci/common/psc.h +++ b/board/davinci/common/psc.h @@ -24,5 +24,8 @@ void lpsc_on(unsigned int id); void dsp_on(void); +void davinci_enable_uart0(void); +void davinci_enable_emac(void); +void davinci_enable_i2c(void); #endif /* __PSC_H */ diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index abf60b3..f740124 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -27,7 +27,6 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> -#include <asm/arch/emac_defs.h> #include "../common/psc.h" #include "../common/misc.h" @@ -41,16 +40,13 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - /* Workaround for TMS320DM6446 errata 1.3.22 */ - REG(PSC_SILVER_BULLET) = 0; + /* Configure AEMIF pins (although this should be configured at boot time + * with pull-up/pull-down resistors) */ + REG(PINMUX0) = 0x00000c1f; + + davinci_errata_workarounds(); /* Power on required peripherals */ - lpsc_on(DAVINCI_LPSC_EMAC); - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); - lpsc_on(DAVINCI_LPSC_MDIO); - lpsc_on(DAVINCI_LPSC_I2C); - lpsc_on(DAVINCI_LPSC_UART0); - lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); #if !defined(CONFIG_SYS_USE_DSPLINK) @@ -58,24 +54,11 @@ int board_init(void) dsp_on(); #endif /* CONFIG_SYS_USE_DSPLINK */ - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x0000e003; - - /* Enable GIO3.3V cells used for EMAC */ - REG(VDD3P3V_PWDN) = 0; - - /* Enable UART0 MUX lines */ - REG(PINMUX1) |= 1; - - /* Enable EMAC and AEMIF pins */ - REG(PINMUX0) = 0x80000c1f; - - /* Enable I2C pin Mux */ - REG(PINMUX1) |= (1 << 7); - - /* Set the Bus Priority Register to appropriate value */ - REG(VBPR) = 0x20; + davinci_enable_uart0(); + davinci_enable_emac(); + davinci_enable_i2c(); + lpsc_on(DAVINCI_LPSC_TIMER1); timer_init(); return(0); diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c index 3504a2e..433769a 100644 --- a/board/davinci/schmoogie/schmoogie.c +++ b/board/davinci/schmoogie/schmoogie.c @@ -27,7 +27,6 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> -#include <asm/arch/emac_defs.h> #include "../common/psc.h" #include "../common/misc.h" @@ -41,16 +40,13 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - /* Workaround for TMS320DM6446 errata 1.3.22 */ - REG(PSC_SILVER_BULLET) = 0; + /* Configure AEMIF pins (although this should be configured at boot time + * with pull-up/pull-down resistors) */ + REG(PINMUX0) = 0x00000c1f; + + davinci_errata_workarounds(); /* Power on required peripherals */ - lpsc_on(DAVINCI_LPSC_EMAC); - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); - lpsc_on(DAVINCI_LPSC_MDIO); - lpsc_on(DAVINCI_LPSC_I2C); - lpsc_on(DAVINCI_LPSC_UART0); - lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); #if !defined(CONFIG_SYS_USE_DSPLINK) @@ -58,24 +54,11 @@ int board_init(void) dsp_on(); #endif /* CONFIG_SYS_USE_DSPLINK */ - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x0000e003; - - /* Enable GIO3.3V cells used for EMAC */ - REG(VDD3P3V_PWDN) = 0; - - /* Enable UART0 MUX lines */ - REG(PINMUX1) |= 1; - - /* Enable EMAC and AEMIF pins */ - REG(PINMUX0) = 0x80000c1f; - - /* Enable I2C pin Mux */ - REG(PINMUX1) |= (1 << 7); - - /* Set the Bus Priority Register to appropriate value */ - REG(VBPR) = 0x20; + davinci_enable_uart0(); + davinci_enable_emac(); + davinci_enable_i2c(); + lpsc_on(DAVINCI_LPSC_TIMER1); timer_init(); return(0); @@ -87,7 +70,7 @@ int misc_init_r(void) int i = 0; /* Set serial number from UID chip */ - u_int8_t crc_tbl[256] = { + const u_int8_t crc_tbl[256] = { 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83, 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41, 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e, diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c index 9296d7b..e76f86d 100644 --- a/board/davinci/sffsdr/sffsdr.c +++ b/board/davinci/sffsdr/sffsdr.c @@ -30,7 +30,6 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> -#include <asm/arch/emac_defs.h> #include "../common/psc.h" #include "../common/misc.h" @@ -51,16 +50,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - /* Workaround for TMS320DM6446 errata 1.3.22 */ - REG(PSC_SILVER_BULLET) = 0; + davinci_errata_workarounds(); /* Power on required peripherals */ - lpsc_on(DAVINCI_LPSC_EMAC); - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); - lpsc_on(DAVINCI_LPSC_MDIO); - lpsc_on(DAVINCI_LPSC_I2C); - lpsc_on(DAVINCI_LPSC_UART0); - lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); #if !defined(CONFIG_SYS_USE_DSPLINK) @@ -68,24 +60,11 @@ int board_init(void) dsp_on(); #endif /* CONFIG_SYS_USE_DSPLINK */ - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x0000e003; - - /* Enable GIO3.3V cells used for EMAC */ - REG(VDD3P3V_PWDN) = 0; - - /* Enable UART0 MUX lines */ - REG(PINMUX1) |= 1; - - /* Enable EMAC and AEMIF pins */ - REG(PINMUX0) = 0x80000c1f; - - /* Enable I2C pin Mux */ - REG(PINMUX1) |= (1 << 7); - - /* Set the Bus Priority Register to appropriate value */ - REG(VBPR) = 0x20; + davinci_enable_uart0(); + davinci_enable_emac(); + davinci_enable_i2c(); + lpsc_on(DAVINCI_LPSC_TIMER1); timer_init(); return(0); diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index 6de9356..d56b443 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -26,7 +26,6 @@ #include <common.h> #include <asm/arch/hardware.h> -#include <asm/arch/emac_defs.h> #include "../common/psc.h" #include "../common/misc.h" @@ -40,16 +39,13 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - /* Workaround for TMS320DM6446 errata 1.3.22 */ - REG(PSC_SILVER_BULLET) = 0; + /* Configure AEMIF pins (although this should be configured at boot time + * with pull-up/pull-down resistors) */ + REG(PINMUX0) = 0x00000c1f; + + davinci_errata_workarounds(); /* Power on required peripherals */ - lpsc_on(DAVINCI_LPSC_EMAC); - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); - lpsc_on(DAVINCI_LPSC_MDIO); - lpsc_on(DAVINCI_LPSC_I2C); - lpsc_on(DAVINCI_LPSC_UART0); - lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); #if !defined(CONFIG_SYS_USE_DSPLINK) @@ -57,24 +53,11 @@ int board_init(void) dsp_on(); #endif /* CONFIG_SYS_USE_DSPLINK */ - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x0000e003; - - /* Enable GIO3.3V cells used for EMAC */ - REG(VDD3P3V_PWDN) = 0; - - /* Enable UART0 MUX lines */ - REG(PINMUX1) |= 1; - - /* Enable EMAC and AEMIF pins */ - REG(PINMUX0) = 0x80000c1f; - - /* Enable I2C pin Mux */ - REG(PINMUX1) |= (1 << 7); - - /* Set the Bus Priority Register to appropriate value */ - REG(VBPR) = 0x20; + davinci_enable_uart0(); + davinci_enable_emac(); + davinci_enable_i2c(); + lpsc_on(DAVINCI_LPSC_TIMER1); timer_init(); return(0); -- 1.5.4.5

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[U-Boot] PCI405 doesn't build anymore
by Stefan Roese 21 Nov '08

21 Nov '08

Hi Matthias, I just noticed that PCI405 doesn't build anymore in the current U-Boot repository (main and ppc4xx): [stefan@kubuntu u-boot-ppc4xx (master)]$ ./MAKEALL PCI405 Configuring for PCI405 board... ppc_4xx-objcopy: u-boot.bin: Bad value ppc_4xx-objcopy: u-boot.bin: Bad value make: *** [u-boot.bin] Error 1 I tracked it down to this commit: commit 49c3a861d11735838f1f1b11999ce433006dc919 Author: Kumar Gala <galak(a)kernel.crashing.org> Date: Tue Oct 21 17:25:45 2008 -0500 bootm: Add subcommands Add the ability to break the steps of the bootm command into several subcommands: start, loados, ramdisk, fdt, bdt, cmdline, prep, go. This allows us to do things like manipulate device trees before they are passed to a booting kernel or setup memory for a secondary core in multicore situations. Not all OS types support all subcommands (currently only start, loados, ramdisk, fdt, and go are supported). Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> The only thing I can think of causing this build problem right now, is that the image size is too big now. Please take a look at it and send a patch to fix this problem if possible. Thanks. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

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[U-Boot] [PATCH] mpc8641: Fix error in README
by Becky Bruce 21 Nov '08

21 Nov '08

I made some updates to the code that didn't make it into the README - fix this Signed-off-by: Becky Bruce <becky.bruce(a)freescale.com> --- doc/README.mpc8641hpcn | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn index dbdf244..2447aae 100644 --- a/doc/README.mpc8641hpcn +++ b/doc/README.mpc8641hpcn @@ -134,15 +134,15 @@ For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit. However, the physical map is altered to reside in 36-bit space, as follows. Addresses are no longer mapped with VA == PA. All accesses from software use the VA; the PA is only used for setting up windows -and mappings. Note that the low 32 bits are the same as the VA above; -only the top 4 bits vary: +and mappings. Note that with the exception of PCI MEM and RIO, the low + 32 bits are the same as the VA above; only the top 4 bits vary: Memory Range Device Size ------------ ------ ---- 0x0_0000_0000 0x0_7fff_ffff DDR 2G - 0xc_8000_0000 0xc_9fff_ffff RIO MEM 512M - 0xc_8000_0000 0xc_9fff_ffff PCI1/PEX1 MEM 512M - 0xc_a000_0000 0xc_bfff_ffff PCI2/PEX2 MEM 512M + 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M + 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M + 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K -- 1.5.6.5

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[U-Boot] Comprehensive Healthcare List
by Alford consistent 21 Nov '08

21 Nov '08

Current MDs in the United States Coverage in many different areas of medicine such as Endocrinology, Pathology, Urology, Neurology, Plastic Surgery, Psychiatry, Cardiology and much more you can sort by many different fields like zip or county Now priced at: $397 {}{}{} You get these for F-Ree with every order this week {}{}{} -> Dentists -> Veterinarians -> Physical Therapists -> Visiting Nurses & RN's send email to - : Simon(a)mediprodat.com good until Nov 21 ======================================= to stop this email in future email us at release(a)mediprodat.com

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Re: [U-Boot] Question about ARM compiler optimization problem
by Choe, Hyun-ho 21 Nov '08

21 Nov '08

After I looked into disassembled ARM codes, found no reason to cause problem. When I compiled with -Os option, the C source code like following: static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) { void *addr; cfiword_t cword; int retval; addr = flash_map (info, sect, offset); flash_make_cmd (info, cmd, &cword); switch (info->portwidth) { case FLASH_CFI_8BIT: retval = flash_read8(addr) != flash_read8(addr); break; case FLASH_CFI_16BIT: retval = flash_read16(addr) != flash_read16(addr); break; case FLASH_CFI_32BIT: retval = flash_read32(addr) != flash_read32(addr); break; case FLASH_CFI_64BIT: retval = flash_read64(addr) != flash_read64(addr); break; default: retval = 0; break; } flash_unmap(info, sect, offset, addr); return retval; } is compiled as following: f0497c: e1a0100a mov r1, sl f04980: e3a02000 mov r2, #0 ; 0x0 f04984: e1a00007 mov r0, r7 f04988: ebfffcbc bl f03c80 <flash_map> f0498c: e3a01040 mov r1, #64 ; 0x40 f04990: e1a04000 mov r4, r0 f04994: e28d2004 add r2, sp, #4 ; 0x4 f04998: e1a00007 mov r0, r7 f0499c: ebfffcbd bl f03c98 <flash_make_cmd> f049a0: e5d732af ldrb r3, [r7, #687] f049a4: e2433001 sub r3, r3, #1 ; 0x1 f049a8: e3530007 cmp r3, #7 ; 0x7 f049ac: 979ff103 ldrls pc, [pc, r3, lsl #2] f049b0: ea000022 b f04a40 <.text+0x4a40> f049b4: 00f049d4 ldreqsbt r4, [r0], #148 f049b8: 00f049e0 rsceqs r4, r0, r0, ror #19 f049bc: 00f04a40 rsceqs r4, r0, r0, asr #20 f049c0: 00f049ec rsceqs r4, r0, ip, ror #19 f049c4: 00f04a40 rsceqs r4, r0, r0, asr #20 f049c8: 00f04a40 rsceqs r4, r0, r0, asr #20 f049cc: 00f04a40 rsceqs r4, r0, r0, asr #20 f049d0: 00f04a00 rsceqs r4, r0, r0, lsl #20 f049d4: e5d42000 ldrb r2, [r4] f049d8: e5d43000 ldrb r3, [r4] f049dc: ea000004 b f049f4 <.text+0x49f4> f049e0: e1d420b0 ldrh r2, [r4] f049e4: e1d430b0 ldrh r3, [r4] f049e8: ea000001 b f049f4 <.text+0x49f4> f049ec: e5942000 ldr r2, [r4] f049f0: e5943000 ldr r3, [r4] f049f4: e0520003 subs r0, r2, r3 f049f8: 13a00001 movne r0, #1 ; 0x1 f049fc: ea00000d b f04a38 <.text+0x4a38> f04a00: e59f317c ldr r3, [pc, #380] ; f04b84 <.text+0x4b84> f04a04: e1a00004 mov r0, r4 f04a08: e1a0e00f mov lr, pc f04a0c: e1a0f003 mov pc, r3 f04a10: e59f216c ldr r2, [pc, #364] ; f04b84 <.text+0x4b84> f04a14: e1a05000 mov r5, r0 f04a18: e1a00004 mov r0, r4 f04a1c: e1a06001 mov r6, r1 f04a20: e1a0e00f mov lr, pc f04a24: e1a0f002 mov pc, r2 f04a28: e1550000 cmp r5, r0 f04a2c: 1affff98 bne f04894 <flash_full_status_check+0x28> f04a30: e1560001 cmp r6, r1 f04a34: ea000000 b f04a3c <.text+0x4a3c> f04a38: e3500000 cmp r0, #0 ; 0x0 f04a3c: 1affff94 bne f04894 <flash_full_status_check+0x28> f049d4 ~ f049f0 is accessing flash_read8/16/32 functions, and this code should be work because two sequential read from CFI flash changes toggle bit while erase/write is in action. But, two read operation gets the same result. Any other things that I wasn't understand ? TIA, Any advice will be appreciated. Best regards, Choe, Hyun-ho 2008-11-20 (목), 12:34 -0600, Andrew Dyer 쓰시길: > On Thu, Nov 20, 2008 at 11:59 AM, Choe, Hyun-ho <firebird(a)legend.co.kr> wrote: > > In cpu dir, there is arm920t/ks8695. > > ks8695p is some modified chip from ks8695. > > > > In board section, OpenGear cm4008 and cm41xx uses ks8695. > > > > > > I would guess the problem is that the compiler is reading the hardware > once and using that value both times, thinking that the location is > memory, not a hardware register, where the value may change from time > to time. > I've always fixed this with a 'volatile' pointer, which is supposed to > force the compiler to read the location every time it is accessed. > Supposedly the 'linux way' is to use special accessor functions that > are written to prevent this optimization from occurring. > > The other problem I've seen with toggle registers is reading them on > hardware that likes to do multiple reads to fill up a word of data. > For example you have a 16 bit flash on a 32-bit bus, and you read the > status register as a 32-bit quantity, then the hardware goes and reads > the register twice to fill up the 32-bit request, and the next time > you read you see the same data again as the first time through because > the value with the toggle in it is in the other half of the first > 32-bits you fetched.

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