November 2008 - U-Boot

[U-Boot] [PATCH-OMAP3 v2] OMAP3: Update ARM's if then else logic in examples Makefile
by dirk.behme＠googlemail.com 21 Nov '08

21 Nov '08

Update ARM's if then else logic. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in v2: - Make make happy regaring if then else logic "each if can only have one else". Don't take examples from mailing list without testing ;) Version v2 makes previous version v1 of this patch obsolete. examples/Makefile | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) Index: u-boot-arm/examples/Makefile =================================================================== --- u-boot-arm.orig/examples/Makefile +++ u-boot-arm/examples/Makefile @@ -30,12 +30,14 @@ LOAD_ADDR = 0x40000 endif ifeq ($(ARCH),arm) -LOAD_ADDR = 0xc100000 ifeq ($(BOARD),omap2420h4) LOAD_ADDR = 0x80300000 -endif +else ifeq ($(CPU),omap3) LOAD_ADDR = 0x80300000 +else +LOAD_ADDR = 0xc100000 +endif endif endif

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[U-Boot] [PATCH-OMAP3] OMAP3: Clean up EVM board file
by dirk.behme＠googlemail.com 21 Nov '08

21 Nov '08

- Use readx/writex instead of direct pointer access - Replace hardcoded values by macros - Minor space to tab conversion Notes: - Instead of read/modify/write GPIO_DATAOUT register use SET/CLEARDATAOUT register for GPIO64 - GPIO 1-6 CM_FCLKEN_PER and CM_ICLKEN_PER are already configured in per_clocks_enable(), remove it here - Remove pin mux. Is done in set_muxconf_regs. No functional change. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- board/omap3/evm/evm.c | 143 +++++++++---------------------------- board/omap3/evm/evm.h | 64 ++++++++-------- include/asm-arm/arch-omap3/cpu.h | 2 include/asm-arm/arch-omap3/mem.h | 8 ++ include/asm-arm/arch-omap3/omap3.h | 1 5 files changed, 78 insertions(+), 140 deletions(-) Index: u-boot-arm/board/omap3/evm/evm.c =================================================================== --- u-boot-arm.orig/board/omap3/evm/evm.c +++ u-boot-arm/board/omap3/evm/evm.c @@ -3,12 +3,11 @@ * Texas Instruments, <www.ti.com> * * Author : - * Manikandan Pillai <mani.pillai(a)ti.com> + * Manikandan Pillai <mani.pillai(a)ti.com> * * Derived from Beagle Board and 3430 SDP code by - * Richard Woodruff <r-woodruff2(a)ti.com> - * Syed Mohammed Khasim <khasim(a)ti.com> - * + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> * * See file CREDITS for list of people who contributed to this * project. @@ -30,6 +29,7 @@ */ #include <common.h> #include <asm/io.h> +#include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <i2c.h> @@ -74,8 +74,8 @@ int misc_init_r(void) /****************************************************************************** * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. + * hardware. Many pins need to be moved from protect to primary + * mode. *****************************************************************************/ void set_muxconf_regs(void) { @@ -85,115 +85,42 @@ void set_muxconf_regs(void) /****************************************************************************** * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. Pin Muxing for the SMC9118 is initialized - * here. + * Ethernet hardware. *****************************************************************************/ -static int setup_net_chip(void) +static void setup_net_chip(void) { - int i = 0; + unsigned int *gpio3_base = (unsigned int *)OMAP34XX_GPIO3_BASE; + unsigned int *gpmc_cs6_base = (unsigned int *)GPMC_CONFIG_CS6_BASE; + unsigned short *ctrl_base = (unsigned short *)OMAP34XX_CTRL_BASE; /* Configure GPMC registers */ - (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0150)) = 0x00001000; - (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0154)) = 0x001e1e01; - (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0158)) = 0x00080300; - (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x015C)) = 0x1c091c09; - (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0160)) = 0x04181f1f; - (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0164)) = 0x00000FCF; - (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0168)) = 0x00000f6c; - - /* - * Configure PIN MUX registers - * Enable GPMC Pin Mux Registers - * Enable GPMC_CLK Pin in CONTROL_PADCONF_gpmc_ncs7 register - */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xBC)) |= 0x00180000; - /* Enable CS5 Pin in CONTROL_PADCONF_gpmc_ncs5 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) |= 0x00000018; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) &= 0xFFFFFFF8; - /* Enable offmode for nwe in CONTROL_PADCONF_GPMC_NWE register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00000F00; - /* En off mode for noe and ale in CONTROL_PADCONF_GPMC_NADV_ALE reg */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC0)) |= 0x0E000E00; - /* Enable gpmc_nbe0_cle in CONTROL_PADCONF_GPMC_NWE register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00180000; - - /* - * Enable gpmc_nbe1 in CONTROL_PADCONF_GPMC_NBE1 register and - * configuring the mux mode to 0 - */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) |= 0x00000018; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) &= 0xFFFFFFF8; - /* Enable d15 in CONTROL_PADCONF_GPMC_D15 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xAC)) |= 0x00000018; - /* Enable d14 - d13 in CONTROL_PADCONF_GPMC_D13 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA8)) |= 0x00180018; - /* Enable d12 - d11 in CONTROL_PADCONF_GPMC_D11 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA4)) |= 0x00180018; - /* Enable d10 - d9 in CONTROL_PADCONF_GPMC_D9 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA0)) |= 0x00180018; - /* Enable d8 - d7 in CONTROL_PADCONF_GPMC_D7 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x9C)) |= 0x00180018; - /* Enable d6 - d5 in CONTROL_PADCONF_GPMC_D5 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x98)) |= 0x00180018; - /* Enable d4 - d3 in CONTROL_PADCONF_GPMC_D3 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x94)) |= 0x00180018; - /* Enable d2 - d1 in CONTROL_PADCONF_GPMC_D1 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x90)) |= 0x00180018; - /* Enable d0 and a10 in CONTROL_PADCONF_GPMC_a10 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x8C)) |= 0x00180018; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x8C)) &= 0xFFFFFFF8; - /* Enable a9 - a8 in CONTROL_PADCONF_GPMC_a8 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x88)) |= 0x00180018; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x88)) &= 0xFFF8FFF8; - /* Enable a7 - a6 in CONTROL_PADCONF_GPMC_a6 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x84)) |= 0x00180018; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x84)) &= 0xFFF8FFF8; - /* Enable a5 - a4 in CONTROL_PADCONF_GPMC_a4 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x80)) |= 0x00180018; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x80)) &= 0xFFF8FFF8; - /* Enable a3 - a2 in CONTROL_PADCONF_GPMC_a2 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x7C)) |= 0x00180018; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x7C)) &= 0xFFF8FFF8; - /* Enable a1 - a0 in CONTROL_PADCONF_GPMC_a0 register */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) |= 0x00000018; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) &= 0xFFFFFFF8; - -#if defined(CPU_3430_ES1) || defined(CPU_3430_ES2) - /* - * GPIO 64 configuration in CONTROL_PADCONF_GPMC_WAIT2 - * register mux mode is 4. - */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000018; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) &= 0xFFFFFFF8; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000004; - - /* - * Configure GPIO 176 in CONTROL_PADCONF_MCSPI1_CS1 - * register for ethernet ISR mux mode is 4 - */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00180000; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) &= 0xFFF8FFFF; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00040000; - - /* - * Enable Clock for GPIO 1-6 module in CM_FCLKEN_PER - * and CM_ICLKEN_PER registers - */ - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5000)) |= 0x0003E800; - (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5010)) |= 0x0003E800; + writel(NET_GPMC_CONFIG1, gpmc_cs6_base + OFFS(GPMC_CONFIG1)); + writel(NET_GPMC_CONFIG2, gpmc_cs6_base + OFFS(GPMC_CONFIG2)); + writel(NET_GPMC_CONFIG3, gpmc_cs6_base + OFFS(GPMC_CONFIG3)); + writel(NET_GPMC_CONFIG4, gpmc_cs6_base + OFFS(GPMC_CONFIG4)); + writel(NET_GPMC_CONFIG5, gpmc_cs6_base + OFFS(GPMC_CONFIG5)); + writel(NET_GPMC_CONFIG6, gpmc_cs6_base + OFFS(GPMC_CONFIG6)); + writel(NET_GPMC_CONFIG7, gpmc_cs6_base + OFFS(GPMC_CONFIG7)); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NWE >> 1)) | 0x0E00, + ctrl_base + (CONTROL_PADCONF_GPMC_NWE >> 1)); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NOE >> 1)) | 0x0E00, + ctrl_base + (CONTROL_PADCONF_GPMC_NOE >> 1)); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NADV_ALE >> 1)) | 0x0E00, + ctrl_base + (CONTROL_PADCONF_GPMC_NADV_ALE >> 1)); /* Make GPIO 64 as output pin */ - (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x34)) &= ~(0x00000001); + writel(readl(gpio3_base + OFFS(GPIO_OE)) & ~(GPIO0), + gpio3_base + OFFS(GPIO_OE)); /* Now send a pulse on the GPIO pin */ - (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) |= 0x00000001; - for (i = 0; i < 99 ; i++); - (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) &= ~(0x00000001); - for (i = 0; i < 99 ; i++); - (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) |= 0x00000001; -#else - printf("Unknown revision... \n\n"); -#endif - return 0; + writel(GPIO0, gpio3_base + OFFS(GPIO_SETDATAOUT)); + udelay(1); + writel(GPIO0, gpio3_base + OFFS(GPIO_CLEARDATAOUT)); + udelay(1); + writel(GPIO0, gpio3_base + OFFS(GPIO_SETDATAOUT)); } Index: u-boot-arm/board/omap3/evm/evm.h =================================================================== --- u-boot-arm.orig/board/omap3/evm/evm.h +++ u-boot-arm/board/omap3/evm/evm.h @@ -36,7 +36,7 @@ const omap3_sysinfo sysinfo = { #endif }; -static int setup_net_chip(void); +static void setup_net_chip(void); /* * IEN - Input Enable @@ -88,46 +88,46 @@ static int setup_net_chip(void); MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/\ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ @@ -278,7 +278,7 @@ static int setup_net_chip(void); MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ /* TS_PEN_IRQ */\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /*GPIO_176*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ /* - LAN_INTR*/\ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\ Index: u-boot-arm/include/asm-arm/arch-omap3/cpu.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/cpu.h +++ u-boot-arm/include/asm-arm/arch-omap3/cpu.h @@ -56,9 +56,11 @@ #define GPMC_CONFIG 0x50 #define GPMC_STATUS 0x54 #define GPMC_CONFIG_CS0 0x60 +#define GPMC_CONFIG_CS6 0x150 #define GPMC_CONFIG_REG (GPMC_BASE + GPMC_CONFIG) #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) +#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6) #define GPMC_CONFIG_WP 0x10 #define GPMC_CONFIG_WIDTH 0x30 Index: u-boot-arm/include/asm-arm/arch-omap3/mem.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/mem.h +++ u-boot-arm/include/asm-arm/arch-omap3/mem.h @@ -197,6 +197,14 @@ typedef enum { #define ONENAND_GPMC_CONFIG5 0x010F1010 #define ONENAND_GPMC_CONFIG6 0x1F060000 +#define NET_GPMC_CONFIG1 0x00001000 +#define NET_GPMC_CONFIG2 0x001e1e01 +#define NET_GPMC_CONFIG3 0x00080300 +#define NET_GPMC_CONFIG4 0x1c091c09 +#define NET_GPMC_CONFIG5 0x04181f1f +#define NET_GPMC_CONFIG6 0x00000FCF +#define NET_GPMC_CONFIG7 0x00000f6c + /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 /* max number of GPMC regs */ Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/omap3.h +++ u-boot-arm/include/asm-arm/arch-omap3/omap3.h @@ -86,6 +86,7 @@ #define OMAP34XX_GPIO6_BASE 0x49058000 #define GPIO_OE 0x34 +#define GPIO_CLEARDATAOUT 0x90 #define GPIO_SETDATAOUT 0x94 #define GPIO0 (0x1 << 0)

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[U-Boot] [PATCH-OMAP3 v2] OMAP3: Fix multiline comment style
by dirk.behme＠googlemail.com 20 Nov '08

20 Nov '08

Fix multiline comment style. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in v2: - Correct patch header style. v2 of this patch makes previous version v1 obsolete. board/omap3/evm/evm.c | 32 ++++++++++++++++++---------- cpu/arm_cortexa8/cpu.c | 12 +++++++--- cpu/arm_cortexa8/omap3/board.c | 41 +++++++++++++++++++++++------------- cpu/arm_cortexa8/omap3/clock.c | 24 ++++++++++++++------- cpu/arm_cortexa8/omap3/interrupts.c | 6 +++-- cpu/arm_cortexa8/omap3/mem.c | 6 +++-- cpu/arm_cortexa8/omap3/sys_info.c | 4 ++- drivers/mtd/nand/omap_gpmc.c | 23 +++++++++++++------- include/asm-arm/arch-omap3/omap3.h | 8 +++---- include/configs/omap3_beagle.h | 3 +- include/configs/omap3_evm.h | 3 +- include/configs/omap3_overo.h | 3 +- 12 files changed, 108 insertions(+), 57 deletions(-) Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/omap3.h +++ u-boot-arm/include/asm-arm/arch-omap3/omap3.h @@ -110,11 +110,11 @@ #define CPU_3430 0x3430 -/* 343x real hardware: +/* + * 343x real hardware: * ES1 = rev 0 - */ - -/* 343x code defines: + * + * 343x code defines: * ES1 = 0+1 = 1 * ES1 = 1+1 = 1 */ Index: u-boot-arm/cpu/arm_cortexa8/cpu.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/cpu.c +++ u-boot-arm/cpu/arm_cortexa8/cpu.c @@ -186,8 +186,10 @@ void l2cache_enable() __asm__ __volatile__("mov %0, r12":"=r"(j)); __asm__ __volatile__("mov %0, r0":"=r"(i)); - /* GP Device ROM code API usage here */ - /* r12 = AUXCR Write function and r0 value */ + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ __asm__ __volatile__("mov r12, #0x3"); __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); __asm__ __volatile__("orr r0, r0, #0x2"); @@ -214,8 +216,10 @@ void l2cache_disable() __asm__ __volatile__("mov %0, r12":"=r"(j)); __asm__ __volatile__("mov %0, r0":"=r"(i)); - /* GP Device ROM code API usage here */ - /* r12 = AUXCR Write function and r0 value */ + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ __asm__ __volatile__("mov r12, #0x3"); __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); __asm__ __volatile__("bic r0, r0, #0x2"); Index: u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/sys_info.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c @@ -63,7 +63,9 @@ u32 get_cpu_type(void) u32 get_cpu_rev(void) { u32 cpuid = 0; - /* On ES1.0 the IDCODE register is not exposed on L4 + + /* + * On ES1.0 the IDCODE register is not exposed on L4 * so using CPU ID to differentiate * between ES2.0 and ES1.0. */ Index: u-boot-arm/cpu/arm_cortexa8/omap3/board.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/board.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/board.c @@ -99,8 +99,10 @@ void secureworld_exit() __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i)); /* enabling co-processor CP10 and CP11 accesses in NS world */ __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); - /* allow allocation of locked TLBs and L2 lines in NS world */ - /* allow use of PLE registers in NS world also */ + /* + * allow allocation of locked TLBs and L2 lines in NS world + * allow use of PLE registers in NS world also + */ __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i)); @@ -128,8 +130,10 @@ void setup_auxcr() __asm__ __volatile__("mov %0, r12":"=r"(j)); __asm__ __volatile__("mov %0, r0":"=r"(i)); - /* GP Device ROM code API usage here */ - /* r12 = AUXCR Write function and r0 value */ + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ __asm__ __volatile__("mov r12, #0x3"); __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); /* Enabling ASA */ @@ -150,17 +154,21 @@ void try_unlock_memory() int mode; int in_sdram = is_running_in_sdram(); - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T */ + /* + * if GP device unlock device SRAM for general use + * secure code breaks for Secure/Emulation device - HS/E/T + */ mode = get_device_type(); if (mode == GP_DEVICE) secure_unlock_mem(); - /* If device is EMU and boot is XIP external booting + /* + * If device is EMU and boot is XIP external booting * Unlock firewalls and disable L2 and put chip * out of secure world + * + * Assuming memories are unlocked by the demon who put us in SDRAM */ - /* Assuming memories are unlocked by the demon who put us in SDRAM */ if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) && (!in_sdram)) { secure_unlock_mem(); @@ -183,8 +191,10 @@ void s_init(void) try_unlock_memory(); - /* Right now flushing at low MPU speed. - Need to move after clock init */ + /* + * Right now flushing at low MPU speed. + * Need to move after clock init + */ v7_flush_dcache_all(get_device_type()); #ifndef CONFIG_ICACHE_OFF icache_enable(); @@ -195,8 +205,9 @@ void s_init(void) #else l2cache_enable(); #endif - /* Writing to AuxCR in U-boot using SMI for GP DEV */ - /* Currently SMI in Kernel on ES2 devices seems to have an isse + /* + * Writing to AuxCR in U-boot using SMI for GP DEV + * Currently SMI in Kernel on ES2 devices seems to have an isse * Once that is resolved, we can postpone this config to kernel */ if (get_device_type() == GP_DEVICE) @@ -231,7 +242,8 @@ void wait_for_command_complete(unsigned *****************************************************************************/ void watchdog_init(void) { - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + /* + * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is * either taken care of by ROM (HS/EMU) or not accessible (GP). * We need to take care of WD2-MPU or take a PRCM reset. WD3 * should not be running and does not generate a PRCM reset. @@ -261,7 +273,8 @@ int dram_init(void) display_board_info(btype); - /* If a second bank of DDR is attached to CS1 this is + /* + * If a second bank of DDR is attached to CS1 this is * where it can be started. Early init code will init * memory on CS0. */ Index: u-boot-arm/cpu/arm_cortexa8/omap3/clock.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/clock.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/clock.c @@ -131,7 +131,8 @@ void prcm_init(void) xip_safe = is_running_in_sram(); - /* Gauge the input clock speed and find out the sys_clkin_sel + /* + * Gauge the input clock speed and find out the sys_clkin_sel * value corresponding to the input clock. */ osc_clk = get_osc_clk_speed(); @@ -148,7 +149,8 @@ void prcm_init(void) clk_index = sys_clkin_sel; } - /* The DPLL tables are defined according to sysclk value and + /* + * The DPLL tables are defined according to sysclk value and * silicon revision. The clk_index value will be used to get * the values for that input sysclk from the DPLL param table * and sil_index will get the values for that SysClk for the @@ -166,12 +168,15 @@ void prcm_init(void) /* Moving it to the right sysclk and ES rev base */ dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; if (xip_safe) { - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ + /* + * CORE DPLL + * sr32(CM_CLKSEL2_EMU) set override to work when asleep + */ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - /* For OMAP3 ES1.0 Errata 1.50, default value directly doesnt + /* + * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't * work. write another value and then default value. */ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ @@ -191,8 +196,10 @@ void prcm_init(void) wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); } else if (is_running_in_flash()) { - /* if running from flash, jump to small relocated code - area in SRAM. */ + /* + * if running from flash, jump to small relocated code + * area in SRAM. + */ p0 = readl(CM_CLKEN_PLL); sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS); sr32((u32) &p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */ @@ -225,7 +232,8 @@ void prcm_init(void) /* Moving it to the right sysclk base */ dpll_param_p = dpll_param_p + clk_index; - /* Errata 1.50 Workaround for OMAP3 ES1.0 only + /* + * Errata 1.50 Workaround for OMAP3 ES1.0 only * If using default divisors, write default divisor + 1 * and then the actual divisor value */ Index: u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/interrupts.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c @@ -177,8 +177,10 @@ int interrupt_init(void) { int32_t val; - /* Start the counter ticking up */ - /* reload value on overflow */ + /* + * Start the counter ticking up + * reload value on overflow + */ *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* mask to enable timer */ val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0; Index: u-boot-arm/cpu/arm_cortexa8/omap3/mem.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/mem.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/mem.c @@ -32,7 +32,8 @@ #include <asm/arch/sys_proto.h> #include <command.h> -/* Only One NAND allowed on board at a time. +/* + * Only One NAND allowed on board at a time. * The GPMC CS Base for the same */ unsigned int boot_flash_base; @@ -250,7 +251,8 @@ void gpmc_init(void) config &= (~0xf00); writel(config, gpmc_base + OFFS(GPMC_CONFIG)); - /* Disable the GPMC0 config set by ROM code + /* + * Disable the GPMC0 config set by ROM code * It conflicts with our MPDB (both at 0x08000000) */ writel(0, gpmc_cs_base + OFFS(GPMC_CONFIG7)); Index: u-boot-arm/drivers/mtd/nand/omap_gpmc.c =================================================================== --- u-boot-arm.orig/drivers/mtd/nand/omap_gpmc.c +++ u-boot-arm/drivers/mtd/nand/omap_gpmc.c @@ -43,7 +43,8 @@ static void omap_nand_hwcontrol(struct m { register struct nand_chip *this = mtd->priv; - /* Point the IO_ADDR to DATA and ADDRESS registers instead + /* + * Point the IO_ADDR to DATA and ADDRESS registers instead * of chip address */ switch (ctrl) { @@ -70,8 +71,10 @@ static void omap_nand_hwcontrol(struct m */ static void omap_hwecc_init(struct nand_chip *chip) { - /* Init ECC Control Register */ - /* Clear all ECC | Enable Reg1 */ + /* + * Init ECC Control Register + * Clear all ECC | Enable Reg1 + */ writel(ECCCLEAR | ECCRESULTREG1, gpmc_base + OFFS(GPMC_ECC_CONTROL)); writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, gpmc_base + OFFS(GPMC_ECC_SIZE_CONFIG)); @@ -183,7 +186,8 @@ static int omap_calculate_ecc(struct mtd ecc_code[1] = (val >> 16) & 0xFF; ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); - /* Stop reading anymore ECC vals and clear old results + /* + * Stop reading anymore ECC vals and clear old results * enable will be called if more reads are required */ writel(0x000, gpmc_base + OFFS(GPMC_ECC_CONFIG)); @@ -207,7 +211,8 @@ static void omap_enable_hwecc(struct mtd /* Clear the ecc result registers, select ecc reg as 1 */ writel(ECCCLEAR | ECCRESULTREG1, gpmc_base + OFFS(GPMC_ECC_CONTROL)); - /* Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes + /* + * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes * tell all regs to generate size0 sized regs * we just have a single ECC engine for all CS */ @@ -222,7 +227,7 @@ static void omap_enable_hwecc(struct mtd } } -/** +/* * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc. * The default is to come up on s/w ecc * @@ -290,14 +295,16 @@ int board_nand_init(struct nand_chip *na int32_t gpmc_config = 0; cs = 0; - /* xloader/Uboot's gpmc configuration would have configured GPMC for + /* + * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the * first CS with NAND type memory. * TBD: need to make this logic generic to handle multiple CS NAND * devices. */ while (cs < GPMC_MAX_CS) { - /* Each GPMC set for a single CS is at offset 0x30 + /* + * Each GPMC set for a single CS is at offset 0x30 * - already remapped for us */ gpmc_cs_base = (void __iomem *)(GPMC_CONFIG_CS0_BASE + Index: u-boot-arm/include/configs/omap3_beagle.h =================================================================== --- u-boot-arm.orig/include/configs/omap3_beagle.h +++ u-boot-arm/include/configs/omap3_beagle.h @@ -179,7 +179,8 @@ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ -/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ #define V_PVT 7 Index: u-boot-arm/board/omap3/evm/evm.c =================================================================== --- u-boot-arm.orig/board/omap3/evm/evm.c +++ u-boot-arm/board/omap3/evm/evm.c @@ -101,9 +101,11 @@ static int setup_net_chip(void) (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0164)) = 0x00000FCF; (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0168)) = 0x00000f6c; - /* Configure PIN MUX registers */ - /* Enable GPMC Pin Mux Registers */ - /* Enable GPMC_CLK Pin in CONTROL_PADCONF_gpmc_ncs7 register */ + /* + * Configure PIN MUX registers + * Enable GPMC Pin Mux Registers + * Enable GPMC_CLK Pin in CONTROL_PADCONF_gpmc_ncs7 register + */ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xBC)) |= 0x00180000; /* Enable CS5 Pin in CONTROL_PADCONF_gpmc_ncs5 register */ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) |= 0x00000018; @@ -115,8 +117,10 @@ static int setup_net_chip(void) /* Enable gpmc_nbe0_cle in CONTROL_PADCONF_GPMC_NWE register */ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00180000; - /* Enable gpmc_nbe1 in CONTROL_PADCONF_GPMC_NBE1 register and - configuring the mux mode to 0 */ + /* + * Enable gpmc_nbe1 in CONTROL_PADCONF_GPMC_NBE1 register and + * configuring the mux mode to 0 + */ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) |= 0x00000018; (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) &= 0xFFFFFFF8; /* Enable d15 in CONTROL_PADCONF_GPMC_D15 register */ @@ -155,20 +159,26 @@ static int setup_net_chip(void) (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) &= 0xFFFFFFF8; #if defined(CPU_3430_ES1) || defined(CPU_3430_ES2) - /* GPIO 64 configuration in CONTROL_PADCONF_GPMC_WAIT2 - register mux mode is 4. */ + /* + * GPIO 64 configuration in CONTROL_PADCONF_GPMC_WAIT2 + * register mux mode is 4. + */ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000018; (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) &= 0xFFFFFFF8; (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000004; - /* Configure GPIO 176 in CONTROL_PADCONF_MCSPI1_CS1 - register for ethernet ISR mux mode is 4 */ + /* + * Configure GPIO 176 in CONTROL_PADCONF_MCSPI1_CS1 + * register for ethernet ISR mux mode is 4 + */ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00180000; (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) &= 0xFFF8FFFF; (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00040000; - /* Enable Clock for GPIO 1-6 module in CM_FCLKEN_PER - and CM_ICLKEN_PER registers */ + /* + * Enable Clock for GPIO 1-6 module in CM_FCLKEN_PER + * and CM_ICLKEN_PER registers + */ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5000)) |= 0x0003E800; (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5010)) |= 0x0003E800; Index: u-boot-arm/include/configs/omap3_evm.h =================================================================== --- u-boot-arm.orig/include/configs/omap3_evm.h +++ u-boot-arm/include/configs/omap3_evm.h @@ -189,7 +189,8 @@ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ -/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ #define V_PVT 7 Index: u-boot-arm/include/configs/omap3_overo.h =================================================================== --- u-boot-arm.orig/include/configs/omap3_overo.h +++ u-boot-arm/include/configs/omap3_overo.h @@ -170,7 +170,8 @@ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ -/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ #define V_PVT 7

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[U-Boot] [PATCH-OMAP3 v2] OMAP3: Add missing GPL headers
by dirk.behme＠googlemail.com 20 Nov '08

20 Nov '08

Add missing GPL headers. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in v2: - Correct patch header style. v2 of this patch makes previous version v1 obsolete. board/omap3/beagle/config.mk | 20 +++++++++++++++++++- board/omap3/evm/config.mk | 20 +++++++++++++++++++- board/omap3/overo/config.mk | 19 +++++++++++++++++++ 3 files changed, 57 insertions(+), 2 deletions(-) Index: u-boot-arm/board/omap3/beagle/config.mk =================================================================== --- u-boot-arm.orig/board/omap3/beagle/config.mk +++ u-boot-arm/board/omap3/beagle/config.mk @@ -2,9 +2,27 @@ # (C) Copyright 2006 # Texas Instruments, <www.ti.com> # -# Begale Board uses OMAP3 (ARM-CortexA8) cpu +# Beagle Board uses OMAP3 (ARM-CortexA8) cpu # see http://www.ti.com/ for more information on Texas Instruments # +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# # Physical Address: # 8000'0000 (bank0) # A000/0000 (bank1) Index: u-boot-arm/board/omap3/evm/config.mk =================================================================== --- u-boot-arm.orig/board/omap3/evm/config.mk +++ u-boot-arm/board/omap3/evm/config.mk @@ -2,9 +2,27 @@ # (C) Copyright 2006 # Texas Instruments, <www.ti.com> # -# Begale Board uses OMAP3 (ARM-CortexA8) cpu +# EVM uses OMAP3 (ARM-CortexA8) cpu # see http://www.ti.com/ for more information on Texas Instruments # +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# # Physical Address: # 8000'0000 (bank0) # A000/0000 (bank1) Index: u-boot-arm/board/omap3/overo/config.mk =================================================================== --- u-boot-arm.orig/board/omap3/overo/config.mk +++ u-boot-arm/board/omap3/overo/config.mk @@ -1,5 +1,24 @@ +# # Overo uses OMAP3 (ARM-CortexA8) cpu # +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# # Physical Address: # 8000'0000 (bank0) # A000/0000 (bank1)

2 1

[U-Boot] [PATCH-OMAP3 v2] OMAP3: Fix typo and cp_delay
by dirk.behme＠googlemail.com 20 Nov '08

20 Nov '08

Fix typo and cp_delay. Note that most of ARM code uses for-loop as cp_delay() implementation. Scott Wood made some tests and volatile prevents gcc from optimizing loop away, so this implemention should be fine. For OMAP some nops are sufficent, though. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in v2: - Correct patch header style. v2 of this patch makes previous version v1 obsolete. cpu/arm_cortexa8/cpu.c | 5 ++--- cpu/arm_cortexa8/start.S | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) Index: u-boot-arm/cpu/arm_cortexa8/start.S =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/start.S +++ u-boot-arm/cpu/arm_cortexa8/start.S @@ -394,7 +394,7 @@ irq: .align 5 fiq: get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ + /* someone ought to write a more effective fiq_save_user_regs */ irq_save_user_regs bl do_fiq irq_restore_user_regs Index: u-boot-arm/cpu/arm_cortexa8/cpu.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/cpu.c +++ u-boot-arm/cpu/arm_cortexa8/cpu.c @@ -68,10 +68,9 @@ static void write_p15_c1(unsigned long v static void cp_delay(void) { - volatile int i; - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++) ; + asm("nop"); + asm("nop"); } /* See also ARM Ref. Man. */

2 1

[U-Boot] [PATCH-OMAP3 v2] OMAP3: Remove BITx magic
by dirk.behme＠googlemail.com 20 Nov '08

20 Nov '08

Remove bits.h and it's macros usage. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in v2: - Correct patch header style. v2 of this patch makes previous version v1 obsolete. cpu/arm_cortexa8/omap3/board.c | 3 -- cpu/arm_cortexa8/omap3/clock.c | 25 +++++++++--------- cpu/arm_cortexa8/omap3/interrupts.c | 18 ++++--------- cpu/arm_cortexa8/omap3/mem.c | 3 -- cpu/arm_cortexa8/omap3/sys_info.c | 14 ---------- cpu/arm_cortexa8/omap3/syslib.c | 1 include/asm-arm/arch-omap3/bits.h | 48 ------------------------------------ include/asm-arm/arch-omap3/cpu.h | 40 ++++++++++++++++++++++++------ 8 files changed, 53 insertions(+), 99 deletions(-) Index: u-boot-arm/include/asm-arm/arch-omap3/bits.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/bits.h +++ /dev/null @@ -1,48 +0,0 @@ -/* bits.h - * Copyright (c) 2004 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1 << 0) -#define BIT1 (1 << 1) -#define BIT2 (1 << 2) -#define BIT3 (1 << 3) -#define BIT4 (1 << 4) -#define BIT5 (1 << 5) -#define BIT6 (1 << 6) -#define BIT7 (1 << 7) -#define BIT8 (1 << 8) -#define BIT9 (1 << 9) -#define BIT10 (1 << 10) -#define BIT11 (1 << 11) -#define BIT12 (1 << 12) -#define BIT13 (1 << 13) -#define BIT14 (1 << 14) -#define BIT15 (1 << 15) -#define BIT16 (1 << 16) -#define BIT17 (1 << 17) -#define BIT18 (1 << 18) -#define BIT19 (1 << 19) -#define BIT20 (1 << 20) -#define BIT21 (1 << 21) -#define BIT22 (1 << 22) -#define BIT23 (1 << 23) -#define BIT24 (1 << 24) -#define BIT25 (1 << 25) -#define BIT26 (1 << 26) -#define BIT27 (1 << 27) -#define BIT28 (1 << 28) -#define BIT29 (1 << 29) -#define BIT30 (1 << 30) -#define BIT31 (1 << 31) - -#endif Index: u-boot-arm/include/asm-arm/arch-omap3/cpu.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/cpu.h +++ u-boot-arm/include/asm-arm/arch-omap3/cpu.h @@ -39,7 +39,8 @@ #define PRODUCTION_ID (OMAP34XX_TAP_BASE + 0x208) /* device type */ -#define DEVICE_MASK (BIT8 | BIT9 | BIT10) +#define DEVICE_MASK (0x7 << 8) +#define SYSBOOT_MASK 0x1F #define TST_DEVICE 0x0 #define EMU_DEVICE 0x1 #define HS_DEVICE 0x2 @@ -104,7 +105,7 @@ #define SMS_SYSCONFIG (OMAP34XX_SMS_BASE + 0x10) #define SMS_RG_ATT0 (OMAP34XX_SMS_BASE + 0x48) #define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE + 0xD0) -#define BURSTCOMPLETE_GROUP7 BIT31 +#define BURSTCOMPLETE_GROUP7 (0x1 << 31) /* SDRC */ #define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE + 0x10) @@ -115,13 +116,13 @@ #define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE + 0x64) #define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE + 0x68) #define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE + 0x6C) -#define DLLPHASE BIT1 -#define LOADDLL BIT2 +#define DLLPHASE (0x1 << 1) +#define LOADDLL (0x1 << 2) #define DLL_DELAY_MASK 0xFF00 -#define DLL_NO_FILTER_MASK (BIT8 | BIT9) +#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) #define SDRC_POWER (OMAP34XX_SDRC_BASE + 0x70) -#define WAKEUPPROC BIT26 +#define WAKEUPPROC (0x1 << 26) #define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE + 0x80) #define SDRC_MR_0 (OMAP34XX_SDRC_BASE + 0x84) @@ -141,7 +142,7 @@ #define CMD_ENTR_SRFRSH 0x5 #define CMD_CKE_HIGH 0x6 #define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 +#define SOFTRESET (0x1 << 1) #define SMART_IDLE (0x2 << 3) #define REF_ON_IDLE (0x1 << 6) @@ -162,7 +163,7 @@ #define TSICR 0x40 /* rw */ #define TCAR2 0x44 /* r */ /* enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0 << 2) | BIT1 | BIT0) +#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) /* Watchdog */ #define WWPS 0x34 /* r */ @@ -210,6 +211,29 @@ #define PRM_CLKSEL 0x48306d40 #define PRM_RSTCTRL 0x48307250 #define PRM_CLKSRC_CTRL 0x48307270 +#define SYSCLKDIV_1 (0x1 << 6) +#define SYSCLKDIV_2 (0x1 << 7) + +#define CLKSEL_GPT1 (0x1 << 0) + +#define EN_GPT1 (0x1 << 0) +#define EN_32KSYNC (0x1 << 2) + +#define ST_WDT2 (0x1 << 5) + +#define ST_MPU_CLK (0x1 << 0) + +#define ST_CORE_CLK (0x1 << 0) + +#define ST_PERIPH_CLK (0x1 << 1) + +#define ST_IVA2_CLK (0x1 << 0) + +#define RESETDONE (0x1 << 0) + +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) /* SMX-APE */ #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) Index: u-boot-arm/cpu/arm_cortexa8/omap3/clock.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/clock.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/clock.c @@ -27,7 +27,6 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/bits.h> #include <asm/arch/clocks.h> #include <asm/arch/clocks_omap3.h> #include <asm/arch/mem.h> @@ -46,17 +45,17 @@ u32 get_osc_clk_speed(void) val = readl(PRM_CLKSRC_CTRL); /* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~BIT7)) | BIT6; + val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1; writel(val, PRM_CLKSRC_CTRL); /* enable timer2 */ - val = readl(CM_CLKSEL_WKUP) | BIT0; + val = readl(CM_CLKSEL_WKUP) | CLKSEL_GPT1; writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ /* Enable I and F Clocks for GPT1 */ - val = readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; + val = readl(CM_ICLKEN_WKUP) | EN_GPT1 | EN_32KSYNC; writel(val, CM_ICLKEN_WKUP); - val = readl(CM_FCLKEN_WKUP) | BIT0; + val = readl(CM_FCLKEN_WKUP) | EN_GPT1; writel(val, CM_FCLKEN_WKUP); writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ @@ -160,7 +159,7 @@ void prcm_init(void) /* Unlock MPU DPLL (slows things down, and needed later) */ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); + wait_on_value(ST_MPU_CLK, 0, CM_IDLEST_PLL_MPU, LDELAY); /* Getting the base address of Core DPLL param table */ dpll_param_p = (dpll_param *) get_core_dpll_param(); @@ -173,7 +172,7 @@ void prcm_init(void) * sr32(CM_CLKSEL2_EMU) set override to work when asleep */ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); + wait_on_value(ST_CORE_CLK, 0, CM_IDLEST_CKGEN, LDELAY); /* * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't @@ -194,7 +193,7 @@ void prcm_init(void) sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); + wait_on_value(ST_CORE_CLK, 1, CM_IDLEST_CKGEN, LDELAY); } else if (is_running_in_flash()) { /* * if running from flash, jump to small relocated code @@ -223,7 +222,7 @@ void prcm_init(void) /* PER DPLL */ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + wait_on_value(ST_PERIPH_CLK, 0, CM_IDLEST_CKGEN, LDELAY); /* Getting the base address to PER DPLL param table */ /* Set N */ @@ -253,7 +252,7 @@ void prcm_init(void) sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); + wait_on_value(ST_PERIPH_CLK, 2, CM_IDLEST_CKGEN, LDELAY); /* Getting the base address to MPU DPLL param table */ dpll_param_p = (dpll_param *) get_mpu_dpll_param(); @@ -267,7 +266,7 @@ void prcm_init(void) sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); + wait_on_value(ST_MPU_CLK, 1, CM_IDLEST_PLL_MPU, LDELAY); /* Getting the base address to IVA DPLL param table */ dpll_param_p = (dpll_param *) get_iva_dpll_param(); @@ -277,13 +276,13 @@ void prcm_init(void) /* IVA DPLL (set to 12*20=240MHz) */ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); + wait_on_value(ST_IVA2_CLK, 0, CM_IDLEST_PLL_IVA2, LDELAY); sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); + wait_on_value(ST_IVA2_CLK, 1, CM_IDLEST_PLL_IVA2, LDELAY); /* Set up GPTimers to sys_clk source only */ sr32(CM_CLKSEL_PER, 0, 8, 0xff); Index: u-boot-arm/cpu/arm_cortexa8/omap3/mem.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/mem.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/mem.c @@ -27,7 +27,6 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/bits.h> #include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> #include <command.h> @@ -177,7 +176,7 @@ void do_sdrc_init(u32 offset, u32 early) if (early) { /* reset sdrc controller */ writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + wait_on_value(RESETDONE, RESETDONE, SDRC_STATUS, 12000000); writel(0, SDRC_SYSCONFIG); /* setup sdrc to ball mux */ Index: u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/sys_info.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c @@ -27,7 +27,6 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/bits.h> #include <asm/arch/mem.h> /* get mem tables */ #include <asm/arch/sys_proto.h> #include <i2c.h> @@ -147,14 +146,6 @@ u32 get_board_type(void) return sysinfo.board_type_v1; } -/****************************************************************** - * get_sysboot_value() - get init word settings - ******************************************************************/ -inline u32 get_sysboot_value(void) -{ - return 0x0000003F & readl(CONTROL_STATUS); -} - /*************************************************************************** * get_gpmc0_base() - Return current address hardware will be * fetching from. The below effectively gives what is correct, its a bit @@ -318,10 +309,7 @@ u32 is_running_in_sdram(void) ***************************************************************/ u32 get_boot_type(void) { - u32 v; - - v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); - return v; + return (readl(CONTROL_STATUS) & SYSBOOT_MASK); } /************************************************************* Index: u-boot-arm/cpu/arm_cortexa8/omap3/board.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/board.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/board.c @@ -34,7 +34,6 @@ */ #include <common.h> #include <asm/io.h> -#include <asm/arch/bits.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> @@ -251,7 +250,7 @@ void watchdog_init(void) sr32(CM_FCLKEN_WKUP, 5, 1, 1); sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + wait_on_value(ST_WDT2, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ writel(WD_UNLOCK1, WD2_BASE + WSPR); wait_for_command_complete(WD2_BASE); Index: u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/interrupts.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c @@ -33,8 +33,7 @@ */ #include <common.h> -#include <asm/arch/bits.h> - +#include <asm/io.h> #include <asm/proc-armv/ptrace.h> #define TIMER_LOAD_VAL 0 @@ -175,16 +174,11 @@ static ulong lastinc; /* nothing really to do with interrupts, just starts up a counter. */ int interrupt_init(void) { - int32_t val; - - /* - * Start the counter ticking up - * reload value on overflow - */ - *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; - /* mask to enable timer */ - val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0; - *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ + /* start the counter ticking up, reload value on overflow */ + writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TLDR); + /* enable timer */ + writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, + CONFIG_SYS_TIMERBASE + TCLR); reset_timer_masked(); /* init the timestamp and lastinc value */ Index: u-boot-arm/cpu/arm_cortexa8/omap3/syslib.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/syslib.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/syslib.c @@ -23,7 +23,6 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/bits.h> #include <asm/arch/mem.h> #include <asm/arch/clocks.h> #include <asm/arch/sys_proto.h>

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[U-Boot] [PATCH-OMAP3] OMAP3: Clean up coding style of board config files
by dirk.behme＠googlemail.com 20 Nov '08

20 Nov '08

Clean up coding style of board config files. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- include/configs/omap3_beagle.h | 204 ++++++++++++++++++++++------------------- include/configs/omap3_evm.h | 184 +++++++++++++++++++----------------- include/configs/omap3_overo.h | 189 +++++++++++++++++++++---------------- 3 files changed, 316 insertions(+), 261 deletions(-) Index: u-boot-arm/include/configs/omap3_beagle.h =================================================================== --- u-boot-arm.orig/include/configs/omap3_beagle.h +++ u-boot-arm/include/configs/omap3_beagle.h @@ -37,29 +37,30 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ -#define CONFIG_DOS_PARTITION 1 -#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> /* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) -#undef CONFIG_USE_IRQ /* no support for IRQs */ +#undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ /* * Hardware drivers @@ -68,28 +69,29 @@ /* * NS16550 Configuration */ -#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* * select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 #define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 /* commands to include */ @@ -114,32 +116,36 @@ #define CONFIG_CMD_RUN /* run command in env variable */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 /* - * Board NAND Info. + * Board NAND Info. */ #define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address to access nand at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +#define SECTORSIZE 512 #define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 #define CONFIG_SYS_NAND_WP #define CONFIG_JFFS2_NAND @@ -147,47 +153,57 @@ #define CONFIG_JFFS2_DEV "nand0" /* start of jffs2 partition */ #define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ /* Environment information */ -#define CONFIG_BOOTDELAY 10 - -#define CONFIG_BOOTCOMMAND "nand read 80200000 280000 400000 ; bootm 80200000" +#define CONFIG_BOOTDELAY 10 -#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 noinitrd root=/dev/mtdblock4 rw rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "nand read 80200000 280000 400000 ; " \ + "bootm 80200000" -#define CONFIG_NETMASK 255.255.254.0 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2," \ + "115200n8 noinitrd " \ + "root=/dev/mtdblock4 " \ + "rw rootfstype=jffs2" + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ -#define V_PROMPT "OMAP3 beagleboard.org # " +#define V_PROMPT "OMAP3 beagleboard.org # " #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT V_PROMPT -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) /* 31MB */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ + /* works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ + /* load address */ /* * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ -#define V_PVT 7 +#define V_PVT 7 -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) /*----------------------------------------------------------------------- * Stack sizes @@ -218,48 +234,52 @@ /* **** PISMO SUPPORT *** */ /* Configure the PISMO */ -#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M -#define PISMO1_NOR_SIZE GPMC_SIZE_64M +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M -#define DBG_MPDB_SIZE GPMC_SIZE_16M -#define PISMO2_SIZE 0 - -#define CONFIG_SYS_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ -#define PHYS_FLASH_SIZE_SDPV2 SZ_128M -#define PHYS_FLASH_SIZE SZ_32M +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M #define CONFIG_SYS_FLASH_BASE boot_flash_base -#define PHYS_FLASH_SECT_SIZE boot_flash_sec +#define PHYS_FLASH_SECT_SIZE boot_flash_sec /* Dummy declaration of flash banks to get compilation right */ #define CONFIG_SYS_FLASH_BANKS_LIST {0, 0} -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at start of flash */ -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define CONFIG_ENV_IS_IN_NAND 1 -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off -#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET /*----------------------------------------------------------------------- * CFI FLASH driver setup */ /* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) /* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) #define CONFIG_SYS_JFFS2_MEM_NAND -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS /* use flash_info[2] */ +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #define ENV_IS_VARIABLE 1 @@ -275,9 +295,9 @@ extern unsigned int boot_flash_type; #define WRITE_NAND_COMMAND(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD))) + writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD))) #define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR))) + writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR))) #define WRITE_NAND(d, adr) writew(d, (nand_cs_base + OFFS(GPMC_NAND_DAT))) #define READ_NAND(adr) readl((nand_cs_base + OFFS(GPMC_NAND_DAT))) @@ -288,4 +308,4 @@ extern unsigned int boot_flash_type; #define NAND_ENABLE_CE(nand) #define NAND_WAIT_READY(nand) udelay(10) -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ Index: u-boot-arm/include/configs/omap3_evm.h =================================================================== --- u-boot-arm.orig/include/configs/omap3_evm.h +++ u-boot-arm/include/configs/omap3_evm.h @@ -1,12 +1,11 @@ /* * (C) Copyright 2006-2008 * Texas Instruments. - * Author : - * Manikandan Pillai <mani.pillai(a)ti.com> + * Manikandan Pillai <mani.pillai(a)ti.com> * Derived from Beagle Board and 3430 SDP code by - * Richard Woodruff <r-woodruff2(a)ti.com> - * Syed Mohammed Khasim <khasim(a)ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> * * Manikandan Pillai <mani.pillai(a)ti.com> * @@ -43,7 +42,6 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_EVM 1 /* working with EVM */ -#define CONFIG_DOS_PARTITION 1 #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> @@ -52,7 +50,7 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#undef CONFIG_USE_IRQ /* no support for IRQs */ +#undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ @@ -63,9 +61,11 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ + /* Sector */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ /* * Hardware drivers @@ -74,7 +74,7 @@ /* * NS16550 Configuration */ -#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -84,18 +84,19 @@ /* * select serial console configuration */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 #define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 /* commands to include */ @@ -103,7 +104,7 @@ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ #define CONFIG_CMD_ONENAND /* ONENAND support */ @@ -118,36 +119,40 @@ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ #define CONFIG_CMD_MISC /* misc functions like sleep etc*/ #define CONFIG_CMD_RUN /* run command in env variable */ -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING -#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 #define CONFIG_DRIVER_OMAP34XX_I2C 1 /* - * Board NAND Info. + * Board NAND Info. */ -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address to access nand at CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define SECTORSIZE 512 #define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 #define CONFIG_SYS_NAND_WP #define CONFIG_JFFS2_NAND @@ -160,11 +165,11 @@ /* Environment information */ #define CONFIG_BOOTDELAY 10 -#define CONFIG_BOOTCOMMAND "onenand read 80200000 280000 400000 ; \ - bootm 80200000" +#define CONFIG_BOOTCOMMAND "onenand read 80200000 280000 400000 ; " \ + "bootm 80200000" -#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 noinitrd \ - root=/dev/mtdblock4 rw rootfstype=jffs2" +#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 noinitrd " \ + "root=/dev/mtdblock4 rw rootfstype=jffs2" #define CONFIG_NETMASK 255.255.254.0 #define CONFIG_BOOTFILE "uImage" @@ -178,22 +183,28 @@ #define CONFIG_SYS_PROMPT V_PROMPT #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) /* 31MB */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */ + /* in Hz */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ /* * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ -#define V_PVT 7 +#define V_PVT 7 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 #define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ @@ -228,51 +239,55 @@ /* **** PISMO SUPPORT *** */ /* Configure the PISMO */ -#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M -#define PISMO1_NOR_SIZE GPMC_SIZE_64M +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M -#define DBG_MPDB_SIZE GPMC_SIZE_16M -#define PISMO2_SIZE 0 - -#define CONFIG_SYS_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ + /* on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ -#define PHYS_FLASH_SIZE_SDPV2 SZ_128M -#define PHYS_FLASH_SIZE SZ_32M +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M #define CONFIG_SYS_FLASH_BASE boot_flash_base -#define PHYS_FLASH_SECT_SIZE boot_flash_sec +#define PHYS_FLASH_SECT_SIZE boot_flash_sec /* Dummy declaration of flash banks to get compilation right */ #define CONFIG_SYS_FLASH_BANKS_LIST {0, 0} -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at start of flash */ -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define CONFIG_ENV_IS_IN_ONENAND 1 -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_ONENAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off -#define CONFIG_ENV_ADDR boot_flash_env_addr +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR boot_flash_env_addr /*----------------------------------------------------------------------- * CFI FLASH driver setup */ /* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) /* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) #define CONFIG_SYS_JFFS2_MEM_NAND -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS /* use flash_info[2] */ +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS #define CONFIG_SYS_JFFS2_NUM_BANKS 1 -#define ENV_IS_VARIABLE 1 +#define ENV_IS_VARIABLE 1 #ifndef __ASSEMBLY__ extern unsigned int *nand_cs_base; @@ -285,9 +300,9 @@ extern unsigned int boot_flash_type; #define WRITE_NAND_COMMAND(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD))) + writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD))) #define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR))) + writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR))) #define WRITE_NAND(d, adr) writel(d, (nand_cs_base + OFFS(GPMC_NAND_DAT))) #define READ_NAND(adr) readl((nand_cs_base + OFFS(GPMC_NAND_DAT))) @@ -300,25 +315,24 @@ extern unsigned int boot_flash_type; /*---------------------------------------------------------------------------- - * SMSC9115 Ethernet from SMSC9118 family - * ---------------------------------------------------------------------------- + * SMSC9115 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- */ #if defined(CONFIG_CMD_NET) #define CONFIG_DRIVER_SMC911X #define CONFIG_DRIVER_SMC911X_32_BIT -#define CONFIG_DRIVER_SMC911X_BASE (0x2C000000) +#define CONFIG_DRIVER_SMC911X_BASE 0x2C000000 -#endif /* (CONFIG_CMD_NET) */ +#endif /* (CONFIG_CMD_NET) */ /* - * BOOTP fields + * BOOTP fields */ - #define CONFIG_BOOTP_SUBNETMASK 0x00000001 #define CONFIG_BOOTP_GATEWAY 0x00000002 #define CONFIG_BOOTP_HOSTNAME 0x00000004 #define CONFIG_BOOTP_BOOTPATH 0x00000010 -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ Index: u-boot-arm/include/configs/omap3_overo.h =================================================================== --- u-boot-arm.orig/include/configs/omap3_overo.h +++ u-boot-arm/include/configs/omap3_overo.h @@ -34,23 +34,25 @@ #include <asm/arch/omap3.h> /* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) #undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ /* * Hardware drivers @@ -59,28 +61,29 @@ /* * NS16550 Configuration */ -#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* * select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 #define CONFIG_SYS_MMC_BASE 0xF0000000 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 /* commands to include */ @@ -109,28 +112,32 @@ #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 #define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 /* - * Board NAND Info. + * Board NAND Info. */ #define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address to access nand at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand */ + /* at CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +#define SECTORSIZE 512 #define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 #define CONFIG_SYS_NAND_WP #define CONFIG_JFFS2_NAND @@ -138,47 +145,57 @@ #define CONFIG_JFFS2_DEV "nand0" /* start of jffs2 partition */ #define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ /* Environment information */ -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_BOOTCOMMAND "mmcinit; fatload mmc 0 82000000 uImage; bootm 82000000" +#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootdelay=1" +#define CONFIG_BOOTCOMMAND "mmcinit; fatload mmc 0 82000000 uImage; "\ + "bootm 82000000" -#define CONFIG_NETMASK 255.255.254.0 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 " \ + "root=/dev/mmcblk0p2 rw rootfstype=ext3 " \ + "rootwait" + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ -#define V_PROMPT "Overo # " +#define V_PROMPT "Overo # " #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT V_PROMPT -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) /* 31MB */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */ + /* in Hz */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ /* * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ -#define V_PVT 7 +#define V_PVT 7 -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) /*----------------------------------------------------------------------- * Stack sizes @@ -209,51 +226,55 @@ /* **** PISMO SUPPORT *** */ /* Configure the PISMO */ -#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M -#define PISMO1_NOR_SIZE GPMC_SIZE_64M +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M -#define DBG_MPDB_SIZE GPMC_SIZE_16M -#define PISMO2_SIZE 0 - -#define CONFIG_SYS_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ -#define PHYS_FLASH_SIZE_SDPV2 SZ_128M -#define PHYS_FLASH_SIZE SZ_32M +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M #define CONFIG_SYS_FLASH_BASE boot_flash_base -#define PHYS_FLASH_SECT_SIZE boot_flash_sec +#define PHYS_FLASH_SECT_SIZE boot_flash_sec /* Dummy declaration of flash banks to get compilation right */ #define CONFIG_SYS_FLASH_BANKS_LIST {0, 0} -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at start of flash */ -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define CONFIG_ENV_IS_IN_NAND 1 -#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ -#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off -#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET /*----------------------------------------------------------------------- * CFI FLASH driver setup */ /* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) /* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) #define CONFIG_SYS_JFFS2_MEM_NAND -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS /* use flash_info[2] */ +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS #define CONFIG_SYS_JFFS2_NUM_BANKS 1 -#define ENV_IS_VARIABLE 1 +#define ENV_IS_VARIABLE 1 #ifndef __ASSEMBLY__ extern unsigned int *nand_cs_base;

2 1

[U-Boot] [PATCH-OMAP3] OMAP3: Clean up board files
by dirk.behme＠googlemail.com 20 Nov '08

20 Nov '08

- Use readx/writex instead of direct pointer access - Replace hardcoded values by macros - Minor space to tab conversion No functional change. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- board/omap3/beagle/beagle.c | 78 +++++++++++++++++++------------- board/omap3/overo/overo.c | 90 ++++++++++++++++++++++--------------- include/asm-arm/arch-omap3/omap3.h | 70 ++++++++++++++++++++++++++++ 3 files changed, 171 insertions(+), 67 deletions(-) Index: u-boot-arm/board/omap3/beagle/beagle.c =================================================================== --- u-boot-arm.orig/board/omap3/beagle/beagle.c +++ u-boot-arm/board/omap3/beagle/beagle.c @@ -3,12 +3,12 @@ * Texas Instruments, <www.ti.com> * * Author : - * Sunil Kumar <sunilsaini05(a)gmail.com> - * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> * * Derived from Beagle Board and 3430 SDP code by - * Richard Woodruff <r-woodruff2(a)ti.com> - * Syed Mohammed Khasim <khasim(a)ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> * * * See file CREDITS for list of people who contributed to this @@ -56,41 +56,59 @@ int board_init(void) /****************************************************************************** * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) + * Description: Configure power supply *****************************************************************************/ int misc_init_r(void) { unsigned char byte; + unsigned int *gpio5_base = (unsigned int *)OMAP34XX_GPIO5_BASE; + unsigned int *gpio6_base = (unsigned int *)OMAP34XX_GPIO6_BASE; #ifdef CONFIG_DRIVER_OMAP34XX_I2C i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif - /* set vaux3 to 2.8V */ - byte = 0x20; - i2c_write(0x4B, 0x7A, 1, &byte, 1); - byte = 0x03; - i2c_write(0x4B, 0x7D, 1, &byte, 1); - - /* set vpll2 to 1.8V */ - byte = 0xE0; - i2c_write(0x4B, 0x8E, 1, &byte, 1); - byte = 0x05; - i2c_write(0x4B, 0x91, 1, &byte, 1); + + /* + * Configure OMAP3 supply voltages in power management + * companion chip. + */ + + /* set VAUX3 to 2.8V */ + byte = DEV_GRP_P1; + i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEV_GRP, 1, &byte, 1); + byte = VAUX3_VSEL_28; + i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEDICATED, 1, &byte, 1); + + /* set VPLL2 to 1.8V */ + byte = DEV_GRP_ALL; + i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEV_GRP, 1, &byte, 1); + byte = VPLL2_VSEL_18; + i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEDICATED, 1, &byte, 1); /* set VDAC to 1.8V */ - byte = 0x20; - i2c_write(0x4B, 0x96, 1, &byte, 1); - byte = 0x03; - i2c_write(0x4B, 0x99, 1, &byte, 1); - - byte = 0x33; - i2c_write(0x4A, 0xEE, 1, &byte, 1); - - *((uint *) 0x49058034) = 0xFFFFFAF9; - *((uint *) 0x49056034) = 0x0F9F0FFF; - *((uint *) 0x49058094) = 0x00000506; - *((uint *) 0x49056094) = 0xF060F000; + byte = DEV_GRP_P1; + i2c_write(PWRMGT_ADDR_ID4, VDAC_DEV_GRP, 1, &byte, 1); + byte = VDAC_VSEL_18; + i2c_write(PWRMGT_ADDR_ID4, VDAC_DEDICATED, 1, &byte, 1); + + /* enable LED */ + byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON; + i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1); + + /* Configure GPIOs to output */ + writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2), + gpio6_base + OFFS(GPIO_OE)); + writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12), + gpio5_base + OFFS(GPIO_OE)); + + /* Set GPIOs */ + writel(GPIO10 | GPIO9 | GPIO3 | GPIO2, + gpio6_base + OFFS(GPIO_SETDATAOUT)); + writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12, + gpio5_base + OFFS(GPIO_SETDATAOUT)); return 0; } @@ -98,8 +116,8 @@ int misc_init_r(void) /****************************************************************************** * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. + * hardware. Many pins need to be moved from protect to primary + * mode. *****************************************************************************/ void set_muxconf_regs(void) { Index: u-boot-arm/board/omap3/overo/overo.c =================================================================== --- u-boot-arm.orig/board/omap3/overo/overo.c +++ u-boot-arm/board/omap3/overo/overo.c @@ -2,10 +2,10 @@ * Maintainer : Steve Sakoman <steve(a)sakoman.com> * * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by - * Richard Woodruff <r-woodruff2(a)ti.com> - * Syed Mohammed Khasim <khasim(a)ti.com> - * Sunil Kumar <sunilsaini05(a)gmail.com> - * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> * * (C) Copyright 2004-2008 * Texas Instruments, <www.ti.com> @@ -55,47 +55,65 @@ int board_init(void) /****************************************************************************** * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) + * Description: Configure power supply *****************************************************************************/ int misc_init_r(void) { unsigned char byte; + unsigned int *gpio5_base = (unsigned int *)OMAP34XX_GPIO5_BASE; + unsigned int *gpio6_base = (unsigned int *)OMAP34XX_GPIO6_BASE; #ifdef CONFIG_DRIVER_OMAP34XX_I2C i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif - /* set vaux2 to 2.8V */ - byte = 0x20; - i2c_write(0x4B, 0x76, 1, &byte, 1); - byte = 0x09; - i2c_write(0x4B, 0x79, 1, &byte, 1); - - /* set vaux3 to 2.8V */ - byte = 0x20; - i2c_write(0x4B, 0x7A, 1, &byte, 1); - byte = 0x03; - i2c_write(0x4B, 0x7D, 1, &byte, 1); - - /* set vpll2 to 1.8V */ - byte = 0xE0; - i2c_write(0x4B, 0x8E, 1, &byte, 1); - byte = 0x05; - i2c_write(0x4B, 0x91, 1, &byte, 1); + + /* + * Configure OMAP3 supply voltages in power management + * companion chip. + */ + + /* set VAUX2 to 2.8V */ + byte = DEV_GRP_P1; + i2c_write(PWRMGT_ADDR_ID4, VAUX2_DEV_GRP, 1, &byte, 1); + byte = VAUX2_VSEL_28; + i2c_write(PWRMGT_ADDR_ID4, VAUX2_DEDICATED, 1, &byte, 1); + + /* set VAUX3 to 2.8V */ + byte = DEV_GRP_P1; + i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEV_GRP, 1, &byte, 1); + byte = VAUX3_VSEL_28; + i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEDICATED, 1, &byte, 1); + + /* set VPLL2 to 1.8V */ + byte = DEV_GRP_ALL; + i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEV_GRP, 1, &byte, 1); + byte = VPLL2_VSEL_18; + i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEDICATED, 1, &byte, 1); /* set VDAC to 1.8V */ - byte = 0x20; - i2c_write(0x4B, 0x96, 1, &byte, 1); - byte = 0x03; - i2c_write(0x4B, 0x99, 1, &byte, 1); - - byte = 0x33; - i2c_write(0x4A, 0xEE, 1, &byte, 1); - - *((uint *) 0x49058034) = 0xFFFFFAF9; - *((uint *) 0x49056034) = 0x0F9F0FFF; - *((uint *) 0x49058094) = 0x00000506; - *((uint *) 0x49056094) = 0xF060F000; + byte = DEV_GRP_P1; + i2c_write(PWRMGT_ADDR_ID4, VDAC_DEV_GRP, 1, &byte, 1); + byte = VDAC_VSEL_18; + i2c_write(PWRMGT_ADDR_ID4, VDAC_DEDICATED, 1, &byte, 1); + + /* enable LED */ + byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON; + i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1); + + /* Configure GPIOs to output */ + writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2), + gpio6_base + OFFS(GPIO_OE)); + writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12), + gpio5_base + OFFS(GPIO_OE)); + + /* Set GPIOs */ + writel(GPIO10 | GPIO9 | GPIO3 | GPIO2, + gpio6_base + OFFS(GPIO_SETDATAOUT)); + writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12, + gpio5_base + OFFS(GPIO_SETDATAOUT)); return 0; } @@ -103,8 +121,8 @@ int misc_init_r(void) /****************************************************************************** * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. + * hardware. Many pins need to be moved from protect to primary + * mode. *****************************************************************************/ void set_muxconf_regs(void) { Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/omap3.h +++ u-boot-arm/include/asm-arm/arch-omap3/omap3.h @@ -77,7 +77,7 @@ #define SYNC_32KTIMER_BASE 0x48320000 #define S32K_CR (SYNC_32KTIMER_BASE + 0x10) -/* omap3 GPIO registers */ +/* OMAP3 GPIO registers */ #define OMAP34XX_GPIO1_BASE 0x48310000 #define OMAP34XX_GPIO2_BASE 0x49050000 #define OMAP34XX_GPIO3_BASE 0x49052000 @@ -85,6 +85,42 @@ #define OMAP34XX_GPIO5_BASE 0x49056000 #define OMAP34XX_GPIO6_BASE 0x49058000 +#define GPIO_OE 0x34 +#define GPIO_SETDATAOUT 0x94 + +#define GPIO0 (0x1 << 0) +#define GPIO1 (0x1 << 1) +#define GPIO2 (0x1 << 2) +#define GPIO3 (0x1 << 3) +#define GPIO4 (0x1 << 4) +#define GPIO5 (0x1 << 5) +#define GPIO6 (0x1 << 6) +#define GPIO7 (0x1 << 7) +#define GPIO8 (0x1 << 8) +#define GPIO9 (0x1 << 9) +#define GPIO10 (0x1 << 10) +#define GPIO11 (0x1 << 11) +#define GPIO12 (0x1 << 12) +#define GPIO13 (0x1 << 13) +#define GPIO14 (0x1 << 14) +#define GPIO15 (0x1 << 15) +#define GPIO16 (0x1 << 16) +#define GPIO17 (0x1 << 17) +#define GPIO18 (0x1 << 18) +#define GPIO19 (0x1 << 19) +#define GPIO20 (0x1 << 20) +#define GPIO21 (0x1 << 21) +#define GPIO22 (0x1 << 22) +#define GPIO23 (0x1 << 23) +#define GPIO24 (0x1 << 24) +#define GPIO25 (0x1 << 25) +#define GPIO26 (0x1 << 26) +#define GPIO27 (0x1 << 27) +#define GPIO28 (0x1 << 28) +#define GPIO29 (0x1 << 29) +#define GPIO30 (0x1 << 30) +#define GPIO31 (0x1 << 31) + /* base address for indirect vectors (internal boot mode) */ #define SRAM_OFFSET0 0x40000000 #define SRAM_OFFSET1 0x00200000 @@ -132,4 +168,36 @@ #define OMAP3EVM_V1 0x1 #define OMAP3EVM_V2 0x2 +/* I2C power management companion definitions */ +#define PWRMGT_ADDR_ID1 0x48 +#define PWRMGT_ADDR_ID2 0x49 +#define PWRMGT_ADDR_ID3 0x4A +#define PWRMGT_ADDR_ID4 0x4B + +/* I2C ID3 (slave3) register */ +#define LEDEN 0xEE + +#define LEDAON (0x1 << 0) +#define LEDBON (0x1 << 1) +#define LEDAPWM (0x1 << 4) +#define LEDBPWM (0x1 << 5) + +/* I2C ID4 (slave4) register */ +#define VAUX2_DEV_GRP 0x76 +#define VAUX2_DEDICATED 0x79 +#define VAUX3_DEV_GRP 0x7A +#define VAUX3_DEDICATED 0x7D +#define VPLL2_DEV_GRP 0x8E +#define VPLL2_DEDICATED 0x91 +#define VDAC_DEV_GRP 0x96 +#define VDAC_DEDICATED 0x99 + +#define DEV_GRP_P1 0x20 +#define DEV_GRP_ALL 0xE0 + +#define VAUX2_VSEL_28 0x09 +#define VAUX3_VSEL_28 0x03 +#define VPLL2_VSEL_18 0x05 +#define VDAC_VSEL_18 0x03 + #endif

2 1

[U-Boot] [PATCH-OMAP3] OMAP3: Use macro instead of value in lowlevel_init.S
by dirk.behme＠googlemail.com 20 Nov '08

20 Nov '08

Add space after comma and use MACRO instead of value. No functional change. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- cpu/arm_cortexa8/omap3/lowlevel_init.S | 136 +++++++------- include/asm-arm/arch-omap3/clocks_omap3.h | 286 ++++++++++++++++++++++++------ 2 files changed, 304 insertions(+), 118 deletions(-) Index: u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/lowlevel_init.S +++ u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S @@ -127,7 +127,7 @@ wait2: nop nop nop - ldmfd sp!, {r4 - r6} + ldmfd sp!, {r4 - r6} mov pc, lr /* back to caller, locked */ _go_to_speed: .word go_to_speed @@ -171,15 +171,15 @@ pll_div_val5: .globl lowlevel_init lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll, mux, memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ /* back to arch calling code */ - mov pc, lr + mov pc, lr /* the literal pools origin */ .ltorg @@ -190,7 +190,9 @@ SRAM_STACK: .word LOW_LEVEL_SRAM_STACK /* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + +/* + * Each of the tables has M, N, FREQSEL, M2 values defined for nominal * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c). * The values are defined for all possible sysclk and for ES1 and ES2. */ @@ -198,162 +200,162 @@ SRAM_STACK: mpu_dpll_param: /* 12MHz */ /* ES1 */ -.word 0x0FE, 0x07, 0x05, 0x01 +.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1 /* ES2 */ -.word 0x0FA, 0x05, 0x07, 0x01 +.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2 /* 3410 */ -.word 0x085, 0x05, 0x07, 0x01 +.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12 /* 13MHz */ /* ES1 */ -.word 0x17D, 0x0C, 0x03, 0x01 +.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1 /* ES2 */ -.word 0x1F4, 0x0C, 0x03, 0x01 +.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2 /* 3410 */ -.word 0x10A, 0x0C, 0x03, 0x01 +.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13 /* 19.2MHz */ /* ES1 */ -.word 0x179, 0x12, 0x04, 0x01 +.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1 /* ES2 */ -.word 0x271, 0x17, 0x03, 0x01 +.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2 /* 3410 */ -.word 0x14C, 0x17, 0x03, 0x01 +.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2 /* 26MHz */ /* ES1 */ -.word 0x17D, 0x19, 0x03, 0x01 +.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1 /* ES2 */ -.word 0x0FA, 0x0C, 0x07, 0x01 +.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2 /* 3410 */ -.word 0x085, 0x0C, 0x07, 0x01 +.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26 /* 38.4MHz */ /* ES1 */ -.word 0x1FA, 0x32, 0x03, 0x01 +.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1 /* ES2 */ -.word 0x271, 0x2F, 0x03, 0x01 +.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2 /* 3410 */ -.word 0x14C, 0x2F, 0x03, 0x01 +.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4 .globl get_mpu_dpll_param get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr + adr r0, mpu_dpll_param + mov pc, lr iva_dpll_param: /* 12MHz */ /* ES1 */ -.word 0x07D, 0x05, 0x07, 0x01 +.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1 /* ES2 */ -.word 0x0B4, 0x05, 0x07, 0x01 +.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2 /* 3410 */ -.word 0x085, 0x05, 0x07, 0x01 +.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12 /* 13MHz */ /* ES1 */ -.word 0x0FA, 0x0C, 0x03, 0x01 +.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1 /* ES2 */ -.word 0x168, 0x0C, 0x03, 0x01 +.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2 /* 3410 */ -.word 0x10A, 0x0C, 0x03, 0x01 +.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13 /* 19.2MHz */ /* ES1 */ -.word 0x082, 0x09, 0x07, 0x01 +.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1 /* ES2 */ -.word 0x0E1, 0x0B, 0x06, 0x01 +.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2 /* 3410 */ -.word 0x14C, 0x17, 0x03, 0x01 +.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2 /* 26MHz */ /* ES1 */ -.word 0x07D, 0x0C, 0x07, 0x01 +.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1 /* ES2 */ -.word 0x0B4, 0x0C, 0x07, 0x01 +.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2 /* 3410 */ -.word 0x085, 0x0C, 0x07, 0x01 +.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26 /* 38.4MHz */ /* ES1 */ -.word 0x13F, 0x30, 0x03, 0x01 +.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1 /* ES2 */ -.word 0x0E1, 0x17, 0x06, 0x01 +.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2 /* 3410 */ -.word 0x14C, 0x2F, 0x03, 0x01 +.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4 .globl get_iva_dpll_param get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr + adr r0, iva_dpll_param + mov pc, lr /* Core DPLL targets for L3 at 166 & L133 */ core_dpll_param: /* 12MHz */ /* ES1 */ -.word M_12_ES1, M_12_ES1, FSL_12_ES1, M2_12_ES1 +.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1 /* ES2 */ -.word M_12, N_12, FSEL_12, M2_12 +.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 /* 3410 */ -.word M_12, N_12, FSEL_12, M2_12 +.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 /* 13MHz */ /* ES1 */ -.word M_13_ES1, N_13_ES1, FSL_13_ES1, M2_13_ES1 +.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1 /* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 +.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 /* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 +.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 /* 19.2MHz */ /* ES1 */ -.word M_19p2_ES1, N_19p2_ES1, FSL_19p2_ES1, M2_19p2_ES1 +.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1 /* ES2 */ -.word M_19p2, N_19p2, FSEL_19p2, M2_19p2 +.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 /* 3410 */ -.word M_19p2, N_19p2, FSEL_19p2, M2_19p2 +.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 /* 26MHz */ /* ES1 */ -.word M_26_ES1, N_26_ES1, FSL_26_ES1, M2_26_ES1 +.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1 /* ES2 */ -.word M_26, N_26, FSEL_26, M2_26 +.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 /* 3410 */ -.word M_26, N_26, FSEL_26, M2_26 +.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 /* 38.4MHz */ /* ES1 */ -.word M_38p4_ES1, N_38p4_ES1, FSL_38p4_ES1, M2_38p4_ES1 +.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1 /* ES2 */ -.word M_38p4, N_38p4, FSEL_38p4, M2_38p4 +.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 /* 3410 */ -.word M_38p4, N_38p4, FSEL_38p4, M2_38p4 +.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 .globl get_core_dpll_param get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr + adr r0, core_dpll_param + mov pc, lr /* PER DPLL values are same for both ES1 and ES2 */ per_dpll_param: /* 12MHz */ -.word 0xD8, 0x05, 0x07, 0x09 +.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12 /* 13MHz */ -.word 0x1B0, 0x0C, 0x03, 0x09 +.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13 /* 19.2MHz */ -.word 0xE1, 0x09, 0x07, 0x09 +.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2 /* 26MHz */ -.word 0xD8, 0x0C, 0x07, 0x09 +.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26 /* 38.4MHz */ -.word 0xE1, 0x13, 0x07, 0x09 +.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4 .globl get_per_dpll_param get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr + adr r0, per_dpll_param + mov pc, lr Index: u-boot-arm/include/asm-arm/arch-omap3/clocks_omap3.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/clocks_omap3.h +++ u-boot-arm/include/asm-arm/arch-omap3/clocks_omap3.h @@ -26,7 +26,8 @@ #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ -/* The following configurations are OPP and SysClk value independant +/* + * The following configurations are OPP and SysClk value independant * and hence are defined here. All the other DPLL related values are * tabulated in lowlevel_init.S. */ @@ -37,7 +38,7 @@ #define CORE_FUSB_DIV 2 /* 41.5MHz: */ #define CORE_L4_DIV 2 /* 83MHz : L4 */ #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ /* PER DPLL */ @@ -48,54 +49,237 @@ #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) -#define M_12 0xA6 -#define N_12 0x05 -#define FSEL_12 0x07 -#define M2_12 0x01 /* M3 of 2 */ - -#define M_12_ES1 0x19F -#define N_12_ES1 0x0E -#define FSL_12_ES1 0x03 -#define M2_12_ES1 0x1 /* M3 of 2 */ - -#define M_13 0x14C -#define N_13 0x0C -#define FSEL_13 0x03 -#define M2_13 0x01 /* M3 of 2 */ - -#define M_13_ES1 0x1B2 -#define N_13_ES1 0x10 -#define FSL_13_ES1 0x03 -#define M2_13_ES1 0x01 /* M3 of 2 */ - -#define M_19p2 0x19F -#define N_19p2 0x17 -#define FSEL_19p2 0x03 -#define M2_19p2 0x01 /* M3 of 2 */ - -#define M_19p2_ES1 0x19F -#define N_19p2_ES1 0x17 -#define FSL_19p2_ES1 0x03 -#define M2_19p2_ES1 0x01 /* M3 of 2 */ - -#define M_26 0xA6 -#define N_26 0x0C -#define FSEL_26 0x07 -#define M2_26 0x01 /* M3 of 2 */ - -#define M_26_ES1 0x1B2 -#define N_26_ES1 0x21 -#define FSL_26_ES1 0x03 -#define M2_26_ES1 0x01 /* M3 of 2 */ - -#define M_38p4 0x19F -#define N_38p4 0x2F -#define FSEL_38p4 0x03 -#define M2_38p4 0x01 /* M3 of 2 */ - -#define M_38p4_ES1 0x19F -#define N_38p4_ES1 0x2F -#define FSL_38p4_ES1 0x03 -#define M2_38p4_ES1 0x01 /* M3 of 2 */ +/* MPU DPLL */ + +#define MPU_M_12_ES1 0x0FE +#define MPU_N_12_ES1 0x07 +#define MPU_FSEL_12_ES1 0x05 +#define MPU_M2_12_ES1 0x01 + +#define MPU_M_12_ES2 0x0FA +#define MPU_N_12_ES2 0x05 +#define MPU_FSEL_12_ES2 0x07 +#define MPU_M2_ES2 0x01 + +#define MPU_M_12 0x085 +#define MPU_N_12 0x05 +#define MPU_FSEL_12 0x07 +#define MPU_M2_12 0x01 + +#define MPU_M_13_ES1 0x17D +#define MPU_N_13_ES1 0x0C +#define MPU_FSEL_13_ES1 0x03 +#define MPU_M2_13_ES1 0x01 + +#define MPU_M_13_ES2 0x1F4 +#define MPU_N_13_ES2 0x0C +#define MPU_FSEL_13_ES2 0x03 +#define MPU_M2_13_ES2 0x01 + +#define MPU_M_13 0x10A +#define MPU_N_13 0x0C +#define MPU_FSEL_13 0x03 +#define MPU_M2_13 0x01 + +#define MPU_M_19P2_ES1 0x179 +#define MPU_N_19P2_ES1 0x12 +#define MPU_FSEL_19P2_ES1 0x04 +#define MPU_M2_19P2_ES1 0x01 + +#define MPU_M_19P2_ES2 0x271 +#define MPU_N_19P2_ES2 0x17 +#define MPU_FSEL_19P2_ES2 0x03 +#define MPU_M2_19P2_ES2 0x01 + +#define MPU_M_19P2 0x14C +#define MPU_N_19P2 0x17 +#define MPU_FSEL_19P2 0x03 +#define MPU_M2_19P2 0x01 + +#define MPU_M_26_ES1 0x17D +#define MPU_N_26_ES1 0x19 +#define MPU_FSEL_26_ES1 0x03 +#define MPU_M2_26_ES1 0x01 + +#define MPU_M_26_ES2 0x0FA +#define MPU_N_26_ES2 0x0C +#define MPU_FSEL_26_ES2 0x07 +#define MPU_M2_26_ES2 0x01 + +#define MPU_M_26 0x085 +#define MPU_N_26 0x0C +#define MPU_FSEL_26 0x07 +#define MPU_M2_26 0x01 + +#define MPU_M_38P4_ES1 0x1FA +#define MPU_N_38P4_ES1 0x32 +#define MPU_FSEL_38P4_ES1 0x03 +#define MPU_M2_38P4_ES1 0x01 + +#define MPU_M_38P4_ES2 0x271 +#define MPU_N_38P4_ES2 0x2F +#define MPU_FSEL_38P4_ES2 0x03 +#define MPU_M2_38P4_ES2 0x01 + +#define MPU_M_38P4 0x14C +#define MPU_N_38P4 0x2F +#define MPU_FSEL_38P4 0x03 +#define MPU_M2_38P4 0x01 + +/* IVA DPLL */ + +#define IVA_M_12_ES1 0x07D +#define IVA_N_12_ES1 0x05 +#define IVA_FSEL_12_ES1 0x07 +#define IVA_M2_12_ES1 0x01 + +#define IVA_M_12_ES2 0x0B4 +#define IVA_N_12_ES2 0x05 +#define IVA_FSEL_12_ES2 0x07 +#define IVA_M2_12_ES2 0x01 + +#define IVA_M_12 0x085 +#define IVA_N_12 0x05 +#define IVA_FSEL_12 0x07 +#define IVA_M2_12 0x01 + +#define IVA_M_13_ES1 0x0FA +#define IVA_N_13_ES1 0x0C +#define IVA_FSEL_13_ES1 0x03 +#define IVA_M2_13_ES1 0x01 + +#define IVA_M_13_ES2 0x168 +#define IVA_N_13_ES2 0x0C +#define IVA_FSEL_13_ES2 0x03 +#define IVA_M2_13_ES2 0x01 + +#define IVA_M_13 0x10A +#define IVA_N_13 0x0C +#define IVA_FSEL_13 0x03 +#define IVA_M2_13 0x01 + +#define IVA_M_19P2_ES1 0x082 +#define IVA_N_19P2_ES1 0x09 +#define IVA_FSEL_19P2_ES1 0x07 +#define IVA_M2_19P2_ES1 0x01 + +#define IVA_M_19P2_ES2 0x0E1 +#define IVA_N_19P2_ES2 0x0B +#define IVA_FSEL_19P2_ES2 0x06 +#define IVA_M2_19P2_ES2 0x01 + +#define IVA_M_19P2 0x14C +#define IVA_N_19P2 0x17 +#define IVA_FSEL_19P2 0x03 +#define IVA_M2_19P2 0x01 + +#define IVA_M_26_ES1 0x07D +#define IVA_N_26_ES1 0x0C +#define IVA_FSEL_26_ES1 0x07 +#define IVA_M2_26_ES1 0x01 + +#define IVA_M_26_ES2 0x0B4 +#define IVA_N_26_ES2 0x0C +#define IVA_FSEL_26_ES2 0x07 +#define IVA_M2_26_ES2 0x01 + +#define IVA_M_26 0x085 +#define IVA_N_26 0x0C +#define IVA_FSEL_26 0x07 +#define IVA_M2_26 0x01 + +#define IVA_M_38P4_ES1 0x13F +#define IVA_N_38P4_ES1 0x30 +#define IVA_FSEL_38P4_ES1 0x03 +#define IVA_M2_38P4_ES1 0x01 + +#define IVA_M_38P4_ES2 0x0E1 +#define IVA_N_38P4_ES2 0x17 +#define IVA_FSEL_38P4_ES2 0x06 +#define IVA_M2_38P4_ES2 0x01 + +#define IVA_M_38P4 0x14C +#define IVA_N_38P4 0x2F +#define IVA_FSEL_38P4 0x03 +#define IVA_M2_38P4 0x01 + +/* CORE DPLL */ + +#define CORE_M_12 0xA6 +#define CORE_N_12 0x05 +#define CORE_FSEL_12 0x07 +#define CORE_M2_12 0x01 /* M3 of 2 */ + +#define CORE_M_12_ES1 0x19F +#define CORE_N_12_ES1 0x0E +#define CORE_FSL_12_ES1 0x03 +#define CORE_M2_12_ES1 0x1 /* M3 of 2 */ + +#define CORE_M_13 0x14C +#define CORE_N_13 0x0C +#define CORE_FSEL_13 0x03 +#define CORE_M2_13 0x01 /* M3 of 2 */ + +#define CORE_M_13_ES1 0x1B2 +#define CORE_N_13_ES1 0x10 +#define CORE_FSL_13_ES1 0x03 +#define CORE_M2_13_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_19P2 0x19F +#define CORE_N_19P2 0x17 +#define CORE_FSEL_19P2 0x03 +#define CORE_M2_19P2 0x01 /* M3 of 2 */ + +#define CORE_M_19P2_ES1 0x19F +#define CORE_N_19P2_ES1 0x17 +#define CORE_FSL_19P2_ES1 0x03 +#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_26 0xA6 +#define CORE_N_26 0x0C +#define CORE_FSEL_26 0x07 +#define CORE_M2_26 0x01 /* M3 of 2 */ + +#define CORE_M_26_ES1 0x1B2 +#define CORE_N_26_ES1 0x21 +#define CORE_FSL_26_ES1 0x03 +#define CORE_M2_26_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_38P4 0x19F +#define CORE_N_38P4 0x2F +#define CORE_FSEL_38P4 0x03 +#define CORE_M2_38P4 0x01 /* M3 of 2 */ + +#define CORE_M_38P4_ES1 0x19F +#define CORE_N_38P4_ES1 0x2F +#define CORE_FSL_38P4_ES1 0x03 +#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ + +/* PER DPLL */ + +#define PER_M_12 0xD8 +#define PER_N_12 0x05 +#define PER_FSEL_12 0x07 +#define PER_M2_12 0x09 + +#define PER_M_13 0x1B0 +#define PER_N_13 0x0C +#define PER_FSEL_13 0x03 +#define PER_M2_13 0x09 + +#define PER_M_19P2 0xE1 +#define PER_N_19P2 0x09 +#define PER_FSEL_19P2 0x07 +#define PER_M2_19P2 0x09 + +#define PER_M_26 0xD8 +#define PER_N_26 0x0C +#define PER_FSEL_26 0x07 +#define PER_M2_26 0x09 + +#define PER_M_38P4 0xE1 +#define PER_N_38P4 0x13 +#define PER_FSEL_38P4 0x07 +#define PER_M2_38P4 0x09 #endif /* endif _CLOCKS_OMAP3_H_ */

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Re: [U-Boot] [PATCH v3] mpc83xx: New board support SIMPC8313
by Ron Madrid 20 Nov '08

20 Nov '08

> Hi Ron, while this looks good, it doesn't build on my system: > > ...Small Page NAND...Configuring for SIMPC8313 board... > ld: NAND bootstrap too big > ld: NAND bootstrap too big > > and large page nand fails identically: > > ...Large Page NAND...Configuring for SIMPC8313 board... > ld: NAND bootstrap too big > ld: NAND bootstrap too big > make[1]: *** [/home/kim/git/u-boot/nand_spl/u-boot-spl] Error 1 > make: *** [nand_spl] Error 2 I did not see this when I built before submitting my patch. It seems to build fine using ELDK version 4.1. I just tried building with 4.2 and am seeing the errors that you described. For some reason, the 4.2 build has about 48 extra bytes to it, and is once again putting me over the 4K bootstrap limit. I'm going to look into getting the size down, but that's a decent number of bytes to try to optimize out. Ron

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