November 2008 - U-Boot

[U-Boot] [PATCH] sh: Changed value of CACHE_OC_NUM_ENTRIES and CACHE_OC_WAY_SHIFT
by Nobuhiro Iwamatsu 25 Nov '08

25 Nov '08

SH4 is different a value of CACHE_OC_NUM_ENTRIES and CACHE_OC_WAY_SHIFT every CPU. This patch corrects these values. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com> --- include/asm-sh/cpu_sh4.h | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h index b6cc6cf..d2dbfcd 100644 --- a/include/asm-sh/cpu_sh4.h +++ b/include/asm-sh/cpu_sh4.h @@ -26,8 +26,15 @@ #define CCR_CACHE_ICI 0x00000800 #define CACHE_OC_ADDRESS_ARRAY 0xf4000000 + +#if defined (CONFIG_CPU_SH7750) || \ + defined(CONFIG_CPU_SH7751) #define CACHE_OC_WAY_SHIFT 14 #define CACHE_OC_NUM_ENTRIES 512 +#else +#define CACHE_OC_WAY_SHIFT 13 +#define CACHE_OC_NUM_ENTRIES 256 +#endif #define CACHE_OC_ENTRY_SHIFT 5 #if defined (CONFIG_CPU_SH7750) || \ -- 1.5.6.5

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[U-Boot] [PATCH-OMAP3] OMAP3: Convert readl/writel and replace hardcoded values
by Dirk Behme 25 Nov '08

25 Nov '08

Convert readl/writel to base + offset style. Replace hardcoded values with macros. No functional change. Signed-off-by: Dirk Behme <dirk.behme(a)googlemail.com> --- cpu/arm_cortexa8/omap3/board.c | 56 ++++++++------- cpu/arm_cortexa8/omap3/clock.c | 47 ++++++++----- cpu/arm_cortexa8/omap3/interrupts.c | 14 +-- cpu/arm_cortexa8/omap3/mem.c | 53 ++++++++------ cpu/arm_cortexa8/omap3/sys_info.c | 14 ++- include/asm-arm/arch-omap3/cpu.h | 129 +++++++++++++++++++----------------- include/asm-arm/arch-omap3/mem.h | 8 +- include/asm-arm/arch-omap3/omap3.h | 2 8 files changed, 180 insertions(+), 143 deletions(-) Index: u-boot-arm/cpu/arm_cortexa8/omap3/mem.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/mem.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/mem.c @@ -106,6 +106,8 @@ u32 *onenand_cs_base; #endif +static u32 *sdrc_base = (u32 *)OMAP34XX_SDRC_BASE; + /************************************************************************** * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow * command line mem=xyz use all memory with out discontinuous support @@ -120,7 +122,7 @@ void make_cs1_contiguous(void) size /= SZ_32M; /* find size to offset CS1 */ a_add_high = (size & 3) << 8; /* set up low field */ a_add_low = (size & 0x3C) >> 2; /* set up high field */ - writel((a_add_high | a_add_low), SDRC_CS_CFG); + writel((a_add_high | a_add_low), sdrc_base + OFFS(SDRC_CS_CFG)); } @@ -175,36 +177,43 @@ void do_sdrc_init(u32 offset, u32 early) if (early) { /* reset sdrc controller */ - writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(RESETDONE, RESETDONE, SDRC_STATUS, 12000000); - writel(0, SDRC_SYSCONFIG); + writel(SOFTRESET, sdrc_base + OFFS(SDRC_SYSCONFIG)); + wait_on_value(RESETDONE, RESETDONE, SDRC_STATUS_REG, 12000000); + writel(0, sdrc_base + OFFS(SDRC_SYSCONFIG)); /* setup sdrc to ball mux */ - writel(SDP_SDRC_SHARING, SDRC_SHARING); + writel(SDP_SDRC_SHARING, sdrc_base + OFFS(SDRC_SHARING)); - /* Disble Power Down of CKE cuz of 1 CKE on combo part */ - writel(0x00000081, SDRC_POWER); + /* Disable Power Down of CKE cuz of 1 CKE on combo part */ + writel(SRFRONRESET | PAGEPOLICY_HIGH, + sdrc_base + OFFS(SDRC_POWER)); - writel(0x0000A, SDRC_DLLA_CTRL); + writel(ENADLL | DLLPHASE_90, sdrc_base + OFFS(SDRC_DLLA_CTRL)); sdelay(0x20000); } - writel(0x02584099, SDRC_MCFG_0 + offset); - writel(0x4e201, SDRC_RFR_CTRL + offset); - writel(0xaa9db4c6, SDRC_ACTIM_CTRLA_0 + actim_offs); - writel(0x11517, SDRC_ACTIM_CTRLB_0 + actim_offs); - - writel(CMD_NOP, SDRC_MANUAL_0 + offset); - writel(CMD_PRECHARGE, SDRC_MANUAL_0 + offset); - writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset); - writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset); - - /* CAS latency 3, Write Burst = Read Burst, Serial Mode, - Burst length = 4 */ - writel(0x00000032, SDRC_MR_0 + offset); + writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY | + RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 | + DEEPPD | DDR_SDRAM, sdrc_base + OFFS(SDRC_MCFG_0 + offset)); + writel(ARCV | ARE_ARCV_1, sdrc_base + OFFS(SDRC_RFR_CTRL + offset)); + writel(V_ACTIMA_165, sdrc_base + + OFFS(SDRC_ACTIM_CTRLA_0 + actim_offs)); + writel(V_ACTIMB_165, sdrc_base + + OFFS(SDRC_ACTIM_CTRLB_0 + actim_offs)); + + writel(CMD_NOP, sdrc_base + OFFS(SDRC_MANUAL_0 + offset)); + writel(CMD_PRECHARGE, sdrc_base + OFFS(SDRC_MANUAL_0 + offset)); + writel(CMD_AUTOREFRESH, sdrc_base + OFFS(SDRC_MANUAL_0 + offset)); + writel(CMD_AUTOREFRESH, sdrc_base + OFFS(SDRC_MANUAL_0 + offset)); + + /* + * CAS latency 3, Write Burst = Read Burst, Serial Mode, + * Burst length = 4 + */ + writel(CASL3 | BURSTLENGTH4, sdrc_base + OFFS(SDRC_MR_0 + offset)); if (!mem_ok(offset)) - writel(0, SDRC_MCFG_0 + offset); + writel(0, sdrc_base + OFFS(SDRC_MCFG_0 + offset)); } void enable_gpmc_config(u32 *gpmc_config, u32 *gpmc_cs_base, u32 base, Index: u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/sys_info.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c @@ -33,6 +33,8 @@ extern omap3_sysinfo sysinfo; static u32 *gpmc_base = (u32 *)GPMC_BASE; +static u32 *sdrc_base = (u32 *)OMAP34XX_SDRC_BASE; +static u32 *ctrl_base = (u32 *)OMAP34XX_CTRL_BASE; /****************************************** * get_cpu_rev(void) - extract version info @@ -59,7 +61,8 @@ u32 get_cpu_rev(void) ****************************************************/ u32 is_mem_sdr(void) { - if (readl(SDRC_MR_0 + SDRC_CS0_OSET) == SDP_SDRC_MR_0_SDR) + if (readl(sdrc_base + OFFS(SDRC_MR_0 + SDRC_CS0_OSET)) == + SDP_SDRC_MR_0_SDR) return 1; return 0; } @@ -72,7 +75,7 @@ u32 get_sdr_cs_size(u32 offset) u32 size; /* get ram size field */ - size = readl(SDRC_MCFG_0 + offset) >> 8; + size = readl(sdrc_base + OFFS(SDRC_MCFG_0 + offset)) >> 8; size &= 0x3FF; /* remove unwanted bits */ size *= SZ_2M; /* find size in MB */ return size; @@ -88,7 +91,7 @@ u32 get_sdr_cs_offset(u32 cs) if (!cs) return 0; - offset = readl(SDRC_CS_CFG); + offset = readl(sdrc_base + OFFS(SDRC_CS_CFG)); offset = (offset & 15) << 27 | (offset & 0x30) >> 17; return offset; @@ -240,7 +243,7 @@ u32 is_running_in_sdram(void) ***************************************************************/ u32 get_boot_type(void) { - return (readl(CONTROL_STATUS) & SYSBOOT_MASK); + return (readl(ctrl_base + OFFS(CONTROL_STATUS)) & SYSBOOT_MASK); } /************************************************************* @@ -248,5 +251,6 @@ u32 get_boot_type(void) *************************************************************/ u32 get_device_type(void) { - return ((readl(CONTROL_STATUS) & (DEVICE_MASK)) >> 8); + return ((readl(ctrl_base + OFFS(CONTROL_STATUS)) & + (DEVICE_MASK)) >> 8); } Index: u-boot-arm/include/asm-arm/arch-omap3/cpu.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/cpu.h +++ u-boot-arm/include/asm-arm/arch-omap3/cpu.h @@ -29,14 +29,7 @@ /* Register offsets of common modules */ /* Control */ -#define CONTROL_STATUS (OMAP34XX_CTRL_BASE + 0x2F0) -#define OMAP34XX_MCR (OMAP34XX_CTRL_BASE + 0x8C) -#define CONTROL_SCALABLE_OMAP_STATUS (OMAP34XX_CTRL_BASE + 0x44C) -#define CONTROL_SCALABLE_OMAP_OCP (OMAP34XX_CTRL_BASE + 0x534) - -/* Tap Information */ -#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE + 0x204) -#define PRODUCTION_ID (OMAP34XX_TAP_BASE + 0x208) +#define CONTROL_STATUS 0x2F0 /* device type */ #define DEVICE_MASK (0x7 << 8) @@ -104,36 +97,52 @@ /* (actual size small port) */ /* SMS */ -#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE + 0x10) -#define SMS_RG_ATT0 (OMAP34XX_SMS_BASE + 0x48) -#define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE + 0xD0) +#define SMS_SYSCONFIG 0x10 +#define SMS_RG_ATT0 0x48 +#define SMS_CLASS_ARB0 0xD0 #define BURSTCOMPLETE_GROUP7 (0x1 << 31) /* SDRC */ -#define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE + 0x10) -#define SDRC_STATUS (OMAP34XX_SDRC_BASE + 0x14) -#define SDRC_CS_CFG (OMAP34XX_SDRC_BASE + 0x40) -#define SDRC_SHARING (OMAP34XX_SDRC_BASE + 0x44) -#define SDRC_DLLA_CTRL (OMAP34XX_SDRC_BASE + 0x60) -#define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE + 0x64) -#define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE + 0x68) -#define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE + 0x6C) -#define DLLPHASE (0x1 << 1) +#define SDRC_SYSCONFIG 0x10 +#define SDRC_STATUS 0x14 +#define SDRC_STATUS_REG (OMAP34XX_SDRC_BASE + SDRC_STATUS) +#define SDRC_CS_CFG 0x40 +#define SDRC_SHARING 0x44 +#define SDRC_DLLA_CTRL 0x60 +#define SDRC_DLLA_STATUS 0x64 +#define SDRC_DLLB_CTRL 0x68 +#define SDRC_DLLB_STATUS 0x6C +#define DLLPHASE_90 (0x1 << 1) #define LOADDLL (0x1 << 2) +#define ENADLL (0x1 << 3) #define DLL_DELAY_MASK 0xFF00 #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) -#define SDRC_POWER (OMAP34XX_SDRC_BASE + 0x70) +#define SDRC_POWER 0x70 +#define PAGEPOLICY_HIGH (0x1 << 0) +#define SRFRONRESET (0x1 << 7) #define WAKEUPPROC (0x1 << 26) -#define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE + 0x80) -#define SDRC_MR_0 (OMAP34XX_SDRC_BASE + 0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP34XX_SDRC_BASE + 0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP34XX_SDRC_BASE + 0xA0) -#define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE + 0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE + 0xC8) -#define SDRC_RFR_CTRL (OMAP34XX_SDRC_BASE + 0xA4) -#define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE + 0xA8) +#define SDRC_MCFG_0 0x80 +#define DDR_SDRAM (0x1 << 0) +#define DEEPPD (0x1 << 3) +#define B32NOT16 (0x1 << 4) +#define BANKALLOCATION (0x2 << 6) +#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ +#define ADDRMUXLEGACY (0x1 << 19) +#define CASWIDTH_10BITS (0x5 << 20) +#define RASWIDTH_13BITS (0x2 << 24) +#define SDRC_MR_0 0x84 +#define BURSTLENGTH4 (0x2 << 0) +#define CASL3 (0x3 << 4) +#define SDRC_ACTIM_CTRLA_0 0x9C +#define SDRC_ACTIM_CTRLB_0 0xA0 +#define SDRC_ACTIM_CTRLA_1 0xC4 +#define SDRC_ACTIM_CTRLB_1 0xC8 +#define SDRC_RFR_CTRL 0xA4 +#define ARE_ARCV_1 (0x1 << 0) +#define ARCV (0x4e2 << 8) /* Autorefresh count */ +#define SDRC_MANUAL_0 0xA8 #define OMAP34XX_SDRC_CS0 0x80000000 #define OMAP34XX_SDRC_CS1 0xA0000000 #define CMD_NOP 0x0 @@ -174,6 +183,7 @@ #define WD_UNLOCK2 0x5555 /* PRCM */ +#define PRCM_BASE 0x48004000 #define CM_FCLKEN_IVA2 0x48004000 #define CM_CLKEN_PLL_IVA2 0x48004004 #define CM_IDLEST_PLL_IVA2 0x48004024 @@ -187,16 +197,22 @@ #define CM_ICLKEN1_CORE 0x48004a10 #define CM_ICLKEN2_CORE 0x48004a14 #define CM_CLKSEL_CORE 0x48004a40 +#define CLKSEL_CORE 0xa40 #define CM_FCLKEN_GFX 0x48004b00 #define CM_ICLKEN_GFX 0x48004b10 #define CM_CLKSEL_GFX 0x48004b40 #define CM_FCLKEN_WKUP 0x48004c00 +#define FCLKEN_WKUP 0xc00 #define CM_ICLKEN_WKUP 0x48004c10 +#define ICLKEN_WKUP 0xc10 #define CM_CLKSEL_WKUP 0x48004c40 +#define CLKSEL_WKUP 0xc40 #define CM_IDLEST_WKUP 0x48004c20 #define CM_CLKEN_PLL 0x48004d00 +#define CLKEN_PLL 0xd00 #define CM_IDLEST_CKGEN 0x48004d20 #define CM_CLKSEL1_PLL 0x48004d40 +#define CLKSEL1_PLL 0xd40 #define CM_CLKSEL2_PLL 0x48004d44 #define CM_CLKSEL3_PLL 0x48004d48 #define CM_FCLKEN_DSS 0x48004e00 @@ -210,9 +226,11 @@ #define CM_CLKSEL_PER 0x48005040 #define CM_CLKSEL1_EMU 0x48005140 +#define PRM_BASE 0x48306000 #define PRM_CLKSEL 0x48306d40 #define PRM_RSTCTRL 0x48307250 #define PRM_CLKSRC_CTRL 0x48307270 +#define CLKSRC_CTRL 0x1270 #define SYSCLKDIV_1 (0x1 << 6) #define SYSCLKDIV_2 (0x1 << 7) @@ -244,35 +262,30 @@ #define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) -#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) -#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) -#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) -#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) - -#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) -#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) -#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) - -#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) -#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) -#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) -#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) - -#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) -#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) -#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) - -#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) -#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) -#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) - -#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) -#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) -#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) - -#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) -#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) -#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) +#define RT_REQ_INFO_PERMISSION_1 0x68 +#define RT_READ_PERMISSION_0 0x50 +#define RT_WRITE_PERMISSION_0 0x58 +#define RT_ADDR_MATCH_1 0x60 + +#define GPMC_REQ_INFO_PERMISSION_0 0x48 +#define GPMC_READ_PERMISSION_0 0x50 +#define GPMC_WRITE_PERMISSION_0 0x58 + +#define OCM_REQ_INFO_PERMISSION_0 0x48 +#define OCM_READ_PERMISSION_0 0x50 +#define OCM_WRITE_PERMISSION_0 0x58 +#define OCM_ADDR_MATCH_2 0x80 + +#define IVA2_REQ_INFO_PERMISSION_0 0x48 +#define IVA2_READ_PERMISSION_0 0x50 +#define IVA2_WRITE_PERMISSION_0 0x58 + +/* Permission values for registers -Full fledged permissions to all */ +#define UNLOCK_1 0xFFFFFFFF +#define UNLOCK_2 0x00000000 +#define UNLOCK_3 0x0000FFFF + +#define NOT_EARLY 0 /* I2C base */ #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) Index: u-boot-arm/include/asm-arm/arch-omap3/mem.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/mem.h +++ u-boot-arm/include/asm-arm/arch-omap3/mem.h @@ -80,16 +80,16 @@ typedef enum { #define TRP_165 3 #define TRAS_165 7 #define TRC_165 10 -#define TRFC_165 12 +#define TRFC_165 21 #define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \ (TRAS_165 << 18) | (TRP_165 << 15) | \ (TRCD_165 << 12) | (TRRD_165 << 9) | \ (TDPL_165 << 6) | (TDAL_165)) #define TWTR_165 1 -#define TCKE_165 2 -#define TXP_165 2 -#define XSR_165 20 +#define TCKE_165 1 +#define TXP_165 5 +#define XSR_165 23 #define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \ (TXP_165 << 8) | (TWTR_165 << 16)) Index: u-boot-arm/cpu/arm_cortexa8/omap3/board.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/board.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/board.c @@ -37,13 +37,6 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> -#define NOT_EARLY 0 - -/* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - extern omap3_sysinfo sysinfo; /****************************************************************************** @@ -63,27 +56,34 @@ static inline void delay(unsigned long l *****************************************************************************/ void secure_unlock_mem(void) { + u32 *pm_rt_ape_base = (u32 *)PM_RT_APE_BASE_ADDR_ARM; + u32 *pm_gpmc_base = (u32 *)PM_GPMC_BASE_ADDR_ARM; + u32 *pm_ocm_ram_base = (u32 *)PM_OCM_RAM_BASE_ADDR_ARM; + u32 *pm_iva2_base = (u32 *)PM_IVA2_BASE_ADDR_ARM; + u32 *sms_base = (u32 *)OMAP34XX_SMS_BASE; + /* Protection Module Register Target APE (PM_RT) */ - writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - writel(UNLOCK_1, RT_READ_PERMISSION_0); - writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - writel(UNLOCK_2, RT_ADDR_MATCH_1); - - writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - writel(UNLOCK_3, OCM_READ_PERMISSION_0); - writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - writel(UNLOCK_2, OCM_ADDR_MATCH_2); + writel(UNLOCK_1, pm_rt_ape_base + OFFS(RT_REQ_INFO_PERMISSION_1)); + writel(UNLOCK_1, pm_rt_ape_base + OFFS(RT_READ_PERMISSION_0)); + writel(UNLOCK_1, pm_rt_ape_base + OFFS(RT_WRITE_PERMISSION_0)); + writel(UNLOCK_2, pm_rt_ape_base + OFFS(RT_ADDR_MATCH_1)); + + writel(UNLOCK_3, pm_gpmc_base + OFFS(GPMC_REQ_INFO_PERMISSION_0)); + writel(UNLOCK_3, pm_gpmc_base + OFFS(GPMC_READ_PERMISSION_0)); + writel(UNLOCK_3, pm_gpmc_base + OFFS(GPMC_WRITE_PERMISSION_0)); + + writel(UNLOCK_3, pm_ocm_ram_base + OFFS(OCM_REQ_INFO_PERMISSION_0)); + writel(UNLOCK_3, pm_ocm_ram_base + OFFS(OCM_READ_PERMISSION_0)); + writel(UNLOCK_3, pm_ocm_ram_base + OFFS(OCM_WRITE_PERMISSION_0)); + writel(UNLOCK_2, pm_ocm_ram_base + OFFS(OCM_ADDR_MATCH_2)); /* IVA Changes */ - writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + writel(UNLOCK_3, pm_iva2_base + OFFS(IVA2_REQ_INFO_PERMISSION_0)); + writel(UNLOCK_3, pm_iva2_base + OFFS(IVA2_READ_PERMISSION_0)); + writel(UNLOCK_3, pm_iva2_base + OFFS(IVA2_WRITE_PERMISSION_0)); - writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ + /* SDRC region 0 public */ + writel(UNLOCK_1, sms_base + OFFS(SMS_RG_ATT0)); } /****************************************************************************** @@ -210,7 +210,7 @@ void s_init(void) #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV - * Currently SMI in Kernel on ES2 devices seems to have an isse + * Currently SMI in Kernel on ES2 devices seems to have an issue * Once that is resolved, we can postpone this config to kernel */ if (get_device_type() == GP_DEVICE) @@ -245,6 +245,8 @@ void wait_for_command_complete(unsigned *****************************************************************************/ void watchdog_init(void) { + u32 *wd2_base = (u32 *)WD2_BASE; + /* * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is * either taken care of by ROM (HS/EMU) or not accessible (GP). @@ -256,9 +258,9 @@ void watchdog_init(void) sr32(CM_ICLKEN_WKUP, 5, 1, 1); wait_on_value(ST_WDT2, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - writel(WD_UNLOCK1, WD2_BASE + WSPR); + writel(WD_UNLOCK1, wd2_base + OFFS(WSPR)); wait_for_command_complete(WD2_BASE); - writel(WD_UNLOCK2, WD2_BASE + WSPR); + writel(WD_UNLOCK2, wd2_base + OFFS(WSPR)); } /****************************************************************************** Index: u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/interrupts.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c @@ -38,9 +38,6 @@ #define TIMER_LOAD_VAL 0 -/* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)) - #ifdef CONFIG_USE_IRQ /* enable IRQ interrupts */ void enable_interrupts(void) @@ -170,15 +167,16 @@ void do_irq(struct pt_regs *pt_regs) static ulong timestamp; static ulong lastinc; +static u32 *timer_base = (u32 *)CONFIG_SYS_TIMERBASE; /* nothing really to do with interrupts, just starts up a counter. */ int interrupt_init(void) { /* start the counter ticking up, reload value on overflow */ - writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TLDR); + writel(TIMER_LOAD_VAL, timer_base + OFFS(TLDR)); /* enable timer */ writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, - CONFIG_SYS_TIMERBASE + TCLR); + timer_base + OFFS(TCLR)); reset_timer_masked(); /* init the timestamp and lastinc value */ @@ -233,14 +231,14 @@ void udelay(unsigned long usec) void reset_timer_masked(void) { - /* reset time */ - lastinc = READ_TIMER; /* capture current incrementer value time */ + /* reset time, capture current incrementer value time */ + lastinc = readl(timer_base + OFFS(TCRR)); timestamp = 0; /* start "advancing" time stamp from 0 */ } ulong get_timer_masked(void) { - ulong now = READ_TIMER; /* current tick value */ + ulong now = readl(timer_base + OFFS(TCRR)); /* current tick value */ if (now >= lastinc) /* normal mode (non roll) */ /* move stamp fordward with absoulte diff ticks */ Index: u-boot-arm/cpu/arm_cortexa8/omap3/clock.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/clock.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/clock.c @@ -41,36 +41,46 @@ u32 get_osc_clk_speed(void) { u32 start, cstart, cend, cdiff, val; + u32 *prcm_base = (u32 *)PRCM_BASE; + u32 *prm_base = (u32 *)PRM_BASE; + u32 *gpt1_base = (u32 *)OMAP34XX_GPT1; + u32 *s32k_base = (u32 *)SYNC_32KTIMER_BASE; - val = readl(PRM_CLKSRC_CTRL); + val = readl(prm_base + OFFS(CLKSRC_CTRL)); /* If SYS_CLK is being divided by 2, remove for now */ val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1; - writel(val, PRM_CLKSRC_CTRL); + writel(val, prm_base + OFFS(CLKSRC_CTRL)); /* enable timer2 */ - val = readl(CM_CLKSEL_WKUP) | CLKSEL_GPT1; - writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ + val = readl(prcm_base + OFFS(CLKSEL_WKUP)) | CLKSEL_GPT1; + + /* select sys_clk for GPT1 */ + writel(val, prcm_base + OFFS(CLKSEL_WKUP)); /* Enable I and F Clocks for GPT1 */ - val = readl(CM_ICLKEN_WKUP) | EN_GPT1 | EN_32KSYNC; - writel(val, CM_ICLKEN_WKUP); - val = readl(CM_FCLKEN_WKUP) | EN_GPT1; - writel(val, CM_FCLKEN_WKUP); + val = readl(prcm_base + OFFS(ICLKEN_WKUP)) | EN_GPT1 | EN_32KSYNC; + writel(val, prcm_base + OFFS(ICLKEN_WKUP)); + val = readl(prcm_base + OFFS(FCLKEN_WKUP)) | EN_GPT1; + writel(val, prcm_base + OFFS(FCLKEN_WKUP)); - writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ + writel(0, gpt1_base + OFFS(TLDR)); /* start counting at 0 */ + writel(GPT_EN, gpt1_base + OFFS(TCLR)); /* enable clock */ /* enable 32kHz source, determine sys_clk via gauging */ - start = 20 + readl(S32K_CR); /* start time in 20 cycles */ - while (readl(S32K_CR) < start) ; /* dead loop till start time */ + + /* start time in 20 cycles */ + start = 20 + readl(s32k_base + OFFS(S32K_CR)); + + /* dead loop till start time */ + while (readl(s32k_base + OFFS(S32K_CR)) < start); /* get start sys_clk count */ - cstart = readl(OMAP34XX_GPT1 + TCRR); + cstart = readl(gpt1_base + OFFS(TCRR)); /* wait for 40 cycles */ - while (readl(S32K_CR) < (start + 20)) ; - cend = readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + while (readl(s32k_base + OFFS(S32K_CR)) < (start + 20)) ; + cend = readl(gpt1_base + OFFS(TCRR)); /* get end sys_clk count */ cdiff = cend - cstart; /* get elapsed ticks */ /* based on number of ticks assign speed */ @@ -123,6 +133,7 @@ void prcm_init(void) int xip_safe, p0, p1, p2, p3; u32 osc_clk = 0, sys_clkin_sel; u32 clk_index, sil_index; + u32 *prcm_base = (u32 *)PRCM_BASE; dpll_param *dpll_param_p; f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + @@ -199,17 +210,17 @@ void prcm_init(void) * if running from flash, jump to small relocated code * area in SRAM. */ - p0 = readl(CM_CLKEN_PLL); + p0 = readl(prcm_base + OFFS(CLKEN_PLL)); sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS); sr32((u32) &p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - p1 = readl(CM_CLKSEL1_PLL); + p1 = readl(prcm_base + OFFS(CLKSEL1_PLL)); sr32((u32) &p1, 27, 2, dpll_param_p->m2); /* Set M2 */ sr32((u32) &p1, 16, 11, dpll_param_p->m); /* Set M */ sr32((u32) &p1, 8, 7, dpll_param_p->n); /* Set N */ sr32((u32) &p1, 6, 1, 0); /* set source for 96M */ - p2 = readl(CM_CLKSEL_CORE); + p2 = readl(prcm_base + OFFS(CLKSEL_CORE)); sr32((u32) &p2, 8, 4, CORE_SSI_DIV); /* ssi */ sr32((u32) &p2, 4, 2, CORE_FUSB_DIV); /* fsusb */ sr32((u32) &p2, 2, 2, CORE_L4_DIV); /* l4 */ Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/omap3.h +++ u-boot-arm/include/asm-arm/arch-omap3/omap3.h @@ -75,7 +75,7 @@ /* 32KTIMER */ #define SYNC_32KTIMER_BASE 0x48320000 -#define S32K_CR (SYNC_32KTIMER_BASE + 0x10) +#define S32K_CR 0x10 /* OMAP3 GPIO registers */ #define OMAP34XX_GPIO1_BASE 0x48310000

4 10

[U-Boot] [PATCH 0/4 v3] powerpc: 83xx: add support for the 8360 based kmeter1 board.
by Heiko Schocher 25 Nov '08

25 Nov '08

This patch series adds support for the keymile board kmeter1 based on a MPC8360 CPU from freescale. The patches 1/4 - 2/4 are adding the basic support for this board. The patches 3/4 and 4/4 do some cleanups for the keymile boards. changes since v2: - [PATCH 1/4 v3] powerpc: net: support for the SMSC LAN8700 PHY added comments from Kim Philips - [PATCH 2/5 v2] powerpc: 83xx: add missing TIMING_CFG1_CASLAT_* defines aplied to "u-boot-mpc83xx master" -> no longer in this patch series - [PATCH 2/4 v3] powerpc: 83xx: add support for the kmeter1 board added comments from Kim Philips added doc/README.kmeter1 - [PATCH 3/4 v3] powerpc: keymile: Add a check for the PIGGY debug board added comments from Ben Warren - [PATCH 4/4 v3] powerpc, keymile boards: extract identical config options just rebased bye Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

2 1

[U-Boot] [PATCH] at91rm9200: fix broken boot from nor flash
by Jens Scharsig 25 Nov '08

25 Nov '08

This patch fix the broken boot from NOR Flash on AT91RM9200 boards, if CONFIG_AT91RM9200 is defined and nor preloader is used. Please see <http://lists.denx.de/pipermail/u-boot/2008-November/043078.html> <http://lists.denx.de/pipermail/u-boot/2008-November/043093.html> for reason Signed-off-by: Jens Scharsig <esw(a)bus-elektronik.de> --- diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 17977c2..52aff13 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -24,7 +24,6 @@ * MA 02111-1307 USA */ - #include <config.h> #include <version.h> #include <status_led.h> @@ -178,8 +177,6 @@ copyex: bl cpu_init_crit #endif -#ifndef CONFIG_AT91RM9200 - #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ @@ -198,7 +195,7 @@ copy_loop: cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ -#endif + /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 633a053..5c239d7 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -72,6 +72,8 @@ #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#else +#define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ /* * Size of malloc() pool diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index 527921e..cdd308d 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -71,6 +71,8 @@ #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#else +#define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ /* diff --git a/include/configs/csb637.h b/include/configs/csb637.h index 38fd25c..682db44 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -72,6 +72,8 @@ #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#else +#define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ /* * Size of malloc() pool diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 55cda32..1ce8c69 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -51,6 +51,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT /* undef this for direct boot from */ + /* NOR flash without preloader */ #define CONFIG_SYS_LONGHELP diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 2ffeae6..cbbdb0c 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -76,6 +76,8 @@ #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#else +#define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ /*

4 6

[U-Boot] [PATCH] AT91RM9200DK: fix broken boot from NOR flash
by Wolfgang Denk 24 Nov '08

24 Nov '08

From: Wolfgang Denk <wd(a)xpert.denx.de> Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- cpu/arm920t/start.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index f99d129..5143cfc 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -258,7 +258,7 @@ cpu_init_crit: * find a lowlevel_init.S in your board directory. */ mov ip, lr -#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) +#if defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) #else bl lowlevel_init -- 1.5.4.rc1.23.g3a969

2 1

[U-Boot] [PATCH v2 1/3] Introduce addr_map library
by Kumar Gala 24 Nov '08

24 Nov '08

Add a library that helps in translating between virtual and physical addresses. This library can be useful as a simple means to implement map_physmem() and virt_to_phys() for platforms that need functionality beyond the simple 1:1 mapping. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- * Use unsigned long * changed virt_to_phys to take void * * changed comparision include/addr_map.h | 29 +++++++++++++++++ lib_generic/Makefile | 1 + lib_generic/addr_map.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+), 0 deletions(-) create mode 100644 include/addr_map.h create mode 100644 lib_generic/addr_map.c diff --git a/include/addr_map.h b/include/addr_map.h new file mode 100644 index 0000000..234487a --- /dev/null +++ b/include/addr_map.h @@ -0,0 +1,29 @@ +#ifndef __ADDR_MAP_H +#define __ADDR_MAP_H + +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/types.h> + +extern phys_addr_t addrmap_virt_to_phys(void *vaddr); +extern unsigned long addrmap_phys_to_virt(phys_addr_t paddr); +extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr, + unsigned long size, int idx); + +#endif diff --git a/lib_generic/Makefile b/lib_generic/Makefile index d62c39b..3f04022 100644 --- a/lib_generic/Makefile +++ b/lib_generic/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libgeneric.a +COBJS-$(CONFIG_ADDR_MAP) += addr_map.o COBJS-y += bzlib.o COBJS-y += bzlib_crctable.o COBJS-y += bzlib_decompress.o diff --git a/lib_generic/addr_map.c b/lib_generic/addr_map.c new file mode 100644 index 0000000..18c0c5a --- /dev/null +++ b/lib_generic/addr_map.c @@ -0,0 +1,81 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <addr_map.h> + +static struct { + phys_addr_t paddr; + unsigned long vaddr; + unsigned long size; +} address_map[CONFIG_SYS_NUM_ADDR_MAP]; + +phys_addr_t addrmap_virt_to_phys(void * vaddr) +{ + int i; + + for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++) { + u64 base, upper, addr; + + if (address_map[i].size == 0) + continue; + + addr = (u64)vaddr; + base = (u64)(address_map[i].vaddr); + upper = (u64)(address_map[i].size) + base - 1; + + if (addr >= base && addr <= upper) { + return addr - address_map[i].vaddr + address_map[i].paddr; + } + } + + return (phys_addr_t)(~0); +} + +unsigned long addrmap_phys_to_virt(phys_addr_t paddr) +{ + int i; + + for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++) { + u64 base, upper, addr; + + if (address_map[i].size == 0) + continue; + + addr = (u64)paddr; + base = (u64)(address_map[i].paddr); + upper = (u64)(address_map[i].size) + base - 1; + + if (addr >= base && addr <= upper) { + return paddr - address_map[i].paddr + address_map[i].paddr; + } + } + + return (unsigned long)(~0); +} + +void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr, + unsigned long size, int idx) +{ + if (idx > CONFIG_SYS_NUM_ADDR_MAP) + return; + + address_map[idx].vaddr = vaddr; + address_map[idx].paddr = paddr; + address_map[idx].size = size; +} -- 1.5.6.5

1 2

[U-Boot] [PATCH 1/3] Introduce addr_map library
by Kumar Gala 24 Nov '08

24 Nov '08

Add a library that helps in translating between virtual and physical addresses. This library can be useful as a simple means to implement map_physmem() and virt_to_phys() for platforms that need functionality beyond the simple 1:1 mapping. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/addr_map.h | 29 +++++++++++++++++ lib_generic/Makefile | 1 + lib_generic/addr_map.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+), 0 deletions(-) create mode 100644 include/addr_map.h create mode 100644 lib_generic/addr_map.c diff --git a/include/addr_map.h b/include/addr_map.h new file mode 100644 index 0000000..c87c3a8 --- /dev/null +++ b/include/addr_map.h @@ -0,0 +1,29 @@ +#ifndef __ADDR_MAP_H +#define __ADDR_MAP_H + +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/types.h> + +extern phys_addr_t addrmap_virt_to_phys(unsigned int vaddr); +extern unsigned int addrmap_phys_to_virt(phys_addr_t paddr); +extern void addrmap_set_entry(unsigned int vaddr, phys_addr_t paddr, + unsigned int size, int idx); + +#endif diff --git a/lib_generic/Makefile b/lib_generic/Makefile index d62c39b..3f04022 100644 --- a/lib_generic/Makefile +++ b/lib_generic/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libgeneric.a +COBJS-$(CONFIG_ADDR_MAP) += addr_map.o COBJS-y += bzlib.o COBJS-y += bzlib_crctable.o COBJS-y += bzlib_decompress.o diff --git a/lib_generic/addr_map.c b/lib_generic/addr_map.c new file mode 100644 index 0000000..9f6596a --- /dev/null +++ b/lib_generic/addr_map.c @@ -0,0 +1,81 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <addr_map.h> + +static struct { + phys_addr_t paddr; + unsigned int vaddr; + unsigned int size; +} address_map[CONFIG_SYS_NUM_ADDR_MAP]; + +phys_addr_t addrmap_virt_to_phys(unsigned int vaddr) +{ + int i; + + for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++) { + u64 base, upper, addr; + + if (address_map[i].size == 0) + continue; + + addr = (u64)vaddr; + base = (u64)(address_map[i].vaddr); + upper = (u64)(address_map[i].size) + base; + + if (addr >= base && addr < upper) { + return vaddr - address_map[i].vaddr + address_map[i].paddr; + } + } + + return (phys_addr_t)(~0); +} + +unsigned int addrmap_phys_to_virt(phys_addr_t paddr) +{ + int i; + + for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++) { + u64 base, upper, addr; + + if (address_map[i].size == 0) + continue; + + addr = (u64)paddr; + base = (u64)(address_map[i].paddr); + upper = (u64)(address_map[i].size) + base; + + if (addr >= base && addr < upper) { + return paddr - address_map[i].paddr + address_map[i].paddr; + } + } + + return (unsigned int)(~0); +} + +void addrmap_set_entry(unsigned int vaddr, phys_addr_t paddr, + unsigned int size, int idx) +{ + if (idx > CONFIG_SYS_NUM_ADDR_MAP) + return ; + + address_map[idx].vaddr = vaddr; + address_map[idx].paddr = paddr; + address_map[idx].size = size; +} -- 1.5.6.5

2 4

[U-Boot] [PATCH 3/3] NAND FSL elbc: Use virt_to_phys to determine which bank is in use
by Kumar Gala 24 Nov '08

24 Nov '08

The current code that determines which bank/chipselect is used for a given NAND instance only worked for 32-bit addresses and assumed a 1:1 mapping. This breaks in 36-bit physical configs. The proper way to handle this is to use the virt_to_phys() and BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address with the the virtual address the NAND code uses. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- drivers/mtd/nand/fsl_elbc_nand.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) This patch puts the plumbing in place to work properly for 36-bit phys support in the future. This requires a proper version of virt_to_phys(). - k diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 367c7d7..3f318e0 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -718,7 +718,7 @@ static void fsl_elbc_ctrl_init(void) int board_nand_init(struct nand_chip *nand) { struct fsl_elbc_mtd *priv; - uint32_t br, or; + uint32_t br = 0, or = 0; if (!elbc_ctrl) { fsl_elbc_ctrl_init(); @@ -737,11 +737,13 @@ int board_nand_init(struct nand_chip *nand) * if we could pass more than one datum to the NAND driver... */ for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { + phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R); + br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br); or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or); if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM && - (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R) + (br & or & BR_BA) == BR_PHYS_ADDR(base_addr)) break; } -- 1.5.6.5

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[U-Boot] [PATCH 1/2] 85xx: Fix relocation of CCSRBAR
by Kumar Gala 24 Nov '08

24 Nov '08

If the virtual address for CCSRBAR is the same after relocation but the physical address is changing we'd end up having two TLB entries with the same VA. Instead we new us the new CCSRBAR virt address + 4k as a temp virt address to access the old CCSRBAR to relocate it. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/cpu_init.c | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 3a8aef2..1cb9ed9 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -140,14 +140,15 @@ void cpu_init_early_f(void) #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) { u32 temp; + volatile u32 *ccsr_virt = + (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - set_tlb(0, CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_DEFAULT, + set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 1, BOOKE_PAGESZ_4K, 0); - temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT); - out_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_PHYS >> 12); - + temp = in_be32(ccsr_virt); + out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); } #endif -- 1.5.6.5

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[U-Boot] [PATCH 2/3] FSL: Moved BR_PHYS_ADDR for localbus to common header
by Kumar Gala 24 Nov '08

24 Nov '08

The BR_PHYS_ADDR macro is useful on all machines that have local bus which is pretty much all 83xx/85xx/86xx chips. Additionally most 85xx & 86xx will need it if they want to support 36-bit physical addresses. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/asm-ppc/fsl_lbc.h | 8 ++++++++ include/configs/MPC8641HPCN.h | 9 --------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index cac7bf6..51fc5c1 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -69,6 +69,14 @@ #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) #endif +/* Convert an address into the right format for the BR registers */ +#ifdef CONFIG_PHYS_64BIT +#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ + ((x & 0x300000000ULL) >> 19))) +#else +#define BR_PHYS_ADDR(x) (x & 0xffff8000) +#endif + /* OR - Option Registers */ #define OR0 0x5004 /* Register offset to immr */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 69b4c44..08a88b0 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -186,17 +186,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ | CONFIG_SYS_PHYS_ADDR_HIGH) - #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -/* Convert an address into the right format for the BR registers */ -#ifdef CONFIG_PHYS_64BIT -#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ - ((x & 0x300000000ULL) >> 19))) -#else -#define BR_PHYS_ADDR(x) (x & 0xffff8000) -#endif - #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | 0x00001001) /* port size 16bit */ #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ -- 1.5.6.5

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