December 2007 - U-Boot

[U-Boot-Users] [PATCH] MMC for PXA 27X (resubmit)
by stefano babic 03 Feb '08

03 Feb '08

MMC support for X_Scale PXA is broken and does not work. Mainly, the mmc_init() function cannot recognize current SD/MMC cards. There were already some patches around the world but none of them was merged into the official u-boot tree. This patch makes order fixing this issue. Resubmit after code cleanup. Applied and tested on PXA 270 (TrizepsIV module). Signed-off-by: Stefano Babic <sbabic(a)denx.de> -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de ===================================================================== >From 27dda61b05047de31b836a51cb4049d740a5351c Mon Sep 17 00:00:00 2001 From: Stefano Babic <sbabic(a)denx.de> Date: Tue, 20 Nov 2007 10:23:52 +0100 Subject: [PATCH] MMC support for X_Scale PXA is broken and does not work. Mainly, the mmc_init() function cannot recognize current SD/MMC cards. There were already some patches around the world but none of them was merged into the official u-boot tree. This patch makes order fixing this issue. Applied and tested on PXA 270 (TrizepsIV module). --- cpu/pxa/mmc.c | 499 +++++++++++++++++++++++++++------------- fs/fat/fat.c | 2 +- include/asm-arm/arch-pxa/mmc.h | 79 ++++--- include/part.h | 1 + 4 files changed, 381 insertions(+), 200 deletions(-) diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c index d76e0cd..c0cfe65 100644 --- a/cpu/pxa/mmc.c +++ b/cpu/pxa/mmc.c @@ -30,14 +30,13 @@ #ifdef CONFIG_MMC -extern int -fat_register_device(block_dev_desc_t *dev_desc, int part_no); +extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no); static block_dev_desc_t mmc_dev; -block_dev_desc_t * mmc_get_dev(int dev) +block_dev_desc_t *mmc_get_dev(int dev) { - return (dev == 0) ? &mmc_dev : NULL; + return ((block_dev_desc_t *) & mmc_dev); } /* @@ -45,72 +44,59 @@ block_dev_desc_t * mmc_get_dev(int dev) * and other parameters */ static uchar mmc_buf[MMC_BLOCK_SIZE]; -static mmc_csd_t mmc_csd; +static uchar spec_ver; static int mmc_ready = 0; +static int wide = 0; - -static uchar * +static uint32_t * /****************************************************/ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat) /****************************************************/ { - static uchar resp[20]; + static uint32_t resp[4], a, b, c; ulong status; - int words, i; + int i; - debug("mmc_cmd %x %x %x %x\n", cmd, argh, argl, cmdat); + debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl, + cmdat | wide); MMC_STRPCL = MMC_STRPCL_STOP_CLK; MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; - while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)); - MMC_CMD = cmd; - MMC_ARGH = argh; - MMC_ARGL = argl; - MMC_CMDAT = cmdat; + while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)) ; + MMC_CMD = cmd; + MMC_ARGH = argh; + MMC_ARGL = argl; + MMC_CMDAT = cmdat | wide; MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES; MMC_STRPCL = MMC_STRPCL_START_CLK; - while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)); + while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)) ; status = MMC_STAT; - debug("MMC status %x\n", status); + debug("MMC status 0x%08x\n", status); if (status & MMC_STAT_TIME_OUT_RESPONSE) { return 0; } - switch (cmdat & 0x3) { - case MMC_CMDAT_R1: - case MMC_CMDAT_R3: - words = 3; - break; - - case MMC_CMDAT_R2: - words = 8; - break; - - default: - return 0; + /* Linux says: + * Did I mention this is Sick. We always need to + * discard the upper 8 bits of the first 16-bit word. + */ + a = (MMC_RES & 0xffff); + for (i = 0; i < 4; i++) { + b = (MMC_RES & 0xffff); + c = (MMC_RES & 0xffff); + resp[i] = (a << 24) | (b << 8) | (c >> 8); + a = c; + debug("MMC resp[%d] = %#08x\n", i, resp[i]); } - for (i = words-1; i >= 0; i--) { - ulong res_fifo = MMC_RES; - int offset = i << 1; - resp[offset] = ((uchar *)&res_fifo)[0]; - resp[offset+1] = ((uchar *)&res_fifo)[1]; - } -#ifdef MMC_DEBUG - for (i=0; i<words*2; i += 2) { - printf("MMC resp[%d] = %02x\n", i, resp[i]); - printf("MMC resp[%d] = %02x\n", i+1, resp[i+1]); - } -#endif return resp; } int /****************************************************/ -mmc_block_read(uchar *dst, ulong src, ulong len) +mmc_block_read(uchar * dst, ulong src, ulong len) /****************************************************/ { - uchar *resp; ushort argh, argl; ulong status; @@ -118,13 +104,13 @@ mmc_block_read(uchar *dst, ulong src, ulong len) return 0; } - debug("mmc_block_rd dst %lx src %lx len %d\n", (ulong)dst, src, len); + debug("mmc_block_rd dst %lx src %lx len %d\n", (ulong) dst, src, len); argh = len >> 16; argl = len & 0xffff; /* set block len */ - resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); + mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); /* send read command */ argh = src >> 16; @@ -133,17 +119,17 @@ mmc_block_read(uchar *dst, ulong src, ulong len) MMC_RDTO = 0xffff; MMC_NOB = 1; MMC_BLKLEN = len; - resp = mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl, - MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); - + mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl, + MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK | + MMC_CMDAT_DATA_EN); MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ; while (len) { if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) { #ifdef CONFIG_PXA27X int i; - for (i=min(len,32); i; i--) { - *dst++ = * ((volatile uchar *) &MMC_RXFIFO); + for (i = min(len, 32); i; i--) { + *dst++ = *((volatile uchar *)&MMC_RXFIFO); len--; } #else @@ -158,7 +144,7 @@ mmc_block_read(uchar *dst, ulong src, ulong len) } } MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; - while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)); + while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ; status = MMC_STAT; if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); @@ -169,10 +155,9 @@ mmc_block_read(uchar *dst, ulong src, ulong len) int /****************************************************/ -mmc_block_write(ulong dst, uchar *src, int len) +mmc_block_write(ulong dst, uchar * src, int len) /****************************************************/ { - uchar *resp; ushort argh, argl; ulong status; @@ -180,13 +165,13 @@ mmc_block_write(ulong dst, uchar *src, int len) return 0; } - debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong)src, len); + debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong) src, len); argh = len >> 16; argl = len & 0xffff; /* set block len */ - resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); + mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); /* send write command */ argh = dst >> 16; @@ -194,15 +179,16 @@ mmc_block_write(ulong dst, uchar *src, int len) MMC_STRPCL = MMC_STRPCL_STOP_CLK; MMC_NOB = 1; MMC_BLKLEN = len; - resp = mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl, - MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); + mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl, + MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK | + MMC_CMDAT_DATA_EN); MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ; while (len) { if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) { - int i, bytes = min(32,len); + int i, bytes = min(32, len); - for (i=0; i<bytes; i++) { + for (i = 0; i < bytes; i++) { MMC_TXFIFO = *src++; } if (bytes < 32) { @@ -217,9 +203,9 @@ mmc_block_write(ulong dst, uchar *src, int len) } } MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; - while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)); + while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ; MMC_I_MASK = ~MMC_I_MASK_PRG_DONE; - while (!(MMC_I_REG & MMC_I_REG_PRG_DONE)); + while (!(MMC_I_REG & MMC_I_REG_PRG_DONE)) ; status = MMC_STAT; if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); @@ -228,10 +214,9 @@ mmc_block_write(ulong dst, uchar *src, int len) return 0; } - int /****************************************************/ -mmc_read(ulong src, uchar *dst, int size) +mmc_read(ulong src, uchar * dst, int size) /****************************************************/ { ulong end, part_start, part_end, part_len, aligned_start, aligned_end; @@ -257,33 +242,46 @@ mmc_read(ulong src, uchar *dst, int size) aligned_end = mmc_block_address & end; /* all block aligned accesses */ - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + debug + ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); if (part_start) { part_len = mmc_block_size - part_start; - debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) { + debug + ("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); + if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < + 0) { return -1; } - memcpy(dst, mmc_buf+part_start, part_len); + memcpy(dst, mmc_buf + part_start, part_len); dst += part_len; src += part_len; } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + debug + ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) { - debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) { + debug + ("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); + if ((mmc_block_read((uchar *) (dst), src, mmc_block_size)) < 0) { return -1; } } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + debug + ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); if (part_end && src < end) { - debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + debug + ("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { return -1; } @@ -294,7 +292,7 @@ mmc_read(ulong src, uchar *dst, int size) int /****************************************************/ -mmc_write(uchar *src, ulong dst, int size) +mmc_write(uchar * src, ulong dst, int size) /****************************************************/ { ulong end, part_start, part_end, part_len, aligned_start, aligned_end; @@ -320,36 +318,50 @@ mmc_write(uchar *src, ulong dst, int size) aligned_end = mmc_block_address & end; /* all block aligned accesses */ - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + debug + ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); if (part_start) { part_len = mmc_block_size - part_start; - debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) { + debug + ("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + (ulong) src, dst, end, part_start, part_end, aligned_start, + aligned_end); + if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < + 0) { return -1; } - memcpy(mmc_buf+part_start, src, part_len); - if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) { + memcpy(mmc_buf + part_start, src, part_len); + if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < + 0) { return -1; } dst += part_len; src += part_len; } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + debug + ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) { - debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) { + debug + ("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); + if ((mmc_block_write(dst, (uchar *) src, mmc_block_size)) < 0) { return -1; } } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + debug + ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); if (part_end && dst < end) { - debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + debug + ("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong) dst, end, part_start, part_end, aligned_start, + aligned_end); if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { return -1; } @@ -363,127 +375,288 @@ mmc_write(uchar *src, ulong dst, int size) ulong /****************************************************/ -mmc_bread(int dev_num, ulong blknr, ulong blkcnt, void *dst) +mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong * dst) /****************************************************/ { int mmc_block_size = MMC_BLOCK_SIZE; ulong src = blknr * mmc_block_size + CFG_MMC_BASE; - mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size); + mmc_read(src, (uchar *) dst, blkcnt * mmc_block_size); return blkcnt; } +#ifdef __GNUC__ +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) +#else +#define likely(x) (x) +#define unlikely(x) (x) +#endif + +#define UNSTUFF_BITS(resp,start,size) \ + ({ \ + const int __size = size; \ + const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; \ + const int32_t __off = 3 - ((start) / 32); \ + const int32_t __shft = (start) & 31; \ + uint32_t __res; \ + \ + __res = resp[__off] >> __shft; \ + if (__size + __shft > 32) \ + __res |= resp[__off-1] << ((32 - __shft) % 32); \ + __res & __mask; \ + }) + +/* + * Given the decoded CSD structure, decode the raw CID to our CID structure. + */ +static void mmc_decode_cid(uint32_t * resp) +{ + if (IF_TYPE_SD == mmc_dev.if_type) { + /* + * SD doesn't currently have a version field so we will + * have to assume we can parse this. + */ + sprintf((char *)mmc_dev.vendor, + "Man %02x OEM %c%c \"%c%c%c%c%c\" Date %02u/%04u", + UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, 112, 8), + UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp, 96, 8), + UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp, 80, 8), + UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp, 64, 8), + UNSTUFF_BITS(resp, 8, 4), UNSTUFF_BITS(resp, 12, + 8) + 2000); + sprintf((char *)mmc_dev.revision, "%d.%d", + UNSTUFF_BITS(resp, 60, 4), UNSTUFF_BITS(resp, 56, 4)); + sprintf((char *)mmc_dev.product, "%u", + UNSTUFF_BITS(resp, 24, 32)); + } else { + /* + * The selection of the format here is based upon published + * specs from sandisk and from what people have reported. + */ + switch (spec_ver) { + case 0: /* MMC v1.0 - v1.2 */ + case 1: /* MMC v1.4 */ + sprintf((char *)mmc_dev.vendor, + "Man %02x%02x%02x \"%c%c%c%c%c%c%c\" Date %02u/%04u", + UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, + 112, + 8), + UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp, + 96, 8), + UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp, + 80, 8), + UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp, + 64, 8), + UNSTUFF_BITS(resp, 56, 8), UNSTUFF_BITS(resp, + 48, 8), + UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8, + 4) + + 1997); + sprintf((char *)mmc_dev.revision, "%d.%d", + UNSTUFF_BITS(resp, 44, 4), UNSTUFF_BITS(resp, + 40, 4)); + sprintf((char *)mmc_dev.product, "%u", + UNSTUFF_BITS(resp, 16, 24)); + break; + + case 2: /* MMC v2.0 - v2.2 */ + case 3: /* MMC v3.1 - v3.3 */ + case 4: /* MMC v4 */ + sprintf((char *)mmc_dev.vendor, + "Man %02x OEM %04x \"%c%c%c%c%c%c\" Date %02u/%04u", + UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, + 104, + 16), + UNSTUFF_BITS(resp, 96, 8), UNSTUFF_BITS(resp, + 88, 8), + UNSTUFF_BITS(resp, 80, 8), UNSTUFF_BITS(resp, + 72, 8), + UNSTUFF_BITS(resp, 64, 8), UNSTUFF_BITS(resp, + 56, 8), + UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8, + 4) + + 1997); + sprintf((char *)mmc_dev.product, "%u", + UNSTUFF_BITS(resp, 16, 32)); + sprintf((char *)mmc_dev.revision, "N/A"); + break; + + default: + printf("MMC card has unknown MMCA version %d\n", + spec_ver); + break; + } + } + printf("%s card.\nVendor: %s\nProduct: %s\nRevision: %s\n", + (IF_TYPE_SD == mmc_dev.if_type) ? "SD" : "MMC", mmc_dev.vendor, + mmc_dev.product, mmc_dev.revision); +} + +/* + * Given a 128-bit response, decode to our card CSD structure. + */ +static void mmc_decode_csd(uint32_t * resp) +{ + unsigned int mult, csd_struct; + + if (IF_TYPE_SD == mmc_dev.if_type) { + csd_struct = UNSTUFF_BITS(resp, 126, 2); + if (csd_struct != 0) { + printf("SD: unrecognised CSD structure version %d\n", + csd_struct); + return; + } + } else { + /* + * We only understand CSD structure v1.1 and v1.2. + * v1.2 has extra information in bits 15, 11 and 10. + */ + csd_struct = UNSTUFF_BITS(resp, 126, 2); + if (csd_struct != 1 && csd_struct != 2) { + printf("MMC: unrecognised CSD structure version %d\n", + csd_struct); + return; + } + + spec_ver = UNSTUFF_BITS(resp, 122, 4); + mmc_dev.if_type = IF_TYPE_MMC; + } + + mult = 1 << (UNSTUFF_BITS(resp, 47, 3) + 2); + mmc_dev.lba = (1 + UNSTUFF_BITS(resp, 62, 12)) * mult; + mmc_dev.blksz = 1 << UNSTUFF_BITS(resp, 80, 4); + + /* FIXME: The following just makes assumes that's the partition type -- should really read it */ + mmc_dev.part_type = PART_TYPE_DOS; + mmc_dev.dev = 0; + mmc_dev.lun = 0; + mmc_dev.type = DEV_TYPE_HARDDISK; + mmc_dev.removable = 0; + mmc_dev.block_read = mmc_bread; + + printf("Detected: %u blocks of %u bytes (%uMB) ", mmc_dev.lba, + mmc_dev.blksz, mmc_dev.lba * mmc_dev.blksz / (1024 * 1024)); +} + int /****************************************************/ mmc_init(int verbose) /****************************************************/ { - int retries, rc = -ENODEV; - uchar *resp; + int retries, rc = -ENODEV; + uint32_t cid_resp[4]; + uint32_t *resp; + uint16_t rca = 0; + + /* Reset device interface type */ + mmc_dev.if_type = IF_TYPE_UNKNOWN; -#ifdef CONFIG_LUBBOCK - set_GPIO_mode( GPIO6_MMCCLK_MD ); - set_GPIO_mode( GPIO8_MMCCS0_MD ); +#if defined (CONFIG_LUBBOCK) || (defined (CONFIG_GUMSTIX) && !defined(CONFIG_PXA27X)) + set_GPIO_mode(GPIO6_MMCCLK_MD); + set_GPIO_mode(GPIO8_MMCCS0_MD); #endif - CKEN |= CKEN12_MMC; /* enable MMC unit clock */ + CKEN |= CKEN12_MMC; /* enable MMC unit clock */ #if defined(CONFIG_ADSVIX) /* turn on the power */ GPCR(114) = GPIO_bit(114); udelay(1000); #endif - mmc_csd.c_size = 0; - - MMC_CLKRT = MMC_CLKRT_0_3125MHZ; - MMC_RESTO = MMC_RES_TO_MAX; - MMC_SPI = MMC_SPI_DISABLE; + MMC_CLKRT = MMC_CLKRT_0_3125MHZ; + MMC_RESTO = MMC_RES_TO_MAX; + MMC_SPI = MMC_SPI_DISABLE; /* reset */ - retries = 10; - resp = mmc_cmd(0, 0, 0, 0); - resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3); - while (retries-- && resp && !(resp[4] & 0x80)) { - debug("resp %x %x\n", resp[0], resp[1]); + mmc_cmd(MMC_CMD_RESET, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); + udelay(200000); + retries = 3; + while (retries--) { + resp = mmc_cmd(MMC_CMD_APP_CMD, 0, 0, MMC_CMDAT_R1); + if (!(resp[0] & 0x00000020)) { /* Card does not support APP_CMD */ + debug("Card does not support APP_CMD\n"); + break; + } + + resp = mmc_cmd(SD_CMD_APP_OP_COND, 0x0020, 0, MMC_CMDAT_R3 | (retries < 2 ? 0 : MMC_CMDAT_INIT)); /* Select 3.2-3.3 and 3.3-3.4V */ + if (resp[0] & 0x80000000) { + mmc_dev.if_type = IF_TYPE_SD; + debug("Detected SD card\n"); + break; + } #ifdef CONFIG_PXA27X udelay(10000); #else - udelay(50); + udelay(200000); #endif - resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3); + } + + if (retries <= 0 || !(IF_TYPE_SD == mmc_dev.if_type)) { + debug("Failed to detect SD Card, trying MMC\n"); + resp = + mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000, MMC_CMDAT_R3); + + retries = 10; + while (retries-- && resp && !(resp[0] & 0x80000000)) { +#ifdef CONFIG_PXA27X + udelay(10000); +#else + udelay(200000); +#endif + resp = + mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000, + MMC_CMDAT_R3); + } } /* try to get card id */ - resp = mmc_cmd(2, 0, 0, MMC_CMDAT_R2); + resp = + mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, 0, MMC_CMDAT_R2 | MMC_CMDAT_BUSY); if (resp) { - /* TODO configure mmc driver depending on card attributes */ - mmc_cid_t *cid = (mmc_cid_t *)resp; - if (verbose) { - printf("MMC found. Card desciption is:\n"); - printf("Manufacturer ID = %02x%02x%02x\n", - cid->id[0], cid->id[1], cid->id[2]); - printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev); - cid->hwrev = cid->fwrev = 0; /* null terminate string */ - printf("Product Name = %s\n",cid->name); - printf("Serial Number = %02x%02x%02x\n", - cid->sn[0], cid->sn[1], cid->sn[2]); - printf("Month = %d\n",cid->month); - printf("Year = %d\n",1997 + cid->year); - } - /* fill in device description */ - mmc_dev.if_type = IF_TYPE_MMC; - mmc_dev.part_type = PART_TYPE_DOS; - mmc_dev.dev = 0; - mmc_dev.lun = 0; - mmc_dev.type = 0; - /* FIXME fill in the correct size (is set to 32MByte) */ - mmc_dev.blksz = 512; - mmc_dev.lba = 0x10000; - sprintf((char*)mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", - cid->id[0], cid->id[1], cid->id[2], - cid->sn[0], cid->sn[1], cid->sn[2]); - sprintf((char*)mmc_dev.product,"%s",cid->name); - sprintf((char*)mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); - mmc_dev.removable = 0; - mmc_dev.block_read = mmc_bread; + memcpy(cid_resp, resp, sizeof(cid_resp)); /* MMC exists, get CSD too */ - resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1); - resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R2); + resp = mmc_cmd(MMC_CMD_SET_RCA, 0, 0, MMC_CMDAT_R1); + if (IF_TYPE_SD == mmc_dev.if_type) + rca = ((resp[0] & 0xffff0000) >> 16); + resp = mmc_cmd(MMC_CMD_SEND_CSD, rca, 0, MMC_CMDAT_R2); if (resp) { - mmc_csd_t *csd = (mmc_csd_t *)resp; - memcpy(&mmc_csd, csd, sizeof(csd)); + mmc_decode_csd(resp); rc = 0; mmc_ready = 1; - /* FIXME add verbose printout for csd */ } + + mmc_decode_cid(cid_resp); } + MMC_CLKRT = 0; /* 20 MHz */ + resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1); + #ifdef CONFIG_PXA27X - MMC_CLKRT = 1; /* 10 MHz - see Intel errata */ -#else - MMC_CLKRT = 0; /* 20 MHz */ + if (IF_TYPE_SD == mmc_dev.if_type) { + resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1); + resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1); + wide = MMC_CMDAT_SD_4DAT; + } #endif - resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1); - fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ + fat_register_device(&mmc_dev, 1); /* partitions start counting with 1 */ return rc; } -int -mmc_ident(block_dev_desc_t *dev) +int mmc_ident(block_dev_desc_t * dev) { return 0; } -int -mmc2info(ulong addr) +int mmc2info(ulong addr) { - /* FIXME hard codes to 32 MB device */ - if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) { + if (addr >= CFG_MMC_BASE + && addr < CFG_MMC_BASE + (mmc_dev.lba * mmc_dev.blksz)) { return 1; } return 0; } -#endif /* CONFIG_MMC */ +#endif /* CONFIG_MMC */ diff --git a/fs/fat/fat.c b/fs/fat/fat.c index e98e50a..dd87e01 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -93,7 +93,7 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) #if (defined(CONFIG_CMD_IDE) || \ defined(CONFIG_CMD_SCSI) || \ defined(CONFIG_CMD_USB) || \ - (defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \ + defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) ) /* First we assume, there is a MBR */ if (!get_partition_info (dev_desc, part_no, &info)) { diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h index a62679a..b9304b1 100644 --- a/include/asm-arm/arch-pxa/mmc.h +++ b/include/asm-arm/arch-pxa/mmc.h @@ -54,14 +54,17 @@ #define MMC_SPI_CRC_ON (0x01UL << 1) /* MMC_CMDAT */ +#define MMC_CMDAT_SD_4DAT (0x0001UL << 8) #define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) #define MMC_CMDAT_INIT (0x0001UL << 6) #define MMC_CMDAT_BUSY (0x0001UL << 5) +#define MMC_CMDAT_BCR (0x0003UL << 5) #define MMC_CMDAT_STREAM (0x0001UL << 4) #define MMC_CMDAT_BLOCK (0x0000UL << 4) #define MMC_CMDAT_WRITE (0x0001UL << 3) #define MMC_CMDAT_READ (0x0000UL << 3) #define MMC_CMDAT_DATA_EN (0x0001UL << 2) +#define MMC_CMDAT_R0 (0) #define MMC_CMDAT_R1 (0x0001UL) #define MMC_CMDAT_R2 (0x0002UL) #define MMC_CMDAT_R3 (0x0003UL) @@ -111,6 +114,7 @@ #define MMC_CMD_SEND_OP_COND 1 #define MMC_CMD_ALL_SEND_CID 2 #define MMC_CMD_SET_RCA 3 +#define MMC_CMD_SELECT_CARD 7 #define MMC_CMD_SEND_CSD 9 #define MMC_CMD_SEND_CID 10 #define MMC_CMD_SEND_STATUS 13 @@ -118,6 +122,10 @@ #define MMC_CMD_READ_BLOCK 17 #define MMC_CMD_RD_BLK_MULTI 18 #define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_APP_CMD 55 + +#define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_APP_OP_COND 41 #define MMC_MAX_BLOCK_SIZE 512 @@ -158,42 +166,41 @@ typedef struct mmc_cid typedef struct mmc_csd { - uchar ecc:2, - file_format:2, - tmp_write_protect:1, - perm_write_protect:1, - copy:1, - file_format_grp:1; - uint64_t content_prot_app:1, - rsvd3:4, - write_bl_partial:1, - write_bl_len:4, - r2w_factor:3, - default_ecc:2, - wp_grp_enable:1, - wp_grp_size:5, - erase_grp_mult:5, - erase_grp_size:5, - c_size_mult1:3, - vdd_w_curr_max:3, - vdd_w_curr_min:3, - vdd_r_curr_max:3, - vdd_r_curr_min:3, - c_size:12, - rsvd2:2, - dsr_imp:1, - read_blk_misalign:1, - write_blk_misalign:1, - read_bl_partial:1; - - ushort read_bl_len:4, - ccc:12; - uchar tran_speed; - uchar nsac; - uchar taac; - uchar rsvd1:2, - spec_vers:4, - csd_structure:2; + uint8_t csd_structure:2, + spec_ver:4, + rsvd1:2; + uint8_t taac; + uint8_t nsac; + uint8_t tran_speed; + uint16_t ccc:12, + read_bl_len:4; + uint64_t read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + erase_blk_en:1, + sector_size:7, + wp_grp_size:7, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:4, + content_prot_app:1; + uint8_t file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; } mmc_csd_t; diff --git a/include/part.h b/include/part.h index 37b2b68..8407aa0 100644 --- a/include/part.h +++ b/include/part.h @@ -59,6 +59,7 @@ typedef struct block_dev_desc { #define IF_TYPE_USB 4 #define IF_TYPE_DOC 5 #define IF_TYPE_MMC 6 +#define IF_TYPE_SD 7 /* Part types */ #define PART_TYPE_UNKNOWN 0x00 -- 1.4.4.2

2 1

[U-Boot-Users] [PATCH] Fix gcc issues in pxa-regs.h
by stefano babic 03 Feb '08

03 Feb '08

Fix gcc4 issue. With some toolchain, a previous patch that fixes gcc4 issues generates wrong code. (Problem was reported with gcc-4.0.2-glibc-2.3.6/arm-softfloat-linux-gnu). This patch fixes the problem and solves the gcc-4 issues as the linux kernel does. Signed-off-by: Stefano Babic <sbabic(a)denx.de> Signed-off-by: Dmitry Ivanov <ivadmitry(a)gmail.com> -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de ===================================================================== >From 903480ff8cc9ff39c2b3379067a8007ce292bd03 Mon Sep 17 00:00:00 2001 From: Stefano Babic <sbabic(a)denx.de> Date: Tue, 20 Nov 2007 10:27:25 +0100 Subject: [PATCH] Fix gcc4 issue. With some toolchain, a previous patch that fixes gcc4 issues generates wrong code. (Problem was reported with gcc-4.0.2-glibc-2.3.6/arm-softfloat-linux-gnu). This patch fixes the problem and solves the gcc-4 issues as the linux kernel does. --- include/asm-arm/arch-pxa/pxa-regs.h | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 9b4da3a..e014568 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1288,15 +1288,15 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) -#define GPLR(x) __REG2(0x40E00000 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GPDR(x) __REG2(0x40E0000C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GPSR(x) __REG2(0x40E00018 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GPCR(x) __REG2(0x40E00024 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GRER(x) __REG2(0x40E00030 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GFER(x) __REG2(0x40E0003C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GEDR(x) __REG2(0x40E00048 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) -#define GAFR(x) __REG2((((x) & 0x7f) < 96) ? 0x40E00054 : \ - ((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3) +#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) +#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) +#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) +#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) +#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) +#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) +#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) +#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ + ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) #else #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -- 1.4.4.2

2 1

[U-Boot-Users] (no subject)
by Yotam Admon 01 Feb '08

01 Feb '08

Hi, I am trying to find EHCI drivers for U-boot, does any one know of a board supporting EHCI in U-boot? Thanks, Yotam

3 2

[U-Boot-Users] [PATCH 1/3 RESEND] ppc4xx: Add initial esd PMC440 board files
by Matthias Fuchs 31 Jan '08

31 Jan '08

This patch adds the first files for the new esd PMC440 boards. The next two patches will complete the PMC440 board support. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- board/{amcc/sequoia => esd/pmc440}/Makefile | 4 +- board/{amcc/sequoia => esd/pmc440}/config.mk | 0 board/{amcc/sequoia => esd/pmc440}/init.S | 64 +-- .../sequoia/sequoia.c => esd/pmc440/pmc440.c} | 564 +++++++++++++++----- board/esd/pmc440/pmc440.h | 154 ++++++ board/{amcc/sequoia => esd/pmc440}/sdram.c | 0 board/{amcc/sequoia => esd/pmc440}/sdram.h | 0 board/{amcc/sequoia => esd/pmc440}/u-boot-nand.lds | 0 board/{amcc/sequoia => esd/pmc440}/u-boot.lds | 0 9 files changed, 595 insertions(+), 191 deletions(-) copy board/{amcc/sequoia => esd/pmc440}/Makefile (95%) copy board/{amcc/sequoia => esd/pmc440}/config.mk (100%) copy board/{amcc/sequoia => esd/pmc440}/init.S (71%) copy board/{amcc/sequoia/sequoia.c => esd/pmc440/pmc440.c} (57%) create mode 100644 board/esd/pmc440/pmc440.h copy board/{amcc/sequoia => esd/pmc440}/sdram.c (100%) copy board/{amcc/sequoia => esd/pmc440}/sdram.h (100%) copy board/{amcc/sequoia => esd/pmc440}/u-boot-nand.lds (100%) copy board/{amcc/sequoia => esd/pmc440}/u-boot.lds (100%) diff --git a/board/amcc/sequoia/Makefile b/board/esd/pmc440/Makefile similarity index 95% copy from board/amcc/sequoia/Makefile copy to board/esd/pmc440/Makefile index e1c9ad4..4dd9c38 100644 --- a/board/amcc/sequoia/Makefile +++ b/board/esd/pmc440/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cmd_sequoia.o sdram.o +COBJS = $(BOARD).o cmd_pmc440.o sdram.o fpga.o \ + ../common/cmd_loadpci.o + SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/amcc/sequoia/config.mk b/board/esd/pmc440/config.mk similarity index 100% copy from board/amcc/sequoia/config.mk copy to board/esd/pmc440/config.mk diff --git a/board/amcc/sequoia/init.S b/board/esd/pmc440/init.S similarity index 71% copy from board/amcc/sequoia/init.S copy to board/esd/pmc440/init.S index c7da521..148af71 100644 --- a/board/amcc/sequoia/init.S +++ b/board/esd/pmc440/init.S @@ -10,7 +10,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -20,57 +20,9 @@ */ #include <ppc_asm.tmpl> +#include <asm-ppc/mmu.h> #include <config.h> -/* General */ -#define TLB_VALID 0x00000200 -#define _256M 0x10000000 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_8M 0x00000060 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - /************************************************************************** * TLB TABLE * @@ -115,8 +67,13 @@ tlbtab: tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) - /* TLB-entry for EBC */ - tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* TLB-entries for EBC */ + /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral + * tlb entry. + * This dummy entry is only for convinience in order not to modify the + * amount of entries. Currently OS/9 relies on this :-) + */ + tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for NAND */ tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) @@ -130,9 +87,10 @@ tlbtab: /* TLB-entry for peripherals */ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - /* TLB-entry PCI IO Space - from sr(a)denx.de */ + /* TLB-entry PCI IO space */ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + /* TODO: what about high IO space */ tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) diff --git a/board/amcc/sequoia/sequoia.c b/board/esd/pmc440/pmc440.c similarity index 57% copy from board/amcc/sequoia/sequoia.c copy to board/esd/pmc440/pmc440.c index f81f071..edf3a14 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/esd/pmc440/pmc440.c @@ -1,5 +1,9 @@ /* - * (C) Copyright 2006-2007 + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh, matthias.fuchs(a)esd-electronics.com. + * Based on board/amcc/sequoia/sequoia.c + * + * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * * (C) Copyright 2006 @@ -28,12 +32,62 @@ #include <ppc440.h> #include <asm/processor.h> #include <asm/io.h> +#include <command.h> +#include <i2c.h> +#ifdef CONFIG_RESET_PHY_R +#include <miiphy.h> +#endif +#include <serial.h> +#include "fpga.h" +#include "pmc440.h" DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -ulong flash_get_size (ulong base, int banknum); +ulong flash_get_size(ulong base, int banknum); +int pci_is_66mhz(void); +int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); + + +struct serial_device *default_serial_console(void) +{ + uchar buf[4]; + ulong delay; + int i; + ulong val; + + /* + * Use default console on P4 when strapping jumper + * is installed (bootstrap option != 'H'). + */ + mfsdr(SDR_PINSTP, val); + if (((val & 0xf0000000) >> 29) != 7) + return &serial1_device; + + ulong scratchreg = in_be32((void*)GPIO0_ISR3L); + if (!(scratchreg & 0x80)) { + /* mark scratchreg valid */ + scratchreg = (scratchreg & 0xffffff00) | 0x80; + + i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4); + if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) { + scratchreg |= buf[2]; + + /* bringup delay for console */ + for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) { + udelay(1000); + } + } else + scratchreg |= 0x01; + out_be32((void*)GPIO0_ISR3L, scratchreg); + } + + if (scratchreg & 0x01) + return &serial1_device; + else + return &serial0_device; +} int board_early_init_f(void) { @@ -41,90 +95,91 @@ int board_early_init_f(void) u32 sdr0_pfc1, sdr0_pfc2; u32 reg; + /* general EBC configuration (disable EBC timeouts) */ mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(ebccfgd, 0xf8400000); /*-------------------------------------------------------------------- * Setup the GPIO pins + * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file *-------------------------------------------------------------------*/ - /* test-only: take GPIO init from pcs440ep ???? in config file */ - out32(GPIO0_OR, 0x00000000); - out32(GPIO0_TCR, 0x0000000f); - out32(GPIO0_OSRL, 0x50015400); - out32(GPIO0_OSRH, 0x550050aa); - out32(GPIO0_TSRL, 0x50015400); - out32(GPIO0_TSRH, 0x55005000); - out32(GPIO0_ISR1L, 0x50000000); + out32(GPIO0_OR, 0x40000002); + out32(GPIO0_TCR, 0x4c90011f); + out32(GPIO0_OSRL, 0x28011400); + out32(GPIO0_OSRH, 0x55005000); + out32(GPIO0_TSRL, 0x08011400); + out32(GPIO0_TSRH, 0x55005000); + out32(GPIO0_ISR1L, 0x54000000); out32(GPIO0_ISR1H, 0x00000000); - out32(GPIO0_ISR2L, 0x00000000); + out32(GPIO0_ISR2L, 0x44000000); out32(GPIO0_ISR2H, 0x00000100); out32(GPIO0_ISR3L, 0x00000000); out32(GPIO0_ISR3H, 0x00000000); - out32(GPIO1_OR, 0x00000000); - out32(GPIO1_TCR, 0xc2000000); - out32(GPIO1_OSRL, 0x5c280000); - out32(GPIO1_OSRH, 0x00000000); - out32(GPIO1_TSRL, 0x0c000000); - out32(GPIO1_TSRH, 0x00000000); - out32(GPIO1_ISR1L, 0x00005550); - out32(GPIO1_ISR1H, 0x00000000); - out32(GPIO1_ISR2L, 0x00050000); + out32(GPIO1_OR, 0x80002408); + out32(GPIO1_TCR, 0xd6003c08); + out32(GPIO1_OSRL, 0x0a5a0000); + out32(GPIO1_OSRH, 0x00000000); + out32(GPIO1_TSRL, 0x00000000); + out32(GPIO1_TSRH, 0x00000000); + out32(GPIO1_ISR1L, 0x00005555); + out32(GPIO1_ISR1H, 0x40000000); + out32(GPIO1_ISR2L, 0x04010000); out32(GPIO1_ISR2H, 0x00000000); out32(GPIO1_ISR3L, 0x01400000); out32(GPIO1_ISR3H, 0x00000000); + /* patch PLB:PCI divider for 66MHz PCI */ + mfcpr(clk_spcid, reg); + if (pci_is_66mhz() && (reg != 0x02000000)) { + mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */ + + mfcpr(clk_icfg, reg); + reg |= CPR0_ICFG_RLI_MASK; + mtcpr(clk_icfg, reg); + + mtspr(dbcr0, 0x20000000); /* do chip reset */ + } + /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic0er, 0x00000000); /* disable all */ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic0pr, 0xfffff7ef); + mtdcr(uic0tr, 0x00000000); mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic1sr, 0xffffffff); /* clear all */ mtdcr(uic1er, 0x00000000); /* disable all */ mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic1pr, 0xffffc7f5); + mtdcr(uic1tr, 0x00000000); mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic1sr, 0xffffffff); /* clear all */ mtdcr(uic2sr, 0xffffffff); /* clear all */ mtdcr(uic2er, 0x00000000); /* disable all */ mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic2pr, 0x27ffffff); + mtdcr(uic2tr, 0x00000000); mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic2sr, 0xffffffff); /* clear all */ - /* 50MHz tmrclk */ - *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; - - /* clear write protects */ - *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; - - /* enable Ethernet */ - *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00; - - /* enable USB device */ - *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20; - /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; mfsdr(SDR0_PFC2, sdr0_pfc2); sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; + + /* enable 2nd IIC */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; + mtsdr(SDR0_PFC2, sdr0_pfc2); mtsdr(SDR0_PFC1, sdr0_pfc1); - /* PCI arbiter enabled */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); - /* setup NAND FLASH */ mfsdr(SDR0_CUST0, sdr0_cust0); sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | @@ -145,12 +200,10 @@ int misc_init_r(void) uint pbcr; int size_val = 0; u32 reg; -#ifdef CONFIG_440EPX unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; char *act = getenv("usbact"); -#endif /* * FLASH stuff... @@ -163,7 +216,7 @@ int misc_init_r(void) gd->bd->bi_flashoffset = 0; #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb3cr); + mtdcr(ebccfga, pb2cr); #else mtdcr(ebccfga, pb0cr); #endif @@ -196,7 +249,7 @@ int misc_init_r(void) } pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb3cr); + mtdcr(ebccfga, pb2cr); #else mtdcr(ebccfga, pb0cr); #endif @@ -224,8 +277,8 @@ int misc_init_r(void) /* * USB suff... */ -#ifdef CONFIG_440EPX - if (act == NULL || strcmp(act, "hostdev") == 0) { + if ((act == NULL || strcmp(act, "hostdev") == 0) && + !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){ /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_USB2D0CR, usb2d0cr); @@ -248,12 +301,8 @@ int misc_init_r(void) usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ - /* To enable the USB 2.0 Device function through the UTMI interface */ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_USB2D0CR, usb2d0cr); @@ -261,14 +310,14 @@ int misc_init_r(void) mtsdr(SDR0_USB2H0CR, usb2h0cr); /*clear resets*/ - udelay (1000); + udelay(1000); mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); + udelay(1000); mtsdr(SDR0_SRST0, 0x00000000); - printf("USB: Host(int phy) Device(ext phy)\n"); + printf("USB: Host\n"); - } else if (strcmp(act, "dev") == 0) { + } else if ((strcmp(act, "dev") == 0) || (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { /*-------------------PATCH-------------------------------*/ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); @@ -318,7 +367,6 @@ int misc_init_r(void) usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ @@ -329,18 +377,13 @@ int misc_init_r(void) mtsdr(SDR0_PFC1, sdr0_pfc1); /*clear resets*/ - udelay (1000); + udelay(1000); mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); + udelay(1000); mtsdr(SDR0_SRST0, 0x00000000); - printf("USB: Device(int phy)\n"); + printf("USB: Device\n"); } -#endif /* CONFIG_440EPX */ - - mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ - reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); - mtsdr(SDR0_SRST1, reg); /* * Clear PLB4A0_ACR[WRP] @@ -350,69 +393,63 @@ int misc_init_r(void) reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; mtdcr(plb4_acr, reg); +#ifdef CONFIG_FPGA + pmc440_init_fpga(); +#endif + + /* turn off POST LED */ + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N); + /* turn on RUN LED */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N); return 0; } -int checkboard(void) +int is_monarch(void) { - char *s = getenv("serial#"); - u8 rev; - u8 val; - -#ifdef CONFIG_440EPX - printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); -#else - printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); -#endif + if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH) + return 0; - rev = in_8((void *)(CFG_BCSR_BASE + 0)); - val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN; - printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); + return 1; +} - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); +int pci_is_66mhz(void) +{ + if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN) + return 1; + return 0; +} - return (0); +int board_revision(void) +{ + return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4); } -#if defined(CFG_DRAM_TEST) -int testdram(void) +int checkboard(void) { - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; + puts("Board: esd GmbH - PMC440"); - mtmsr(0); + gd->board_type = board_revision(); + printf(", Rev 1.%ld, ", gd->board_type); - for (k = 0; k < CFG_MBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } + if (!is_monarch()) { + puts("non-"); + } - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } + printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33"); + return (0); +} - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; + +#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) +/* + * Assign interrupts to PCI devices. Some OSs rely on this. + */ +void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB}; + + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + int_line[PCI_DEV(dev) & 0x03]); } #endif @@ -467,6 +504,10 @@ int pci_pre_init(struct pci_controller *hose) addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; mtdcr(plb1_acr, addr); +#ifdef CONFIG_PCI_PNP + hose->fixup_irq = pmc440_pci_fixup_irq; +#endif + return 1; } #endif /* defined(CONFIG_PCI) */ @@ -488,7 +529,7 @@ void pci_target_init(struct pci_controller *hose) /*--------------------------------------------------------------------------+ | PowerPC440EPX PCI Master configuration. | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + | PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF | Use byte reversed out routines to handle endianess. | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ @@ -496,30 +537,39 @@ void pci_target_init(struct pci_controller *hose) out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, and enable region */ + + if (!is_monarch()) { + /* BAR1: top 64MB of RAM */ + out32r(PCIX0_PTM1MS, 0xfc000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0x0c000000); /* Local Addr. Reg */ + } else { + /* BAR1: complete 256MB RAM (TODO: make dynamic) */ + out32r(PCIX0_PTM1MS, 0xf0000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0x00000000); /* Local Addr. Reg */ + } - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + /* BAR2: 16 MB FPGA registers */ + out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */ - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + if (is_monarch()) { + /* BAR2: map FPGA registers behind system memory at 1GB */ + pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008); + } /*--------------------------------------------------------------------------+ * Set up Configuration registers *--------------------------------------------------------------------------*/ - /* Program the board's subsystem id/vendor id */ + /* Program the board's vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); +#if 0 /* disabled for PMC405 backward compatibility */ /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); +#endif /* 240nS PCI clock */ pci_write_config_word(0, PCI_LATENCY_TIMER, 1); @@ -529,8 +579,25 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + if (!is_monarch()) { + /* Program the board's subsystem id/classcode */ + pci_write_config_word(0, PCI_SUBSYSTEM_ID, + CFG_PCI_SUBSYS_ID_NONMONARCH); + pci_write_config_word(0, PCI_CLASS_SUB_CODE, + CFG_PCI_CLASSCODE_NONMONARCH); + + /* PCI configuration done: release ERREADY */ + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY); + out_be32((void*)GPIO1_TCR, in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY); + } else { + /* Program the board's subsystem id/classcode */ + pci_write_config_word(0, PCI_SUBSYSTEM_ID, + CFG_PCI_SUBSYS_ID_MONARCH); + pci_write_config_word(0, PCI_CLASS_SUB_CODE, + CFG_PCI_CLASSCODE_MONARCH); + } } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init @@ -546,12 +613,42 @@ void pci_master_init(struct pci_controller *hose) | Enable PowerPC440 EP to be a master on the PCI bus (PMM). | Enable PowerPC440 EP to act as a PCI memory target (PTM). +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); + if (is_monarch()) { + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); + } } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + + +static void wait_for_pci_ready(void) +{ + int i; + char *s = getenv("pcidelay"); + if (s) { + int ms = simple_strtoul(s, NULL, 10); + printf("PCI: Waiting for %d ms\n", ms); + for (i=0; i<ms; i++) + udelay(1000); + } + + if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) { + printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); + while (1) { + if (ctrlc()) { + puts("abort\n"); + break; + } + if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) { + printf("done\n"); + break; + } + } + } +} + /************************************************************************* * is_pci_host @@ -571,10 +668,19 @@ void pci_master_init(struct pci_controller *hose) #if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { - /* Cactus is always configured as host. */ - return (1); + char *s = getenv("pciscan"); + if (s == NULL) + if (is_monarch()) { + wait_for_pci_ready(); + return 1; + } else + return 0; + else if (!strcmp(s, "yes")) + return 1; + + return 0; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) */ #if defined(CONFIG_POST) /* * Returns 1 if keys pressed to start the power-on long-running tests @@ -586,6 +692,190 @@ int post_hotkeys_pressed(void) } #endif /* CONFIG_POST */ + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ + if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) { + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000); + } + + if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) { + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000); + } +} +#endif + +#if defined(CFG_EEPROM_WREN) +/* Input: <dev_addr> I2C address of EEPROM device to enable. + * <state> -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if <state> was -1. + */ +int eeprom_write_enable(unsigned dev_addr, int state) +{ + if ((CFG_I2C_EEPROM_ADDR != dev_addr) && (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access, clear bit GPIO_SINT2. */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~GPIO0_EP_EEP); + state = 0; + break; + case 0: + /* Disable write access, set bit GPIO_SINT2. */ + out32(GPIO0_OR, in32(GPIO0_OR) | GPIO0_EP_EEP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in32(GPIO0_OR) & GPIO0_EP_EEP)); + break; + } + } + return state; +} +#endif /* #if defined(CFG_EEPROM_WREN) */ + + +#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3 +int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) +{ + unsigned end = offset + cnt; + unsigned blk_off; + int rcode = 0; + +#if defined(CFG_EEPROM_WREN) + eeprom_write_enable(dev_addr, 1); +#endif + /* Write data until done or would cross a write page boundary. + * We must write the address again when changing pages + * because the address counter only increments within a page. + */ + + while (offset < end) { + unsigned alen, len; + unsigned maxlen; + uchar addr[2]; + + blk_off = offset & 0xFF; /* block offset */ + + addr[0] = offset >> 8; /* block number */ + addr[1] = blk_off; /* block offset */ + alen = 2; + addr[0] |= dev_addr; /* insert device address */ + + len = end - offset; + +#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS) +#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) + + maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET(blk_off); + if (maxlen > I2C_RXTX_LEN) + maxlen = I2C_RXTX_LEN; + + if (len > maxlen) + len = maxlen; + + if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0) + rcode = 1; + + buffer += len; + offset += len; + +#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) + udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#endif + } +#if defined(CFG_EEPROM_WREN) + eeprom_write_enable(dev_addr, 0); +#endif + return rcode; +} + + +int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) +{ + unsigned end = offset + cnt; + unsigned blk_off; + int rcode = 0; + + /* Read data until done or would cross a page boundary. + * We must write the address again when changing pages + * because the next page may be in a different device. + */ + while (offset < end) { + unsigned alen, len; + unsigned maxlen; + uchar addr[2]; + + blk_off = offset & 0xFF; /* block offset */ + + addr[0] = offset >> 8; /* block number */ + addr[1] = blk_off; /* block offset */ + alen = 2; + + addr[0] |= dev_addr; /* insert device address */ + + len = end - offset; + + maxlen = 0x100 - blk_off; + if (maxlen > I2C_RXTX_LEN) + maxlen = I2C_RXTX_LEN; + if (len > maxlen) + len = maxlen; + + if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0) + rcode = 1; + buffer += len; + offset += len; + } + + return rcode; +} + + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) +int usb_board_init(void) +{ + char *act = getenv("usbact"); + int i; + + if ((act == NULL || strcmp(act, "hostdev") == 0) && + !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) + /* enable power on USB socket */ + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + + for (i=0; i<1000; i++) + udelay(1000); + + return 0; +} + +int usb_board_stop(void) +{ + /* disable power on USB socket */ + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N); + return 0; +} + +int usb_board_init_fail(void) +{ + usb_board_stop(); + return 0; +} +#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h new file mode 100644 index 0000000..7e70fd1 --- /dev/null +++ b/board/esd/pmc440/pmc440.h @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh, matthias.fuchs(a)esd-electronics.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __PMC440_H__ +#define __PMC440_H__ + + +/*----------------------------------------------------------------------- + * GPIOs + */ +#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */ +#define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */ +#define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */ +#define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */ +#define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */ +#define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */ +#define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */ + +#define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */ +#define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */ +#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */ +#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */ +#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */ +#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */ + +/* FPGA programming pin configuration */ +#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */ +#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */ +#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */ +#define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */ +#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */ +#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */ + +/*----------------------------------------------------------------------- + * FPGA interface + */ +#define FPGA_BA CFG_FPGA_BASE0 +#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v)) +#define FPGA_IN32(p) in_be32((void*)(p)) +#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v)) +#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v)) + +struct pmc440_fifo_s { + u32 data; + u32 ctrl; +}; + +/* fifo ctrl register */ +#define FIFO_IE (1 << 15) +#define FIFO_OVERFLOW (1 << 10) +#define FIFO_EMPTY (1 << 9) +#define FIFO_FULL (1 << 8) +#define FIFO_LEVEL_MASK 0x000000ff + +#define FIFO_COUNT 4 + +struct pmc440_fpga_s { + u32 ctrla; + u32 status; + u32 ctrlb; + u32 pad1[0x40 / sizeof(u32) - 3]; + u32 irig_time; /* offset: 0x0040 */ + u32 irig_tod; + u32 irig_cf; + u32 pad2; + u32 irig_rx_time; /* offset: 0x0050 */ + u32 pad3[3]; + u32 hostctrl; /* offset: 0x0060 */ + u32 pad4[0x20 / sizeof(u32) - 1]; + struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */ +}; + +typedef struct pmc440_fpga_s pmc440_fpga_t; + +/* ctrl register */ +#define CTRL_HOST_IE (1 << 8) + +/* outputs */ +#define RESET_EN (1 << 31) +#define CLOCK_EN (1 << 30) +#define RESET_OUT (1 << 19) +#define CLOCK_OUT (1 << 22) +#define RESET_OUT (1 << 19) +#define IRIGB_R_OUT (1 << 14) + + +/* status register */ +#define STATUS_VERSION_SHIFT 24 +#define STATUS_VERSION_MASK 0xff000000 +#define STATUS_HWREV_SHIFT 20 +#define STATUS_HWREV_MASK 0x00f00000 + +#define STATUS_CAN_ISF (1 << 11) +#define STATUS_CSTM_ISF (1 << 10) +#define STATUS_FIFO_ISF (1 << 9) +#define STATUS_HOST_ISF (1 << 8) + + +/* inputs */ +#define RESET_IN (1 << 0) +#define CLOCK_IN (1 << 1) +#define IRIGB_R_IN (1 << 5) + + +/* hostctrl register */ +#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17) +#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16) +#define HOSTCTRL_CSTM1IE_GATE (1 << 7) +#define HOSTCTRL_CSTM1IW_FLAG (1 << 6) +#define HOSTCTRL_CSTM0IE_GATE (1 << 5) +#define HOSTCTRL_CSTM0IW_FLAG (1 << 4) +#define HOSTCTRL_FIFOIE_GATE (1 << 3) +#define HOSTCTRL_FIFOIE_FLAG (1 << 2) +#define HOSTCTRL_HCINT_GATE (1 << 1) +#define HOSTCTRL_HCINT_FLAG (1 << 0) + +#define NGCC_CTRL_BASE (CFG_FPGA_BASE0 + 0x80000) +#define NGCC_CTRL_FPGARST_N (1 << 2) + +/*----------------------------------------------------------------------- + * FPGA to PPC interrupt + */ +#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */ +#define IRQ1_FPGA (32+30) /* UIC1 - custom module */ +#define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */ +#define IRQ_ETH0 (64+ 4) /* UIC2 */ +#define IRQ_ETH1 ( 27) /* UIC0 */ +#define IRQ_RTC (64+ 0) /* UIC2 */ +#define IRQ_PCIA (64+ 1) /* UIC2 */ +#define IRQ_PCIB (32+18) /* UIC1 */ +#define IRQ_PCIC (32+19) /* UIC1 */ +#define IRQ_PCID (32+20) /* UIC1 */ + +#endif /* __PMC440_H__ */ diff --git a/board/amcc/sequoia/sdram.c b/board/esd/pmc440/sdram.c similarity index 100% copy from board/amcc/sequoia/sdram.c copy to board/esd/pmc440/sdram.c diff --git a/board/amcc/sequoia/sdram.h b/board/esd/pmc440/sdram.h similarity index 100% copy from board/amcc/sequoia/sdram.h copy to board/esd/pmc440/sdram.h diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds similarity index 100% copy from board/amcc/sequoia/u-boot-nand.lds copy to board/esd/pmc440/u-boot-nand.lds diff --git a/board/amcc/sequoia/u-boot.lds b/board/esd/pmc440/u-boot.lds similarity index 100% copy from board/amcc/sequoia/u-boot.lds copy to board/esd/pmc440/u-boot.lds -- 1.5.3

5 9

[U-Boot-Users] [PATCH] Add S3C2410 MMC/SD support
by Harald Welte 28 Jan '08

28 Jan '08

This patch adds MMC/SD support to the S3C2410 SoC code in u-boot Signed-off-by: Harald Welte <laforge(a)openmoko.org> Index: u-boot/cpu/arm920t/s3c24x0/Makefile =================================================================== --- u-boot.orig/cpu/arm920t/s3c24x0/Makefile 2007-02-16 23:42:19.000000000 +0100 +++ u-boot/cpu/arm920t/s3c24x0/Makefile 2007-02-16 23:42:19.000000000 +0100 @@ -26,7 +26,7 @@ LIB = $(obj)lib$(SOC).a COBJS = i2c.o interrupts.o serial.o speed.o \ - usb_ohci.o nand_read.o nand.o cmd_s3c2410.o + usb_ohci.o nand_read.o nand.o mmc.o cmd_s3c2410.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) Index: u-boot/cpu/arm920t/s3c24x0/mmc.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot/cpu/arm920t/s3c24x0/mmc.c 2007-02-16 23:43:28.000000000 +0100 @@ -0,0 +1,504 @@ +/* + * u-boot S3C2410 MMC/SD card driver + * (C) Copyright 2006 by OpenMoko, Inc. + * Author: Harald Welte <laforge(a)openmoko.org> + * + * based on u-boot pxa MMC driver and linux/drivers/mmc/s3c2410mci.c + * (C) 2005-2005 Thomas Kleffel + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <mmc.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <s3c2410.h> +#include <part.h> + +#ifdef CONFIG_MMC + +#define CONFIG_MMC_WIDE + +//#define MMC_DEBUG + +#ifdef MMC_DEBUG +#define DEBUGP printf +#else +#define DEBUGP(x, args ...) do { } while(0) +#endif + +static S3C2410_SDI *sdi; + +extern int +fat_register_device(block_dev_desc_t *dev_desc, int part_no); + +static block_dev_desc_t mmc_dev; + +block_dev_desc_t * mmc_get_dev(int dev) +{ + return ((block_dev_desc_t *)&mmc_dev); +} + +/* + * FIXME needs to read cid and csd info to determine block size + * and other parameters + */ +static uchar mmc_buf[MMC_BLOCK_SIZE]; +static mmc_csd_t mmc_csd; +static int mmc_ready = 0; +static int wide = 0; + + +#define CMD_F_RESP 0x01 +#define CMD_F_RESP_LONG 0x02 + +static u_int32_t * +/****************************************************/ +mmc_cmd(ushort cmd, ulong arg, ushort flags) +/****************************************************/ +{ + static u_int32_t resp[5]; + ulong status; + int i; + + u_int32_t ccon, csta; + u_int32_t csta_rdy_bit = S3C2410_SDICMDSTAT_CMDSENT; + + memset(resp, 0, sizeof(resp)); + + DEBUGP("mmc_cmd CMD%d arg=0x%08x flags=%x\n", cmd, arg, flags); + + sdi->SDICSTA = 0xffffffff; + sdi->SDIDSTA = 0xffffffff; + sdi->SDIFSTA = 0xffffffff; + + sdi->SDICARG = arg; + + ccon = cmd & S3C2410_SDICMDCON_INDEX; + ccon |= S3C2410_SDICMDCON_SENDERHOST|S3C2410_SDICMDCON_CMDSTART; + + if (flags & CMD_F_RESP) { + ccon |= S3C2410_SDICMDCON_WAITRSP; + csta_rdy_bit = S3C2410_SDICMDSTAT_RSPFIN; /* 1 << 9 */ + } + + if (flags & CMD_F_RESP_LONG) + ccon |= S3C2410_SDICMDCON_LONGRSP; + + sdi->SDICCON = ccon; + + while (1) { + csta = sdi->SDICSTA; + if (csta & csta_rdy_bit) + break; + if (csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) { + printf("===============> MMC CMD Timeout\n"); + sdi->SDICSTA |= S3C2410_SDICMDSTAT_CMDTIMEOUT; + break; + } + } + + DEBUGP("final MMC CMD status 0x%x\n", csta); + + sdi->SDICSTA |= csta_rdy_bit; + + if (flags & CMD_F_RESP) { + resp[0] = sdi->SDIRSP0; + resp[1] = sdi->SDIRSP1; + resp[2] = sdi->SDIRSP2; + resp[3] = sdi->SDIRSP3; + } + + return resp; +} + +#define FIFO_FILL(host) ((host->SDIFSTA & S3C2410_SDIFSTA_COUNTMASK) >> 2) + +static int +/****************************************************/ +mmc_block_read(uchar *dst, ulong src, ulong len) +/****************************************************/ +{ + u_int32_t dcon, fifo; + u_int32_t *dst_u32 = (u_int32_t *)dst; + u_int32_t *resp; + + if (len == 0) { + return 0; + } + + DEBUGP("mmc_block_rd dst %lx src %lx len %d\n", (ulong)dst, src, len); + + /* set block len */ + resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, len, CMD_F_RESP); + sdi->SDIBSIZE = len; + + //sdi->SDIPRE = 0xff; + + /* setup data */ + dcon = (len >> 9) & S3C2410_SDIDCON_BLKNUM_MASK; + dcon |= S3C2410_SDIDCON_BLOCKMODE; + dcon |= S3C2410_SDIDCON_RXAFTERCMD|S3C2410_SDIDCON_XFER_RXSTART; + if (wide) + dcon |= S3C2410_SDIDCON_WIDEBUS; + sdi->SDIDCON = dcon; + + /* send read command */ + resp = mmc_cmd(MMC_CMD_READ_BLOCK, src, CMD_F_RESP); + + while (len > 0) { + u_int32_t sdidsta = sdi->SDIDSTA; + fifo = FIFO_FILL(sdi); + if (sdidsta & (S3C2410_SDIDSTA_FIFOFAIL| + S3C2410_SDIDSTA_CRCFAIL| + S3C2410_SDIDSTA_RXCRCFAIL| + S3C2410_SDIDSTA_DATATIMEOUT)) { + printf("mmc_block_read: err SDIDSTA=0x%08x\n", sdidsta); + return -EIO; + } + + while (fifo--) { + //DEBUGP("dst_u32 = 0x%08x\n", dst_u32); + *(dst_u32++) = sdi->SDIDAT; + if (len >= 4) + len -= 4; + else { + len = 0; + break; + } + } + } + + DEBUGP("waiting for SDIDSTA (currently 0x%08x\n", sdi->SDIDSTA); + while (!(sdi->SDIDSTA & (1 << 4))) {} + DEBUGP("done waiting for SDIDSTA (currently 0x%08x\n", sdi->SDIDSTA); + + sdi->SDIDCON = 0; + + if (!(sdi->SDIDSTA & S3C2410_SDIDSTA_XFERFINISH)) + DEBUGP("mmc_block_read; transfer not finished!\n"); + + return 0; +} + +static int +/****************************************************/ +mmc_block_write(ulong dst, uchar *src, int len) +/****************************************************/ +{ + printf("MMC block write not yet supported on S3C2410!\n"); + return -1; +} + + +int +/****************************************************/ +mmc_read(ulong src, uchar *dst, int size) +/****************************************************/ +{ + ulong end, part_start, part_end, part_len, aligned_start, aligned_end; + ulong mmc_block_size, mmc_block_address; + + if (size == 0) { + return 0; + } + + if (!mmc_ready) { + printf("Please initialize the MMC first\n"); + return -1; + } + + mmc_block_size = MMC_BLOCK_SIZE; + mmc_block_address = ~(mmc_block_size - 1); + + src -= CFG_MMC_BASE; + end = src + size; + part_start = ~mmc_block_address & src; + part_end = ~mmc_block_address & end; + aligned_start = mmc_block_address & src; + aligned_end = mmc_block_address & end; + + /* all block aligned accesses */ + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_start) { + part_len = mmc_block_size - part_start; + DEBUGP("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) { + return -1; + } + memcpy(dst, mmc_buf+part_start, part_len); + dst += part_len; + src += part_len; + } + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) { + DEBUGP("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) { + return -1; + } + } + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_end && src < end) { + DEBUGP("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { + return -1; + } + memcpy(dst, mmc_buf, part_end); + } + return 0; +} + +int +/****************************************************/ +mmc_write(uchar *src, ulong dst, int size) +/****************************************************/ +{ + ulong end, part_start, part_end, part_len, aligned_start, aligned_end; + ulong mmc_block_size, mmc_block_address; + + if (size == 0) { + return 0; + } + + if (!mmc_ready) { + printf("Please initialize the MMC first\n"); + return -1; + } + + mmc_block_size = MMC_BLOCK_SIZE; + mmc_block_address = ~(mmc_block_size - 1); + + dst -= CFG_MMC_BASE; + end = dst + size; + part_start = ~mmc_block_address & dst; + part_end = ~mmc_block_address & end; + aligned_start = mmc_block_address & dst; + aligned_end = mmc_block_address & end; + + /* all block aligned accesses */ + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_start) { + part_len = mmc_block_size - part_start; + DEBUGP("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) { + return -1; + } + memcpy(mmc_buf+part_start, src, part_len); + if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) { + return -1; + } + dst += part_len; + src += part_len; + } + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) { + DEBUGP("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) { + return -1; + } + } + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_end && dst < end) { + DEBUGP("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { + return -1; + } + memcpy(mmc_buf, src, part_end); + if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) { + return -1; + } + } + return 0; +} + +ulong +/****************************************************/ +mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst) +/****************************************************/ +{ + int mmc_block_size = MMC_BLOCK_SIZE; + ulong src = blknr * mmc_block_size + CFG_MMC_BASE; + + mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size); + return blkcnt; +} + +static u_int16_t rca = MMC_DEFAULT_RCA; + +static u_int32_t mmc_size(const struct mmc_csd *csd) +{ + u_int32_t block_len, mult, blocknr; + + block_len = csd->read_bl_len << 12; + mult = csd->c_size_mult1 << 8; + blocknr = (csd->c_size+1) * mult; + + return blocknr * block_len; +} + +int +/****************************************************/ +mmc_init(int verbose) +/****************************************************/ +{ + int retries, rc = -ENODEV; + int is_sd = 0; + u_int32_t *resp; + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + + sdi = S3C2410_GetBase_SDI(); + + DEBUGP("mmc_init(PCLK=%u)\n", get_PCLK()); + + clk_power->CLKCON |= (1 << 9); + + /* S3C2410 has some bug that prevents reliable operation at higher speed */ + //sdi->SDIPRE = 0x3e; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ + sdi->SDIPRE = 0x02; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ + sdi->SDIBSIZE = 512; + sdi->SDIDTIMER = 0xffff; + sdi->SDIIMSK = 0x0; + sdi->SDICON = S3C2410_SDICON_FIFORESET|S3C2440_SDICON_MMCCLOCK; + udelay(125000); /* FIXME: 74 SDCLK cycles */ + + mmc_csd.c_size = 0; + + /* reset */ + retries = 10; + resp = mmc_cmd(MMC_CMD_RESET, 0, 0); + + printf("trying to detect SD Card...\n"); + while (retries--) { + int i; + udelay(100000); + resp = mmc_cmd(55, 0x00000000, CMD_F_RESP); + resp = mmc_cmd(41, 0x00300000, CMD_F_RESP); + + if (resp[0] & (1 << 31)) { + is_sd = 1; + break; + } + } + + if (retries == 0 && !is_sd) { + retries = 10; + printf("failed to detect SD Card, trying MMC\n"); + resp = mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ffc000, CMD_F_RESP); + while (retries-- && resp && !(resp[4] & 0x80)) { + DEBUGP("resp %x %x\n", resp[0], resp[1]); + udelay(50); + resp = mmc_cmd(1, 0x00ffff00, CMD_F_RESP); + } + } + + /* try to get card id */ + resp = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, CMD_F_RESP|CMD_F_RESP_LONG); + if (resp) { + /* TODO configure mmc driver depending on card attributes */ + mmc_cid_t *cid = (mmc_cid_t *)resp; + if (verbose) { + printf("MMC found. Card desciption is:\n"); + printf("Manufacturer ID = %02x%02x%02x\n", + cid->id[0], cid->id[1], cid->id[2]); + printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev); + cid->hwrev = cid->fwrev = 0; /* null terminate string */ + printf("Product Name = %s\n",cid->name); + printf("Serial Number = %02x%02x%02x\n", + cid->sn[0], cid->sn[1], cid->sn[2]); + printf("Month = %d\n",cid->month); + printf("Year = %d\n",1997 + cid->year); + } + /* fill in device description */ + mmc_dev.if_type = IF_TYPE_MMC; + mmc_dev.part_type = PART_TYPE_DOS; + mmc_dev.dev = 0; + mmc_dev.lun = 0; + mmc_dev.type = 0; + /* FIXME fill in the correct size (is set to 32MByte) */ + mmc_dev.blksz = 512; + mmc_dev.lba = 0x10000; + sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", + cid->id[0], cid->id[1], cid->id[2], + cid->sn[0], cid->sn[1], cid->sn[2]); + sprintf(mmc_dev.product,"%s",cid->name); + sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); + mmc_dev.removable = 0; + mmc_dev.block_read = mmc_bread; + + /* MMC exists, get CSD too */ + resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, CMD_F_RESP); + if (is_sd) + rca = resp[0] >> 16; + + resp = mmc_cmd(MMC_CMD_SEND_CSD, rca<<16, CMD_F_RESP|CMD_F_RESP_LONG); + if (resp) { + mmc_csd_t *csd = (mmc_csd_t *)resp; + memcpy(&mmc_csd, csd, sizeof(csd)); + rc = 0; + mmc_ready = 1; + /* FIXME add verbose printout for csd */ + printf("READ_BL_LEN=%u, C_SIZE_MULT=%u, C_SIZE=%u\n", + csd->read_bl_len, csd->c_size_mult1, csd->c_size); + printf("size = %u\n", mmc_size(csd)); + } + } + + resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca<<16, CMD_F_RESP); + +#ifdef CONFIG_MMC_WIDE + if (is_sd) { + resp = mmc_cmd(55, rca<<16, CMD_F_RESP); + resp = mmc_cmd(6, 0x02, CMD_F_RESP); + wide = 1; + } +#endif + + fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ + + return rc; +} + +int +mmc_ident(block_dev_desc_t *dev) +{ + return 0; +} + +int +mmc2info(ulong addr) +{ + /* FIXME hard codes to 32 MB device */ + if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) { + return 1; + } + return 0; +} + +#endif /* CONFIG_MMC */ Index: u-boot/include/asm-arm/arch-s3c24x0/mmc.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot/include/asm-arm/arch-s3c24x0/mmc.h 2007-02-16 23:42:19.000000000 +0100 @@ -0,0 +1,112 @@ +/* + * linux/drivers/mmc/mmc_pxa.h + * + * Author: Vladimir Shebordaev, Igor Oblakov + * Copyright: MontaVista Software Inc. + * + * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __MMC_PXA_P_H__ +#define __MMC_PXA_P_H__ + +#include <asm/arch/regs-sdi.h> + +#define MMC_DEFAULT_RCA (1<<16) + +#define MMC_BLOCK_SIZE 512 +#define MMC_CMD_RESET 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RCA 3 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_BLOCK 17 +#define MMC_CMD_RD_BLK_MULTI 18 +#define MMC_CMD_WRITE_BLOCK 24 + +#define MMC_MAX_BLOCK_SIZE 512 + +#define MMC_R1_IDLE_STATE 0x01 +#define MMC_R1_ERASE_STATE 0x02 +#define MMC_R1_ILLEGAL_CMD 0x04 +#define MMC_R1_COM_CRC_ERR 0x08 +#define MMC_R1_ERASE_SEQ_ERR 0x01 +#define MMC_R1_ADDR_ERR 0x02 +#define MMC_R1_PARAM_ERR 0x04 + +#define MMC_R1B_WP_ERASE_SKIP 0x0002 +#define MMC_R1B_ERR 0x0004 +#define MMC_R1B_CC_ERR 0x0008 +#define MMC_R1B_CARD_ECC_ERR 0x0010 +#define MMC_R1B_WP_VIOLATION 0x0020 +#define MMC_R1B_ERASE_PARAM 0x0040 +#define MMC_R1B_OOR 0x0080 +#define MMC_R1B_IDLE_STATE 0x0100 +#define MMC_R1B_ERASE_RESET 0x0200 +#define MMC_R1B_ILLEGAL_CMD 0x0400 +#define MMC_R1B_COM_CRC_ERR 0x0800 +#define MMC_R1B_ERASE_SEQ_ERR 0x1000 +#define MMC_R1B_ADDR_ERR 0x2000 +#define MMC_R1B_PARAM_ERR 0x4000 + +typedef struct mmc_cid +{ +/* FIXME: BYTE_ORDER */ + uchar year:4, + month:4; + uchar sn[3]; + uchar fwrev:4, + hwrev:4; + uchar name[6]; + uchar id[3]; +} mmc_cid_t; + +typedef struct mmc_csd +{ + uchar ecc:2, + file_format:2, + tmp_write_protect:1, + perm_write_protect:1, + copy:1, + file_format_grp:1; + uint64_t content_prot_app:1, + rsvd3:4, + write_bl_partial:1, + write_bl_len:4, + r2w_factor:3, + default_ecc:2, + wp_grp_enable:1, + wp_grp_size:5, + erase_grp_mult:5, + erase_grp_size:5, + c_size_mult1:3, + vdd_w_curr_max:3, + vdd_w_curr_min:3, + vdd_r_curr_max:3, + vdd_r_curr_min:3, + c_size:12, + rsvd2:2, + dsr_imp:1, + read_blk_misalign:1, + write_blk_misalign:1, + read_bl_partial:1; + + ushort read_bl_len:4, + ccc:12; + uchar tran_speed; + uchar nsac; + uchar taac; + uchar rsvd1:2, + spec_vers:4, + csd_structure:2; +} mmc_csd_t; + + +#endif /* __MMC_PXA_P_H__ */ Index: u-boot/include/asm-arm/arch-s3c24x0/regs-sdi.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot/include/asm-arm/arch-s3c24x0/regs-sdi.h 2007-02-16 23:42:19.000000000 +0100 @@ -0,0 +1,110 @@ +/* linux/include/asm/arch-s3c2410/regs-sdi.h + * + * Copyright (c) 2004 Simtec Electronics <linux(a)simtec.co.uk> + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 MMC/SDIO register definitions + * + * Changelog: + * 18-Aug-2004 Ben Dooks Created initial file + * 29-Nov-2004 Koen Martens Added some missing defines, fixed duplicates + * 29-Nov-2004 Ben Dooks Updated Koen's patch +*/ + +#ifndef __ASM_ARM_REGS_SDI +#define __ASM_ARM_REGS_SDI "regs-sdi.h" + +#define S3C2440_SDICON_SDRESET (1<<8) +#define S3C2440_SDICON_MMCCLOCK (1<<5) +#define S3C2410_SDICON_BYTEORDER (1<<4) +#define S3C2410_SDICON_SDIOIRQ (1<<3) +#define S3C2410_SDICON_RWAITEN (1<<2) +#define S3C2410_SDICON_FIFORESET (1<<1) +#define S3C2410_SDICON_CLOCKTYPE (1<<0) + +#define S3C2410_SDICMDCON_ABORT (1<<12) +#define S3C2410_SDICMDCON_WITHDATA (1<<11) +#define S3C2410_SDICMDCON_LONGRSP (1<<10) +#define S3C2410_SDICMDCON_WAITRSP (1<<9) +#define S3C2410_SDICMDCON_CMDSTART (1<<8) +#define S3C2410_SDICMDCON_SENDERHOST (1<<6) +#define S3C2410_SDICMDCON_INDEX (0x3f) + +#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) +#define S3C2410_SDICMDSTAT_CMDSENT (1<<11) +#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) +#define S3C2410_SDICMDSTAT_RSPFIN (1<<9) +#define S3C2410_SDICMDSTAT_XFERING (1<<8) +#define S3C2410_SDICMDSTAT_INDEX (0xff) + +#define S3C2440_SDIDCON_DS_BYTE (0<<22) +#define S3C2440_SDIDCON_DS_HALFWORD (1<<22) +#define S3C2440_SDIDCON_DS_WORD (2<<22) +#define S3C2410_SDIDCON_IRQPERIOD (1<<21) +#define S3C2410_SDIDCON_TXAFTERRESP (1<<20) +#define S3C2410_SDIDCON_RXAFTERCMD (1<<19) +#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) +#define S3C2410_SDIDCON_BLOCKMODE (1<<17) +#define S3C2410_SDIDCON_WIDEBUS (1<<16) +#define S3C2410_SDIDCON_DMAEN (1<<15) +#define S3C2410_SDIDCON_STOP (1<<14) +#define S3C2440_SDIDCON_DATSTART (1<<14) +#define S3C2410_SDIDCON_DATMODE (3<<12) +#define S3C2410_SDIDCON_BLKNUM (0x7ff) + +/* constants for S3C2410_SDIDCON_DATMODE */ +#define S3C2410_SDIDCON_XFER_READY (0<<12) +#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) +#define S3C2410_SDIDCON_XFER_RXSTART (2<<12) +#define S3C2410_SDIDCON_XFER_TXSTART (3<<12) + +#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) +#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) + +#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) +#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) +#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ +#define S3C2410_SDIDSTA_CRCFAIL (1<<7) +#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) +#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) +#define S3C2410_SDIDSTA_XFERFINISH (1<<4) +#define S3C2410_SDIDSTA_BUSYFINISH (1<<3) +#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ +#define S3C2410_SDIDSTA_TXDATAON (1<<1) +#define S3C2410_SDIDSTA_RXDATAON (1<<0) + +#define S3C2440_SDIFSTA_FIFORESET (1<<16) +#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ +#define S3C2410_SDIFSTA_TFDET (1<<13) +#define S3C2410_SDIFSTA_RFDET (1<<12) +#define S3C2410_SDIFSTA_TFHALF (1<<11) +#define S3C2410_SDIFSTA_TFEMPTY (1<<10) +#define S3C2410_SDIFSTA_RFLAST (1<<9) +#define S3C2410_SDIFSTA_RFFULL (1<<8) +#define S3C2410_SDIFSTA_RFHALF (1<<7) +#define S3C2410_SDIFSTA_COUNTMASK (0x7f) + +#define S3C2410_SDIIMSK_RESPONSECRC (1<<17) +#define S3C2410_SDIIMSK_CMDSENT (1<<16) +#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) +#define S3C2410_SDIIMSK_RESPONSEND (1<<14) +#define S3C2410_SDIIMSK_READWAIT (1<<13) +#define S3C2410_SDIIMSK_SDIOIRQ (1<<12) +#define S3C2410_SDIIMSK_FIFOFAIL (1<<11) +#define S3C2410_SDIIMSK_CRCSTATUS (1<<10) +#define S3C2410_SDIIMSK_DATACRC (1<<9) +#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) +#define S3C2410_SDIIMSK_DATAFINISH (1<<7) +#define S3C2410_SDIIMSK_BUSYFINISH (1<<6) +#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ +#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) +#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) +#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) +#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) +#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) + +#endif /* __ASM_ARM_REGS_SDI */ Index: u-boot/include/s3c24x0.h =================================================================== --- u-boot.orig/include/s3c24x0.h 2007-02-16 23:42:02.000000000 +0100 +++ u-boot/include/s3c24x0.h 2007-02-16 23:42:19.000000000 +0100 @@ -637,13 +637,7 @@ S3C24X0_REG32 SDIDCNT; S3C24X0_REG32 SDIDSTA; S3C24X0_REG32 SDIFSTA; -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res[3]; - S3C24X0_REG8 SDIDAT; -#else - S3C24X0_REG8 SDIDAT; - S3C24X0_REG8 res[3]; -#endif + S3C24X0_REG32 SDIDAT; S3C24X0_REG32 SDIIMSK; } /*__attribute__((__packed__))*/ S3C2410_SDI; @@ -1123,11 +1117,7 @@ #define rSDIDatCnt (*(volatile unsigned *)0x5A000030) #define rSDIDatSta (*(volatile unsigned *)0x5A000034) #define rSDIFSTA (*(volatile unsigned *)0x5A000038) -#ifdef __BIG_ENDIAN -#define rSDIDAT (*(volatile unsigned char *)0x5A00003F) -#else -#define rSDIDAT (*(volatile unsigned char *)0x5A00003C) -#endif +#define rSDIDAT (*(volatile unsigned *)0x5A00003C) #define rSDIIntMsk (*(volatile unsigned *)0x5A000040) #endif -- - Harald Welte <laforge(a)openmoko.org> http://openmoko.org/ ============================================================================ Software for the world's first truly open Free Software mobile phone

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[U-Boot-Users] AT91SAM9260-EK: Trying to load U-Boot env from NAND
by Destrukto 25 Jan '08

25 Jan '08

Hello, this is my first post in this Forum and my English is not very good so I give my best to describe my problem. I have a AT91SAM9260 eval kit board and until now there were not very much problem. But what stops me now is a really tough problem. I use the Bootstraploader for NAND boot which is compiled by Atmel in the Demo. I've compiled the U-Boot by my self and its starts without problem, but what get on my nerves is that I can't write the U-Boot env over .tcl file. To explain that, I load everything, just like it is done in the demo, with this batch- and .tcl-file. So, I've checked the checksum for the env's but everytime I uploaded it and trying to boot I get this: U-Boot 1.1.5 (Nov 2 2006 - 10:20:33) DRAM: 64 MB NAND: NAND device: Manufacturer ID: 0xec, Chip ID: 0xda (<NULL> NAND 256MiB 3,3V 8-bit) 256 MiB DataFlash:AT45DB642 Nb pages: 8192 Page Size: 1056 Size= 8650752 bytes Logical address: 0xD0000000 Area 0: D0000000 to D0003FFF (RO) Area 1: D0004000 to D0007FFF Area 2: D0008000 to D0037FFF (RO) Area 3: D0038000 to D083FFFF *** Warning - bad CRC or NAND, using default environment In: serial Out: serial Err: serial DM9161A PHY Detected End of Autonegociation U-Boot> U-Boot> U-Boot> printenv bootdelay=3 baudrate=115200 stdin=serial stdout=serial stderr=serial Environment size: 69/131068 bytes U-Boot> I checked the env (nand read to copy them in the RAM and md to hae a look at them) and they're still correct. Well, I could write the env every by hand that would work but if you have to do this 20 times a day and you have really much to write this wouldn't be very funny. So I hope I haven't forget anything, but if there is any question I will try to answer. Greets, Destrukto -- View this message in context: http://www.nabble.com/AT91SAM9260-EK%3A-Trying-to-load-U-Boot-env-from-NAND… Sent from the Uboot - Users mailing list archive at Nabble.com.

4 11

[U-Boot-Users] [patch 0/3] KB9202 CodeSourcery ARM EABI toolchain build fixes
by Johannes Stezenbach 24 Jan '08

24 Jan '08

Hi, I'm pretty new to u-boot and ARM stuff, so please review carefully. I wanted to build u-boot-1.3.0-rc3 for the KwikByte KB9202 board with the current ARM toolchain from CodeSourcery. I needed the following three patches to get it to build. The first one is probably a bugfix needed for other toolchains, too. The other two patches are specific to the CodeSourcery toolchain (or probably to any EABI toolchain with gcc-4.2.x). I haven't checked if they break the build for other ARM toolchains, so it's probably better to not apply them unless someone else confirms they're OK. Regards, Johannes

3 12

[U-Boot-Users] Target support for qemu -M mips
by Vlad Lungu 17 Jan '08

17 Jan '08

With serial, NE2000, IDE support. Tested in big-endian mode. Memory size hard-coded to 128M for now, so don't play with the -m option. Signed-off-by: Vlad Lungu <vlad(a)comsys.ro> --- MAKEALL | 1 + Makefile | 6 ++ board/qemu-mips/Makefile | 45 +++++++++++ board/qemu-mips/README | 11 +++ board/qemu-mips/config.mk | 11 +++ board/qemu-mips/flash.c | 43 ++++++++++ board/qemu-mips/lowlevel_init.S | 41 ++++++++++ board/qemu-mips/qemu-mips.c | 89 +++++++++++++++++++++ board/qemu-mips/u-boot.lds | 70 +++++++++++++++++ include/configs/qemu-mips.h | 164 +++++++++++++++++++++++++++++++++++++++ 10 files changed, 481 insertions(+), 0 deletions(-) create mode 100644 board/qemu-mips/Makefile create mode 100644 board/qemu-mips/README create mode 100644 board/qemu-mips/config.mk create mode 100644 board/qemu-mips/flash.c create mode 100644 board/qemu-mips/lowlevel_init.S create mode 100644 board/qemu-mips/qemu-mips.c create mode 100644 board/qemu-mips/u-boot.lds create mode 100644 include/configs/qemu-mips.h diff --git a/MAKEALL b/MAKEALL index a02412b..7647d67 100755 --- a/MAKEALL +++ b/MAKEALL @@ -524,6 +524,7 @@ LIST_arm=" \ LIST_mips4kc=" \ incaip \ + qemu_mips \ " LIST_mips5kc=" \ diff --git a/Makefile b/Makefile index 1ff80b5..3e1b074 100644 --- a/Makefile +++ b/Makefile @@ -2514,6 +2514,12 @@ pb1000_config : unconfig @echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h @$(MKCONFIG) -a pb1x00 mips mips pb1x00 +qemu_mips_config : unconfig + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @echo "#define CONFIG_QEMU_MIPS 1" >>$(obj)include/config.h + @$(MKCONFIG) -a qemu-mips mips mips qemu-mips + ######################################################################### ## MIPS64 5Kc ######################################################################### diff --git a/board/qemu-mips/Makefile b/board/qemu-mips/Makefile new file mode 100644 index 0000000..23be447 --- /dev/null +++ b/board/qemu-mips/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/qemu-mips/README b/board/qemu-mips/README new file mode 100644 index 0000000..39570b1 --- /dev/null +++ b/board/qemu-mips/README @@ -0,0 +1,11 @@ +By Vlad Lungu vlad(a)comsys.ro 2007-Oct-01 +---------------------------------------- +Qemu is a full system emulator. See + +http://fabrice.bellard.free.fr/qemu + +Limitations & comments +---------------------- +Supports the "-m mips" configuration of qemu: serial,NE2000,IDE. +Support is big endian only for now (or at least this is what I tested). +Derived from au1x00 with a lot of things cut out. diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk new file mode 100644 index 0000000..61269ce --- /dev/null +++ b/board/qemu-mips/config.mk @@ -0,0 +1,11 @@ + +# +# Qemu -M mips system emulator +# See http://fabrice.bellard.free.fr/qemu +# + +# ROM version +TEXT_BASE = 0xbfc00000 + +# RAM version +#TEXT_BASE = 0x80001000 diff --git a/board/qemu-mips/flash.c b/board/qemu-mips/flash.c new file mode 100644 index 0000000..49f0134 --- /dev/null +++ b/board/qemu-mips/flash.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if 0 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +#endif +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + printf ("Skipping flash_init\n"); + return (0); +} + +int write_buff ( void * info, uchar * src, ulong addr, ulong cnt) +{ + printf ("write_buff not implemented\n"); + return (-1); +} diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S new file mode 100644 index 0000000..28166bc --- /dev/null +++ b/board/qemu-mips/lowlevel_init.S @@ -0,0 +1,41 @@ +/* Memory sub-system initialization code */ + +#include <config.h> +#include <version.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> + + .text + .set noreorder + .set mips32 + + .globl lowlevel_init +lowlevel_init: + + /* + * Step 2) Establish Status Register + * (set BEV, clear ERL, clear EXL, clear IE) + */ + li t1, 0x00400000 + mtc0 t1, CP0_STATUS + + /* + * Step 3) Establish CP0 Config0 + * (set K0=3) + */ + li t1, 0x00000003 + mtc0 t1, CP0_CONFIG + + /* + * Step 7) Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + + j ra + nop diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c new file mode 100644 index 0000000..345bb95 --- /dev/null +++ b/board/qemu-mips/qemu-mips.c @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2007 + * Vlad Lungu vlad(a)comsys.ro + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/mipsregs.h> +#include <asm/io.h> + +long int initdram(int board_type) +{ + /* Sdram is setup by assembler code */ + /* If memory could be changed, we should return the true value here */ + return MEM_SIZE*1024*1024; +} + + +int checkboard (void) +{ + u32 proc_id; + u32 config1; + + proc_id = read_32bit_cp0_register(CP0_PRID); + printf("Board: Qemu -M mips CPU: "); + switch (proc_id) { + case 0x00018000: + printf("4Kc"); + break; + case 0x00018400: + printf("4KEcR1"); + break; + case 0x00019000: + printf("4KEc"); + break; + case 0x00019300: + config1 = read_mips32_cp0_config1(); + if (config1&1) + printf("24Kf"); + else + printf("24Kc"); + break; + case 0x00019500: + printf("34Kf"); + break; + case 0x00000400: + printf("R4000"); + break; + case 0x00018100: + config1 = read_mips32_cp0_config1(); + if (config1&1) + printf("5Kf"); + else + printf("5Kc"); + break; + case 0x000182a0: + printf("20Kc"); + break; + + default: + printf("unknown"); + } + printf (" proc_id=0x%x\n", proc_id); + + return 0; +} + +int misc_init_r(void){ +set_io_port_base(0); +return 0; +} diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds new file mode 100644 index 0000000..8793320 --- /dev/null +++ b/board/qemu-mips/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, <wd(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(16); + _gp = .; + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h new file mode 100644 index 0000000..1f93ad7 --- /dev/null +++ b/include/configs/qemu-mips.h @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for the dbau1x00 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_QEMU_MIPS 1 +#define CONFIG_MISC_INIT_R + +#undef DEBUG + +/*IP address is default used by Qemu*/ +#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */ +#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address*/ + +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ + +#define CONFIG_BAUDRATE 115200 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "panic=1\0" \ + "bootfile=/tftpboot/vmlinux\0" \ + "load=tftp 80500000 ${u-boot}\0" \ + "" + +#define CONFIG_BOOTCOMMAND "bootp;bootelf" + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_DHCP + +#define CONFIG_DRIVER_NE2000 +#define CONFIG_DRIVER_NE2000_BASE (0xb4000300) + +#define CFG_NO_FLASH +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 115200 +#define CFG_NS16550_COM1 (0xb40003f8) +#define CONFIG_CONS_INDEX 1 + +#define CONFIG_CMD_IDE +#define CONFIG_DOS_PARTITION + +#define CFG_IDE_MAXBUS 2 +#define CFG_ATA_IDE0_OFFSET (0x1f0) +#define CFG_ATA_IDE1_OFFSET (0x170) +#define CFG_ATA_DATA_OFFSET (0) +#define CFG_ATA_REG_OFFSET (0) +#define CFG_ATA_BASE_ADDR (0xb4000000) + +#define CFG_IDE_MAXDEVICE (4) + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ + +#define CFG_PROMPT "qemu-mips # " /* Monitor Command Prompt */ + +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ + +#define CFG_MALLOC_LEN 128*1024 + +#define CFG_BOOTPARAMS_LEN 128*1024 + +#define CFG_MHZ 132 + +#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ + +#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ + +#define CFG_LOAD_ADDR 0x81000000 /* default load address */ + +#define CFG_MEMTEST_START 0x80100000 +#define CFG_MEMTEST_END 0x80800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* The following #defines are needed to get flash environment right */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +#define CFG_INIT_SP_OFFSET 0x400000 + +/* We boot from this flash, selected with dip switch */ +#define CFG_FLASH_BASE 0xbfc00000 + +#define CFG_ENV_IS_NOWHERE 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_SIZE 0x10000 +#undef CONFIG_NET_MULTI + +#define MEM_SIZE 128 + +#undef CONFIG_MEMSIZE_IN_BYTES + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_ICACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */ -- 1.5.2.2

4 14

[U-Boot-Users] [PATCH] Add support for MS7720RP02 board
by Yoshihiro Shimoda 14 Jan '08

14 Jan '08

Add support for MS7720RP02 board. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- Makefile | 8 board/ms7720se/Makefile | 51 +++++ board/ms7720se/config.mk | 35 ++++ board/ms7720se/lowlevel_init.S | 269 +++++++++++++++++++++++++++++++ board/ms7720se/ms7720se.c | 61 +++++++ board/ms7720se/u-boot.lds | 109 ++++++++++++ include/configs/ms7720se.h | 134 +++++++++++++++ 7 files changed, 667 insertions(+) diff -uprN a/board/ms7720se/config.mk b/board/ms7720se/config.mk --- a/board/ms7720se/config.mk 1970-01-01 09:00:00.000000000 +0900 +++ b/board/ms7720se/config.mk 2007-12-03 19:56:13.000000000 +0900 @@ -0,0 +1,35 @@ +# +# Copyright (C) 2007 +# Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# board/ms7722se/config.mk +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x8FFC0000 + diff -uprN a/board/ms7720se/lowlevel_init.S b/board/ms7720se/lowlevel_init.S --- a/board/ms7720se/lowlevel_init.S 1970-01-01 09:00:00.000000000 +0900 +++ b/board/ms7720se/lowlevel_init.S 2007-11-28 10:47:05.000000000 +0900 @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2007 + * Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + mov.l WTCSR_A,r1 + mov.l WTCSR_D,r0 + mov.w r0,@r1 + + mov.l WTCNT_A,r1 + mov.l WTCNT_D,r0 + mov.w r0,@r1 + + mov.l FRQCR_A,r1 + mov.l FRQCR_D,r0 + mov.w r0,@r1 + + mov.l UCLKCR_A,r1 + mov.l UCLKCR_D,r0 + mov.w r0,@r1 + + mov.l CMNCR_A, r1 + mov.l CMNCR_D, r0 + mov.l r0, @r1 + + mov.l CS0BCR_A, r1 + mov.l CS0BCR_D, r0 + mov.l r0, @r1 + + mov.l CS2BCR_A, r1 + mov.l CS2BCR_D, r0 + mov.l r0, @r1 + + mov.l CS3BCR_A, r1 + mov.l CS3BCR_D, r0 + mov.l r0, @r1 + + mov.l CS4BCR_A, r1 + mov.l CS4BCR_D, r0 + mov.l r0, @r1 + + mov.l CS5ABCR_A, r1 + mov.l CS5ABCR_D, r0 + mov.l r0, @r1 + + mov.l CS5BBCR_A, r1 + mov.l CS5BBCR_D, r0 + mov.l r0, @r1 + + mov.l CS6ABCR_A, r1 + mov.l CS6ABCR_D, r0 + mov.l r0, @r1 + + mov.l CS6BBCR_A, r1 + mov.l CS6BBCR_D, r0 + mov.l r0, @r1 + + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 + mov.l r0, @r1 + + mov.l CS2WCR_A, r1 + mov.l CS2WCR_D, r0 + mov.l r0, @r1 + + mov.l CS3WCR_A, r1 + mov.l CS3WCR_D, r0 + mov.l r0, @r1 + + mov.l CS4WCR_A, r1 + mov.l CS4WCR_D, r0 + mov.l r0, @r1 + + mov.l CS5AWCR_A, r1 + mov.l CS5AWCR_D, r0 + mov.l r0, @r1 + + mov.l CS5BWCR_A, r1 + mov.l CS5BWCR_D, r0 + mov.l r0, @r1 + + mov.l CS6AWCR_A, r1 + mov.l CS6AWCR_D, r0 + mov.l r0, @r1 + + mov.l CS6BWCR_A, r1 + mov.l CS6BWCR_D, r0 + mov.l r0, @r1 + + mov.l SDCR_A, r1 + mov.l SDCR_D1, r0 + mov.l r0, @r1 + + mov.l RTCSR_A, r1 + mov.l RTCSR_D, r0 + mov.l r0, @r1 + + mov.l RTCNT_A, r1 + mov.l RTCNT_D, r0 + mov.l r0, @r1 + + mov.l RTCOR_A, r1 + mov.l RTCOR_D, r0 + mov.l r0, @r1 + + mov.l SDCR_A, r1 + mov.l SDCR_D2, r0 + mov.l r0, @r1 + + mov.l SDMR3_A, r1 + mov.l SDMR3_D, r0 + mov.w r0, @r1 + + mov.l PCCR_A, r1 + mov.l PCCR_D, r0 + mov.w r0, @r1 + + mov.l PDCR_A, r1 + mov.l PDCR_D, r0 + mov.w r0, @r1 + + mov.l PECR_A, r1 + mov.l PECR_D, r0 + mov.w r0, @r1 + + mov.l PGCR_A, r1 + mov.l PGCR_D, r0 + mov.w r0, @r1 + + mov.l PHCR_A, r1 + mov.l PHCR_D, r0 + mov.w r0, @r1 + + mov.l PPCR_A, r1 + mov.l PPCR_D, r0 + mov.w r0, @r1 + + mov.l PTCR_A, r1 + mov.l PTCR_D, r0 + mov.w r0, @r1 + + mov.l PVCR_A, r1 + mov.l PVCR_D, r0 + mov.w r0, @r1 + + mov.l PSELA_A, r1 + mov.l PSELA_D, r0 + mov.w r0, @r1 + + mov.l CCR_A, r1 + mov.l CCR_D, r0 + mov.l r0, @r1 + + mov.l LED_A, r1 + mov.l LED_D, r0 + mov.b r0, @r1 + + rts + nop + + .align 4 + +FRQCR_A: .long 0xA415FF80 /* FRQCR Address */ +WTCNT_A: .long 0xA415FF84 +WTCSR_A: .long 0xA415FF86 +UCLKCR_A: .long 0xA40A0008 +FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .long 0x5A00 +WTCSR_D: .long 0xA506 +UCLKCR_D: .long 0xA5C0 + +#define BSC_BASE 0xA4FD0000 +CMNCR_A: .long BSC_BASE +CS0BCR_A: .long BSC_BASE + 0x04 +CS2BCR_A: .long BSC_BASE + 0x08 +CS3BCR_A: .long BSC_BASE + 0x0C +CS4BCR_A: .long BSC_BASE + 0x10 +CS5ABCR_A: .long BSC_BASE + 0x14 +CS5BBCR_A: .long BSC_BASE + 0x18 +CS6ABCR_A: .long BSC_BASE + 0x1C +CS6BBCR_A: .long BSC_BASE + 0x20 +CS0WCR_A: .long BSC_BASE + 0x24 +CS2WCR_A: .long BSC_BASE + 0x28 +CS3WCR_A: .long BSC_BASE + 0x2C +CS4WCR_A: .long BSC_BASE + 0x30 +CS5AWCR_A: .long BSC_BASE + 0x34 +CS5BWCR_A: .long BSC_BASE + 0x38 +CS6AWCR_A: .long BSC_BASE + 0x3C +CS6BWCR_A: .long BSC_BASE + 0x40 +SDCR_A: .long BSC_BASE + 0x44 +RTCSR_A: .long BSC_BASE + 0x48 +RTCNT_A: .long BSC_BASE + 0x4C +RTCOR_A: .long BSC_BASE + 0x50 +SDMR3_A: .long BSC_BASE + 0x58C0 + +CMNCR_D: .long 0x00000010 +CS0BCR_D: .long 0x36DB0400 +CS2BCR_D: .long 0x36DB0400 +CS3BCR_D: .long 0x36DB4600 +CS4BCR_D: .long 0x36DB0400 +CS5ABCR_D: .long 0x36DB0400 +CS5BBCR_D: .long 0x36DB0200 +CS6ABCR_D: .long 0x36DB0400 +CS6BBCR_D: .long 0x36DB0400 +CS0WCR_D: .long 0x00000B01 +CS2WCR_D: .long 0x00000500 +CS3WCR_D: .long 0x00006D1B +CS4WCR_D: .long 0x00000500 +CS5AWCR_D: .long 0x00000500 +CS5BWCR_D: .long 0x00000500 +CS6AWCR_D: .long 0x00000500 +CS6BWCR_D: .long 0x00000500 +SDCR_D1: .long 0x00000011 +RTCSR_D: .long 0xA55A0010 +RTCNT_D: .long 0xA55A001F +RTCOR_D: .long 0xA55A001F +SDMR3_D: .long 0x0000 +SDCR_D2: .long 0x00000811 + +#define PFC_BASE 0xA4050100 +PCCR_A: .long PFC_BASE + 0x04 +PDCR_A: .long PFC_BASE + 0x06 +PECR_A: .long PFC_BASE + 0x08 +PGCR_A: .long PFC_BASE + 0x0C +PHCR_A: .long PFC_BASE + 0x0E +PPCR_A: .long PFC_BASE + 0x18 +PTCR_A: .long PFC_BASE + 0x1E +PVCR_A: .long PFC_BASE + 0x22 +PSELA_A: .long PFC_BASE + 0x24 + +PCCR_D: .long 0x0000 +PDCR_D: .long 0x0000 +PECR_D: .long 0x0000 +PGCR_D: .long 0x0000 +PHCR_D: .long 0x0000 +PPCR_D: .long 0x00AA +PTCR_D: .long 0x0280 +PVCR_D: .long 0x0000 +PSELA_D: .long 0x0000 + +CCR_A: .long 0xFFFFFFEC +!CCR_D: .long 0x0000000D +CCR_D: .long 0x0000000B + +LED_A: .long 0xB6800000 +LED_D: .long 0xFF + diff -uprN a/board/ms7720se/Makefile b/board/ms7720se/Makefile --- a/board/ms7720se/Makefile 1970-01-01 09:00:00.000000000 +0900 +++ b/board/ms7720se/Makefile 2007-12-03 18:50:49.000000000 +0900 @@ -0,0 +1,51 @@ +# +# Copyright (C) 2007 +# Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# board/ms7720se/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := ms7720se.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff -uprN a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c --- a/board/ms7720se/ms7720se.c 1970-01-01 09:00:00.000000000 +0900 +++ b/board/ms7720se/ms7720se.c 2007-12-03 22:17:35.000000000 +0900 @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2007 + * Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> + * + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> + * + * Copyright (C) 2007 + * Kenati Technologies, Inc. + * + * board/ms7720se/ms7720se.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> + +#define LED_BASE 0xB0800000 + +int checkboard(void) +{ + puts("BOARD: Hitachi UL MS7720SE\n"); + return 0; +} + +int board_init(void) +{ + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ + outw(value & 0xFF, LED_BASE); +} + diff -uprN a/board/ms7720se/u-boot.lds b/board/ms7720se/u-boot.lds --- a/board/ms7720se/u-boot.lds 1970-01-01 09:00:00.000000000 +0900 +++ b/board/ms7720se/u-boot.lds 2007-12-03 18:52:03.000000000 +0900 @@ -0,0 +1,109 @@ +/* + * Copyrigth (c) 2007 + * Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> + * + * Copyrigth (c) 2007 + * Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x8C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh3/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} + diff -uprN a/include/configs/ms7720se.h b/include/configs/ms7720se.h --- a/include/configs/ms7720se.h 1970-01-01 09:00:00.000000000 +0900 +++ b/include/configs/ms7720se.h 2007-12-03 22:56:12.000000000 +0900 @@ -0,0 +1,134 @@ +/* + * Configuation settings for the Hitachi Solution Engine 7720 + * + * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MS7720SE_H +#define __MS7720SE_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH3 1 +#define CONFIG_CPU_SH7720 1 +#define CONFIG_MS7720SE 1 + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_ENV +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_PCMCIA +#define CONFIG_CMD_IDE +#define CONFIG_CMD_EXT2 + +#define CFG_CMD_PCMCIA 0x01 +#define CFG_CMD_IDE 0x02 + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_IDE|CFG_CMD_PCMCIA) & \ + ~(CFG_CMD_FPGA)) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS "console=ttySC0,115200" +#define CONFIG_BOOTFILE /boot/zImage +#define CONFIG_LOADADDR 0x8E000000 + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* MEMORY */ +#define MS7720SE_SDRAM_BASE 0x8C000000 +#define MS7720SE_FLASH_BASE_1 0xA0000000 +#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ +#define CFG_PBSIZE 256 /* Buffer size for Console output */ +#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ +/* Buffer size for Boot Arguments passed to kernel */ +#define CFG_BARGSIZE 512 +/* List of legal baudrate settings for this board */ +#define CFG_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF0 1 + +#define CFG_MEMTEST_START MS7720SE_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) + +#define CFG_SDRAM_BASE MS7720SE_SDRAM_BASE +#define CFG_SDRAM_SIZE (64 * 1024 * 1024) + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) +#define CFG_MONITOR_BASE MS7720SE_FLASH_BASE_1 +#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_GBL_DATA_SIZE 256 +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + + +/* FLASH */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_BASE MS7720SE_FLASH_BASE_1 + +#define CFG_MAX_FLASH_SECT 150 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE (64 * 1024) +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_FLASH_ERASE_TOUT 120000 +#define CFG_FLASH_WRITE_TOUT 500 + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 33333333 +#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */ +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +/* PCMCIA */ +#define CONFIG_IDE_PCMCIA 1 +#define CONFIG_MARUBUN_PCCARD 1 +#define CONFIG_PCMCIA_SLOT_A 1 +#define CFG_IDE_MAXDEVICE 1 +#define CFG_MARUBUN_MRSHPC 0xb83fffe0 +#define CFG_MARUBUN_MW1 0xb8400000 +#define CFG_MARUBUN_MW2 0xb8500000 +#define CFG_MARUBUN_IO 0xb8600000 + +#define CFG_PIO_MODE 1 +#define CFG_IDE_MAXBUS 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_ATA_BASE_ADDR CFG_MARUBUN_IO /* base address */ +#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ +#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ + +#endif /* __MS7720SE_H */ --- a/Makefile 2007-11-14 21:06:32.000000000 +0900 +++ b/Makefile 2007-11-14 18:06:12.000000000 +0900 @@ -2596,6 +2596,14 @@ atstk1002_config : unconfig ######################################################################### ######################################################################### +## sh3 (Renesas SuperH) +######################################################################### +ms7720se_config: unconfig + @ >include/config.h + @echo "#define CONFIG_MS7720SE 1" >> include/config.h + @./mkconfig -a $(@:_config=) sh sh3 ms7720se + +######################################################################### ## sh4 (Renesas SuperH) ######################################################################### ms7750se_config: unconfig

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[U-Boot-Users] [PATCH] serial_sh: Add support for SH7720
by Yoshihiro Shimoda 14 Jan '08

14 Jan '08

Add support for SH7720 in serial_sh driver. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/serial_sh.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) --- a/drivers/serial_sh.c 2007-11-14 21:06:34.000000000 +0900 +++ b/drivers/serial_sh.c 2007-12-03 22:27:15.000000000 +0900 @@ -30,6 +30,17 @@ #error "Default SCIF doesn't set....." #endif +#if defined(CONFIG_SH3) +/* There are SH7720's register */ +#define SCSMR (volatile unsigned short *)(SCIF_BASE + 0x0) +#define SCBRR (volatile unsigned char *)(SCIF_BASE + 0x4) +#define SCSCR (volatile unsigned short *)(SCIF_BASE + 0x8) +#define SCFSR (volatile unsigned short *)(SCIF_BASE + 0x14) /* SCSSR */ +#define SCFCR (volatile unsigned short *)(SCIF_BASE + 0x18) +#define SCFDR (volatile unsigned short *)(SCIF_BASE + 0x1C) +#define SCFTDR (volatile unsigned char *)(SCIF_BASE + 0x20) +#define SCFRDR (volatile unsigned char *)(SCIF_BASE + 0x24) +#else #define SCSMR (volatile unsigned short *)(SCIF_BASE + 0x0) #define SCBRR (volatile unsigned char *)(SCIF_BASE + 0x4) #define SCSCR (volatile unsigned short *)(SCIF_BASE + 0x8) @@ -38,16 +49,21 @@ #define SCFRDR (volatile unsigned char *)(SCIF_BASE + 0x14) #define SCFCR (volatile unsigned short *)(SCIF_BASE + 0x18) #define SCFDR (volatile unsigned short *)(SCIF_BASE + 0x1C) +#endif + #if defined(CONFIG_SH4A) #define SCRFDR (volatile unsigned short *)(SCIF_BASE + 0x20) #define SCSPTR (volatile unsigned short *)(SCIF_BASE + 0x24) #define SCLSR (volatile unsigned short *)(SCIF_BASE + 0x28) #define SCRER (volatile unsigned short *)(SCIF_BASE + 0x2C) +#define LSR_ORER 1 #elif defined (CONFIG_SH4) #define SCSPTR (volatile unsigned short *)(SCIF_BASE + 0x20) #define SCLSR (volatile unsigned short *)(SCIF_BASE + 0x24) +#define LSR_ORER 1 #elif defined (CONFIG_SH3) -#define SCLSR (volatile unsigned short *)(SCIF_BASE + 0x24) +#define SCLSR SCFSR /* SCSSR */ +#define LSR_ORER 0x0200 #endif #define SCR_RE (1 << 4) @@ -67,10 +83,17 @@ void serial_setbrg (void) { DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_CPU_SH7720) + int divisor = gd->baudrate * 16; + + *SCBRR = (CONFIG_SYS_CLK_FREQ * 2 + (divisor / 2)) / + (gd->baudrate * 32) - 1; +#else int divisor = gd->baudrate * 32; *SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) / (gd->baudrate * 32) - 1; +#endif } int serial_init (void) @@ -133,7 +156,6 @@ int serial_tstc (void) #define FSR_ERR_CLEAR 0x0063 #define RDRF_CLEAR 0x00fc -#define LSR_ORER 1 void handle_error( void ){ (void)*SCFSR ;

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