December 2007 - U-Boot

[U-Boot-Users] [PATCH 2/2] mpc85xx: Add support for SBC8548
by Joe Hamman 13 Dec '07

13 Dec '07

Add support for Wind River's SBC8548 reference board. Signed-off by: Joe Hamman <joe.hamman(a)embeddedspecialties.com> diff --git a/board/sbc8548/u-boot.lds b/board/sbc8548/u-boot.lds new file mode 100644 index 0000000..4cd177e --- /dev/null +++ b/board/sbc8548/u-boot.lds @@ -0,0 +1,149 @@ +/* + * Copyright 2004, 2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/sbc8548/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/sbc8548/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + drivers/net/tsec.o (.text) + cpu/mpc85xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/doc/README.sbc8548 @@ -0,0 +1,27 @@ +Wind River SBC8548 reference board +=========================== + +Copyright 2007, Embedded Specialties, Inc. +Copyright 2007 Wind River Systemes, Inc. +----------------------------- + +1. Building U-Boot +------------------ +The SBC8548 code is known to build using ELDK 4.1. + + $ make sbc8548_config + Configuring for sbc8548 board... + + $ make + + +2. Switch and Jumper Settings +----------------------------- +All Jumpers & Switches are in their default positions. Please refer to +the board documentation for details. Some settings control CPU voltages +and settings may change with board revisions. + +3. Known limitations +-------------------- +PCI: + The code to support PCI is currently disabled and has not been verified. diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h new file mode 100644 index 0000000..51c66d0 --- /dev/null +++ b/include/configs/sbc8548.h @@ -0,0 +1,663 @@ +/* + * Copyright 2007 Wind River Systems <www.windriver.com> + * Copyright 2007 Embedded Specialties, Inc. + * Copyright 2004, 2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * sbc8548 board configuration file + * + * Please refer to doc/README.sbc85xx for more info. + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 /* MPC8548 specific */ +#define CONFIG_SBC8548 1 /* SBC8548 board specific */ + +#undef CONFIG_PCI /* enable any pci type devices */ +#undef CONFIG_PCI1 /* PCI controller 1 */ +#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#undef CONFIG_RIO +#undef CONFIG_PCI2 +#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ + + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM + #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * FLASH on the Local Bus + * Two banks, one 8MB the other 64MB, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff80_0000 + * Alternate BR6/OR6 bank at 0xfb80_0000 + * + * BR0: + * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 + * Port Size = 8 bits = BRx[19:20] = 01 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 + * + * BR6: + * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 + * Port Size = 32 bits = BRx[19:20] = 11 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 + * + * OR0: + * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 + * XAM = OR0[17:18] = 11 + * CSNT = OR0[20] = 1 + * ACS = half cycle delay = OR0[21:22] = 11 + * SCY = 6 = OR0[24:27] = 0110 + * TRLX = use relaxed timing = OR0[29] = 1 + * EAD = use external address latch delay = OR0[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 + * + * OR6: + * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 + * XAM = OR6[17:18] = 11 + * CSNT = OR6[20] = 1 + * ACS = half cycle delay = OR6[21:22] = 11 + * SCY = 6 = OR6[24:27] = 0110 + * TRLX = use relaxed timing = OR6[29] = 1 + * EAD = use external address latch delay = OR6[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6 + */ + +#define CFG_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ +#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ + +#define CFG_BR0_PRELIM 0xff800801 +#define CFG_BR6_PRELIM 0xfb801801 + +#define CFG_OR0_PRELIM 0xff806e65 +#define CFG_OR6_PRELIM 0xfc006e65 + +#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +/* CS5 = Local bus peripherals controlled by the EPLD */ + +#define CFG_BR5_PRELIM 0xf8000801 +#define CFG_OR5_PRELIM 0xff006e65 +#define CFG_EPLD_BASE 0xf8000000 +#define CFG_LED_DISP_BASE 0xf8000000 +#define CFG_USER_SWITCHES_BASE 0xf8100000 +#define CFG_BD_REV 0xf8300000 +#define CFG_EEPROM_BASE 0xf8b00000 + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * Base Register 3 and Option Register 3 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR3, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + */ + +#define CFG_BR3_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR3, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CFG_OR3_PRELIM 0xfc006cc0 + +#define CFG_LBC_LCRR 0x00000002 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 400000000 /* get_bus_freq(0) */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x3000 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ + +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#ifdef CONFIG_PCI2 +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2800000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#endif + +#ifdef CONFIG_PCIE1 +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe3000000 +#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif + +#ifdef CONFIG_RIO +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xC0000000 +#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif + +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC2" +#define CONFIG_TSEC4 +#define CONFIG_TSEC4_NAME "eTSEC3" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 02:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD +#endif + +#define CONFIG_IPADDR 192.168.0.55 + +#define CONFIG_HOSTNAME sbc8548 +#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx +#define CONFIG_BOOTFILE /uImage +#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ + +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#if defined(CONFIG_PCIE1) +#define PCIE_ENV \ + "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ + "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ + "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ + "pci d $b.0 130 1\0" \ + "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \ + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\ + "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ + "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ + "pcie1regs=setenv a e000a; run pciereg\0" \ + "pcie1cfg=setenv b 3; run pciecfg\0" \ + "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ + "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" +#else +#define PCIE_ENV "" +#endif + +#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) +#define PCI_ENV \ + "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ + "echo e;md ${a}e00 9\0" \ + "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1\0" \ + "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" +#else +#define PCI_ENV "" +#endif + +#if defined(CONFIG_PCI1) +#define PCI_ENV1 \ + "pci1regs=setenv a e0008; run pcireg\0" \ + "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \ + "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0" +#else +#define PCI_ENV1 "" +#endif + +#if defined(CONFIG_PCI2) +#define PCI_ENV2 \ + "pci2regs=setenv a e0009; run pcireg\0" \ + "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \ + "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0" +#else +#define PCI_ENV2 "" +#endif + +#if defined(CONFIG_TSEC_ENET) +#define ENET_ENV \ + "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ + "md ${a}098 2\0" \ + "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ + "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ + "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ + "echo mib;md ${a}680 31\0" \ + "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ + "enet1regs=setenv a e0024; run enetreg\0" \ + "enet2regs=setenv a e0025; run enetreg\0" \ + "enet3regs=setenv a e0026; run enetreg\0" \ + "enet4regs=setenv a e0027; run enetreg\0" +#else +#define ENET_ENV "" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=uRamdisk\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=sbc8548.dtb\0" \ + "eoi=mw e00400b0 0\0" \ + "iack=md e00400a0 1\0" \ + "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ + "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ + "ddrregs=setenv a e0002; run ddrreg\0" \ + "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ + "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ + "guregs=setenv a e00e0; run gureg\0" \ + "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ + "ecmregs=setenv a e0001; run ecmreg\0" \ + "lawregs=md e0000c08 4b\0" \ + "lbcregs=md e0005000 36\0" \ + "dma0regs=md e0021100 12\0" \ + "dma1regs=md e0021180 12\0" \ + "dma2regs=md e0021200 12\0" \ + "dma3regs=md e0021280 12\0" \ + PCIE_ENV \ + PCI_ENV \ + PCI_ENV1 \ + PCI_ENV2 \ + ENET_ENV + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */

2 2

[U-Boot-Users] [PATCH 1/2] mpc85xx: Add support for SBC8548
by Joe Hamman 13 Dec '07

13 Dec '07

Add support for Wind River's SBC8548 reference board. Signed-off by: Joe Hamman <joe.hamman(a)embeddedspecialties.com> diff --git a/MAINTAINERS b/MAINTAINERS index b8c1fdc..ac11985 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -190,6 +190,7 @@ Howard Gray <mvsensor(a)matrix-vision.de> Joe Hamman <joe.hamman(a)embeddedspecialties.com> + sbc8548 MPC8548 sbc8641d MPC8641D Klaus Heydeck <heydeck(a)kieback-peter.de> diff --git a/Makefile b/Makefile index bde38ca..75841c0 100644 --- a/Makefile +++ b/Makefile @@ -1992,6 +1992,9 @@ sbc8540_66_config: unconfig fi @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 +sbc8548_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548 + sbc8560_config \ sbc8560_33_config \ sbc8560_66_config: unconfig diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile new file mode 100644 index 0000000..1596525 --- /dev/null +++ b/board/sbc8548/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2004-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. +# Added support for Wind River SBC8560 board +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sbc8548/config.mk b/board/sbc8548/config.mk new file mode 100644 index 0000000..c9fa3ad --- /dev/null +++ b/board/sbc8548/config.mk @@ -0,0 +1,32 @@ +# +# Copyright 2004, 2007 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# sbc8548 board +# +ifndef TEXT_BASE +TEXT_BASE = 0xfff80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 diff --git a/board/sbc8548/init.S b/board/sbc8548/init.S new file mode 100644 index 0000000..716057e --- /dev/null +++ b/board/sbc8548/init.S @@ -0,0 +1,247 @@ +/* + * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> + * Copyright 2007 Embedded Specialties, Inc. + * + * Copyright 2004 Freescale Semiconductor. + * Copyright 2002,2003, Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <config.h> +#include <mpc85xx.h> + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + .section .bootpg, "ax" + .globl tlb1_entry + +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xe4010000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff800000 16M TLB for 8MB FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Cacheable, non-guarded + * 0x0 256M DDR SDRAM + */ + #if !defined(CONFIG_SPD_EEPROM) + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + #endif + + /* + * TLB 4: 64M Non-cacheable, guarded + * 0xe0000000 1M CCSRBAR + * 0xe2000000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Cacheable, non-guarded + * 0xf0000000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 16M Cacheable, non-guarded + * 0xf8000000 1M 7-segment LED display + * 0xf8100000 1M User switches + * 0xf8300000 1M Board revision + * 0xf8b00000 1M EEPROM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_EPLD_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_EPLD_BASE), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x0fff_ffff DDR 256M + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf8b0_0000 0xf80f_ffff EEPROM 1M + * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + + +#if !defined(CONFIG_SPD_EEPROM) + #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) + #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else + #define LAWBAR0 0 + #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ +#define LAWBAR3 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long 4 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + entry_end diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c new file mode 100644 index 0000000..95608de --- /dev/null +++ b/board/sbc8548/sbc8548.c @@ -0,0 +1,553 @@ +/* + * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> + * Copyright 2007 Embedded Specialties, Inc. + * + * Copyright 2004, 2007 Freescale Semiconductor. + * + * (C) Copyright 2002 Scott McNutt <smcnutt(a)artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <spd.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +DECLARE_GLOBAL_DATA_PTR; + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); +long int fixed_sdram (void); +unsigned int get_board_rev(void); + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + + printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", + get_board_rev ()); + + /* + * Initialize local bus. + */ + local_bus_init (); + + /* + * Fix CPU2 errata: A core hang possible while executing a + * msync instruction and a snoopable transaction from an I/O + * master tagged to make quick forward progress is present. + */ + ecm->eebpcr |= (1 << 16); + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + + ecm->eedr = 0xffffffff; /* clear ecm errors */ + ecm->eeer = 0xffffffff; /* enable ecm errors */ + return 0; +} + +long int +initdram(int board_type) +{ + long dram_size = 0; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay(200); + } +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + clkdiv = (lbc->lcrr & 0x0f) * 2; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + gur->lbiuiplldcr1 = 0x00078080; + if (clkdiv == 16) { + gur->lbiuiplldcr0 = 0x7c0f1bf0; + } else if (clkdiv == 8) { + gur->lbiuiplldcr0 = 0x6c0f1bf0; + } else if (clkdiv == 4) { + gur->lbiuiplldcr0 = 0x5c0f1bf0; + } + + lbc->lcrr |= 0x00030000; + + asm("sync;isync;msync"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void +sdram_init(void) +{ +#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) + + uint idx; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + uint lsdmr_common; + + puts(" SDRAM: "); + + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or3 = CFG_OR3_PRELIM; + asm("msync"); + + lbc->br3 = CFG_BR3_PRELIM; + asm("msync"); + + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("msync"); + + /* + * MPC8548 uses "new" 15-16 style addressing. + */ + lsdmr_common = CFG_LBC_LSDMR_COMMON; + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, + CFG_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed_sdram init -- doesn't use serial presence detect. + * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. + ************************************************************************/ +long int fixed_sdram (void) +{ + #define CFG_DDR_CONTROL 0xc300c000 + + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); + + ddr->cs0_bnds = 0x0000007f; + ddr->cs1_bnds = 0x008000ff; + ddr->cs2_bnds = 0x00000000; + ddr->cs3_bnds = 0x00000000; + ddr->cs0_config = 0x80010101; + ddr->cs1_config = 0x80010101; + ddr->cs2_config = 0x00000000; + ddr->cs3_config = 0x00000000; + ddr->ext_refrec = 0x00000000; + ddr->timing_cfg_0 = 0x00220802; + ddr->timing_cfg_1 = 0x38377322; + ddr->timing_cfg_2 = 0x0fa044C7; + ddr->sdram_cfg = 0x4300C000; + ddr->sdram_cfg_2 = 0x24401000; + ddr->sdram_mode = 0x23C00542; + ddr->sdram_mode_2 = 0x00000000; + ddr->sdram_interval = 0x05080100; + ddr->sdram_md_cntl = 0x00000000; + ddr->sdram_data_init = 0x00000000; + ddr->sdram_clk_cntl = 0x03800000; + asm("sync;isync;msync"); + udelay(500); + + #if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + #else + ddr->sdram_cfg = CFG_DDR_CONTROL; + #endif + + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif + +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. + */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } + +static struct pci_config_table pci_sbc8548_config_table[] = { + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, + mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, + mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, + {}, +}; + +static struct pci_controller pci1_hose = { + config_table: pci_sbc8548_config_table}; +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ + +int first_free_busno=0; + +void +pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + struct pci_config_table *table; + + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + + uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { + printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter" + ); + + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + hose->region_count = 3; + + /* relocate config table pointers */ + hose->config_table = \ + (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); + for (table = hose->config_table; table && table->vendor; table++) + table->config_device += gd->reloc_off; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); +#ifdef CONFIG_PCIX_CHECK + if (!(gur->pordevsr & PORDEVSR_PCI)) { + /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + printf("PCI-X will only work at 66 MHz\n"); + + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); + } +#endif + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif + +#ifdef CONFIG_PCI2 +{ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE connected to slot as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); + + first_free_busno=hose->last_busno+1; + + } else { + printf (" PCIE: disabled\n"); + } + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif + +} + +int last_stage_init(void) +{ + return 0; +} + +typedef struct epld_reg { + u_char bd_rev; /* Board revision */ +} epld_reg_t; + +unsigned int get_board_rev(void) +{ + volatile epld_reg_t *epld = (epld_reg_t *)CFG_BD_REV; + + return ((epld->bd_rev) >> 4); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif +

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[U-Boot-Users] [PATCH 0/6] cfi_flash cleanups
by Haavard Skinnemoen 13 Dec '07

13 Dec '07

This is a series of cleanups to the CFI driver I did while debugging why it refused to work on my AVR32 boards, rebased on top of the latest CFI custodian tree with "[PATCH] CFI: synchronize command offsets with Linux CFI driver" applied as well. I'm not completely done yet, as I need more fixes to make the CFI driver work on boards like the ATNGW100. But these initial patches are seriously painful to rebase (especially #3 in this series,) so I'd like some feedback from others if I'm moving in an acceptable direction with this. I've compile-tested the whole thing using MAKEALL on ppc (no point in testing on avr32 since no boards use this driver yet.) mcc200 failed, but it complains about lots of undefined symbols that has nothing to do with the CFI driver, so I'm pretty sure it isn't my fault. Please let me know which parts of this are acceptable, and if there's something that can be done in a better way. And if you merge parts 1-3 (or even more of them), I'd be _very_ happy :-) There are a couple of remaining cleanups I'd like to make that go on top of this stuff, mostly related to refactoring the command set handling and adding manufacturer-specific fixups. Haavard Skinnemoen (6): cfi_flash: Break long lines cfi_flash: Make some needlessly global functions static cfi_flash: Reorder functions and eliminate extra prototypes cfi_flash: Introduce read and write accessors Introduce map_physmem() and unmap_physmem() cfi_flash: Use map_physmem() and unmap_physmem() drivers/mtd/cfi_flash.c | 1677 +++++++++++++++++++++++-------------------- include/asm-arm/io.h | 17 + include/asm-avr32/io.h | 20 + include/asm-blackfin/io.h | 17 + include/asm-i386/io.h | 17 + include/asm-m68k/io.h | 18 + include/asm-microblaze/io.h | 17 + include/asm-mips/io.h | 17 + include/asm-nios/io.h | 17 + include/asm-nios2/io.h | 17 + include/asm-ppc/io.h | 17 + 11 files changed, 1077 insertions(+), 774 deletions(-)

2 5

[U-Boot-Users] dividable
by Janette Eng 13 Dec '07

13 Dec '07

Goedendag, Virus found in this message, please delete it without futher reading A summer day dream of love and of love always up last night with his wainsbad land this to journey beluchistan. Northern khorassan is the great centre.

1 0

[U-Boot-Users] RFC: Some improvements for the FPGA subsystem
by Matthias Fuchs 13 Dec '07

13 Dec '07

Hi, we had some discussions about the FPGA subsystem some days (and also a couple of months) before on this list. I have also some local improvements for the FPGA subsystem. Before posting a couple of clean patches I dare to post a single patch just to get an ok for the different topics. When all points are clear, I will split my patch into one patch per per topic. This is what I like to get into U-Boot: 1) Replace the CONFIG_FPGA bit mask by U-Boot like configuration options: CONFIG_FPGA - enable FPGA subsystem CONFIG_FPGA_<vendor> - enable support for specific chip vendors (ALTERA, XILINX) CONFIG_FPGA_<family> - enable support for FPGA family (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX) This means when you have an Xilinx Spartan3 FPGA on your board you typically have these lines in your board configuration: #define CONFIG_FPGA #define CONFIG_FPGA_XILINX #define CONFIG_FPGA_SPARTAN3 (TODO: add this to the README file) 2) Fix FPGA support for some boards that will get broken through the above change (GEN860T, ...) 3) Remove bit swapping in fpga_loadbitstream(). 4) Use AND-operation for checking MSB of bytes instead of sign check for Spartan2/3 FPGAs in slave serial code. 5) Add post() and pre() callback for Spartan2/3 FPGAs inslave serial mode. 6) Add some new FPGA types. Matthias diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index 2ba7e0e..5997584 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_FPGA) +#ifdef CONFIG_FPGA #if 0 #define GEN860T_FPGA_DEBUG diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index d448f9f..70341f8 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -254,7 +254,7 @@ int misc_init_r (void) mii_init (); #endif -#if (CONFIG_FPGA) +#ifdef CONFIG_FPGA gen860t_init_fpga (); #endif return 0; diff --git a/common/ACEX1K.c b/common/ACEX1K.c index 2a421e2..76dc166 100644 --- a/common/ACEX1K.c +++ b/common/ACEX1K.c @@ -28,7 +28,7 @@ #include <common.h> /* core U-Boot definitions */ #include <ACEX1K.h> /* ACEX device family */ -#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K) /* Define FPGA_DEBUG to get debug printf's */ #ifdef FPGA_DEBUG @@ -363,4 +363,4 @@ static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset) } -#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */ +#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */ diff --git a/common/altera.c b/common/altera.c index 06e8a95..eb874e4 100644 --- a/common/altera.c +++ b/common/altera.c @@ -40,7 +40,7 @@ #define PRINTF(fmt,args...) #endif -#if (CONFIG_FPGA & CFG_FPGA_ALTERA) +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) /* Local Static Functions */ static int altera_validate (Altera_desc * desc, char *fn); @@ -56,11 +56,11 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize ) switch (desc->family) { case Altera_ACEX1K: case Altera_CYC2: -#if (CONFIG_FPGA & CFG_ACEX1K) +#ifdef CONFIG_FPGA_ACEX1K PRINTF ("%s: Launching the ACEX1K Loader...\n", __FUNCTION__); ret_val = ACEX1K_load (desc, buf, bsize); -#elif (CONFIG_FPGA & CFG_CYCLON2) +#elif defined CONFIG_FPGA_CYCLON2 PRINTF ("%s: Launching the CYCLON II Loader...\n", __FUNCTION__); ret_val = CYC2_load (desc, buf, bsize); @@ -88,7 +88,7 @@ int altera_dump( Altera_desc *desc, void *buf, size_t bsize ) } else { switch (desc->family) { case Altera_ACEX1K: -#if (CONFIG_FPGA & CFG_ACEX) +#ifdef CONFIG_FPGA_ACEX PRINTF ("%s: Launching the ACEX1K Reader...\n", __FUNCTION__); ret_val = ACEX1K_dump (desc, buf, bsize); @@ -156,9 +156,9 @@ int altera_info( Altera_desc *desc ) switch (desc->family) { case Altera_ACEX1K: case Altera_CYC2: -#if (CONFIG_FPGA & CFG_ACEX1K) +#ifdef CONFIG_FPGA_ACEX1K ACEX1K_info (desc); -#elif (CONFIG_FPGA & CFG_CYCLON2) +#elif defined CONFIG_FPGA_CYCLON2 CYC2_info (desc); #else /* just in case */ @@ -192,7 +192,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset) } else { switch (desc->family) { case Altera_ACEX1K: -#if (CONFIG_FPGA & CFG_ACEX1K) +#ifdef CONFIG_FPGA_ACEX1K ret_val = ACEX1K_reloc (desc, reloc_offset); #else printf ("%s: No support for ACEX devices.\n", @@ -200,7 +200,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset) #endif break; case Altera_CYC2: -#if (CONFIG_FPGA & CFG_CYCLON2) +#ifdef CONFIG_FPGA_CYCLON2 ret_val = CYC2_reloc (desc, reloc_offset); #else printf ("%s: No support for CYCLON II devices.\n", @@ -249,4 +249,4 @@ static int altera_validate (Altera_desc * desc, char *fn) /* ------------------------------------------------------------------------- */ -#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */ +#endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */ diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index cce23ad..3813140 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -60,14 +60,11 @@ static int fpga_get_op (char *opstr); /* Convert bitstream data and load into the fpga */ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) { -#if (CONFIG_FPGA & CFG_FPGA_XILINX) +#ifdef CONFIG_FPGA_XILINX unsigned int length; - unsigned char* swapdata; unsigned int swapsize; char buffer[80]; - unsigned char *ptr; unsigned char *dataptr; - unsigned char data; unsigned int i; int rc; @@ -142,42 +139,10 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) ((unsigned int) *(dataptr+1) <<16) + ((unsigned int) *(dataptr+2) <<8 ) + ((unsigned int) *(dataptr+3) ) ; - dataptr+=4; + dataptr += 4; printf(" bytes in bitstream = %d\n", swapsize); - /* check consistency of length obtained */ - if (swapsize >= size) { - printf("%s: Could not find right length of data in bitstream\n", - __FUNCTION__); - return FPGA_FAIL; - } - - /* allocate memory */ - swapdata = (unsigned char *)malloc(swapsize); - if (swapdata == NULL) { - printf("%s: Could not allocate %d bytes memory !\n", - __FUNCTION__, swapsize); - return FPGA_FAIL; - } - - /* read data into memory and swap bits */ - ptr = swapdata; - for (i = 0; i < swapsize; i++) { - data = 0x00; - data |= (*dataptr & 0x01) << 7; - data |= (*dataptr & 0x02) << 5; - data |= (*dataptr & 0x04) << 3; - data |= (*dataptr & 0x08) << 1; - data |= (*dataptr & 0x10) >> 1; - data |= (*dataptr & 0x20) >> 3; - data |= (*dataptr & 0x40) >> 5; - data |= (*dataptr & 0x80) >> 7; - *ptr++ = data; - dataptr++; - } - - rc = fpga_load(dev, swapdata, swapsize); - free(swapdata); + rc = fpga_load(dev, dataptr, swapsize); return rc; #else printf("Bitstream support only for Xilinx devices\n"); diff --git a/common/cyclon2.c b/common/cyclon2.c index dce13b5..06f5e8a 100644 --- a/common/cyclon2.c +++ b/common/cyclon2.c @@ -27,7 +27,7 @@ #include <altera.h> #include <ACEX1K.h> /* ACEX device family */ -#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_CYCLON2) /* Define FPGA_DEBUG to get debug printf's */ #ifdef FPGA_DEBUG @@ -302,4 +302,4 @@ static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset) return ret_val; } -#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */ +#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_CYCLON2 */ diff --git a/common/fpga.c b/common/fpga.c index 2eff239..e4073be 100644 --- a/common/fpga.c +++ b/common/fpga.c @@ -67,14 +67,11 @@ static int fpga_dev_info( int devnum ); static void fpga_no_sup( char *fn, char *msg ) { if ( fn && msg ) { - printf( "%s: No support for %s. CONFIG_FPGA defined as 0x%x.\n", - fn, msg, CONFIG_FPGA ); + printf( "%s: No support for %s.\n", fn, msg); } else if ( msg ) { - printf( "No support for %s. CONFIG_FPGA defined as 0x%x.\n", - msg, CONFIG_FPGA ); + printf( "No support for %s.\n", msg); } else { - printf( "No FPGA suport! CONFIG_FPGA defined as 0x%x.\n", - CONFIG_FPGA ); + printf( "No FPGA suport!\n"); } } @@ -112,11 +109,6 @@ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_va printf( "%s: Null buffer.\n", fn ); return (fpga_desc * const)NULL; } - if ( !bsize ) { - printf( "%s: Null buffer size.\n", fn ); - return (fpga_desc * const)NULL; - } - return desc; } @@ -135,7 +127,7 @@ static int fpga_dev_info( int devnum ) switch ( desc->devtype ) { case fpga_xilinx: -#if CONFIG_FPGA & CFG_FPGA_XILINX +#ifdef CONFIG_FPGA_XILINX printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc ); ret_val = xilinx_info( desc->devdesc ); #else @@ -143,7 +135,7 @@ static int fpga_dev_info( int devnum ) #endif break; case fpga_altera: -#if CONFIG_FPGA & CFG_FPGA_ALTERA +#ifdef CONFIG_FPGA_ALTERA printf( "Altera Device\nDescriptor @ 0x%p\n", desc ); ret_val = altera_info( desc->devdesc ); #else @@ -175,14 +167,14 @@ int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off ) switch ( devtype ) { case fpga_xilinx: -#if CONFIG_FPGA & CFG_FPGA_XILINX +#ifdef CONFIG_FPGA_XILINX ret_val = xilinx_reloc( desc, reloc_off ); #else fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: -#if CONFIG_FPGA & CFG_FPGA_ALTERA +#ifdef CONFIG_FPGA_ALTERA ret_val = altera_reloc( desc, reloc_off ); #else fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); @@ -268,14 +260,14 @@ int fpga_load( int devnum, void *buf, size_t bsize ) if ( desc ) { switch ( desc->devtype ) { case fpga_xilinx: -#if CONFIG_FPGA & CFG_FPGA_XILINX +#ifdef CONFIG_FPGA_XILINX ret_val = xilinx_load( desc->devdesc, buf, bsize ); #else fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: -#if CONFIG_FPGA & CFG_FPGA_ALTERA +#ifdef CONFIG_FPGA_ALTERA ret_val = altera_load( desc->devdesc, buf, bsize ); #else fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); @@ -301,14 +293,14 @@ int fpga_dump( int devnum, void *buf, size_t bsize ) if ( desc ) { switch ( desc->devtype ) { case fpga_xilinx: -#if CONFIG_FPGA & CFG_FPGA_XILINX +#ifdef CONFIG_FPGA_XILINX ret_val = xilinx_dump( desc->devdesc, buf, bsize ); #else fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: -#if CONFIG_FPGA & CFG_FPGA_ALTERA +#ifdef CONFIG_FPGA_ALTERA ret_val = altera_dump( desc->devdesc, buf, bsize ); #else fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); diff --git a/common/spartan2.c b/common/spartan2.c index 0fb23b6..6d1ed96 100644 --- a/common/spartan2.c +++ b/common/spartan2.c @@ -25,7 +25,7 @@ #include <common.h> /* core U-Boot definitions */ #include <spartan2.h> /* Spartan-II device family */ -#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2)) +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN2) /* Define FPGA_DEBUG to get debug printf's */ #ifdef FPGA_DEBUG @@ -441,7 +441,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; int i; - char val; + unsigned char val; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -516,7 +516,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) (*fn->clk) (FALSE, TRUE, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val < 0), TRUE, cookie); + (*fn->wr) ((val & 0x80), TRUE, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); @@ -561,6 +561,13 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) } putc ('\n'); /* terminate the dotted line */ + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) { + (*fn->post) (cookie); + } + #ifdef CFG_FPGA_PROG_FEEDBACK if (ret_val == FPGA_SUCCESS) { puts ("Done.\n"); @@ -615,8 +622,10 @@ static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, desc); - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; + if (fn->pre) { + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + } addr = (ulong) (fn->pgm) + reloc_offset; fn_r->pgm = (Xilinx_pgm_fn) addr; @@ -633,6 +642,11 @@ static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) addr = (ulong) (fn->wr) + reloc_offset; fn_r->wr = (Xilinx_wr_fn) addr; + if (fn->post) { + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Xilinx_post_fn) addr; + } + fn_r->relocated = TRUE; } else { diff --git a/common/spartan3.c b/common/spartan3.c index c0f2b05..4fe3e89 100644 --- a/common/spartan3.c +++ b/common/spartan3.c @@ -30,7 +30,7 @@ #include <common.h> /* core U-Boot definitions */ #include <spartan3.h> /* Spartan-II device family */ -#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3)) +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3) /* Define FPGA_DEBUG to get debug printf's */ #ifdef FPGA_DEBUG @@ -446,7 +446,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; int i; - char val; + unsigned char val; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -514,6 +514,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) puts ("** CRC error during FPGA load.\n"); return (FPGA_FAIL); } + val = data [bytecount ++]; i = 8; do { @@ -521,7 +522,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) (*fn->clk) (FALSE, TRUE, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val < 0), TRUE, cookie); + (*fn->wr) ((val & 0x80), TRUE, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); @@ -566,6 +567,13 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) } putc ('\n'); /* terminate the dotted line */ + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) { + (*fn->post) (cookie); + } + #ifdef CFG_FPGA_PROG_FEEDBACK if (ret_val == FPGA_SUCCESS) { puts ("Done.\n"); @@ -620,8 +628,10 @@ static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, desc); - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; + if (fn->pre) { + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + } addr = (ulong) (fn->pgm) + reloc_offset; fn_r->pgm = (Xilinx_pgm_fn) addr; @@ -638,6 +648,11 @@ static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) addr = (ulong) (fn->wr) + reloc_offset; fn_r->wr = (Xilinx_wr_fn) addr; + if (fn->post) { + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Xilinx_post_fn) addr; + } + fn_r->relocated = TRUE; } else { diff --git a/common/virtex2.c b/common/virtex2.c index b5dc366..1283ff6 100644 --- a/common/virtex2.c +++ b/common/virtex2.c @@ -31,7 +31,7 @@ #include <common.h> #include <virtex2.h> -#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2)) +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_VIRTEX2) #if 0 #define FPGA_DEBUG diff --git a/common/xilinx.c b/common/xilinx.c index e03e78c..2a7e9f4 100644 --- a/common/xilinx.c +++ b/common/xilinx.c @@ -32,7 +32,7 @@ #include <spartan2.h> #include <spartan3.h> -#if (CONFIG_FPGA & CFG_FPGA_XILINX) +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX) #if 0 #define FPGA_DEBUG @@ -59,7 +59,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) } else switch (desc->family) { case Xilinx_Spartan2: -#if (CONFIG_FPGA & CFG_SPARTAN2) +#ifdef CONFIG_FPGA_SPARTAN2 PRINTF ("%s: Launching the Spartan-II Loader...\n", __FUNCTION__); ret_val = Spartan2_load (desc, buf, bsize); @@ -69,7 +69,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) #endif break; case Xilinx_Spartan3: -#if (CONFIG_FPGA & CFG_SPARTAN3) +#ifdef CONFIG_FPGA_SPARTAN3 PRINTF ("%s: Launching the Spartan-III Loader...\n", __FUNCTION__); ret_val = Spartan3_load (desc, buf, bsize); @@ -79,7 +79,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) #endif break; case Xilinx_Virtex2: -#if (CONFIG_FPGA & CFG_VIRTEX2) +#ifdef CONFIG_FPGA_VIRTEX2 PRINTF ("%s: Launching the Virtex-II Loader...\n", __FUNCTION__); ret_val = Virtex2_load (desc, buf, bsize); @@ -106,7 +106,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) } else switch (desc->family) { case Xilinx_Spartan2: -#if (CONFIG_FPGA & CFG_SPARTAN2) +#ifdef CONFIG_FPGA_SPARTAN2 PRINTF ("%s: Launching the Spartan-II Reader...\n", __FUNCTION__); ret_val = Spartan2_dump (desc, buf, bsize); @@ -116,7 +116,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) #endif break; case Xilinx_Spartan3: -#if (CONFIG_FPGA & CFG_SPARTAN3) +#ifdef CONFIG_FPGA_SPARTAN3 PRINTF ("%s: Launching the Spartan-III Reader...\n", __FUNCTION__); ret_val = Spartan3_dump (desc, buf, bsize); @@ -126,7 +126,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) #endif break; case Xilinx_Virtex2: -#if (CONFIG_FPGA & CFG_VIRTEX2) +#ifdef CONFIG_FPGA_VIRTEX2 PRINTF ("%s: Launching the Virtex-II Reader...\n", __FUNCTION__); ret_val = Virtex2_dump (desc, buf, bsize); @@ -198,7 +198,7 @@ int xilinx_info (Xilinx_desc * desc) printf ("Device Function Table @ 0x%p\n", desc->iface_fns); switch (desc->family) { case Xilinx_Spartan2: -#if (CONFIG_FPGA & CFG_SPARTAN2) +#ifdef CONFIG_FPGA_SPARTAN2 Spartan2_info (desc); #else /* just in case */ @@ -207,7 +207,7 @@ int xilinx_info (Xilinx_desc * desc) #endif break; case Xilinx_Spartan3: -#if (CONFIG_FPGA & CFG_SPARTAN3) +#ifdef CONFIG_FPGA_SPARTAN3 Spartan3_info (desc); #else /* just in case */ @@ -216,7 +216,7 @@ int xilinx_info (Xilinx_desc * desc) #endif break; case Xilinx_Virtex2: -#if (CONFIG_FPGA & CFG_VIRTEX2) +#ifdef CONFIG_FPGA_VIRTEX2 Virtex2_info (desc); #else /* just in case */ @@ -249,7 +249,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset) } else switch (desc->family) { case Xilinx_Spartan2: -#if (CONFIG_FPGA & CFG_SPARTAN2) +#ifdef CONFIG_FPGA_SPARTAN2 ret_val = Spartan2_reloc (desc, reloc_offset); #else printf ("%s: No support for Spartan-II devices.\n", @@ -257,7 +257,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset) #endif break; case Xilinx_Spartan3: -#if (CONFIG_FPGA & CFG_SPARTAN3) +#ifdef CONFIG_FPGA_SPARTAN3 ret_val = Spartan3_reloc (desc, reloc_offset); #else printf ("%s: No support for Spartan-III devices.\n", @@ -265,7 +265,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset) #endif break; case Xilinx_Virtex2: -#if (CONFIG_FPGA & CFG_VIRTEX2) +#ifdef CONFIG_FPGA_VIRTEX2 ret_val = Virtex2_reloc (desc, reloc_offset); #else printf ("%s: No support for Virtex-II devices.\n", @@ -308,4 +308,4 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn) return ret_val; } -#endif /* CONFIG_FPGA & CFG_FPGA_XILINX */ +#endif /* CONFIG_FPGA && CONFIG_FPGA_XILINX */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index bfbf3a8..3eb3131 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -273,7 +273,9 @@ * Virtex2 FPGA configuration support */ #define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA CFG_XILINX_VIRTEX2 +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_VIRTEX2 #define CFG_FPGA_PROG_FEEDBACK diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 6f4859c..487d2fc 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -190,7 +190,9 @@ /* FPGA - Spartan 2 */ /* experiment -#define CONFIG_FPGA CFG_SPARTAN3 +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 #define CONFIG_FPGA_COUNT 1 #define CFG_FPGA_PROG_FEEDBACK #define CFG_FPGA_CHECK_CTRLC diff --git a/include/configs/alpr.h b/include/configs/alpr.h index aff9823..bd32f6f 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -296,7 +296,10 @@ /*----------------------------------------------------------------------- * FPGA stuff *-----------------------------------------------------------------------*/ -#define CONFIG_FPGA CFG_ALTERA_CYCLON2 +#define CONFIG_FPGA +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 + #define CFG_FPGA_CHECK_CTRLC #define CFG_FPGA_PROG_FEEDBACK #define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in diff --git a/include/spartan2.h b/include/spartan2.h index d2e81e3..bd159e1 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -58,6 +58,7 @@ typedef struct { Xilinx_init_fn init; Xilinx_done_fn done; Xilinx_wr_fn wr; + Xilinx_post_fn post; int relocated; } Xilinx_Spartan2_Slave_Serial_fns; @@ -69,6 +70,7 @@ typedef struct { #define XILINX_XC2S50_SIZE 559232/8 #define XILINX_XC2S100_SIZE 781248/8 #define XILINX_XC2S150_SIZE 1040128/8 +#define XILINX_XC2S200_SIZE 1335872/8 /* Spartan-IIE (1.8V) */ #define XILINX_XC2S50E_SIZE 630048/8 @@ -95,6 +97,9 @@ typedef struct { #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } +#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie } + #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } diff --git a/include/spartan3.h b/include/spartan3.h index 65a3f5a..c203eeb 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -58,6 +58,7 @@ typedef struct { Xilinx_init_fn init; Xilinx_done_fn done; Xilinx_wr_fn wr; + Xilinx_post_fn post; int relocated; } Xilinx_Spartan3_Slave_Serial_fns; @@ -80,9 +81,12 @@ typedef struct { #define XILINX_XC3S1200E_SIZE 3841184/8 #define XILINX_XC3S1600E_SIZE 5969696/8 +/* Spartan-IIIE (1.2V) */ +#define XILINX_XC3S1200E_SIZE 3841184/8 + /* Descriptor Macros *********************************************************************/ -/* Spartan-II devices */ +/* Spartan-III devices */ #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } @@ -124,4 +128,9 @@ typedef struct { #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } + +/* Spartan-IIIE devices */ +#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } + #endif /* _SPARTAN3_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index 3704e1d..95ebe3d 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -31,11 +31,11 @@ *********************************************************************/ #define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 ) #define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 ) -#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 ) +#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 ) #define CFG_SPARTAN3 CFG_FPGA_DEV( 0x8 ) #define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2) #define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E) -#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2) +#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2) #define CFG_XILINX_SPARTAN3 (CFG_FPGA_XILINX | CFG_SPARTAN3) /* XXX - Add new models here */

5 16

Re: [U-Boot-Users] Request to mailing list U-Boot-Users rejected
by Haavard Skinnemoen 13 Dec '07

13 Dec '07

On Tue, 11 Dec 2007 08:23:21 -0800 u-boot-users-bounces(a)lists.sourceforge.net wrote: > "Your message was too big; please trim it to less than 40 KB in size." Oh for fsck sakes... > Message body is too big: 40979 bytes with a limit of 40 KB If you can't cut me 900 bytes of slack, I'm not going to bother anymore. That patch was _seriously_ painful and I'm not going to do it again just to shave off enough to get it below the arbitrary mailing-list limit. Haavard

11 18

[U-Boot-Users] mpc83xx boot error
by Russell McGuire 13 Dec '07

13 Dec '07

All, I have downloaded the latest U-boot 1.3.0 dirty <a week old> and compiled it up for a 8360E-MDS board. I have downloaded the latest version of the DTC 1.0.0-ge1109207 today, and compiled up a preconfigured dts file and burnt that into flash. Also I have downloaded denx's latest linux-git tree 2.6.23.1 and configured it for said board. However, when I try to boot Linux, I get an immediate error as follows: > bootm $kerneladdr - $blobaddr .. Bla bla standard printf.. Uncompressing the Kernel Image . OK Booting using the fdt at 0xe0080000 Loading device tree to 0x007fe000, end 0x007ff432 . ERROR: fdt move failed - must reset board to recover. Resetting the board. I am coming at this from my experience with U-boot 1.1.2 and 1.1.6 and a 1 yr old version of the dtc compiler. Are there new options, or less options that should be used with the dtc compiler to avoid this error? I know before we had to fix the version of the blob, so perhaps I am compiling the blob wrong? The dts file compiles fine with no warnings. dtc -I dts -O dtb -f -V 0x10 Using this without -V 0x10 gives me a different error dtc -I dts -O dtb -f WARNING: could not create /chosen FDT_ERR_NOSPACE ERROR: /chosen node create failed - must RESET the board to recover Anybody have any ideas?

3 3

[U-Boot-Users] Patches for 85xx question
by robert lazarski 12 Dec '07

12 Dec '07

Hi all, I'd like to submit patches for our project 'atum' (Tuna in Brazilian portuguese, its a custom to name projects after fishes) for inclusion into u-boot. Its a 8548 based board. Should I base patches off of u-boot 1.3.1 , http://opensource.freescale.com/pub/scm/u-boot-85xx.git , or some other git repo? BTW, thanks for this excellent community and all the help we received so far, Robert

3 4

[U-Boot-Users] [PATCH v2] qe: add ability to upload QE firmware
by Timur Tabi 12 Dec '07

12 Dec '07

Define the layout of a binary blob that contains a QE firmware and instructions on how to upload it. Add function qe_upload_firmware() to parse the blob and perform the actual upload. Add command-line command "qe fw" to take a firmware blob in memory and upload it. Update ft_cpu_setup() on 83xx to create the 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- cpu/mpc83xx/cpu.c | 53 +++++++++++ drivers/qe/qe.c | 219 ++++++++++++++++++++++++++++++++++++++++++++ drivers/qe/qe.h | 56 +++++++++++ include/asm-ppc/immap_qe.h | 35 +++++++- 4 files changed, 360 insertions(+), 3 deletions(-) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index b2c35d3..b098982 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -36,6 +36,9 @@ #elif defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif +#ifdef CONFIG_QE +#include "../../drivers/qe/qe.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -412,6 +415,38 @@ static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t tmp = cpu_to_be32(gd->brg_clk); return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); } + +/* + * If a QE firmware has been uploaded, then add the 'firmware' node under + * the 'qe' node. + */ +static int fdt_set_qe_firmware(void *blob, int nodeoffset, const char *name, bd_t *bd) +{ + struct qe_firmware_info *qe_fw_info; + int ret; + + qe_fw_info = qe_get_firmware_info(); + + if (qe_fw_info) { + /* We assume the node doesn't exist yet */ + nodeoffset = fdt_add_subnode(blob, nodeoffset, name); + if (nodeoffset < 0) + return nodeoffset; + ret = fdt_setprop_typed(blob, nodeoffset, "extended_modes", + qe_fw_info->extended_modes); + if (ret < 0) + return ret; + + ret = fdt_setprop_string(blob, nodeoffset, "id", qe_fw_info->id); + if (ret < 0) + return ret; + + return fdt_setprop(blob, nodeoffset, "virtual_traps", + qe_fw_info->vtraps, sizeof(qe_fw_info->vtraps)); + } + + return 0; +} #endif /* @@ -558,6 +593,24 @@ ft_cpu_setup(void *blob, bd_t *bd) tmp[1] = cpu_to_be32(bd->bi_memsize); fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); } + + /* We can't call fdt_set_qe_firmware() from the fixup_props[] table + * because the relocation bug causes fdt_setprop() to return + * FDT_ERR_NOSPACE if called with the return value of fdt_add_subnode(). + * So we need to call it directly here. This problem should go away + * when the 83xx relocation code is changed to match 85xx. + */ +#ifdef CONFIG_QE + nodeoffset = fdt_find_node_by_path(blob, "/" OF_QE); + if (nodeoffset >= 0) { + err = fdt_set_qe_firmware(blob, nodeoffset, "firmware", NULL); + if (err < 0) { + debug("Could not add qe/firmware node: %s\n", + fdt_strerror(err)); + fdt_del_node(blob, nodeoffset); + } + } +#endif } #elif defined(CONFIG_OF_FLAT_TREE) void diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 7559e92..276788c 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -21,6 +21,7 @@ */ #include "common.h" +#include <command.h> #include "asm/errno.h" #include "asm/io.h" #include "asm/immap_qe.h" @@ -248,4 +249,222 @@ int qe_set_mii_clk_src(int ucc_num) return 0; } +/* The maximum number of RISCs we support */ +#define MAX_QE_RISC 2 + +/* Firmware information stored here for qe_get_firmware_info() */ +static struct qe_firmware_info qe_firmware_info; + +/* + * Set to 1 if QE firmware has been uploaded, and therefore + * qe_firmware_info contains valid data. + */ +static int qe_firmware_uploaded; + +/* + * Upload a QE microcode + * + * This function is a worker function for qe_upload_firmware(). It does + * the actual uploading of the microcode. + */ +static void qe_upload_microcode(const void *base, + const struct qe_microcode *ucode) +{ + const u32 *code = base + be32_to_cpu(ucode->code_offset); + unsigned int i; + + if (ucode->major || ucode->minor || ucode->revision) + printf("QE: uploading microcode '%s' version %u.%u.%u\n", + ucode->id, ucode->major, ucode->minor, ucode->revision); + else + printf("QE: uploading microcode '%s'\n", ucode->id); + + /* Use auto-increment */ + out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) | + QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR); + + for (i = 0; i < be32_to_cpu(ucode->count); i++) + out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i])); +} + +/* + * Upload a microcode to the I-RAM at a specific address. + * + * See docs/README.qe_firmware for information on QE microcode uploading. + * + * Currently, only version 1 is supported, so the 'version' field must be + * set to 1. + * + * The SOC model and revision are not validated, they are only displayed for + * informational purposes. + * + * 'calc_size' is the calculated size, in bytes, of the firmware structure and + * all of the microcode structures, minus the CRC. + * + * 'length' is the size that the structure says it is, including the CRC. + */ +int qe_upload_firmware(const struct qe_firmware *firmware) +{ + unsigned int i; + unsigned int j; + u32 crc; + size_t calc_size = sizeof(struct qe_firmware); + size_t length; + const struct qe_header *hdr; + + if (!firmware) { + printf("Invalid address\n"); + return -EINVAL; + } + + hdr = &firmware->header; + length = be32_to_cpu(hdr->length); + + /* Check the magic */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Not a microcode\n"); + return -EPERM; + } + + /* Check the version */ + if (hdr->version != 1) { + printf("Unsupported version\n"); + return -EPERM; + } + + /* Validate some of the fields */ + if ((firmware->count < 1) || (firmware->count >= MAX_QE_RISC)) { + printf("Invalid data\n"); + return -EINVAL; + } + + /* Validate the length and check if there's a CRC */ + calc_size += (firmware->count - 1) * sizeof(struct qe_microcode); + + for (i = 0; i < firmware->count; i++) + /* + * For situations where the second RISC uses the same microcode + * as the first, the 'code_offset' and 'count' fields will be + * zero, so it's okay to add those. + */ + calc_size += sizeof(u32) * + be32_to_cpu(firmware->microcode[i].count); + + /* Validate the length */ + if (length != calc_size + sizeof(u32)) { + printf("Invalid length\n"); + return -EPERM; + } + + /* + * Validate the CRC. We would normally call crc32_no_comp(), but that + * function isn't available unless you turn on JFFS support. + */ + crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size)); + if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) { + printf("Firmware CRC is invalid\n"); + return -EIO; + } + + /* + * If the microcode calls for it, split the I-RAM. + */ + if (!firmware->split) { + out_be16(&qe_immr->cp.cercr, + in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR); + } + + if (firmware->soc.model) + printf("Firmware '%s' for %u V%u.%u\n", + firmware->id, be16_to_cpu(firmware->soc.model), + firmware->soc.major, firmware->soc.minor); + else + printf("Firmware '%s'\n", firmware->id); + + /* + * The QE only supports one microcode per RISC, so clear out all the + * saved microcode information and put in the new. + */ + memset(&qe_firmware_info, 0, sizeof(qe_firmware_info)); + strcpy(qe_firmware_info.id, firmware->id); + qe_firmware_info.extended_modes = firmware->extended_modes; + memcpy(qe_firmware_info.vtraps, firmware->vtraps, + sizeof(firmware->vtraps)); + qe_firmware_uploaded = 1; + + /* Loop through each microcode. */ + for (i = 0; i < firmware->count; i++) { + const struct qe_microcode *ucode = &firmware->microcode[i]; + + /* Upload a microcode if it's present */ + if (ucode->code_offset) + qe_upload_microcode(firmware, ucode); + + /* Program the traps for this processor */ + for (j = 0; j < 16; j++) { + u32 trap = be32_to_cpu(ucode->traps[j]); + + if (trap) + out_be32(&qe_immr->rsp[i].tibcr[j], trap); + } + + /* Enable traps */ + out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr)); + } + + return 0; +} + +struct qe_firmware_info *qe_get_firmware_info(void) +{ + return qe_firmware_uploaded ? &qe_firmware_info : NULL; +} + +static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "fw") == 0) { + addr = simple_strtoul(argv[2], NULL, 16); + + if (!addr) { + printf("Invalid address\n"); + return -EINVAL; + } + + /* + * If a length was supplied, compare that with the 'length' + * field. + */ + + if (argc > 3) { + ulong length = simple_strtoul(argv[3], NULL, 16); + struct qe_firmware *firmware = (void *) addr; + + if (length != be32_to_cpu(firmware->header.length)) { + printf("Length mismatch\n"); + return -EINVAL; + } + } + + return qe_upload_firmware((const struct qe_firmware *) addr); + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + qe, 4, 0, qe_cmd, + "qe - QUICC Engine commands\n", + "fw <addr> [<length>] - Upload firmware binary at address <addr> to " + "the QE,\n\twith optional length <length> verification.\n" + ); + #endif /* CONFIG_QE */ diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index 400b1a6..4c96c67 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -222,6 +222,60 @@ typedef enum qe_clock { #define QE_SDEBCR_BA_MASK 0x01FFFFFF +/* Communication Processor */ +#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ +#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ +#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ + +/* I-RAM */ +#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ +#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ + +/* Structure that defines QE firmware binary files. + * + * See doc/README.qe_firmware for a description of these fields. + */ +struct qe_firmware { + struct qe_header { + u32 length; /* Length of the entire structure, in bytes */ + u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ + u8 version; /* Version of this layout. First ver is '1' */ + } header; + u8 id[62]; /* Null-terminated identifier string */ + u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ + u8 count; /* Number of microcode[] structures */ + struct { + u16 model; /* The SOC model */ + u8 major; /* The SOC revision major */ + u8 minor; /* The SOC revision minor */ + } __attribute__ ((packed)) soc; + u8 padding[4]; /* Reserved, for alignment */ + u64 extended_modes; /* Extended modes */ + u32 vtraps[8]; /* Virtual trap addresses */ + u8 reserved[4]; /* Reserved, for future expansion */ + struct qe_microcode { + u8 id[32]; /* Null-terminated identifier */ + u32 traps[16]; /* Trap addresses, 0 == ignore */ + u32 eccr; /* The value for the ECCR register */ + u32 iram_offset; /* Offset into I-RAM for the code */ + u32 count; /* Number of 32-bit words of the code */ + u32 code_offset; /* Offset of the actual microcode */ + u8 major; /* The microcode version major */ + u8 minor; /* The microcode version minor */ + u8 revision; /* The microcode version revision */ + u8 padding; /* Reserved, for alignment */ + u8 reserved[4]; /* Reserved, for future expansion */ + } __attribute__ ((packed)) microcode[1]; + /* All microcode binaries should be located here */ + /* CRC32 should be located here, after the microcode binaries */ +} __attribute__ ((packed)); + +struct qe_firmware_info { + char id[64]; /* Firmware name */ + u32 vtraps[8]; /* Virtual trap addresses */ + u64 extended_modes; /* Extended modes */ +}; + void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); uint qe_muram_alloc(uint size, uint align); @@ -233,5 +287,7 @@ void qe_reset(void); void qe_assign_page(uint snum, uint para_ram_base); int qe_set_brg(uint brg, uint rate); int qe_set_mii_clk_src(int ucc_num); +int qe_upload_firmware(const struct qe_firmware *firmware); +struct qe_firmware_info *qe_get_firmware_info(void); #endif /* __QE_H__ */ diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index a16a6d3..bec54aa 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -513,10 +513,39 @@ typedef struct dbg { u8 res2[0x48]; } __attribute__ ((packed)) dbg_t; -/* RISC Special Registers (Trap and Breakpoint) -*/ +/* + * RISC Special Registers (Trap and Breakpoint). These are described in + * the QE Developer's Handbook. + */ typedef struct rsp { - u8 fixme[0x100]; + u32 tibcr[16]; /* Trap/instruction breakpoint control regs */ + u8 res0[64]; + u32 ibcr0; + u32 ibs0; + u32 ibcnr0; + u8 res1[4]; + u32 ibcr1; + u32 ibs1; + u32 ibcnr1; + u32 npcr; + u32 dbcr; + u32 dbar; + u32 dbamr; + u32 dbsr; + u32 dbcnr; + u8 res2[12]; + u32 dbdr_h; + u32 dbdr_l; + u32 dbdmr_h; + u32 dbdmr_l; + u32 bsr; + u32 bor; + u32 bior; + u8 res3[4]; + u32 iatr[4]; + u32 eccr; /* Exception control configuration register */ + u32 eicr; + u8 res4[0x100-0xf8]; } __attribute__ ((packed)) rsp_t; typedef struct qe_immap { -- 1.5.2.4

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[U-Boot-Users] UBoot on Zylonite dev. board with PXA300
by Alex Kreimer 12 Dec '07

12 Dec '07

I have hard time getting u-boot to work on subj. It would be interesting to head if someone has this configuration working and what are possible configuration settings that I missed? -- Alex

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