December 2007 - U-Boot

[U-Boot-Users] reducing size of u-boot binary
by vibi 14 Dec '07

14 Dec '07

hello, can any one please tell me how to reduce the size of u-boot.bin. i tried by disabling commands in the include/config/at91rm9200dk.h,as per the read me document even after this when i compile,i was unable to decrease the size. thanks in advance. regards vibi sreenivasan

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[U-Boot-Users] Multicultural Business Conference
by DiversityBusiness 14 Dec '07

14 Dec '07

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[U-Boot-Users] 85xx pci problems
by robert lazarski 14 Dec '07

14 Dec '07

Hi all, On our custom 8548, at the moment our priority is bringing up PCI for the first time. However, we can't get any cards recognized. To be honest, I found the device tree and TLB code of PCI to be the hardest part of the coding of the port, and I may have problems. We have a PCI1, PCI2 and one PCIE. Furthermore, since this is a new board we may have hardware issues. >From the u-boot monitor off of the latest git, I'm getting this: => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1057 0x0012 Processor 0x20 => pci long Scanning PCI devices on bus 0 Found PCI device 00.00.00: vendor ID = 0x1057 device ID = 0x0012 command register = 0x0006 status register = 0x20b0 revision ID = 0x20 class code = 0x0b (Processor) sub class code = 0x20 programming interface = 0x00 cache line = 0x08 latency time = 0x80 header type = 0x00 BIST = 0x00 base address 0 = 0x00000000 base address 1 = 0x00000000 base address 2 = 0x00000004 base address 3 = 0x00000000 base address 4 = 0x0000000c base address 5 = 0x00000000 cardBus CIS pointer = 0x00000000 sub system vendor ID = 0x0000 sub system ID = 0x0000 expansion ROM base address = 0x00000000 interrupt line = 0x00 interrupt pin = 0x01 min Grant = 0x00 max Latency = 0x00 => pci 1 long Scanning PCI devices on bus 1 Found PCI device 01.00.00: vendor ID = 0x1057 device ID = 0x0012 command register = 0x0006 status register = 0x20a0 revision ID = 0x20 class code = 0x0b (Processor) sub class code = 0x20 programming interface = 0x00 cache line = 0x08 latency time = 0x80 header type = 0x00 BIST = 0x00 base address 0 = 0x00000000 base address 1 = 0x00000000 base address 2 = 0x00000004 base address 3 = 0x00000000 base address 4 = 0x0000000c base address 5 = 0x00000000 cardBus CIS pointer = 0x00000000 sub system vendor ID = 0x0000 sub system ID = 0x0000 expansion ROM base address = 0x00000000 interrupt line = 0x00 interrupt pin = 0x01 min Grant = 0x00 max Latency = 0x00 >From linux I get: bash-3.00# lspci -vv 00:00.0 Class 0b20: 1057:0012 (rev 20) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 128, Cache Line Size 08 Interrupt: pin A routed to IRQ 19 Region 1: Memory at <unassigned> (32-bit, prefetchable) Region 2: Memory at <unassigned> (64-bit, non-prefetchable) Region 4: Memory at <unassigned> (64-bit, non-prefetchable) Capabilities: [60] #00 [0000] Not sure why I get "Status: Cap+ 66Mhz" - I need 33mhz and my device tree has "clock-frequency = <1fca055>". My device tree is mapped to have PCI at the root level to match the current 2.6.24RC2 . I've coded my TLB's to match this device tree: pci@e0008000 { interrupt-map-mask = <f800 0 0 7>; interrupt-map = < /* IDSEL 0x11 J17 Slot 1 */ 8800 0 0 1 &mpic 2 1 8800 0 0 2 &mpic 3 1 8800 0 0 3 &mpic 4 1 8800 0 0 4 &mpic 1 1 /* IDSEL 0x12 J16 Slot 2 */ 9000 0 0 1 &mpic 3 1 9000 0 0 2 &mpic 4 1 9000 0 0 3 &mpic 2 1 9000 0 0 4 &mpic 1 1>; interrupt-parent = <&mpic>; interrupts = <4 2>; bus-range = <0 ff>; ranges = <02000000 0 80000000 80000000 0 20000000 01000000 0 00000000 e2000000 0 00100000>; clock-frequency = <1fca055>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <e0008000 1000>; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; }; pci@e000c000 { interrupt-map-mask = <f800 0 0 7>; interrupt-map = < /* IDSEL 0x11 J17 Slot 1 */ 8800 0 0 1 &mpic 2 1 8800 0 0 2 &mpic 3 1 8800 0 0 3 &mpic 4 1 8800 0 0 4 &mpic 1 1 /* IDSEL 0x12 J16 Slot 2 */ 9000 0 0 1 &mpic 3 1 9000 0 0 2 &mpic 4 1 9000 0 0 3 &mpic 2 1 9000 0 0 4 &mpic 1 1>; interrupt-parent = <&mpic>; interrupts = <18 2>; bus-range = <0 ff>; ranges = <02000000 0 c0000000 c0000000 0 20000000 01000000 0 00000000 e2800000 0 00100000>; clock-frequency = <1fca055>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <e000c000 1000>; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; }; pcie@e000a000 { interrupt-map-mask = <f800 0 0 7>; interrupt-map = < /* IDSEL 0x0 (PEX) */ 00000 0 0 1 &mpic 0 1 00000 0 0 2 &mpic 1 1 00000 0 0 3 &mpic 2 1 00000 0 0 4 &mpic 3 1>; interrupt-parent = <&mpic>; interrupts = <1a 2>; bus-range = <0 ff>; ranges = <02000000 0 a0000000 a0000000 0 20000000 01000000 0 00000000 e3000000 0 08000000>; clock-frequency = <1fca055>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <e000a000 1000>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; pcie@0 { reg = <0 0 0 0 0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <02000000 0 a0000000 02000000 0 a0000000 0 20000000 01000000 0 00000000 01000000 0 00000000 0 08000000>; }; }; We are putting the o-scope on the board to look for hardware issues. Any help on what to look for concerning PCI hardware issues or my TLB / device tree issues would be highly appreciated - we're running out of time! Thanks, Robert

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[U-Boot-Users] libfdt problem when loading device tree
by Joakim Tjernlund 13 Dec '07

13 Dec '07

I get this when I try to boot my board: ## Booting image at 00200000 ... Image Name: oskernel02a:p1a:99 Created: 2007-12-13 9:59:43 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 1238992 Bytes = 1.2 MB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK Loading Device Tree to 007fe000, end 007ff6f9 ... OK WARNING: could not create /bd_t FDT_ERR_NOSPACE. fdt_bd_t: FDT_ERR_NOSPACE ERROR: /bd_t node create failed - must RESET the board to recover. Resetting the board. I have tried different combinations of -S and -R options to dtc, but nothing helps: dtc -S 2000 -R 2000 -f of-tmcu.dts -O asm > of-tmcu.S If I remove the chosen node from my dts file, I get the error when libfdt tries to create a chosen node. I am using dtc 1.0.0 and u-boot 1.3.1 Jocke

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[U-Boot-Users] [PATCH] Nios2: remove common/cmd_bdinfo.c unused variable
by Jean-Christophe PLAGNIOL-VILLARD 13 Dec '07

13 Dec '07

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index d059983..c28a155 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -152,7 +152,9 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { +#if defined(CONFIG_CMD_NET) int i; +#endif bd_t *bd = gd->bd; print_num ("mem start", (ulong)bd->bi_memstart); -- 1.5.3.7

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[U-Boot-Users] Problems Building u-boot-1.3.1
by raptorbrino＠aim.com 13 Dec '07

13 Dec '07

Hi All, I'm having a problem building u-boot-1.3.1. It complains when using the host compiler to compile sha1.c because it doesn't know what the data type __u64 is. This datatype is defined in u-boot/include/asm/types.h. However, I'm using cygwin, and it has the file /usr/include/asm/types.h. The types.h file in cygwin does not define __u64. Because the compile uses the flag -idirafter, the cygwin types.h is used in the include, hence an unkown symbol compile error. I fixed this problem in my local build by adding the flag -ansi to CPPFLAGS in tools/makefile. Is that appropriate or would you recommend fixing it another way?? Thanks, Brian ________________________________________________________________________ More new features than ever. Check out the new AIM(R) Mail ! - http://webmail.aim.com

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[U-Boot-Users] hush variables, syntax change?
by Joakim Tjernlund 13 Dec '07

13 Dec '07

in 1.1.4 I could write tftp $loadaddr $bootfile but in 1.3.1 I need to write tftp ${loadaddr} ${bootfile} Have I made a mistake in my board port? Jocke

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[U-Boot-Users] MPC boot sequence.
by Muneet 13 Dec '07

13 Dec '07

Hello Friends, I am facing some problem in understanding the booting sequence of MPC8323E. The MPC refernce manual says:- -- At PORESET, the processor loads RCW from Local Bus EEPROM or I2C EEPROM. After decoding the RCWH, it jumps to the boot code location found in it.-- The MPC8323E-RDB memory map is as follows:- 0x0000_0000 - 0x01FF_FFFF -- DDR 2GB -- PCI -- PCI 0xE000_0000 - 0xE01F_FFFF -- IMMR 0xFE00_0000 - 0xFEFF_FFFF -- Local Bus EEPROM(Flash 16 MB) RCWH - A060_0000 RCWL - 4205_0083 My understanding is as follows:-- 1. At PORESET, the processor loads RCW from Local Bus Flash. The address at that time is 0x0000_0000. 2. After reading the BMS and ROMLOC of RCWH, it locates to the address 0x0000_0100 and here it finds "uboot", the execution proceeds and the LBLAWBAR0 is programmed with 0xFE00_0000. thus Flash relocation occurs and then the kernel is uncompressed to DDR if allowed to boot. If this is Ok, or there is some flaw in it..? Thanks.. -- View this message in context: http://www.nabble.com/MPC-boot-sequence.-tp14316774p14316774.html Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] [PATCH 0/7] cfi_flash cleanups, take 3
by Haavard Skinnemoen 13 Dec '07

13 Dec '07

This is a resend of the whole series rebased onto the latest head of the CFI tree. Patch #3 is not actually present since it's too large to fit under the 40K limit. I've put it on a web server instead: http://avr32linux.org/twiki/pub/Sandbox/UbootCfiCleanup/0003-cfi_flash-Reor… I did a quick test on one of my avr32 boards and while it identified the flash just fine, it couldn't erase it. I think the flash chip needs to be unprotected, and the current code doesn't do this (it's kind of a quirk with the particular Atmel chip I'm using, AT49BV6416.) I'm planning to rework the code dealing with chip-specific quirks later on and add code to smack this chip on the head as needed. It also has a geometry reversal issue which is not detected properly by the current code (I think there's a reason this chip was quickly replaced by AT49BV642D, which doesn't have any of these problems.) Haavard Skinnemoen (7): cfi_flash: Break long lines cfi_flash: Make some needlessly global functions static cfi_flash: Reorder functions and eliminate extra prototypes Implement __raw_{read,write}[bwl] on all architectures cfi_flash: Introduce read and write accessors Introduce map_physmem() and unmap_physmem() cfi_flash: Use map_physmem() and unmap_physmem() drivers/mtd/cfi_flash.c | 1699 +++++++++++++++++++++++-------------------- include/asm-arm/io.h | 26 + include/asm-avr32/io.h | 32 + include/asm-blackfin/io.h | 26 + include/asm-i386/io.h | 26 + include/asm-m68k/io.h | 41 + include/asm-microblaze/io.h | 26 + include/asm-mips/io.h | 26 + include/asm-nios/io.h | 34 + include/asm-nios2/io.h | 34 + include/asm-ppc/io.h | 58 ++- 11 files changed, 1249 insertions(+), 779 deletions(-)

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[U-Boot-Users] [PATCH 2/2] mpc85xx: Add support for SBC8548 (updated)
by Joe Hamman 13 Dec '07

13 Dec '07

Add support for Wind River's SBC8548 reference board. Signed-off by: Joe Hamman <joe.hamman(a)embeddedspecialties.com> diff --git a/board/sbc8548/u-boot.lds b/board/sbc8548/u-boot.lds new file mode 100644 index 0000000..4cd177e --- /dev/null +++ b/board/sbc8548/u-boot.lds @@ -0,0 +1,149 @@ +/* + * Copyright 2004, 2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/sbc8548/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/sbc8548/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + drivers/net/tsec.o (.text) + cpu/mpc85xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/doc/README.sbc8548 @@ -0,0 +1,27 @@ +Wind River SBC8548 reference board +=========================== + +Copyright 2007, Embedded Specialties, Inc. +Copyright 2007 Wind River Systemes, Inc. +----------------------------- + +1. Building U-Boot +------------------ +The SBC8548 code is known to build using ELDK 4.1. + + $ make sbc8548_config + Configuring for sbc8548 board... + + $ make + + +2. Switch and Jumper Settings +----------------------------- +All Jumpers & Switches are in their default positions. Please refer to +the board documentation for details. Some settings control CPU voltages +and settings may change with board revisions. + +3. Known limitations +-------------------- +PCI: + The code to support PCI is currently disabled and has not been verified. diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h new file mode 100644 index 0000000..83ac4dc --- /dev/null +++ b/include/configs/sbc8548.h @@ -0,0 +1,576 @@ +/* + * Copyright 2007 Wind River Systems <www.windriver.com> + * Copyright 2007 Embedded Specialties, Inc. + * Copyright 2004, 2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * sbc8548 board configuration file + * + * Please refer to doc/README.sbc85xx for more info. + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 /* MPC8548 specific */ +#define CONFIG_SBC8548 1 /* SBC8548 board specific */ + +#undef CONFIG_PCI /* enable any pci type devices */ +#undef CONFIG_PCI1 /* PCI controller 1 */ +#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#undef CONFIG_RIO +#undef CONFIG_PCI2 +#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ + + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM + #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * FLASH on the Local Bus + * Two banks, one 8MB the other 64MB, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff80_0000 + * Alternate BR6/OR6 bank at 0xfb80_0000 + * + * BR0: + * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 + * Port Size = 8 bits = BRx[19:20] = 01 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 + * + * BR6: + * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 + * Port Size = 32 bits = BRx[19:20] = 11 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 + * + * OR0: + * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 + * XAM = OR0[17:18] = 11 + * CSNT = OR0[20] = 1 + * ACS = half cycle delay = OR0[21:22] = 11 + * SCY = 6 = OR0[24:27] = 0110 + * TRLX = use relaxed timing = OR0[29] = 1 + * EAD = use external address latch delay = OR0[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 + * + * OR6: + * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 + * XAM = OR6[17:18] = 11 + * CSNT = OR6[20] = 1 + * ACS = half cycle delay = OR6[21:22] = 11 + * SCY = 6 = OR6[24:27] = 0110 + * TRLX = use relaxed timing = OR6[29] = 1 + * EAD = use external address latch delay = OR6[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6 + */ + +#define CFG_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ +#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ + +#define CFG_BR0_PRELIM 0xff800801 +#define CFG_BR6_PRELIM 0xfb801801 + +#define CFG_OR0_PRELIM 0xff806e65 +#define CFG_OR6_PRELIM 0xfc006e65 + +#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +/* CS5 = Local bus peripherals controlled by the EPLD */ + +#define CFG_BR5_PRELIM 0xf8000801 +#define CFG_OR5_PRELIM 0xff006e65 +#define CFG_EPLD_BASE 0xf8000000 +#define CFG_LED_DISP_BASE 0xf8000000 +#define CFG_USER_SWITCHES_BASE 0xf8100000 +#define CFG_BD_REV 0xf8300000 +#define CFG_EEPROM_BASE 0xf8b00000 + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * Base Register 3 and Option Register 3 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR3, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + */ + +#define CFG_BR3_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR3, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CFG_OR3_PRELIM 0xfc006cc0 + +#define CFG_LBC_LCRR 0x00000002 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 400000000 /* get_bus_freq(0) */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x3000 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ + +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#ifdef CONFIG_PCI2 +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2800000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#endif + +#ifdef CONFIG_PCIE1 +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe3000000 +#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif + +#ifdef CONFIG_RIO +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xC0000000 +#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif + +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC2" +#define CONFIG_TSEC4 +#define CONFIG_TSEC4_NAME "eTSEC3" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 02:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD +#endif + +#define CONFIG_IPADDR 192.168.0.55 + +#define CONFIG_HOSTNAME sbc8548 +#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx +#define CONFIG_BOOTFILE /uImage +#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ + +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=uRamdisk\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=sbc8548.dtb\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */

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