July 2006 - U-Boot

[U-Boot-Users] [PATCH 01/08]: General code modification for mpc7448hpc2 board
by Zang Roy-r61911 28 Jul '06

28 Jul '06

General code modification for mpc7448hpc2 board support. The modification do not affect other board behavior. Signed-off-by: Alexandre Bounine <alexandreb(a)tundra.com> Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- MAKEALL | 4 +-- Makefile | 3 ++ README | 22 ++++++++-------- cpu/74xx_7xx/cpu.c | 22 ++++++++++++++-- cpu/74xx_7xx/cpu_init.c | 2 + cpu/74xx_7xx/speed.c | 55 ++++++++++++++++++++++++++++++++++++++--- include/74xx_7xx.h | 1 + include/asm-ppc/global_data.h | 3 ++ lib_ppc/extable.c | 11 ++++++++ net/eth.c | 4 +++ 10 files changed, 107 insertions(+), 20 deletions(-) diff --git a/MAKEALL b/MAKEALL index 467a9be..2f41936 100755 --- a/MAKEALL +++ b/MAKEALL @@ -139,8 +139,8 @@ ## 74xx/7xx Systems ######################################################################## # LIST_74xx=" \ - DB64360 DB64460 EVB64260 P3G4 \ - PCIPPC2 PCIPPC6 ZUMA \ + DB64360 DB64460 EVB64260 mpc7448hpc2 \ + P3G4 PCIPPC2 PCIPPC6 ZUMA \ " LIST_7xx=" \ diff --git a/Makefile b/Makefile index 128ae59..c910f39 100644 --- a/Makefile +++ b/Makefile @@ -1489,6 +1489,9 @@ EVB64260_config \ EVB64260_750CX_config: unconfig @./mkconfig EVB64260 ppc 74xx_7xx evb64260 +mpc7448hpc2_config: unconfig + @./mkconfig $(@:_config=) ppc 74xx_7xx mpc7448hpc2 + P3G4_config: unconfig @./mkconfig $(@:_config=) ppc 74xx_7xx evb64260 diff --git a/README b/README index e772c1a..f7f53d1 100644 --- a/README +++ b/README @@ -2289,17 +2289,17 @@ configurations; the following names are csb272_config lwmon_config sbc8260_config CU824_config MBX860T_config sbc8560_33_config DUET_ADS_config MBX_config sbc8560_66_config - EBONY_config MPC8260ADS_config SM850_config - ELPT860_config MPC8540ADS_config SPD823TS_config - ESTEEM192E_config MPC8540EVAL_config stxgp3_config - ETX094_config MPC8560ADS_config SXNI855T_config - FADS823_config NETVIA_config TQM823L_config - FADS850SAR_config omap1510inn_config TQM850L_config - FADS860T_config omap1610h2_config TQM855L_config - FPS850L_config omap1610inn_config TQM860L_config - omap5912osk_config walnut_config - omap2420h4_config Yukon8220_config - ZPC1900_config + EBONY_config mpc7448hpc2_config SM850_config + ELPT860_config MPC8260ADS_config SPD823TS_config + ESTEEM192E_config MPC8540ADS_config stxgp3_config + ETX094_config MPC8540EVAL_config SXNI855T_config + FADS823_config NMPC8560ADS_config TQM823L_config + FADS850SAR_config NETVIA_config TQM850L_config + FADS860T_config omap1510inn_config TQM855L_config + FPS850L_config omap1610h2_config TQM860L_config + omap1610inn_config walnut_config + omap5912osk_config Yukon8220_config + omap2420h4_config ZPC1900_config Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index ca45e17..4e112dc 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -101,6 +101,14 @@ get_cpu_type(void) type = CPU_7457; break; + case 0x8003: + type = CPU_7447A; + break; + + case 0x8004: + type = CPU_7448; + break; + default: break; } @@ -164,6 +172,14 @@ int checkcpu (void) str = "MPC7457"; break; + case CPU_7447A: + str = "MPC7447A"; + break; + + case CPU_7448: + str = "MPC7448"; + break; + default: printf("Unknown CPU -- PVR: 0x%08x\n", pvr); return -1; @@ -256,18 +272,18 @@ #endif /* * For the 7400 the TB clock runs at 1/4 the cpu bus speed. */ -#ifdef CONFIG_AMIGAONEG3SE +#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_MPC7448HPC2) unsigned long get_tbclk(void) { return (gd->bus_clk / 4); } -#else /* ! CONFIG_AMIGAONEG3SE */ +#else /* ! CONFIG_AMIGAONEG3SE and !CONFIG_MPC7448HPC2*/ unsigned long get_tbclk (void) { return CFG_BUS_HZ / 4; } -#endif /* CONFIG_AMIGAONEG3SE */ +#endif /* CONFIG_AMIGAONEG3SE or CONFIG_MPC7448HPC2*/ /* ------------------------------------------------------------------------ - */ #if defined(CONFIG_WATCHDOG) diff --git a/cpu/74xx_7xx/cpu_init.c b/cpu/74xx_7xx/cpu_init.c index 93f180f..1dd1b2c 100644 --- a/cpu/74xx_7xx/cpu_init.c +++ b/cpu/74xx_7xx/cpu_init.c @@ -43,6 +43,8 @@ cpu_init_f (void) case CPU_7450: case CPU_7455: case CPU_7457: + case CPU_7447A: + case CPU_7448: /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); break; diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c index 2dc5107..dce055f 100644 --- a/cpu/74xx_7xx/speed.c +++ b/cpu/74xx_7xx/speed.c @@ -31,6 +31,8 @@ #endif DECLARE_GLOBAL_DATA_PTR; +extern unsigned long get_board_bus_clk(void); + static const int hid1_multipliers_x_10[] = { 25, /* 0000 - 2.5x */ 75, /* 0001 - 7.5x */ @@ -50,6 +52,41 @@ static const int hid1_multipliers_x_10[] 0 /* 1111 - off */ }; +static const int hid1_7447A_multipliers_x_10[] = { + 115, /* 00000 - 11.5x */ + 170, /* 00001 - 17x */ + 75, /* 00010 - 7.5x */ + 150, /* 00011 - 15x */ + 70, /* 00100 - 7x */ + 180, /* 00101 - 18x */ + 10, /* 00110 - bypass */ + 200, /* 00111 - 20x */ + 20, /* 01000 - 2x */ + 210, /* 01001 - 21x */ + 65, /* 01010 - 6.5x */ + 130, /* 01011 - 13x */ + 85, /* 01100 - 8.5x */ + 240, /* 01101 - 13x */ + 95, /* 01110 - 9.5x */ + 90, /* 01111 - 9x */ + 30, /* 10000 - 3x */ + 105, /* 10001 - 10.5x */ + 55, /* 10010 - 5.5x */ + 110, /* 10011 - 11x */ + 40, /* 10100 - 4x */ + 100, /* 10101 - 10x */ + 50, /* 10110 - 5x */ + 120, /* 10111 - 12x */ + 80, /* 11000 - 8x */ + 140, /* 11001 - 14x */ + 60, /* 11010 - 6x */ + 160, /* 11011 - 16x */ + 135, /* 11100 - 13.5x */ + 280, /* 11101 - 28x */ + 0, /* 11110 - off */ + 125 /* 11111 - 12.5x */ +}; + static const int hid1_fx_multipliers_x_10[] = { 00, /* 0000 - off */ 00, /* 0001 - off */ @@ -89,8 +126,19 @@ int get_clocks (void) { ulong clock = 0; +#ifdef CFG_BUS_CLK + gd->bus_clk = CFG_BUS_CLK; +#else + gd->bus_clk = get_board_bus_clk(); +#endif + /* calculate the clock frequency based upon the CPU type */ switch (get_cpu_type()) { + case CPU_7447A: + case CPU_7448: + clock = (gd->bus_clk / 10) * hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F]; + break; + case CPU_7455: case CPU_7457: /* @@ -98,12 +146,12 @@ int get_clocks (void) * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ - clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; + clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; break; case CPU_750GX: case CPU_750FX: - clock = CFG_BUS_CLK * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; + clock = gd->bus_clk * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; break; case CPU_7450: @@ -120,7 +168,7 @@ int get_clocks (void) * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ - clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[get_hid1 () >> 28]; + clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[get_hid1 () >> 28]; break; case CPU_UNKNOWN: @@ -130,7 +178,6 @@ int get_clocks (void) } gd->cpu_clk = clock; - gd->bus_clk = CFG_BUS_CLK; return (0); } diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index a628798..7cd2f10 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -112,6 +112,7 @@ typedef enum __cpu_t { CPU_7400, CPU_7410, CPU_7450, CPU_7455, CPU_7457, + CPU_7447A, CPU_7448, CPU_UNKNOWN} cpu_t; extern cpu_t get_cpu_type(void); diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index b73af96..166afbe 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -49,6 +49,9 @@ #if defined(CONFIG_CPM2) unsigned long scc_clk; unsigned long brg_clk; #endif +#if defined(CONFIG_MPC7448HPC2) + unsigned long mem_clk; +#endif #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c index d92f142..851aa55 100644 --- a/lib_ppc/extable.c +++ b/lib_ppc/extable.c @@ -55,9 +55,16 @@ search_one_table(const struct exception_ long diff; mid = (last - first) / 2 + first; +#ifdef CONFIG_MPC7448HPC2 + DECLARE_GLOBAL_DATA_PTR; + diff = (mid->insn + gd->reloc_off) - value; + if (diff == 0) + return (mid->fixup + gd->reloc_off); +#else diff = mid->insn - value; if (diff == 0) return mid->fixup; +#endif else if (diff < 0) first = mid+1; else @@ -66,7 +73,11 @@ search_one_table(const struct exception_ return 0; } +#ifdef CONFIG_MPC7448HPC2 +int ex_tab_message = 0; +#else int ex_tab_message = 1; +#endif unsigned long search_exception_table(unsigned long addr) diff --git a/net/eth.c b/net/eth.c index 6f48aac..cfc0232 100644 --- a/net/eth.c +++ b/net/eth.c @@ -52,6 +52,7 @@ extern int rtl8139_initialize(bd_t*); extern int rtl8169_initialize(bd_t*); extern int scc_initialize(bd_t*); extern int skge_initialize(bd_t*); +extern int tsi108_eth_initialize(bd_t*); extern int tsec_initialize(bd_t*, int, char *); extern int npe_initialize(bd_t *); @@ -229,6 +230,9 @@ #endif #ifdef CONFIG_NS8382X ns8382x_initialize(bis); #endif +#if defined(CONFIG_TSI108_ETH) + tsi108_eth_initialize(bis); +#endif #if defined(CONFIG_RTL8139) rtl8139_initialize(bis); #endif -- 1.4.0

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[U-Boot-Users] [PATCH 00/08]: Add mpc7448hpc2 board support
by Zang Roy-r61911 28 Jul '06

28 Jul '06

This series of eight patches add mpc7448hpc2 board support. Mpc7448hpc2 (taiga) board is a high-performance PowerPC server reference design. Roy

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Re: [U-Boot-Users] qajadVjlAGRA
by Athanasios Olander 28 Jul '06

28 Jul '06

CIjALIlS from 3 , 75 $ AMjBlIEN VAjLIlUM from 1 , 25 $ VlljAGRA from 3 , 35 $ http://www.mearagico.com , , , , would do a good job of sorting out this repellent world. I would do equally well as I slipped away between the interstices of society. In six months I would be far from here, my trail cold, my bank

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[U-Boot-Users] 440SP DDR2 Issue
by Jeff Stevens 28 Jul '06

28 Jul '06

I have a custom board I am trying to bring up that is a pretty close architecture to the Luan2 board. I have an unregistered 2GB DDR2 module in the DIMM slot, and it works fine using the BDI2000. However, using the same DDR2 configuration in U-Boot doesn't work. It boots up until the point it transfers over to memory. I have enabled the memory test and it fails at the first address. I have verified all of the memory configuration registers, and all seem to be set correctly. I know there is something in the configuration I am missing, but I can't seem to figure it out. Please help. I would greatly appreciate it. Thanks, Jeff Stevens __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

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Re: [U-Boot-Users] [DNX#2006072742000035] [PATCH] improve the CSB bus and DMA performance of [...]
by DENX Support System 27 Jul '06

27 Jul '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006072742000035] was created: <snip> > All, > > The default pipeline depth of 83xx CSB is 1 outstanding transcation. If > change it to 4, the CSB performace will improve. Change the DMA transfer > with cache line burst read/write The DMA performance improved 6x. > > CHANGELOG: > * improve the coherency system bus performance and > improve the DMA transfer performace. > Patch by Dave Liu, 21 July 2006 > > > diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c > index 20bba6c..2eea221 100644 > --- a/cpu/mpc83xx/cpu.c > +++ b/cpu/mpc83xx/cpu.c > @@ -257,9 +257,7 @@ int dma_xfer(void *dest, u32 count, void > __asm__ __volatile__ ("isync"); > > /* init direct transfer, clear CS bit */ > - dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT | > - DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B | > - DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN); > + dmamr0 = DMA_CHANNEL_TRANSFER_MODE_DIRECT; > > dma->dmamr0 = swab32(dmamr0); > > diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index > 6ed0992..8366cb7 100644 > --- a/cpu/mpc83xx/cpu_init.c > +++ b/cpu/mpc83xx/cpu_init.c > @@ -69,7 +69,8 @@ #endif > #ifdef CFG_SICRL > im->sysconf.sicrl = CFG_SICRL; > #endif > - > + /* Set CSB bus pipeline depth */ > + im->arbiter.acr |= ACR_PIPE_DEP_IS_03; > /* > * Memory Controller: > */ > > diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h > index c2b4c5c..24191c5 100644 > --- a/include/asm-ppc/immap_83xx.h > +++ b/include/asm-ppc/immap_83xx.h > @@ -371,6 +371,7 @@ typedef struct arbiter8349 { > u32 acr; /* Arbiter Configuration Register */ > #define ACR_COREDIS 0x10000000 /* Core disable. */ > #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of > outstanding transactions). */ > +#define ACR_PIPE_DEP_IS_03 0x00030000 /* Pipeline depth is 4 > */ > #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ > #define ACR_RPTCNT 0x00000700 /* Repeat count. */ > #define ACR_APARK 0x00000030 /* Address parking. */ </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006072742000035] [PATCH] improve the [...]
by U-Boot patch tracking system 27 Jul '06

27 Jul '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006072742000035]. Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006072742000044] [PATCH] fix the inco [...]
by U-Boot patch tracking system 27 Jul '06

27 Jul '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006072742000044]. Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006072742000044] [PATCH] fix the incorrect dcbz operation of 83xx
by DENX Support System 27 Jul '06

27 Jul '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006072742000044] was created: <snip> > All, > > The 834x Rev1.1 silicon has one bug inside. The issue is when the dcache > locked with HID0[DLOCK], the dcbz instruction looks like no-op > instruction. > > The right behavior of the dcache is when the dcache locked with > HID0[DLOCK], the dcbz instruction allocates new tags in cache. > > The bug is only in 834x rev1.1, PVR is 0x80830011. The 834x rev2.0 and > later and 8360 have not this bug inside. > > So, when 834x rev2.0/8360 are working with ECC, the dcbz instruction > will corrupt the stack in cache, the processor will checkstop reset. > > However, the 834x rev1.1 can work with ECC with these code, because the > sillicon has this cache bug. The dcbz will not corrupt the stack in > cache. Really, it is the fault code running fault sillicon. > > This patch fix the incorrect dcbz operation. Instead of CPU FP writing > to initialise the ECC. > > > CHANGELOG: > * fix the incorrect dcbz operation instead of CPU FP writing to > initialise > the ECC memory. > Patch by Dave Liu, 21 July 2006 > > > > diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index > 48624fe..8eaa6f6 100644 > --- a/cpu/mpc83xx/spd_sdram.c > +++ b/cpu/mpc83xx/spd_sdram.c > @@ -429,54 +429,37 @@ static __inline__ unsigned long get_tbms > /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */ > void ddr_enable_ecc(unsigned int dram_size) > { > - uint *p; > volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; > volatile ddr8349_t *ddr = &immap->ddr; > unsigned long t_start, t_end; > + register u64 *p; > + register uint size; > + unsigned int pattern[2]; > #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) > uint i; > #endif > - > - debug("Initialize a Cachline in DRAM\n"); > icache_enable(); > + t_start = get_tbms(); > > -#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) > - /* Initialise DMA for direct Transfers */ > - dma_init(); > -#endif > - > - t_start = get_tbms(); > + pattern[0] = 0xdeadbeef; > + pattern[1] = 0xdeadbeef; > > #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA) > - debug("DDR init: Cache flush method\n"); > - for (p = 0; p < (uint *)(dram_size); p++) { > - if (((unsigned int)p & 0x1f) == 0) { > - ppcDcbz((unsigned long) p); > - } > - > - /* write pattern to cache and flush */ > - *p = (unsigned int)0xdeadbeef; > - > - if (((unsigned int)p & 0x1c) == 0x1c) { > - ppcDcbf((unsigned long) p); > - } > + debug("DDR init: CPU FP write method\n"); > + size = dram_size; > + for (p = 0; p < (u64*)(size); p++) { > + ppcDWstore((u32*)p, pattern); > } > + __asm__ __volatile__("sync"); > #else > - printf("DDR init: DMA method\n"); > - for (p = 0; p < (uint *)(8 * 1024); p++) { > - /* zero one data cache line */ > - if (((unsigned int)p & 0x1f) == 0) { > - ppcDcbz((unsigned long)p); > - } > - > - /* write pattern to it and flush */ > - *p = (unsigned int)0xdeadbeef; > - > - if (((unsigned int)p & 0x1c) == 0x1c) { > - ppcDcbf((unsigned long)p); > - } > + debug("DDR init: DMA method\n"); > + size = 0x2000; > + for (p = 0; p < (u64*)(size); p++) { > + ppcDWstore((u32*)p, pattern); </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006072742000026] [PATCH] fix incorrec [...]
by U-Boot patch tracking system 27 Jul '06

27 Jul '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006072742000026]. Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006072742000026] [PATCH] fix incorrect bus clk of 83xx
by DENX Support System 27 Jul '06

27 Jul '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006072742000026] was created: <snip> > All, > > The gd->bus_clk of 83xx should be csb_clk, not libu_clk, > If it don't be changed, will make the timer incorrect. > > CHANGELOG: > * fix incorrect gd->bus_clk, it should be csb_clk > Patch by Dave Liu, 21 July 2006 > > > diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c > index ad6b3f6..bc689c1 100644 > --- a/cpu/mpc83xx/speed.c > +++ b/cpu/mpc83xx/speed.c > @@ -333,7 +333,7 @@ #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) > gd->pci_clk = pci_sync_in; > > gd->cpu_clk = gd->core_clk; > - gd->bus_clk = gd->lbiu_clk; > + gd->bus_clk = gd->csb_clk; > return 0; > } </snip> Your U-Boot support team

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