December 2006 - U-Boot

[U-Boot-Users] MPC83xx SPI driver
by Ben Warren 07 Dec '06

07 Dec '06

Hello, I'm ready to re-submit a hard SPI driver for some members of the MPC83xx family of CPUs, but am unsure where to put it. While designed for the MPC834x chips, it should also work with the upcoming MPC8313, if the online datasheet is accurate. The other 83xx chips handle SPI with a CPM, so this driver won't work there. Should I put it in cpu/mpc83xx/, drivers/, or somewhere else? And given the unusual chip compatibilities, what should the file be called? Suggestions? regards, Ben

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[U-Boot-Users] possible ELDK4 gcc compiler bug
by Matthias Fuchs 07 Dec '06

07 Dec '06

Hi, I noticed some strange behavior when using the ELDK4 gcc for compiling U-Boot for a (new) 405 target based on the current PMC405 board. The code needs to read-modify-write a memory mapped FPGA internal register. But the FPGA access does not appear in the object and therefore it is never done. Here are some code snippets: 1) my 'fifo' BSP command: int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { struct pmc405v2_fpga_s *fpga = (struct pmc405v2_fpga_s *)FPGA_BA; int i; int n = 0; u32 ctrl, data, f; char str[] = "\\|/-"; int abort = 0; int count = 0; int count2 = 0; switch(argc) { case 2: /* completely read out fifo 'n' */ if (!strcmp(argv[1],"read")) { printf(" # fifo level data\n"); printf("__________________________________\n"); for (i=0; i<FIFO_COUNT; i++) { dump_fifo(fpga, i, &n); } } else if (!strcmp(argv[1],"wait")) { got_fifoirq = 0; irq_install_handler (FPGA_IRQ, (interrupt_handler_t *)fpga_interrupt, (void*)fpga); printf(" # fifo level data\n"); printf("__________________________________\n"); fpga->ctrl |= CTRL_FIFO_IE; for (i=0; i<FIFO_COUNT; i++) { /* enable interrupts from all fifos */ printf("DEBUG1: %p:%08x\n", &(fpga->fifo[i].ctrl), fpga->fifo[i].ctrl); --> These RMW-ops do not appear in the object and is never done! --> fpga->fifo[i].ctrl |= 0x8000; printf("DEBUG2: %p:%08x\n", &(fpga->fifo[i].ctrl), fpga->fifo[i].ctrl); } while (1) { /* wait loop */ while(!got_fifoirq) { ... 2) Here are the used structs for the fpga variable: struct pmc405v2_fifo_s { volatile u32 data; volatile u32 ctrl; }; /* fifo ctrl register */ #define FIFO_OVERFLOW 0x00000400 #define FIFO_EMPTY 0x00000200 #define FIFO_FULL 0x00000100 #define FIFO_IE 0x00008000 #define FIFO_LEVEL_MASK 0x000000ff #define FIFO_COUNT 4 struct pmc405v2_fpga_s { volatile u32 ctrl; volatile u32 status; volatile u32 test1; volatile u32 test2; u32 pad1[0x60 / sizeof(u32) - 4]; volatile u32 hostctrl; /* 0x0060 */ u32 pad2[0x20 / sizeof(u32) - 1]; struct pmc405v2_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */ }; 3) Here are some lines from the objectdump. I do not find anything from the RMW-op to the FPGA register (fpga->fifo[i].ctrl |= 0x8000;). /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:556 dd8: 48 00 00 01 bl dd8 <do_fifo+0x178> dd8: R_PPC_PLTREL24 printf /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:558 ddc: 3d 20 ef 00 lis r9,-4352 de0: 80 09 00 00 lwz r0,0(r9) de4: 3b 40 00 00 li r26,0 de8: 60 00 02 00 ori r0,r0,512 dec: 90 09 00 00 stw r0,0(r9) df0: 7f 7f db 78 mr r31,r27 /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:561 for (i=0; i<FIFO_COUNT; i++) { /* enable interrupts from all fifos */ printf("DEBUG1: %p:%08x\n", df4: 83 9b 00 00 lwz r28,0(r27) df8: 80 7e 80 cc lwz r3,-32564(r30) dfc: 7f e4 fb 78 mr r4,r31 e00: 7f 85 e3 78 mr r5,r28 e04: 48 00 00 01 bl e04 <do_fifo+0x1a4> e04: R_PPC_PLTREL24 printf /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:564 &(fpga->fifo[i].ctrl), fpga->fifo[i].ctrl); fpga->fifo[i].ctrl |= 0x8000; printf("DEBUG2: %p:%08x\n", e08: 80 7e 80 d0 lwz r3,-32560(r30) e0c: 7f e4 fb 78 mr r4,r31 e10: 7f 85 e3 78 mr r5,r28 e14: 48 00 00 01 bl e14 <do_fifo+0x1b4> e14: R_PPC_PLTREL24 printf /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:559 e18: 2f 9a 00 03 cmpwi cr7,r26,3 e1c: 3b ff 00 08 addi r31,r31,8 e20: 3b 7b 00 08 addi r27,r27,8 e24: 3b 5a 00 01 addi r26,r26,1 e28: 40 9e ff cc bne+ cr7,df4 <do_fifo+0x194> e2c: 3b e0 00 00 li r31,0 e30: 48 00 00 6c b e9c <do_fifo+0x23c> /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:571 &(fpga->fifo[i].ctrl), fpga->fifo[i].ctrl); } while (1) { /* wait loop */ while(!got_fifoirq) { count++; e34: 3b ff 00 01 addi r31,r31,1 /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:572 4) This is how the compiler is called for the code file: ppc_4xx-gcc -g -Os -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -D__KERNEL__ -DTEXT_BASE=0xFFF80000 -I/data/home/matthias/projects/pmc405/V2_u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/eldk_400/usr/bin/../lib/gcc/powerpc-linux/4.0.0/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m405 -mcpu=405 -msoft-float -Wall -Wstrict-prototypes -c -o cmd_pmc405v2.o cmd_pmc405v2.c Any idea about what I am doing wrong? BTW: Using -O0 instead of -Os makes everything fine - at least for the code above. Matthias -- ----------------------------------------------------------------------- Dipl.-Ing. Matthias Fuchs esd electronic system design gmbh http://www.esd-electronics.com Vahrenwalder Str. 207 phone: +49-511-37298-0, fax: -68 30165 Hannover, Germany -----------------------------------------------------------------------

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Re: [U-Boot-Users] [PATCH] 83xx: Put the version (and magic) after the HRCW.
by Joakim Tjernlund 07 Dec '06

07 Dec '06

> -----Original Message----- > From: u-boot-users-bounces(a)lists.sourceforge.net > [mailto:u-boot-users-bounces@lists.sourceforge.net] On Behalf > Of Jerry Van Baren > Sent: 07 December 2006 14:23 > To: Joakim Tjernlund > Cc: u-boot-users(a)lists.sourceforge.net > Subject: Re: [U-Boot-Users] [PATCH] 83xx: Put the version > (and magic) after the HRCW. > > Joakim Tjernlund wrote: > >> Sam Song wrote: > >>> Jerry Van Baren <gerald.vanbaren(a)comcast.net> wrote: > >>>> Put the version (and magic) after the HRCW. This > >>>> puts it in a fixed location in flash, not at the > >>> start > >>>> of flash but as close as we can get. > >>> Nice effort. Space saving and better version check. > >>> > >>> I guess the same change could apply for MPC8260/47/8. > >>> > >>> Thanks, > >>> > >>> Sam > >> Yes. Most boards have the version in the first bytes of > >> flash, but this > >> was not possible on the 82xx because of the HRCW, so it was put in > >> .data. This set up was copied for the 83xx (which also has a > >> HRCW). My > >> change moves it back to .text just after the HRCW. I put also the > >> u-boot magic number back in in honor of Wolfgang. ;-) > >> > >> If you change the file names in the patch, it probably would > >> apply. :-) > >> I intend to do this (perhaps literally), but ran out of > >> ambition tonight. > >> > > > > Looks almost the same as the patch I sent the other day. I am good > > with either version. > > > > Jocke > > Hi Jocke, > > Yes, your patch, and my objection to its removal of the HRCW, was the > genesis of this one. The two differences are (a) I kept the HRCW and > (b) I put the "u-boot magic number" in (no known reason to do > this, but > it Just Seemed Right[tm]). The result of (b) is that the > version starts > at flash offset 0x44 rather than 0x40. Should be NBD. (a) yeah, I don't really need this either, I just added that to give others a choice. (b) uh, I want the "u-boot magic number". If I didn't have it in my patch then it was a typo. Thanks Jocke

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Re: [U-Boot-Users] [DNX#2006120742000027] [PATCH] Add support for 8641 Rev 2 silicon.
by DENX Support System 07 Dec '06

07 Dec '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006120742000027] was created: <snip> > From: Ed Swarthout <ed.swarthout(a)freescale.com> > > Without this patch, I am unable to get to the prompt on rev 2 silicon. > Only set ddrioovcr for rev1. > > Signed-off-by: Ed Swarthout<ed.swarthout(a)freescale.com> > Signed-off-by: Jon Loeliger <jdl(a)freescale.com> > --- > cpu/mpc86xx/spd_sdram.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c > index b18e822..ac9ff81 100644 > --- a/cpu/mpc86xx/spd_sdram.c > +++ b/cpu/mpc86xx/spd_sdram.c > @@ -284,9 +284,9 @@ #endif > } > > /* > - * Adjust DDR II IO voltage biasing. It just makes it work. > + * Adjust DDR II IO voltage biasing. Rev1 only > */ > - if (spd.mem_type == SPD_MEMTYPE_DDR2) { > + if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == > SPD_MEMTYPE_DDR2)) { > gur->ddrioovcr = (0 > | 0x80000000 /* Enable */ > | 0x10000000 /* VSEL to 1.8V */ > -- > 1.4.2.3 </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006120742000036] [PATCH] Set Rev 2.x 86xx PIC in mixed mode.
by DENX Support System 07 Dec '06

07 Dec '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006120742000036] was created: <snip> > From: Haiying Wang <haiying.wang(a)freescale.com> > > Prevent false interrupt from hanging Linux as MSR[EE] is set > to enable interrupts by changing the PIC out of the default > pass through mode into mixed mode. > > Signed-off-by: Haiying Wang <haiying.wang(a)freescale.com> > Signed-off-by: Jon Loeliger <jdl(a)freescale.com> > --- > cpu/mpc86xx/interrupts.c | 20 ++++++++++++++++++++ > include/asm-ppc/immap_86xx.h | 2 ++ > 2 files changed, 22 insertions(+), 0 deletions(-) > > diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c > index 1df6cdc..49820bb 100644 > --- a/cpu/mpc86xx/interrupts.c > +++ b/cpu/mpc86xx/interrupts.c > @@ -80,6 +80,26 @@ int interrupt_init(void) > { > int ret; > > + /* > + * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to > + * implement PEX10 errata. As INT is active high, it > + * will cause core to take 0x500 interrupt. > + * > + * Due to the PIC's default pass through mode, as soon > + * as interrupts are enabled (MSR[EE] = 1), an interrupt > + * will be taken and u-boot will hang. This is due to a > + * hardware change (per an errata fix) on new revisions > + * of the board with Rev 2.x parts. > + * > + * Setting the PIC to mixed mode prevents the hang. > + */ > + if ((get_svr() & 0xf0) == 0x20) { > + volatile immap_t *immr = (immap_t *)CFG_IMMR; > + immr->im_pic.gcr = MPC86xx_PICGCR_RST; > + while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); > + immr->im_pic.gcr = MPC86xx_PICGCR_MODE; > + } > + > /* call cpu specific function from $(CPU)/interrupts.c */ > ret = interrupt_init_cpu(&decrementer_count); > > diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h > index a5552c4..0e3fc34 100644 > --- a/include/asm-ppc/immap_86xx.h > +++ b/include/asm-ppc/immap_86xx.h > @@ -721,6 +721,8 @@ typedef struct ccsr_pic { > uint frr; /* 0x41000 - Feature Reporting Register */ > char res10[28]; > uint gcr; /* 0x41020 - Global Configuration Register */ > +#define MPC86xx_PICGCR_RST 0x80000000 > +#define MPC86xx_PICGCR_MODE 0x20000000 > char res11[92]; > uint vir; /* 0x41080 - Vendor Identification Register */ > char res12[12]; > -- > 1.4.2.3 </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006120742000027] [PATCH] Add support for 8641 Rev 2 silicon.
by U-Boot patch tracking system 07 Dec '06

07 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006120742000027]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006120742000036] [PATCH] Set Rev 2.x 86xx PIC in mixed mode.
by U-Boot patch tracking system 07 Dec '06

07 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006120742000036]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006120742000018] [PATCH] Add flash cmd function to 8641HPCN ramboot
by U-Boot patch tracking system 07 Dec '06

07 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006120742000018]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006120742000018] [PATCH] Add flash cmd function to 8641HPCN ramboot [...]
by DENX Support System 07 Dec '06

07 Dec '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006120742000018] was created: <snip> > From: Jason Jin <jason.jin(a)freescale.com> > > Also fixes some commmand for 8641 HPCN ramboot case. > > Signed-off-by: Jason Jin <jason.jin(a)freescale.com> > Signed-off-by: Jon Loeliger <jdl(a)freescale.com> > --- > include/configs/MPC8641HPCN.h | 16 +++------------- > 1 files changed, 3 insertions(+), 13 deletions(-) > > diff --git a/include/configs/MPC8641HPCN.h > b/include/configs/MPC8641HPCN.h > index 4a313af..0e42fa0 100644 > --- a/include/configs/MPC8641HPCN.h > +++ b/include/configs/MPC8641HPCN.h > @@ -212,7 +212,6 @@ #undef CFG_RAMBOOT > #endif > > #if defined(CFG_RAMBOOT) > -#undef CFG_FLASH_CFI_DRIVER > #undef CONFIG_SPD_EEPROM > #define CFG_SDRAM_SIZE 256 > #endif > @@ -468,7 +467,6 @@ #ifndef CFG_RAMBOOT > #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ > #define CFG_ENV_SIZE 0x2000 > #else > - #define CFG_NO_FLASH 1 /* Flash is not usable now */ > #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ > #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) > #define CFG_ENV_SIZE 0x2000 > @@ -486,21 +484,13 @@ #if defined(CFG_RAMBOOT) > | CFG_CMD_SCSI \ > | CFG_CMD_EXT2) \ > & \ > - ~(CFG_CMD_ENV \ > - | CFG_CMD_IMLS \ > - | CFG_CMD_FLASH \ > - | CFG_CMD_LOADS)) > + ~(CFG_CMD_ENV)) > #else > #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ > | CFG_CMD_PING \ > - | CFG_CMD_I2C \ > - | CFG_CMD_SCSI \ > - | CGF_CMD_EXT2) \ > + | CFG_CMD_I2C) \ > & \ > - ~(CFG_CMD_ENV \ > - | CFG_CMD_IMLS \ > - | CFG_CMD_FLASH \ > - | CFG_CMD_LOADS)) > + ~(CFG_CMD_ENV)) > #endif > #else > #if defined(CONFIG_PCI) > -- > 1.4.2.3 </snip> Your U-Boot support team

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[U-Boot-Users] [PATCH] Set Rev 2.x 86xx PIC in mixed mode.
by Jon Loeliger 07 Dec '06

07 Dec '06

From: Haiying Wang <haiying.wang(a)freescale.com> Prevent false interrupt from hanging Linux as MSR[EE] is set to enable interrupts by changing the PIC out of the default pass through mode into mixed mode. Signed-off-by: Haiying Wang <haiying.wang(a)freescale.com> Signed-off-by: Jon Loeliger <jdl(a)freescale.com> --- cpu/mpc86xx/interrupts.c | 20 ++++++++++++++++++++ include/asm-ppc/immap_86xx.h | 2 ++ 2 files changed, 22 insertions(+), 0 deletions(-) diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 1df6cdc..49820bb 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -80,6 +80,26 @@ int interrupt_init(void) { int ret; + /* + * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to + * implement PEX10 errata. As INT is active high, it + * will cause core to take 0x500 interrupt. + * + * Due to the PIC's default pass through mode, as soon + * as interrupts are enabled (MSR[EE] = 1), an interrupt + * will be taken and u-boot will hang. This is due to a + * hardware change (per an errata fix) on new revisions + * of the board with Rev 2.x parts. + * + * Setting the PIC to mixed mode prevents the hang. + */ + if ((get_svr() & 0xf0) == 0x20) { + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_pic.gcr = MPC86xx_PICGCR_RST; + while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); + immr->im_pic.gcr = MPC86xx_PICGCR_MODE; + } + /* call cpu specific function from $(CPU)/interrupts.c */ ret = interrupt_init_cpu(&decrementer_count); diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index a5552c4..0e3fc34 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -721,6 +721,8 @@ typedef struct ccsr_pic { uint frr; /* 0x41000 - Feature Reporting Register */ char res10[28]; uint gcr; /* 0x41020 - Global Configuration Register */ +#define MPC86xx_PICGCR_RST 0x80000000 +#define MPC86xx_PICGCR_MODE 0x20000000 char res11[92]; uint vir; /* 0x41080 - Vendor Identification Register */ char res12[12]; -- 1.4.2.3

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