December 2006 - U-Boot

[U-Boot-Users] [PATCH] Infineon ADM5120 support
by Robert Deliën 11 Dec '06

11 Dec '06

Hi, The patch attached adds support for the Infineon ADM5120 (formerly ADMtek ADM5120) SoC to U-Boot. This SoC can be found in countless low-end router products. See http://www.linux-mips.org/wiki/Adm5120#Products_based_on_the_ADM5120 for a list of devices using the ADM5120. This patch applies cleanly if my previous patches have been applied: 1. pnx8550support.diff 2. nxp_i2c.diff 3. mips_timer2.diff 4. nxp_pci.diff 5. serial_pl010.patch (required) This U-Boot port for ADM5120 is a private project of mine. With kind regards, Robert.

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[U-Boot-Users] (no subject)
by Robert Deliën 11 Dec '06

11 Dec '06

Hi, The patch attached adds support for the Infineon ADM5120 (formerly ADMtek ADM5120) SoC to U-Boot. This SoC can be found in countless low-end router products. See http://www.linux-mips.org/wiki/Adm5120#Products_based_on_the_ADM5120 for a list of devices using the ADM5120. This patch applies cleanly if my previous patches have been applied: 1. pnx8550support.diff 2. nxp_i2c.diff 3. mips_timer2.diff 4. nxp_pci.diff 5. serial_pl010.patch (required) This U-Boot port for ADM5120 is a private project of mine. With kind regards, Robert.

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[U-Boot-Users] [PATCH] NXP Semiconductors PCI IP block driver
by Robert Deliën 11 Dec '06

11 Dec '06

Hi, The patch attached contains a driver for the NXP Semiconductors A051 PCI IP block as present on the PNX8550, PNX8535 and PNX8536. The configuration for the SilverBox development target has been updated for PCI support. This patch applies cleanly if my previous patches have been applied: 1. pnx8550support.diff 2. nxp_i2c.diff 3. mips_timer2.diff 4. nxp_pci.diff Either the driver drivers/pci_indirect.c is not processor endianness independent or the IO functionality for MIPS is a bit outdated. In order to satisfy the need of drivers/pci_indirect.c for prototypes of out_le32 etc, I have added externals for those in include/asm-mips/io.h. With kind regards, Robert.

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[U-Boot-Users] Porting U-Boot to AMCC 440 Spe
by William Oppermann 11 Dec '06

11 Dec '06

Has anybody ported U-Boot to the AMCC 440-Spe processor at PVR version 53421891. 1. We have an AMCC Yucca board using a processor with PVR 53421890 (revA silicon), the start.s code runs fine. 2. When running this same code on our board with PVR version 53421891 (revB silicon) we always have an ESR set to 0x8000000, as soon as we enable the MSR[ME] Bit is set we of course get a machine check. 3. We have tried a Denx patch to write all three words of the TLB table (to make sure no parity errors are occuring) however we still have the problem. 4. We have applied a Denx patch to write the TLB table depending on whether its revA or revB silicon. Neither patch has cured the problem? Has anybody seen this issue ? William Oppermann -- No virus found in this outgoing message. Checked by AVG Free Edition. Version: 7.1.409 / Virus Database: 268.15.15/581 - Release Date: 09/12/2006

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[U-Boot-Users] U-boot - Access to files
by Ram 11 Dec '06

11 Dec '06

Hi, Im trying to provide something like an audio interface to the bootloader. I want to play some audio - (It could be name of the command or simply "Downloading the kernel") - something like that. Basically, What i want is access to some sound data in flash, i have an small audio driver in place in the boot loader, All i want is to download the audio data file sitting somewhere in the flash and access it. It could be a file or it could be some data flashed at some predetermined location in the flash. Does u-boot provide any facility to do that or has anyone tried that in u-boot?. I know this is some kinda of a wired requirement. Please Advice, Regards, sriram

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Re: [U-Boot-Users] [PATCH] MIPS time.c fix
by Robert Deliën 11 Dec '06

11 Dec '06

> The above is not true for all MIPS. A lot (almost all) of older MIPS > parts run the cpu CP0 counter at half the core clock rate. Thanks for your feedback; I wasn't aware of this. I've encountered a couple of /2 constructions in some configurations, but I though that was just a quick fix that degrades the granularity of the timer by half in order to prevent overflows in net.c. > I would suggest changing CPU_CLOCK_RATE to CPU_CP0_COUNT_RATE since > they are not always the same. I have changed it to CFG_CP0_COUNT_RATE, if you don't mind. The IncaIP and Purple platform seem to have cores with half-speed COUNT registers so those have been fixed too. Behold the new patch ;-)

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Re: [U-Boot-Users] location independence
by TXEMA LOPEZ 11 Dec '06

11 Dec '06

Is the part of the U-Boot code that is executed from flash "location independent"? By "location independent" I mean code that can be executed from any address range (in flash) without any modification. The target is MPC85xx. I don't know the details of the MPC85xx architecture, I'm only familiar with the MPC5200 architecture but I think both cases could be familiar. The U-Boot code running from flash is linker address dependent, so you can not, by example, put an image of U-Boot in a different address that it was linked and jump to it from a smaller boot. It is because you must reassign the GOT and the FIXUP sections in a similar way It's done when U-Boot is relocated in RAM.

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Re: [U-Boot-Users] new gatherin
by Korbin Mascarenas 10 Dec '06

10 Dec '06

VfAGRA from $3. 30 and other goods. http://www.zaseruijintunhfeunhans.com through that school of his. So watch out for the Durmstrang champion as well. Okay, said Harry slowly. But... are you saying Karkaroff put my name

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[U-Boot-Users] BDI2000 CFG file for 8560
by Dig Dis 10 Dec '06

10 Dec '06

Hello, Got U-boot programmed on a custom board with the MPC8560 CPU (the board is actually derived from the sbc8560 EVB). I'm tryin to debug it with BDI2000, but I'm facing some startup problems. Before diving in, I'd like to make sure I have the proper configuration file for the BDI. Browsed the denx ftp site, but it only holds some PQ2 based files. Can anyone post a proper 8560 (preferably sbc8560 or ads8560 compatible) cfg file? If there is one, I'd kindly ask to update the ftp as well. Regards, D.

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[U-Boot-Users] AM29LV160DB flash + cfi-driver
by Andre Puschmann 10 Dec '06

10 Dec '06

Hey Folks, we got a custom PPC-based board with a 2MB AM29LV160DB flash chip. I am trying to use U-Boots CFI driver but it seems that there are still some problems with this configuration, reading e.g. the wrong vendor id. This is my output if I boot the board: 0.01> U-Boot 1.1.6-ge4bbd8da-dirty (Dec 8 2006 - 12:25:48) 0.01> 0.01> CPU: MPC5200 v1.2, Core v1.1 at 396 MHz 0.03> Bus 132 MHz, IPB 132 MHz, PCI 33 MHz 0.03> Board: MPC5200 ECU 0.03> I2C: 85 kHz, ready 0.03> DRAM: 8 MB 0.03> Top of RAM usable for U-Boot at: 00800000 0.03> Reserving 164k for U-Boot at: 007d6000 0.04> Reserving 129k for malloc() at: 007b5c00 0.04> Reserving 68 Bytes for Board Info at: 007b5bbc 0.04> Reserving 56 Bytes for Global Data at: 007b5b84 0.04> Stack Pointer at: 007b5b68 0.06> New Stack Pointer is: 007b5b68 0.10> Now running in RAM - U-Boot at: 007d6000 0.10> FLASH: flash detect cfi 0.12> fwc addr ffe00000 cmd 0 0 8bit x 8 bit 0.12> fwc addr ffe00055 cmd 98 98 8bit x 8 bit 0.12> is= cmd 51(Q) addr ffe00010 is= ff 51 0.12> fwc addr ffe00000 cmd 0 0000 16bit x 8 bit 0.14> fwc addr ffe000aa cmd 98 9898 16bit x 8 bit 0.14> is= cmd 51(Q) addr ffe00020 is= ffff 5151 0.14> fwc addr ffe00000 cmd 0 0000 16bit x 16 bit 0.14> fwc addr ffe000aa cmd 98 0098 16bit x 16 bit 0.15> is= cmd 51(Q) addr ffe00020 is= ffff 0051 0.15> fwc addr ffe00000 cmd 0 00000000 32bit x 8 bit 0.15> fwc addr ffe00154 cmd 98 98989898 32bit x 8 bit 0.15> is= cmd 51(Q) addr ffe00040 is= ffffffff 51515151 0.17> fwc addr ffe00000 cmd 0 00000000 32bit x 16 bit 0.17> fwc addr ffe00154 cmd 98 00980098 32bit x 16 bit 0.17> is= cmd 51(Q) addr ffe00040 is= ffffffff 00510051 0.18> fwc addr ffe00000 cmd 0 00000000 32bit x 32 bit 0.18> fwc addr ffe00154 cmd 98 00000098 32bit x 32 bit 0.18> is= cmd 51(Q) addr ffe00040 is= ffffffff 00000051 0.18> fwrite addr ffe00000 cmd 0 0000000000000000 64 bit x 8 bit 0.20> fwrite addr ffe002a8 cmd 98 9898989898989898 64 bit x 8 bit 0.20> is= cmd 51(Q) addr ffe00080 is= ffffffffffffffff 5151515151515151 0.21> fwrite addr ffe00000 cmd 0 0000000000000000 64 bit x 16 bit 0.21> fwrite addr ffe002a8 cmd 98 0098009800980098 64 bit x 16 bit 0.21> is= cmd 51(Q) addr ffe00080 is= ffffffffffffffff 0051005100510051 0.23> fwrite addr ffe00000 cmd 0 0000000000000000 64 bit x 32 bit 0.23> fwrite addr ffe002a8 cmd 98 0000009800000098 64 bit x 32 bit 0.23> is= cmd 51(Q) addr ffe00080 is= ffffffffffffffff 0000005100000051 0.25> fwrite addr ffe00000 cmd 0 0000000000000000 64 bit x 64 bit 0.25> fwrite addr ffe002a8 cmd 98 0000000000000098 64 bit x 64 bit 0.25> is= cmd 51(Q) addr ffe00080 is= ffffffffffffffff 0000000000000051 0.26> not found 0.26> ## Unknown FLASH on Bank 0 - Size = 0x00000000 = 0 MB 0.26> flash_protect ON: from 0xFFF00000 to 0xFFF23FFF 0.26> flash_protect ON: from 0xFFE0FA00 to 0xFFE0FDFF 0.26> *** failed *** 0.28> ### ERROR ### Please RESET the board ### There already was a discussion about this flash chip and u-boot but this thread doesn't came to an end. http://www.nabble.com/Help%3A-flash-driver-for-CFI-complient-flash-t893564.… Any hints? Best regards, Andre

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