December 2006 - U-Boot

[U-Boot-Users] [PATCH] Proposed change to PL010 serial driver
by Robert Deliën 05 Dec '06

05 Dec '06

Hi, I am currently cleaning up my patch that provides ADM5120 support in U-Boot. But before submitting it I'd like to propose a change to the PL010 serial port driver. As far as I know, the PL010 uart is mostly used in ARM based SoCs. It's currently implemented for big endian only. The ADM5120 is MIPS based and has two PL010 serial ports on board. Most of the targets using the ADM5120 are configured for little endian mode. The patch below replaces the IO_READ and IO_WRITE macros with the readl and writel functions from asm/io.h, the designated functions for reading from and writing to IO, swapping endianness if necessary. It also replaces the various bitrate macros with one macro containing a unified bitrate calculation formula, using the newly introduced CFG_UART_PL010_CLOCK macro. The only other target using this serial port driver is intergratorap.h. I have backward calculated the uart clock for this target and added it to its configuration. With kind regards, Robert.

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[U-Boot-Users] dwarf hypothetically
by Clayton 05 Dec '06

05 Dec '06

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[U-Boot-Users] [PATCH] AS352X SOC02:Part03 for U-boot1.1.6
by thomas.luo 05 Dec '06

05 Dec '06

U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525… Part 3: Br Signed-off-by: Thomas Luothomas.luo(a)austriamicrosystems.com -------------------------------------------------------------------------------------------------- diff -upBNr u-boot-1.1.6.org/include/as352x.h u-boot-1.1.6/include/as352x.h --- u-boot-1.1.6.org/include/as352x.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/as352x.h 2006-12-05 09:50:51.000000000 +0800 @@ -0,0 +1,492 @@ +/* +* (C) Copyright 2006 +* Copyright (C) 2006 Austriamicrosystems, by thomas.luo +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ +#ifndef __AS352X_H__ +#define __AS352X_H__ + +#define AS352X_UART_CHANNELS 1 + +/* AS352X only supports 512 Byte HW ECC */ +#define AS352X_ECCSIZE 512 +#define AS352X_ECCBYTES 3 + + +/* AS352X device base addresses */ + + +/* ----------------------------------------------------------------- +* AS352X Registers +* ------------------------------------------------------------------ +* +*/ + + +/* AHB */ +#define AS352X_USB_BASE 0xC6000000 +#define AS352X_VIC_BASE 0xC6010000 +#define AS352X_DMAC_BASE 0xC6020000 +#define AS352X_MPMC_BASE 0xC6030000 +#define AS352X_MEMSTICK_BASE 0xC6040000 +#define AS352X_CF_IDE_BASE 0xC6050000 + +/* APB */ +#define AS352X_NAND_FLASH_BASE 0xC8000000 +#define AS352X_BIST_MANAGER_BASE 0xC8010000 +#define AS352X_SD_MCI_BASE 0xC8020000 +#define AS352X_TIMER_BASE 0xC8040000 +#define AS352X_WDT_BASE 0xC8050000 +#define AS352X_I2C_MS_BASE 0xC8060000 +#define AS352X_I2C_AUDIO_BASE 0xC8070000 +#define AS352X_SSP_BASE 0xC8080000 +#define AS352X_I2SIN_BASE 0xC8090000 +#define AS352X_I2SOUT_BASE 0xC80A0000 +#define AS352X_GPIO1_BASE 0xC80B0000 +#define AS352X_GPIO2_BASE 0xC80C0000 +#define AS352X_GPIO3_BASE 0xC80D0000 +#define AS352X_GPIO4_BASE 0xC80E0000 +#define AS352X_CGU_BASE 0xC80F0000 +#define AS352X_CCU_BASE 0xC8100000 +#define AS352X_UART0_BASE 0xC8110000 +#define AS352X_DBOP_BASE 0xC8120000 + + + +/* ------------------------------------------------------------------------ +* AS352X control registers +* ------------------------------------------------------------------------ +*/ + +#define CCU_SRC ( (AS352X_CCU_BASE) + 0x00) +#define CCU_SRL ( (AS352X_CCU_BASE) + 0x04) +#define CCU_MEMMAP ( (AS352X_CCU_BASE) + 0x08) +#define CCU_IO ( (AS352X_CCU_BASE) + 0x0C) +#define CCU_SCON ( (AS352X_CCU_BASE) + 0x10) +#define CCU_VERS ( (AS352X_CCU_BASE) + 0x14) + + +/** +* Reset Control Lines in CCU_SRC register +**/ +#define CCU_SRC_DBOP_EN ( 1 << 24 ) +#define CCU_SRC_SPDIF_EN ( 1 << 22 ) +#define CCU_SRC_TIMER_EN ( 1 << 21 ) +#define CCU_SRC_SSP_EN ( 1 << 20 ) +#define CCU_SRC_WDO_EN ( 1 << 19 ) +#define CCU_SRC_IDE_EN ( 1 << 18 ) +#define CCU_SRC_IDE_AHB_EN ( 1 << 17 ) +#define CCU_SRC_UART0 ( 1 << 16 ) +#define CCU_SRC_NAF_EN ( 1 << 15 ) +#define CCU_SRC_SDMCI_EN ( 1 << 14 ) +#define CCU_SRC_GPIO_EN ( 1 << 13 ) +#define CCU_SRC_I2C_AUDIO_EN ( 1 << 12 ) +#define CCU_SRC_I2C_EN ( 1 << 11 ) +#define CCU_SRC_MST_EN ( 1 << 10 ) +#define CCU_SRC_I2SIN ( 1 << 9 ) +#define CCU_SRC_I2SOUT ( 1 << 8 ) +#define CCU_SRC_USB_AHB_EN ( 1 << 7 ) +#define CCU_SRC_USB_PHY_EN ( 1 << 6 ) +#define CCU_SRC_DMAC_EN ( 1 << 5 ) +#define CCU_SRC_VIC_EN ( 1 << 4 ) + +/** +* Magic number for CCU_SRL for reset. +**/ +#define CCU_SRL_MAGIC_NUMBER 0x1A720212 + +/** +* Chip select lines for NAF. Use these constants to +*select/deselct the CE lines for NAND flashes in Register CCU_IO. +**/ +#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 ) +#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 ) +#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 ) +#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 ) + +/* CCU IO Select/Deselect IDE */ +#define CCU_IO_IDE ( 1 << 5 ) + +/* CCU IO Select/desect I2C */ +#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 ) + +/* CCU IO Select/desect UART */ +#define CCU_IO_UART0 ( 1 << 0 ) + + +#define CCU_RESET_ALL_BUT_MEMORY \ + ( CCU_SRC_DBOP_EN \ + | CCU_SRC_SPDIF_EN \ + | CCU_SRC_TIMER_EN \ + | CCU_SRC_SSP_EN \ + | CCU_SRC_WDO_EN \ + | CCU_SRC_IDE_EN \ + | CCU_SRC_IDE_AHB_EN \ + | CCU_SRC_UART0 \ + | CCU_SRC_NAF_EN \ + | CCU_SRC_SDMCI_EN \ + | CCU_SRC_GPIO_EN \ + | CCU_SRC_I2C_AUDIO_EN \ + | CCU_SRC_I2C_EN \ + | CCU_SRC_MST_EN \ + | CCU_SRC_I2SIN \ + | CCU_SRC_I2SOUT \ + | CCU_SRC_USB_AHB_EN \ + | CCU_SRC_USB_PHY_EN \ + | CCU_SRC_DMAC_EN \ + | CCU_SRC_VIC_EN \ + ) + +/** +* Magic number for CCU_SRL for reset. +**/ +#define CCU_SRL_MAGIC_NUMBER 0x1A720212 + +/** +* Chip select lines for NAF. Use these constants to select/deselct +* the CE lines for NAND flashes in Register CCU_IO. +**/ +#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 ) +#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 ) +#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 ) +#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 ) + +/* CCU IO Select/Deselect IDE */ +#define CCU_IO_IDE ( 1 << 5 ) + +/* CCU IO Select/desect I2C */ +#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 ) + +/* CCU IO Select/desect UART */ +#define CCU_IO_UART ( 1 << 0 ) + + +#define CCU_COUNT_MIN_10_MICROSEC 640 + +/* ------------------------------------------------------------------------ +* AS352X clock control registers +* ------------------------------------------------------------------------ +*/ + +#define CGU_REG_PLLA ( (AS352X_CGU_BASE) + 0x00 ) +#define CGU_REG_PLLB ( (AS352X_CGU_BASE) + 0x04 ) +#define CGU_REG_PLLASUP ( (AS352X_CGU_BASE) + 0x08 ) +#define CGU_REG_PLLBSUP ( (AS352X_CGU_BASE) + 0x0C ) +#define CGU_REG_PROC ( (AS352X_CGU_BASE) + 0x10 ) +#define CGU_REG_PERI ( (AS352X_CGU_BASE) + 0x14 ) +#define CGU_REG_AUDIO ( (AS352X_CGU_BASE) + 0x18 ) +#define CGU_REG_USB ( (AS352X_CGU_BASE) + 0x1C ) +#define CGU_REG_INTCTRL ( (AS352X_CGU_BASE) + 0x20 ) +#define CGU_REG_IRQ ( (AS352X_CGU_BASE) + 0x24 ) +#define CGU_REG_COUNTA ( (AS352X_CGU_BASE) + 0x28 ) +#define CGU_REG_COUNTB ( (AS352X_CGU_BASE) + 0x2C ) +#define CGU_REG_IDE ( (AS352X_CGU_BASE) + 0x30 ) +#define CGU_REG_MEMSTICK ( (AS352X_CGU_BASE) + 0x34 ) +#define CGU_REG_DBOP ( (AS352X_CGU_BASE) + 0x38 ) + + +/* --- are disabled after reset --- */ +/* dma */ +#define CGU_DMA_CLOCK_ENABLE ( 1 << 22 ) +/* usb */ +#define CGU_USB_CLOCK_ENABLE ( 1 << 21 ) +/* i2sout */ +#define CGU_I2SOUT_APB_CLOCK_ENABLE ( 1 << 20 ) +/* i2sin */ +#define CGU_I2SIN_APB_CLOCK_ENABLE ( 1 << 19 ) +/* i2c master/slave */ +#define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE ( 1 << 18 ) +/* i2c audio master */ +#define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE ( 1 << 17 ) +/* gpio */ +#define CGU_GPIO_CLOCK_ENABLE ( 1 << 16 ) +/* mmc + sd */ +#define CGU_MCI_CLOCK_ENABLE ( 1 << 15 ) +/* naf */ +#define CGU_NAF_CLOCK_ENABLE ( 1 << 14 ) + /* uart */ +#define CGU_UART_APB_CLOCK_ENABLE ( 1 << 13 ) +/* watchdog counter */ +#define CGU_WDOCNT_CLOCK_ENABLE ( 1 << 12 ) + /* watchdog timer module */ +#define CGU_WDOIF_CLOCK_ENABLE ( 1 << 11 ) +/* ssp */ +#define CGU_SSP_CLOCK_ENABLE ( 1 << 10 ) +/* timer 1 */ +#define CGU_TIMER1_CLOCK_ENABLE ( 1 << 9 ) +/* timer 2 */ +#define CGU_TIMER2_CLOCK_ENABLE ( 1 << 8 ) +/* timer interface */ +#define CGU_TIMERIF_CLOCK_ENABLE ( 1 << 7 ) + +/** ------------------------------------------------------------------ +* Number of cycles to wait before cgu is safely locked. +**/ +#define CGU_LOCK_CNT 0xFF + +/* FIFO depth is 16 for tx and rx fifo */ +#define UART_FIFO_DEPTH 16 + +/* ------------------- UART Line Control Register bit fields ------------- */ + +#define UART_LNCTL_DLSEN (1 << 7) /* Device latch select bit */ + + +/* -------------- UART Interrupt Control Register bit fields ---------- */ + +#define UART_INTR_RXDRDY 0x1 /* Data ready interrupt */ +#define UART_INTR_TXEMT 0x2 /* Transmit data empty interrupt */ +#define UART_INTR_RXLINESTATUS 0x4 /* Receive line status interrupt */ + +/* ------------------- UART Line Status Register bit fields ------------- */ + +#define UART_ERRORBITS 0x1E +#define UART_RX_DATA_READY (1 << 0) +#define UART_TX_HOLD_REG_EMPTY (1 << 5) + +/* ------------------- FIFO CNTL Register contants --------------*/ + +#define UART_FIFO_EN (1 << 0) /* Enable the UART FIFO */ +#define UART_TX_FIFO_RST (1 << 1) /* Enable the UART FIFO */ +#define UART_RX_FIFO_RST (1 << 2) +#define UART_RXFIFO_TRIGLVL_1 (0 << 4) /* RX FIFO TRIGGER_LEVEL 1 */ +#define UART_RXFIFO_TRIGLVL_4 0x08 /* RX FIFO TRIGGER_LEVEL 4 */ +#define UART_RXFIFO_TRIGLVL_8 0x10 /* RX FIFO TRIGGER_LEVEL 8 */ +#define UART_RXFIFO_TRIGLVL_14 0x18 /* RX FIFO TRIGGER_LEVEL 14 */ + + +/* ------------------- FIFO status Register contants -----------*/ +#define UART_TX_FIFO_FULL (1 << 0) +#define UART_RX_FIFO_FULL (1 << 1) +#define UART_TX_FIFO_EMPTY (1 << 2) +#define UART_RX_FIFO_EMPTY (1 << 3) + + +/* ----------------------- defines -------------------------------------- */ +/* Data register */ +#define UART_DATA_REG ( (AS352X_UART0_BASE) + 0x00 ) +/* Clock divider(lower byte) register */ +#define UART_DLO_REG ( (AS352X_UART0_BASE) + 0x00 ) +/* Clock divider(higher byte) register */ +#define UART_DHI_REG ( (AS352X_UART0_BASE) + 0x04 ) +/* Interrupt enable register */ +#define UART_INTEN_REG ( (AS352X_UART0_BASE) + 0x04 ) +/* Interrupt status register */ +#define UART_INTSTATUS_REG ( (AS352X_UART0_BASE) + 0x08 ) +/* Fifo control register */ +#define UART_FCTL_REG ( (AS352X_UART0_BASE) + 0x0C ) +/* Fifo status register */ +#define UART_FSTATUS_REG ( (AS352X_UART0_BASE) + 0x0C ) +/* Line control register */ +#define UART_LNCTL_REG ( (AS352X_UART0_BASE) + 0x10 ) +/* Line status register */ +#define UART_LNSTATUS_REG ( (AS352X_UART0_BASE) + 0x14 ) + +/* 32-bit width */ +#define TIMER_LOAD ( (AS352X_TIMER_BASE) + 0x00 ) +/* 32 bit width */ +#define TIMER_VALUE ( (AS352X_TIMER_BASE) + 0x04 ) +/* 8 bit width */ +#define TIMER_CONTROL ( (AS352X_TIMER_BASE) + 0x08 ) +/* clears ir by write access */ +#define TIMER_INTCLR ( (AS352X_TIMER_BASE) + 0x0C ) +/* 1 bit width */ +#define TIMER_RIS ( (AS352X_TIMER_BASE) + 0x10 ) + /* 1 bit width */ +#define TIMER_MIS ( (AS352X_TIMER_BASE) + 0x14 ) + +/** +* Counter/Timer control register bits +**/ +#define TIMER_ENABLE 0x80 +#define TIMER_PERIODIC 0x40 +#define TIMER_INT_ENABLE 0x20 +#define TIMER_32_BIT 0x02 +#define TIMER_ONE_SHOT 0x01 +#define TIMER_PRESCALE_1 0x00 +#define TIMER_PRESCALE_16 0x04 +#define TIMER_PRESCALE_256 0x08 + + + +#define NAF_CONFIG ( (AS352X_NAND_FLASH_BASE) + 0x00 ) +#define NAF_CONTROL ( (AS352X_NAND_FLASH_BASE) + 0x04 ) +#define NAF_ECC ( (AS352X_NAND_FLASH_BASE) + 0x08 ) +#define NAF_DATA ( (AS352X_NAND_FLASH_BASE) + 0x0C ) +#define NAF_MODE ( (AS352X_NAND_FLASH_BASE) + 0x10 ) +#define NAF_STATUS ( (AS352X_NAND_FLASH_BASE) + 0x14 ) +#define NAF_MASK ( (AS352X_NAND_FLASH_BASE) + 0x18 ) +#define NAF_FIFODATA ( (AS352X_NAND_FLASH_BASE) + 0x1C ) +#define NAF_WORDS ( (AS352X_NAND_FLASH_BASE) + 0x20 ) +#define NAF_CLEAR ( (AS352X_NAND_FLASH_BASE) + 0x24 ) +#define NAF_TEST ( (AS352X_NAND_FLASH_BASE) + 0x28 ) + +/* Macro introduced to compensate for no support for floating +point division operation in the processor. So to get the correct value, +roundup is peformed to provide accurate results for certain conditions. */ + +#define DIVIDE_AND_ROUND_UP(dividend,divisor) \ + ( ( (dividend) + (divisor) - 1 ) / (divisor) ) + +/* For sake of completness and for easier exchanging of +round-up and round-down divisions provide also a round-down macro */ + +#define DIVIDE_AND_ROUND_DOWN( a , b ) ((a)/(b)) + +/* Macro which evaluates to the absolute value of an integer value*/ +#define ABS(A) (((A)>0)?(A):(-(A))) + + +/* ------------------------defines for Dynamic Mem ----------------- */ +#define AS352X_SDRAM_BASE_ADDR(offset) (0xc6030000 + offset) + +#define AS352X_MPMC_CONTROL AS352X_SDRAM_BASE_ADDR( 0x00 ) +#define AS352X_MPMC_CONFIG AS352X_SDRAM_BASE_ADDR( 0x08 ) +#define AS352X_MPMC_DYRDCFG AS352X_SDRAM_BASE_ADDR( 0x28 ) +#define AS352X_MPMC_DYTRP AS352X_SDRAM_BASE_ADDR( 0x30 ) +#define AS352X_MPMC_DYTRAS AS352X_SDRAM_BASE_ADDR( 0x34 ) +#define AS352X_MPMC_DYTSREX AS352X_SDRAM_BASE_ADDR( 0x38 ) +#define AS352X_MPMC_DYTAPR AS352X_SDRAM_BASE_ADDR( 0x3C ) +#define AS352X_MPMC_DYTDAL AS352X_SDRAM_BASE_ADDR( 0x40 ) +#define AS352X_MPMC_DYTWR AS352X_SDRAM_BASE_ADDR( 0x44 ) +#define AS352X_MPMC_DYTRC AS352X_SDRAM_BASE_ADDR( 0x48 ) +#define AS352X_MPMC_DYTRFC AS352X_SDRAM_BASE_ADDR( 0x4C ) +#define AS352X_MPMC_DYTXSR AS352X_SDRAM_BASE_ADDR( 0x50 ) +#define AS352X_MPMC_DYTRRD AS352X_SDRAM_BASE_ADDR( 0x54 ) +#define AS352X_MPMC_DYTMRD AS352X_SDRAM_BASE_ADDR( 0x58 ) +#define AS352X_MPMC_DYRASCAS0 AS352X_SDRAM_BASE_ADDR( 0x104 ) +#define AS352X_MPMC_DYCONFIG0 AS352X_SDRAM_BASE_ADDR( 0x100 ) +#define AS352X_MPMC_DYCNTL AS352X_SDRAM_BASE_ADDR( 0x20 ) +#define AS352X_MPMC_DYREF AS352X_SDRAM_BASE_ADDR( 0x24 ) + +/* --- MT48LC4M16A2 SDRAM & MT48LC32M16A2 SDRAM ----------------- */ +#define MPMC_DY_TRP_IN_NS 20 +#define MPMC_CLK_IN_MHZ_MIN 20 +#define MPMC_1_CLKCYCLE_IN_NS_MIN 50 + +#define MPMC_CLK_IN_MHZ 66 +#if MPMC_CLK_IN_MHZ == 24 +#define MPMC_1_CLKCYCLE_IN_NS 42 +#elif MPMC_CLK_IN_MHZ == 66 +#define MPMC_1_CLKCYCLE_IN_NS 16 +#else +#define MPMC_1_CLKCYCLE_IN_NS 16 +#endif +#define MPMC_SDRAM_TCK_IN_NS 10 + +#define MPMC_DY_TRAS_MIN_IN_NS 50 +#define MPMC_DY_TRAS_IN_NS MPMC_DY_TRAS_MIN_IN_NS + +/* tAPR not available for micron MT48LC4M16A2 SDRAM */ +#define MPMC_DY_TAPR_INNS 0 + +#define MPMC_DY_TDAL_IN_NS (5 * (MPMC_SDRAM_TCK_IN_NS)) + +/* tWR can be minimum 15ns or 1CLK * 7ns */ +#define MPMC_DY_TWR_IN_NS (MPMC_1_CLKCYCLE_IN_NS + 8) +#define MPMC_DY_TRC_IN_NS 70 + +#define MPMC_DY_TRFC_INNS 70 + +#define MPMC_DY_TXSR_IN_NS 80 + +#define MPMC_DY_TRRD_IN_NS 20 +#define MPMC_DY_TMRD_IN_NS (2 * (MPMC_SDRAM_TCK_IN_NS)) + +#define MPMC_SDRAM_CAS 0x2 +#define MPMC_SDRAM_RAS 0x2 /* hha??? */ + +/* Low Power device bit settings */ +/* Device Type for APP Board 2.0 and 1.0 */ +/* MT48LC32M16A2 - 512Mbit and MT48LC4M16 - 64Mbit -both NOT Low Power */ +#define MPMC_SDRAM_DEVICE_TYPE (0 << 3) + +/*ROW and COLUMN size mapping for mpmc SoC device */ + +/* Addr Mapping for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +#define MPMC_SDRAM_ADDR_MAPPING (0x11 << 7) + +#define MPMC_SDRAM_32BIT_EXTBUS (0 <<14) +#define MPMC_SDRAM_BUFFER_DISABLE (0 <<19) +#define MPMC_SDRAM_BUFFER_ENABLE (1 <<19) +#define MPMC_SDRAM_WP_ENABLE (0 <<20) + +#define MPMC_SDRAM_DYN_CONFIG ((MPMC_SDRAM_DEVICE_TYPE) | \ + (MPMC_SDRAM_ADDR_MAPPING) | \ + (MPMC_SDRAM_32BIT_EXTBUS) | \ + (MPMC_SDRAM_BUFFER_DISABLE) | \ + (MPMC_SDRAM_WP_ENABLE)) + +#define MPMC_SDRAM_START_2_REF_CYCLES 2 +/* TREF for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +/*64ms divided by 8192 */ +#define MPMC_SDRAM_tREF_inNs 7812 + + +#define MPMC_SDRAM_DYNAMIC_REF ((MPMC_SDRAM_tREF_inNs) \ + / (MPMC_1_CLKCYCLE_IN_NS_MIN)) + +/* CAS Latency for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +#if MPMC_SDRAM_CAS == 2 +#define MPMC_SDRAM_MODEVALUE (0x23 << 13) +#else +#define MPMC_SDRAM_MODEVALUE (0x33 << 13) +#endif +/* Quarter Strength*/ +#define MPMC_SDRAM_EXMODEVALUE ((0x40 << 12) | (0x1 << 11)) + +#define set_reg_bits32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) |= ( (u32)(value) ) ) + + +#define clr_reg_bits32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) &= ( ~( (u32)(value) ) ) ) + +#define read_reg32( registerAddress ) \ + ( *( ( const volatile u32 * )( registerAddress ) ) ) + +#define write_reg32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) = ( (u32)(value) ) ) + + + +#define read_reg16( registerAddress ) \ + ( *( ( const volatile u16 * )( registerAddress ) ) ) + +#define write_reg16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) = ( (u16)(value) ) ) + +#define set_reg_bits16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) |= ( (u16)(value) ) ) + +#define clr_reg_bits16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) &= ( ~( (u16)(value) ) ) ) + + +#define read_reg8( registerAddress ) \ + ( *( ( const volatile u8 * )( registerAddress ) ) ) + +#define write_reg8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) = ( (u8)(value) ) ) + +#define set_reg_bits8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) |= ( (u8)(value) ) ) + +#define clr_reg_bits8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) &= ( ~( (u8)(value) ) ) ) +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#endif /*__AS352X_H__*/ diff -upBNr u-boot-1.1.6.org/include/asm-arm/mach-types.h u-boot-1.1.6/include/asm-arm/mach-types.h --- u-boot-1.1.6.org/include/asm-arm/mach-types.h 2006-12-01 17:49:35.000000000 +0800 +++ u-boot-1.1.6/include/asm-arm/mach-types.h 2006-12-01 18:01:45.000000000 +0800 @@ -737,6 +737,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 #define MACH_TYPE_PDNB3 1002 +#define MACH_TYPE_AS352X 1166 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -6054,7 +6055,7 @@ extern unsigned int __machine_arch_type; # define machine_is_ess710() (0) #endif -#ifdef CONFIG_MACH_MX3ADS +#ifdef CONFIG_MACH_MX31ADS # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type @@ -9401,6 +9402,18 @@ extern unsigned int __machine_arch_type; #else # define machine_is_mp2usb() (0) #endif +#ifdef CONFIG_MACH_AS352X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS352X +# endif +# define machine_is_as352x() (machine_arch_type == MACH_TYPE_AS352X) +#else +# define machine_is_as352x() (0) +#endif + /* * These have not yet been registered diff -upBNr u-boot-1.1.6.org/include/configs/as352xpb.h u-boot-1.1.6/include/configs/as352xpb.h --- u-boot-1.1.6.org/include/configs/as352xpb.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/configs/as352xpb.h 2006-12-05 16:06:36.000000000 +0800 @@ -0,0 +1,232 @@ +/* +* (C) Copyright 2006 +* Copyright (C) 2006 Austriamicrosystems, by thomas.luo +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* +* High Level Configuration Options +* (easy to change) +*/ +#define CONFIG_ARM922T 1 /* This is an ARM922T Core */ +#define CONFIG_AS352X 1 /* in a AS352X SoC */ +#define CONFIG_AS352XPB 1 /* on a AS352XPB Board */ +#define CFG_NO_FLASH 1 + +/* input clock of PLL */ +/* the AS352XPB has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + + +#define USE_922T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* +* Size of malloc() pool +*/ +#define CFG_MALLOC_LEN (((CFG_ENV_SIZE + 128*1024 + 0x4000-1) \ + /0x4000)*0x4000) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 128 + +/* +* Hardware drivers +*/ + +/* +* select serial console configuration +*/ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on AS352XPB */ + +/************************************************************ +* RTC +************************************************************/ +#define CONFIG_RTC_AS352X 0 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +/*********************************************************** +* Command definition +***********************************************************/ +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + /* CFG_CMD_CACHE |*/ \ + CFG_CMD_NAND | \ + /*CFG_CMD_EEPROM |*/ \ + /*CFG_CMD_I2C |*/ \ + /*CFG_CMD_USB |*/ \ + CFG_CMD_REGINFO \ + /*CFG_CMD_ELF*/ )& ~(CFG_CMD_FLASH| \ + CFG_CMD_IMLS|CFG_CMD_NET|CFG_CMD_XIMG)) +/*this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTARGS "root=/dev/ram0 rw init=/linuxrc console=ttyS0 mem=64M" +#define CONFIG_BOOTCOMMAND "nand read 0x30007FC0 0x80000 0x200000; \ +nand read 0x32000000 0x280000 0x420000;bootm 0x30007FC0 0x32000000" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "autoboot in %d seconds (stop with 's')...\n" +#define CONFIG_AUTOBOOT_STOP_STR "s" +/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ +/*#define CONFIG_NETMASK 255.255.255.0*/ +/*#define CONFIG_IPADDR 10.0.0.110*/ +/*#define CONFIG_SERVERIP 10.0.0.1*/ +/*#define CONFIG_BOOTFILE "" */ +/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +/* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 +/* what's this ? it's not used anywhere */ +/* which serial port to use */ +#define CONFIG_KGDB_SER_INDEX 1 +#endif + +#undef CFG_ENV_IS_IN_FLASH +/* +* Miscellaneous configurable options +*/ +#define CFG_LONGHELP 1 /* undef to save memory*/ +/* Monitor Command Prompt */ +#define CFG_PROMPT "AS352X # " +#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 8 /* max number of command args*/ +/* Boot Argument Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE + +#define CFG_MEMTEST_START 0x30000000 /* memtest works on*/ +#define CFG_MEMTEST_END 0x33F00000/* 63 MB in DRAM*/ +/* everything, incl board info, in Hz */ +#undef CFG_CLKS_IN_HZ +/* default load address */ +#define CFG_LOAD_ADDR 0x30008000 + +#define CFG_HZ 1500000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_ENV_IS_IN_NAND 1 + +#define CFG_ENV_NAND_ERASE_SIZE 0x20000 +/* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x800 +#if CFG_ENV_IS_IN_NAND +#define CFG_ENV_OFFSET 0x60000 + +#endif +/*------------------------------------------------------------------ +* Stack sizes +* +* The stack sizes are set up in start.S using the settings below +*/ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*------------------------------------------------------------------- +* Physical Memory Map +*/ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*------------------------------------------------------------------- +* FLASH and environment organization +*/ +/* uncomment this if you have a LV400 flash */ +#define CONFIG_AMD_LV400 0 +#if 0 +/* uncomment this if you have a LV800 flash */ +#define CONFIG_AMD_LV800 1 +#endif + +#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks*/ +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +/* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT (19) +/* addr of environment */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) +#endif +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +/* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT (11) +/* addr of environment */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) +#endif + + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices*/ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + + +#define NAND_DISABLE_CE(nand) do { } while(0) +#define NAND_ENABLE_CE(nand) do { } while(0) + +#define NAND_WAIT_READY(nand) + +#define WRITE_NAND_COMMAND(d, adr) do{ } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ } while(0) +#define WRITE_NAND(d, adr) do{} while(0) +#define READ_NAND(adr) () +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +/* timeout values are in ticks */ +/* Timeout for Flash Erase */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) +/* Timeout for Flash Write */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) + +#include <as352x.h> +#define CFG_NAND_BASE NAF_DATA +#include <cmd_confdefs.h> + +#define NAND_ALLOW_ERASE_ALL + + + +#endif /* __CONFIG_H */ diff -upBNr u-boot-1.1.6.org/MAINTAINERS u-boot-1.1.6/MAINTAINERS --- u-boot-1.1.6.org/MAINTAINERS 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/MAINTAINERS 2006-12-04 10:20:27.000000000 +0800 @@ -566,6 +566,17 @@ Zachary P. Landau <zachary.landau@labxte Haavard Skinnemoen <hskinnemoen(a)atmel.com> ATSTK1000 AT32AP7000 +######################################################################### +# AS352X Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Thomas Luo <thomas.luo(a)austriamicrosystems.com> + + AS352XPB AS352X + ######################################################################### # End of MAINTAINERS list # diff -upBNr u-boot-1.1.6.org/MAKEALL u-boot-1.1.6/MAKEALL --- u-boot-1.1.6.org/MAKEALL 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/MAKEALL 2006-12-04 10:20:27.000000000 +0800 @@ -189,13 +189,13 @@ LIST_ARM7=" \ LIST_ARM9=" \ at91rm9200dk cmc_pu2 \ ap920t ap922_XA10 ap926ejs ap946es \ - ap966 cp920t cp922_XA10 cp926ejs \ + ap966 cp920t cp922t cp922_XA10 cp926ejs \ cp946es cp966 lpd7a400 mp2usb \ mx1ads mx1fs2 netstar omap1510inn \ omap1610h2 omap1610inn omap730p2 sbc2410x \ scb9328 smdk2400 smdk2410 trab \ VCMA9 versatile versatileab versatilepb \ - voiceblue \ + voiceblue as3525pb \ " ######################################################################### diff -upBNr u-boot-1.1.6.org/Makefile u-boot-1.1.6/Makefile --- u-boot-1.1.6.org/Makefile 2006-12-01 17:49:33.000000000 +0800 +++ u-boot-1.1.6/Makefile 2006-12-04 10:20:27.000000000 +0800 @@ -2253,6 +2253,9 @@ atstk1002_config : unconfig @./mkconfig $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000 ######################################################################### +as352xpb_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm922t as352xpb NULL as352x + ######################################################################### #########################################################################

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[U-Boot-Users] [PATCH] AS352X SOC02:Part02 for U-boot1.1.6
by thomas.luo 05 Dec '06

05 Dec '06

U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525… Part 2: Br Signed-off-by: Thomas Luothomas.luo(a)austriamicrosystems.com -------------------------------------------------------------------------------------------------- diff -upBNr u-boot-1.1.6.org/cpu/arm922t/as352x/serial.c u-boot-1.1.6/cpu/arm922t/as352x/serial.c --- u-boot-1.1.6.org/cpu/arm922t/as352x/serial.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/serial.c 2006-12-04 10:30:49.000000000 +0800 @@ -0,0 +1,145 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#if defined(CONFIG_AS352X) +#include <as352x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* +* Initialise the serial port with the given baudrate. The settings +* are always 8 data bits, no parity, 1 stop bit, no start bits. +*/ +void serial_setbrg (void) +{ + u8 controlData; + set_reg_bits32(CCU_IO,CCU_IO_UART); + + /* reset the uart + */ + set_reg_bits32(CCU_SRC, CCU_SRC_UART0); + write_reg32(CCU_SRL, CCU_SRL_MAGIC_NUMBER); + clr_reg_bits32(CCU_SRC, CCU_SRC_UART0); + write_reg32(CCU_SRL, 0x0); + write_reg32(UART_FCTL_REG, 0); + write_reg32(UART_INTEN_REG, 0); + controlData = 3; + write_reg32(UART_LNCTL_REG,controlData| UART_LNCTL_DLSEN); + write_reg32(UART_DLO_REG,0x68); + write_reg32(UART_DHI_REG,0x0); + write_reg32(UART_LNCTL_REG,controlData& (~UART_LNCTL_DLSEN)); + +} +int serial_init (void) +{ + int i; + serial_setbrg(); + for (i = 0; i < 100; i++); + return (0); +} + +/* +* Read a single byte from the serial port. Returns 1 on success, 0 +* otherwise. When the function is succesfull, the character read is +* written into its argument c. +*/ +int serial_getc (void) +{ + u8 c; + + while (!(read_reg32(UART_LNSTATUS_REG) & UART_RX_DATA_READY)); + c = read_reg32(UART_DATA_REG); + return c&0xff; +} + +#ifdef CONFIG_HWFLOW +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ + switch(on) { + case 0: + default: + break; /* return current */ + case 1: + hwflow = 0; /* turn on */ + break; + case -1: + hwflow = 0; /* turn off */ + break; + } + return hwflow; +} +#endif + +#ifdef CONFIG_MODEM_SUPPORT +static int be_quiet = 0; +void disable_putc(void) +{ + be_quiet = 1; +} + +void enable_putc(void) +{ + be_quiet = 0; +} +#endif + + +/* +* Output a single byte to the serial port. +*/ +void serial_putc (const char c) +{ +#ifdef CONFIG_MODEM_SUPPORT + if (be_quiet) + return; +#endif + + /* wait for room in the tx FIFO */ + while (!(read_reg32(UART_LNSTATUS_REG) & UART_TX_HOLD_REG_EMPTY)); + write_reg32(UART_DATA_REG,c); + + + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* +* Test whether a character is in the RX buffer +*/ +int serial_tstc (void) +{ + return (read_reg32(UART_LNSTATUS_REG) & UART_RX_DATA_READY); +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#endif /* defined(CONFIG_AS352X)*/ diff -upBNr u-boot-1.1.6.org/cpu/arm922t/config.mk u-boot-1.1.6/cpu/arm922t/config.mk --- u-boot-1.1.6.org/cpu/arm922t/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/config.mk 2006-11-24 16:43:15.000000000 +0800 @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + + +PLATFORM_CPPFLAGS += -march=armv4 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff -upBNr u-boot-1.1.6.org/cpu/arm922t/cpu.c u-boot-1.1.6/cpu/arm922t/cpu.c --- u-boot-1.1.6.org/cpu/arm922t/cpu.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/cpu.c 2006-12-04 09:51:34.000000000 +0800 @@ -0,0 +1,194 @@ +/* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Marius Groeger <mgroeger(a)sysgo.de> +* +* (C) Copyright 2002 +* Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +/* +* CPU specific code +*/ + +#include <common.h> +#include <command.h> +#include <arm922t.h> + +#ifdef CONFIG_USE_IRQ +DECLARE_GLOBAL_DATA_PTR; +#endif + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + +#ifdef MMU_DEBUG + printf ("p15/c1 is = %08lx\n", value); +#endif + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ +#ifdef MMU_DEBUG + printf ("write %08lx to p15/c1\n", value); +#endif + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM922T Technical reference Manual */ +/* mmu off/on */ +#define C1_MMU (1<<0) +/* alignment faults off/on */ +#define C1_ALIGN (1<<1) +/* dcache off/on */ +#define C1_DC (1<<2) + +/* big endian off/on */ +#define C1_BIG_ENDIAN (1<<7) +/* system protection */ +#define C1_SYS_PROT (1<<8) +/* ROM protection */ +#define C1_ROM_PROT (1<<9) +/* icache off/on */ +#define C1_IC (1<<12) +/* location of vectors: low/high addresses */ +#define C1_HIGH_VECTORS (1<<13) + + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + IRQ_STACK_START = _armboot_start - + CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + /* get control reg. */ + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IC) != 0; +} + +#ifdef USE_922T_MMU +/* It makes no sense to use the dcache if the MMU is not enabled */ +void dcache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_DC); +} + +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + reg &= ~C1_DC; + write_p15_c1 (reg); +} + +int dcache_status (void) +{ + return (read_p15_c1 () & C1_DC) != 0; +} +#endif diff -upBNr u-boot-1.1.6.org/cpu/arm922t/interrupts.c u-boot-1.1.6/cpu/arm922t/interrupts.c --- u-boot-1.1.6.org/cpu/arm922t/interrupts.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/interrupts.c 2006-11-23 17:01:25.000000000 +0800 @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <arm920t.h> +#include <asm/proc-armv/ptrace.h> + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} diff -upBNr u-boot-1.1.6.org/cpu/arm922t/Makefile u-boot-1.1.6/cpu/arm922t/Makefile --- u-boot-1.1.6.org/cpu/arm922t/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/Makefile 2006-11-02 22:15:02.000000000 +0800 @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = cpu.o interrupts.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -upBNr u-boot-1.1.6.org/cpu/arm922t/start.S u-boot-1.1.6/cpu/arm922t/start.S --- u-boot-1.1.6.org/cpu/arm922t/start.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/start.S 2006-11-30 10:25:41.000000000 +0800 @@ -0,0 +1,353 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * relocate armboot to ram + * setup stack + * jump to second stage + * + ************************************************************************* + */ + +RAM_END: + .word 0x50000 + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word _end+200 + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word _end+400 +#endif + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + /* Set up the stack */ +stack_setup: + ldr r0, RAM_END /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + ldr r0,RAM_END + ldr r1,_bss_end + str r0,_armboot_start + add r1,r1,r0 + str r1,_bss_end + ldr r1,_bss_start + add r1,r1,r0 + str r1,_bss_start + ldr pc,_start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + mrc p15, 0, r0, c1, c0, 0 @ read CP15 register 1 into r0 + bic r0, r0, #0x0001 @ clear bit 0 MMU disable + bic r0, r0, #0x0004 @ clear bit 2 D-cache disable + bic r0, r0, #0x1000 @ clear bit 12 I-cache disable + bic r0, r0, #0xc0000000 @ clear bit 30,31 fast bus mode + mcr p15, 0, r0, c1, c0, 0 @ write value back + + @ invalidate all caches to have a clean startup + mov r2, #0 + mcr p15, 0, r2, c7, c7, 0 @ Invalidate D- and I-Cache + mcr p15, 0, r2, c8, c7, 0 @ invalidate all TLBs + + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + mov ip, lr + bl lowlevel_init + mov lr, ip + mov pc, lr +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get pc, cpsr + add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif diff -upBNr u-boot-1.1.6.org/CREDITS u-boot-1.1.6/CREDITS --- u-boot-1.1.6.org/CREDITS 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/CREDITS 2006-12-04 10:20:27.000000000 +0800 @@ -465,3 +465,8 @@ N: James MacAulay E: james.macaulay(a)amirix.com D: Suppport for Amirix AP1000 W: www.amirix.com + +N: Thomas Luo +E: thomas.luo(a)austriamicrosystems.com +D: Port to ARM base SOC AS352X. +W: www.austriamicrosystems.com diff -upBNr u-boot-1.1.6.org/include/arm922t.h u-boot-1.1.6/include/arm922t.h --- u-boot-1.1.6.org/include/arm922t.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/arm922t.h 2006-11-23 16:30:48.000000000 +0800 @@ -0,0 +1,12 @@ +/************************************************ + * NAME : arm922t.h + * Version : 30 April 2002 * + * + * empty for now + ************************************************/ + +#ifndef __ARM922T_H__ +#define __ARM922T_H__ + + +#endif /*__ARM922T_H__*/

1 0

[U-Boot-Users] [PATCH] AS352X SOC02:Part01 for U-boot1.1.6
by thomas.luo 05 Dec '06

05 Dec '06

U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525… Part 1: Br Signed-off-by: Thomas Luothomas.luo(a)austriamicrosystems.com -------------------------------------------------------------------------------------------------- diff -upBNr u-boot-1.1.6.org/board/as352xpb/as352xpb.c u-boot-1.1.6/board/as352xpb/as352xpb.c --- u-boot-1.1.6.org/board/as352xpb/as352xpb.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/as352xpb.c 2006-12-05 09:45:02.000000000 +0800 @@ -0,0 +1,212 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <as352x.h> + +DECLARE_GLOBAL_DATA_PTR; + + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} +void sdram_init(void ) +{ + volatile u32 temp; + *(volatile u32 *)AS352X_MPMC_CONTROL = 0x00000001; + *(volatile u32 *)(AS352X_MPMC_CONFIG) = 0x00000000; + *(volatile u32 *)(AS352X_MPMC_DYRDCFG) = 0x00000001; + /* MPMCDynamicRP setup */ + *(volatile u32 *)(AS352X_MPMC_DYTRP) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRP_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)) ; + /* MPMCDytRAS setup */ + *(volatile u32 *)(AS352X_MPMC_DYTRAS) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRAS_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamicSREX */ + *(volatile u32 *)(AS352X_MPMC_DYTSREX) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TXSR_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictAPR */ + *(volatile u32 *)(AS352X_MPMC_DYTAPR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TAPR_INNS), + (MPMC_1_CLKCYCLE_IN_NS)); + *(volatile u32 *)(AS352X_MPMC_DYTDAL) = + (1+(DIVIDE_AND_ROUND_UP((MPMC_DY_TDAL_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)))); + /* Setup MPMCDynamictWR */ + *(volatile u32 *)(AS352X_MPMC_DYTWR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TWR_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictRC */ + *(volatile u32 *)(AS352X_MPMC_DYTRC) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRC_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictRFC */ + *(volatile u32 *)(AS352X_MPMC_DYTRFC) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRFC_INNS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictXSR */ + *(volatile u32 *)(AS352X_MPMC_DYTXSR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TXSR_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictRRD */ + *(volatile u32 *)(AS352X_MPMC_DYTRRD) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRRD_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictMRD */ + *(volatile u32 *)(AS352X_MPMC_DYTMRD) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TMRD_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + *(volatile u32 *)(AS352X_MPMC_DYRASCAS0) = + ((MPMC_SDRAM_CAS << 0x8) | (MPMC_SDRAM_RAS)); + *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) = MPMC_SDRAM_DYN_CONFIG; + + /*wait for 200uS by performing dummy + read operation which consumes two */ + /* clock cycles for each operation */ + delay(200); + + /* apply NOP */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000183; + delay(1); + /* write to MPMCDyCntl reg to start PRECHARGing: PRECHARGE ALL */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000103; + delay(100); + /* start two auto refresh */ + *(volatile u32 *)(AS352X_MPMC_DYREF) = + MPMC_SDRAM_START_2_REF_CYCLES ; + /*- wait for 64 clk cycles of HCLK-*/ + delay(128); + /* Program the operational value of the Refresh cycles, + depending upon the device specified period */ + *(volatile u32 *)(AS352X_MPMC_DYREF) = + MPMC_SDRAM_DYNAMIC_REF / 16; + + /* Send the Mode set command to SDRAM */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000083; + + /*------------------------------------------------------------*/ + + /* Read the SDRAM address with the mode value */ + temp = *(volatile u32 *) (0x30000000 + MPMC_SDRAM_MODEVALUE) ; + + /* Merged with S.U. */ +#ifdef SDRAM_MT48H8M16LF + /* (MT48H8M16LF - 128Mbit - Low Power) */ + temp = *(volatile u32 *) (0x30000000 + MPMC_SDRAM_EXMODEVALUE) ; +#endif /*SDRAM_MT48H8M16LF*/ + /*--------------------------------------*/ + /* Send the Normal mode set command to the SDRAM */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000003; + /* Enable the buffer for the SDRAM */ + temp = *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) ; + *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) = + temp | (MPMC_SDRAM_BUFFER_ENABLE); +} + +/*Miscellaneous platform dependent initialisations*/ +void ccu_reset_device +( u32 device_mask + ) +{ + int i; + /* reset devices */ + write_reg32( CCU_SRC, device_mask ); + write_reg32( CCU_SRL, CCU_SRL_MAGIC_NUMBER ); + /* hold the reset for at least 10 microseconds */ + for ( i = CCU_COUNT_MIN_10_MICROSEC; i > 0; i-- ){ + write_reg32( CCU_SRL, CCU_SRL_MAGIC_NUMBER ); + } + /* remove lock */ + write_reg32( CCU_SRL, 0 ); + write_reg32( CCU_SRC, 0 ); +} + +void clk_set_async_mode() +{ + unsigned long i; + /* read CP15 register 1 into r0*/ + asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i)); + /*enable asynchronous clocking mode*/ + asm("orr r0, %0, #(0x3 <<30) ": :"r"(i)); + /* write cp15 register 1*/ + asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i)); +} + +int board_init (void) +{ + ccu_reset_device( CCU_RESET_ALL_BUT_MEMORY ); + /*init cgu regs*/ + write_reg32(CGU_REG_PERI, 0x0F802000); + write_reg32(CGU_REG_PROC,0); + write_reg32(CGU_REG_AUDIO,0); + write_reg32(CGU_REG_USB,0); + write_reg32(CGU_REG_INTCTRL,0); + + write_reg32(CGU_REG_COUNTA,0); + write_reg32(CGU_REG_COUNTB,0); + write_reg32(CGU_REG_IDE,0); + write_reg32(CGU_REG_MEMSTICK,0); + write_reg32(CGU_REG_DBOP,0); + + + write_reg32(CGU_REG_PLLASUP,0x8); + write_reg32(CGU_REG_PLLBSUP,0x8); + + write_reg32(CGU_REG_PLLA,0); + write_reg32(CGU_REG_PLLB,0); + + clk_set_async_mode(); + /*set cpu and bus default clock + plla 384M, CPU 192M,mpmc 64M,pclk 64M */ + + write_reg32(CGU_REG_PLLA,0x2630); + write_reg32(CGU_REG_PLLASUP,0); + write_reg32(CGU_REG_COUNTA,CGU_LOCK_CNT); + while (!(read_reg32(CGU_REG_INTCTRL)&1)) ; + + write_reg32( CGU_REG_PROC, 0x011); + write_reg32(CGU_REG_PERI,0x0EF2E295); + + /* arch number of AS352X-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AS352X; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + sdram_init(); + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff -upBNr u-boot-1.1.6.org/board/as352xpb/config.mk u-boot-1.1.6/board/as352xpb/config.mk --- u-boot-1.1.6.org/board/as352xpb/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/config.mk 2006-12-04 09:48:37.000000000 +0800 @@ -0,0 +1,23 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> +# +# AMS AS352XPB board with AS352X (ARM922T) cpu +# +# see http://www.austriamicrosystems.com for more information +# +# +# AS352X has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3400'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# optionally with a ramdisk at 3080'0000 +# +# we load ourself to 0000'0000 +# +# download area is 3300'0000 +# + +TEXT_BASE = 0x00000000 diff -upBNr u-boot-1.1.6.org/board/as352xpb/lowlevel_init.S u-boot-1.1.6/board/as352xpb/lowlevel_init.S --- u-boot-1.1.6.org/board/as352xpb/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/lowlevel_init.S 2006-12-04 09:48:37.000000000 +0800 @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + +/* some parameters for the board */ + +/* + * + */ + + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ diff -upBNr u-boot-1.1.6.org/board/as352xpb/Makefile u-boot-1.1.6/board/as352xpb/Makefile --- u-boot-1.1.6.org/board/as352xpb/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/Makefile 2006-12-04 09:48:37.000000000 +0800 @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := as352xpb.o nandas.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -upBNr u-boot-1.1.6.org/board/as352xpb/nandas.c u-boot-1.1.6/board/as352xpb/nandas.c --- u-boot-1.1.6.org/board/as352xpb/nandas.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/nandas.c 2006-12-04 10:30:57.000000000 +0800 @@ -0,0 +1,410 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> +#include <asm/errno.h> +/* +* hardware specific access to control-lines +*/ + +#define NAF_X8_X16_CODE 0x03 /* only for big block nand */ + +/** +* Power bit in NAF mode register. +**/ +#define NAF_POWER_ON 0x0C +#define NAF_POWER_OFF 0x00 + +/** +* NAF Config register bits. +**/ +#define NAF_X16 0x00000001 +#define NAF_FIFO_ENABLE 0x00000004 +#define NAF_DMA_ON 0x00000008 + +/* read strobe high is 4 PLCK cycles */ +#define NAF_READ_STROBE_H 0x00000020 + +/* read strobe low is 5 PLCK cycles */ +#define NAF_READ_STROBE_L 0x00000400 + +/* write strobe high is 4 PCLK cycles */ +#define NAF_WRITE_STROBE_H 0x00003000 + +/* write strobe high is 4 PCLK cycles */ +#define NAF_WRITE_STROBE_L 0x00040000 + +#define NAF_STROBE_CONFIG \ + ( NAF_READ_STROBE_H | NAF_READ_STROBE_L \ + | NAF_WRITE_STROBE_H | NAF_WRITE_STROBE_L ) + + +/** +* NAF modi +**/ +#define NAF_MODE_CLE 1<<0 +#define NAF_MODE_ALE 1<<1 +#define NAF_MODE_NCE 1<<4 +#define NAF_MODE_WP 1<<7 + +#define NAF_MODE_DATA_READ_NO_ECC 0x14 +#define NAF_MODE_DATA_WRITE_ECC_RESET 0xF4 +#define NAF_MODE_DATA_WRITE_NO_ECC 0x94 +/* +* chip R/B detection +*/ +static int as352x_read_status; + +static int as352x_nand_ready(struct mtd_info *mtd) +{ + return ( ( read_reg16( NAF_STATUS ) & 0x0080 ) == 0x0080 ); + +} +static int as352x_nand_strobe() +{ + return ( ( read_reg16( NAF_STATUS ) & 0x0100 ) == 0x0100 ); +} +static int as352x_fifo_isfull() +{ + return ( ( read_reg16( NAF_STATUS ) & 0x01000 ) ); +} + +static int as352x_fifo_isempty() +{ + return ( ( read_reg16( NAF_STATUS ) & 0x0200 ) ); +} +/** +* nand_read_byte - [DEFAULT] read one byte from the chip +* @mtd: MTD device structure +* +* Default read function for 8bit buswith +*/ +static u_char as352x_nand_read_byte(struct mtd_info *mtd) +{ + u_char data; + write_reg8 ( NAF_CONTROL, 0x1 ); /* generate read strobe */ + while (!as352x_nand_strobe(mtd)); + data = read_reg16( NAF_DATA ); + if (as352x_read_status) + data |= 0x80; + return data; +} + +/** +* nand_write_byte - [DEFAULT] write one byte to the chip +* @mtd: MTD device structure +* @byte: pointer to data byte to write +* +* Default write function for 8it buswith +*/ +static void as352x_nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + + write_reg16( NAF_DATA, byte ); + while (!as352x_nand_strobe(mtd)); +} + +void as352x_nand_wait_fifo_empty( ) +{ + /* wait for got empty and ready */ + while ( ( read_reg16( NAF_STATUS ) & 0x0004 ) != 0x0004 ) ; +} + +/** +* nand_write_buf - [DEFAULT] write buffer to chip +* @mtd: MTD device structure +* @buf: data buffer +* @len: number of bytes to write +* +* Default write function for 8bit buswith +*/ +static void as352x_nand_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + int i; + u32 *p =(u32 *)buf; + struct nand_chip *this = mtd->priv; + len /=4; + write_reg8( NAF_CLEAR, 0x7f ); + write_reg32( NAF_WORDS, len ); + for (i=0; i<len; i++){ + while (as352x_fifo_isfull()); + write_reg32( NAF_FIFODATA, p[i] ); + } + as352x_nand_wait_fifo_empty(); +} + +/** +* nand_read_buf - [DEFAULT] read chip data into buffer +* @mtd: MTD device structure +* @buf: buffer to store date +* @len: number of bytes to read +* +* Default read function for 8bit buswith +*/ +static void as352x_nand_read_buf(struct mtd_info *mtd, + u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u32 *p =(u32 *)buf; + len /=4; + write_reg8( NAF_CLEAR, 0x7f ); + write_reg32( NAF_WORDS, len ); + for (i=0; i<len; i++){ + while (as352x_fifo_isempty()); + p[i] = read_reg32( NAF_FIFODATA ); + } + as352x_nand_wait_fifo_empty( ); +} +/** +* nand_verify_buf - [DEFAULT] Verify chip data against buffer +* @mtd: MTD device structure +* @buf: buffer containing the data to compare +* @len: number of bytes to compare +* +* Default verify function for 8bit buswith +*/ +static int nand_verify_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; i<len; i++) + if (buf[i] != as352x_nand_read_byte(mtd)) + return -EFAULT; + + return 0; +} + +static void as352x_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + + struct nand_chip *this = mtd->priv; + + switch (cmd) { + case NAND_CTL_SETCLE:{ + set_reg_bits16 ( NAF_MODE, NAF_MODE_CLE ); + } + break; + case NAND_CTL_CLRCLE: + clr_reg_bits16( NAF_MODE, NAF_MODE_CLE ); + break; + case NAND_CTL_SETALE:{ + set_reg_bits16 ( NAF_MODE, NAF_MODE_ALE ); + + } + break; + case NAND_CTL_CLRALE: + clr_reg_bits16( NAF_MODE, NAF_MODE_ALE ); + break; + case NAND_CTL_SETNCE: + set_reg_bits16 ( NAF_MODE, NAF_MODE_NCE ); + break; + case NAND_CTL_CLRNCE: + clr_reg_bits16( NAF_MODE, NAF_MODE_NCE ); + break; + case NAND_CTL_SETWP: + set_reg_bits16 ( NAF_MODE, NAF_MODE_WP ); + break; + case NAND_CTL_CLRWP: + clr_reg_bits16( NAF_MODE, NAF_MODE_WP ); + break; + + } +} +/** +* nand_command_lp - [DEFAULT] Send command to NAND large page device +* @mtd: MTD device structure +* @command: the command to be sent +* @column: the column address for this command, -1 if none +* @page_addr: the page address for this command, -1 if none +* +* Send command to NAND device. + This is the version for the new large page devices +* We dont have the seperate regions as we have in the small page devices. +* We must emulate NAND_CMD_READOOB to keep the code compatible. +* +*/ + +static void as352x_nand_command_lp (struct mtd_info *mtd, + unsigned command, int column, + int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + column += mtd->oobblock; + command = NAND_CMD_READ0; + } + + as352x_read_status =0; + switch (command) { + case NAND_CMD_SEQIN: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2:{ + write_reg8( NAF_MASK, 0xFF ); + write_reg8( NAF_CLEAR, 0x7f ); + } + case NAND_CMD_CACHEDPROG: + case NAND_CMD_PAGEPROG:{ + this->hwcontrol(mtd, NAND_CTL_SETWP); + } + break; + case NAND_CMD_READ0: + write_reg8( NAF_MASK, 0xFF ); + write_reg8( NAF_CLEAR, 0x7f ); + write_reg8( NAF_MODE,NAF_MODE_DATA_READ_NO_ECC); + default: + this->hwcontrol(mtd, NAND_CTL_CLRWP); + } + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the command to the device. */ + this->write_byte(mtd, command); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column & 0xff); + this->write_byte(mtd, column >> 8); + } + if (page_addr != -1) { + this->write_byte(mtd, + (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, + (unsigned char) + ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 128MiB */ + if (this->chipsize > (128 << 20)) + this->write_byte(mtd, + (unsigned char) ((page_addr >> 16) & 0xff)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + case NAND_CMD_SEQIN:{ + write_reg8( NAF_MODE, NAF_MODE_DATA_WRITE_ECC_RESET ); + break; + } + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + break; + case NAND_CMD_STATUS: + as352x_read_status =1; + break; + case NAND_CMD_CACHEDPROG: + + case NAND_CMD_PAGEPROG: + write_reg8( NAF_MODE, NAF_MODE_DATA_WRITE_NO_ECC ); + break; + + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + case NAND_CMD_READ0: + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the start read command */ + this->write_byte(mtd, NAND_CMD_READSTART); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + /* Fall through into ready check */ + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, + we apply the given command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (1000); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + + +void board_nand_init(struct nand_chip *nand) +{ + /* clear all NAF chip select bits*/ + clr_reg_bits32( CCU_IO , + ( CCU_IO_NAF_CE_LINE_0 | CCU_IO_NAF_CE_LINE_1 + | CCU_IO_NAF_CE_LINE_2 | CCU_IO_NAF_CE_LINE_3 ) ); + + set_reg_bits32( CCU_IO , CCU_IO_NAF_CE_LINE_0 ); + + /* configure NAF */ + write_reg8( NAF_MODE, NAF_POWER_ON ); /* turn power on */ + write_reg8( NAF_MASK, 0xFF ); + write_reg8( NAF_CLEAR, 0x7f ); /* clear any pending error indication */ + + /* configure fifo on but dma still off */ + write_reg32( NAF_CONFIG, NAF_FIFO_ENABLE | NAF_STROBE_CONFIG ); + + /* 2. change into read mode */ + write_reg8 ( NAF_MODE, NAF_MODE_DATA_READ_NO_ECC ); + + nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = as352x_nand_hwcontrol; + nand->dev_ready = as352x_nand_ready; + nand->chip_delay = 18; + nand->read_byte = as352x_nand_read_byte; + nand->write_byte = as352x_nand_write_byte; + nand->read_buf = as352x_nand_read_buf; + nand->write_buf = as352x_nand_write_buf; + nand->cmdfunc = as352x_nand_command_lp; +} +#endif diff -upBNr u-boot-1.1.6.org/board/as352xpb/u-boot.lds u-boot-1.1.6/board/as352xpb/u-boot.lds --- u-boot-1.1.6.org/board/as352xpb/u-boot.lds 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/u-boot.lds 2006-12-04 09:48:37.000000000 +0800 @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm922t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -upBNr u-boot-1.1.6.org/common/env_nand.c u-boot-1.1.6/common/env_nand.c --- u-boot-1.1.6.org/common/env_nand.c 2006-12-01 17:49:33.000000000 +0800 +++ u-boot-1.1.6/common/env_nand.c 2006-11-30 09:35:19.000000000 +0800 @@ -162,9 +162,13 @@ int saveenv(void) if(gd->env_valid == 1) { puts ("Erasing redundant Nand..."); - if (nand_erase(&nand_info[0], - CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) - return 1; +#ifdef CONFIG_AS352X + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET_REDUND, CFG_ENV_NAND_ERASE_SIZE)) + return 1; +#else + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) + return 1; +#endif puts ("Writing to redundant Nand... "); ret = nand_write(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, (u_char*) env_ptr); @@ -192,9 +196,13 @@ int saveenv(void) int ret = 0; puts ("Erasing Nand..."); +#ifdef CONFIG_AS352X + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_NAND_ERASE_SIZE)) + return 1; +#else if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE)) return 1; - +#endif puts ("Writing to Nand... "); total = CFG_ENV_SIZE; ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); diff -upBNr u-boot-1.1.6.org/cpu/arm922t/as352x/interrupts.c u-boot-1.1.6/cpu/arm922t/as352x/interrupts.c --- u-boot-1.1.6.org/cpu/arm922t/as352x/interrupts.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/interrupts.c 2006-12-04 10:30:50.000000000 +0800 @@ -0,0 +1,212 @@ +/* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Marius Groeger <mgroeger(a)sysgo.de> +* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Alex Zuepke <azu(a)sysgo.de> +* +* (C) Copyright 2002 +* Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <arm922t.h> +#include <as352x.h> + +#if defined(CONFIG_AS352X) +#define TIMER_LOAD_VAL 0xffffffff +static ulong timestamp; +static ulong lastdec; +#define CFG_TIMER_INTERVAL 1500000 +#define CFG_TIMER_RELOAD (CFG_TIMER_INTERVAL) + +int interrupt_init (void) +{ + u32 val = read_reg32(CGU_REG_PERI); + + write_reg32(val|CGU_TIMER1_CLOCK_ENABLE ,CGU_REG_PERI); + + /* + * Initialise to a known state (all timers off) + */ + write_reg32(TIMER_CONTROL,0); + write_reg32(TIMER_CONTROL,0); + + write_reg32(TIMER_INTCLR,1); + write_reg32(TIMER_INTCLR,1); + + write_reg32(TIMER_LOAD,CFG_TIMER_RELOAD ); + write_reg32(TIMER_VALUE,CFG_TIMER_RELOAD); + + write_reg32(TIMER_CONTROL,TIMER_PRESCALE_1 | TIMER_ENABLE |TIMER_32_BIT ); + + reset_timer_masked(); + return (0); +} + + + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if(usec >= 1000){ +/* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; +/* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; + /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; + /* finish normalize. */ + }else{ + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + /* get current timestamp */ + tmp = get_timer (0); + /* if setting this fordward will roll time stamp */ + if( (tmo + tmp + 1) < tmp ) + /* reset "advancing" timestamp to 0, set lastdec value */ + reset_timer_masked (); + else + /* else, set advancing stamp wake up time */ + tmo += tmp; + + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + + +void reset_timer_masked (void) +{ + /* reset time */ + /* capure current decrementer value time */ + lastdec = read_reg32(TIMER_VALUE); + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + /* current tick value */ + ulong now = read_reg32(TIMER_VALUE); + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + /* move stamp fordward with absoulte diff ticks */ + timestamp += lastdec - now; + } else { + /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"... + *it could also roll and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + /* if "big" number, spread normalization to seconds */ + if (usec >= 1000) { + /* start to normalize for usec to ticks per sec */ + tmo = usec / 1000; + /* find number of "ticks" to wait to achieve target */ + tmo *= CFG_HZ; + tmo /= 1000; /* finish normalize. */ + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* +* This function is derived from PowerPC code (read timebase as long long). +* On ARM it just returns the timer value. +*/ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* +* This function is derived from PowerPC code (timebase clock frequency). +* On ARM it returns the number of timer ticks per second. +*/ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} + + +/* +* reset the cpu by setting up the watchdog timer and let him time out +*/ +void reset_cpu (ulong ignored) +{ + + /* Disable watchdog */ + + /* Initialize watchdog timer count register */ + + /* Enable watchdog timer; assert reset at timer timeout */ + + while(1); /* loop forever and wait for reset to happen */ + + /*NOTREACHED*/ +} + +#endif /* defined(CONFIG_AS352X) */ diff -upBNr u-boot-1.1.6.org/cpu/arm922t/as352x/Makefile u-boot-1.1.6/cpu/arm922t/as352x/Makefile --- u-boot-1.1.6.org/cpu/arm922t/as352x/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/Makefile 2006-12-04 09:55:14.000000000 +0800 @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = interrupts.o serial.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################

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[U-Boot-Users] usbtty .inf file
by Chris B 05 Dec '06

05 Dec '06

Does anybody have a sample Windows .INF file that would allow one to connect to u-boot's USBTTY...such as the one needed for the Siemen's SX1? Thanks, Chris ____________________________________________________________________________________ Want to start your own business? Learn how on Yahoo! Small Business. http://smallbusiness.yahoo.com/r-index

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[U-Boot-Users] to check the board
by Nethra 05 Dec '06

05 Dec '06

hi, i am using 8248 custom board. Now i want check the board by toggling the led without using u-boot. Is it possible?If possible which one we have to use(flash,sdram)........... with regards Nethra -- View this message in context: http://www.nabble.com/to-check-the-board-tf2759113.html#a7692851 Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] [PATCH] use CFI-Flash and board depended driver together
by Jens Scharsig 05 Dec '06

05 Dec '06

Hello, i need to use cfi and board flash driver together. This Patch contains a simple way to do this with a minimun changes at cfi_flash.c. All changes will only enable if CFG_FLASH_BOARD_DRIVER defined. CHANGELOG * Rename flash_print_info, flash_erase, write_buff and flash_real_protect to cfi_xxxx, if CFG_FLASH_BOARD_DRIVER is defined. This will allow use cfi driver together with board a dependent flash driver (see README.board-dependent-flash for an example) diff --git a/doc/README.board-dependent-flash b/doc/README.board-dependent-flash new file mode 100644 index 0000000..d71cf49 --- /dev/null +++ b/doc/README.board-dependent-flash @@ -0,0 +1,145 @@ +How to use CFI-Flash and board depended driver together +========================================================= + +1. OVERVIEW +----------- +If CFG_FLASH_BOARD_DRIVER is defined, the following functions are renamed +in CFI_XXXX: flash_print_info + flash_erase + write_buff + flash_real_protect + +They can be called now by the board flash functions. + + +2. Target/Broard dependent Driver +--------------------------------- + +You can use the following functions as pattern for your own implementation: + + +/*---------------------------------------------------------------------------*/ +/* boardflash.c */ +/*---------------------------------------------------------------------------*/ + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*---------------------------------------------------------------------------*/ + +ulong board_flash_get_size (ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + + if (base == CFG_INT_FLASH_BASE) + { + debug("Use Board Flash-Init at %p\n",base); + /* put your on code here */ + } + else + { + debug("Use CFI Flash-Init at %p\n",base); + flash_get_size (base,banknum); + } + + return (info->size); +} + +/*---------------------------------------------------------------------------*/ + +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case <your vendor>: + /* put your on code here */ + break; + default: + cfi_flash_print_info (info); + return; + break; + } + + puts (" Size: "); + if ((info->size >> 20) > 0) + { + printf ("%ld MiB",info->size >> 20); + } + else + { + printf ("%ld KiB",info->size >> 10); + } + printf (" in %d Sectors\n", info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 4) == 0) { + printf ("\n "); + } + printf ("%02d: %08lX%s ", i,info->start[i], + info->protect[i] ? " P" : " "); + } + printf ("\n\n"); +} + +/*---------------------------------------------------------------------------*/ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int iflag, cflag; + int sector; + int rc; + + switch (info->flash_id & FLASH_VENDMASK) + { + case <your vendor>: + /* put your on code here */ + break; + default: + rc=cfi_flash_erase (info,s_first,s_last); + } + return rc; +} + +/*---------------------------------------------------------------------------*/ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + + switch (info->flash_id & FLASH_VENDMASK) + { + case (<your vendor>: + /* put your on code here */ + break; + default: + rc = cfi_write_buff (info,src,addr,cnt); + } + return rc; +} + +/*---------------------------------------------------------------------------*/ + +#ifdef CFG_FLASH_PROTECTION + +int flash_real_protect(flash_info_t * info,long sector,int prot) +{ + int rc; + + switch (info->flash_id & FLASH_VENDMASK) + { + case <your vendor>: + /* put your on code here */ + break; + default: + rc = cfi_flash_real_protect(info,sector,prot); + } + return rc; +} + +#endif +/*---------------------------------------------------------------------------*/ +/* end of boardflash.c */ +/*---------------------------------------------------------------------------*/ + + diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index fd0a186..9c05130 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -71,6 +71,13 @@ * Verify erase and program timeouts. */ +#ifdef CFG_FLASH_BOARD_DRIVER +#define flash_print_info cfi_flash_print_info +#define flash_erase cfi_flash_erase +#define write_buff cfi_write_buff +#define flash_real_protect cfi_flash_real_protect +#endif + #ifndef CFG_FLASH_BANKS_LIST #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #endif @@ -353,8 +360,13 @@ unsigned long flash_init (void) /* Init: no FLASHes known */ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; +#ifdef CFG_FLASH_BOARD_DRIVER + size += flash_info[i].size = board_flash_get_size (bank_base[i], i); +#else size += flash_info[i].size = flash_get_size (bank_base[i], i); +#endif if (flash_info[i].flash_id == FLASH_UNKNOWN) { #ifndef CFG_FLASH_QUIET_TEST printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", @@ -641,7 +653,7 @@ int write_buff (flash_info_t * info, uch i = cnt; if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) return rc; - i -= i & (info->portwidth - 1); + i -= (i % info->portwidth); wp += i; src += i; cnt -= i;

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[U-Boot-Users] Problem with the ST Microlectronics M29W320B flash and the CFI driver.
by Txema Lopez 05 Dec '06

05 Dec '06

Hi all, We have a MPC5200B based custom board with a ST Microelectronics M29W320B (x8/x16 flash in x8 mode) as boot flash. We are able to program the flash using a BDI2000 and start up U-Boot. But U-Boot is unable to detect the boot flash using the CFI driver. With the same hardware (but other board) and a flash from other vendor (Spansion S29GL32A) the CFI driver works properly. Has anyone tested the CFI driver for the M29W320B flash? This is the BDI2000 output when we write a CFI Query command ffc00000 : 2000 5722 FFFF FFFF FFFF FFFF FFFF FFFF .W"............ ffc00010 : FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF ................ ffc00020 : 5100 5200 5900 0200 0000 4000 0000 0000 Q.R.Y.....@..... ffc00030 : 0000 0000 0000 2700 3600 b500 c500 0400 ......'.6....... ffc00040 : 0000 0a00 0000 0400 0000 0300 0000 1600 ................ ffc00050 : 0200 0000 0000 0000 0200 0700 0000 2000 .............. . ffc00060 : 0000 3e00 0000 0000 0100 0000 0000 8000 ..>............. ffc00070 : 0000 3e00 0000 0000 0100 FFFF FFFF FFFF ..>............. ffc00080 : 5000 5200 4900 3100 3000 0000 0200 0100 P.R.I.1.0....... ffc00090 : 0100 0400 0000 0000 0000 b500 c500 0200 ................ ffc000a0 : FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF ................ ffc000b0 : FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF ................ ffc000c0 : FFFF 6012 4e3b f07d 9b54 3500 2002 2003 ..`.N;.}.T5. . . ffc000d0 : 1200 2700 3a00 0100 0000 0000 0000 0000 ..'.:........... ffc000e0 : 0000 0f00 0700 0200 0000 0100 0100 0000 ................ ffc000f0 : 0000 0000 0000 0100 0000 0000 0000 0000 ................ AFAIK the CFI driver is waiting an output like this for a x8/x16 device in x8 mode: ffc00020 : 5151 5252 5959 QQRRYY Am I wrong? Best regards,

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[U-Boot-Users] bus fault in calling eth_init()
by Tom Brown 05 Dec '06

05 Dec '06

Hi, I've compiled up 1.1.6 and loaded it onto our board. I can't load linux because I can't do a tftp. I get a bus fault every time I use the tftp command or the ping command. I put some printf's into u-boot to try to diagnose the problem. What I've come up with is the call to eth_init() is the problem. Not the code in eth_init(), but the actuall call. Any ideas on what the problem may be or what I need to be looking at? The output of the bootup and result of the ping command is given below. Thanks, Tom U-Boot 1.1.6.2 (Dec 4 2006 - 15:11:37)for the 195Eg CPU: AMCC PowerPC 405EP Rev. B at 250 MHz (PLB=62, OPB=31, EBC=31 MHz) I2C boot EEPROM disabled Internal PCI arbiter enabled 16 kB I-Cache 16 kB D-Cache I2C: ready DRAM: 16 MB Top of RAM usable for U-Boot at: 01000000 Reserving 263k for U-Boot at: 00fbe000 Reserving 256k for malloc() at: 00f7e000 Reserving 144 Bytes for Board Info at: 00f7df70 Reserving 48 Bytes for Global Data at: 00f7df40 Stack Pointer at: 00f7df28 New Stack Pointer is: 00f7df28 Now running in RAM - U-Boot at: 00fbe000 FLASH: manufact type value = 1f8b02 flash_protect ON: from 0xFFFC0000 to 0xFFFFFFFF protect on 67 protect on 68 protect on 69 protect on 70 4 MB In: serial Out: serial Err: serial U-Boot relocated to 00fbe000 ### main_loop entered: bootdelay=1 ### main_loop: bootcmd="bootm ffc20000" Hit any key to stop autoboot: 0 => ping 172.16.32.9 find_cmd BEGIN cmd == ping find_cmd full match END cmdtp == 0xff5ec808 do_ping call NetLoop NetLoop BEGIN Setup packet buffers, aligned correctly PktBuf[0] == 002 Fill NeRxPackets Setup NetArpWaitTxPacket eth_halt == 0xfc235408 call eth_halt() bd == 0xf7df7008 eth_init == 0xfc200c08 call eth_init() Bus Fault @ 0x00fc2018, fixup 0x00000000 Machine check in kernel mode. Caused by (from msr): regs 00f7d828 Unknown values in msr NIP: 00FC2018 XER: 00000000 LR: 00FC2018 REGS: 00f7d828 TRAP: 0200 DAR: 00F7DF40 MSR: 00001000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 00FC20FC 00F7D918 C017F8D0 00000000 00FC2080 00F7E1D8 00000000 00000000 GPR08: 00000002 600022E8 00200000 00FF6358 00000000 00000000 00FFBA00 00FFE000 GPR16: 00000000 00000001 FFFFFFFF 00F7DC48 00001000 00F7D978 00000000 00FC019C GPR24: 00000000 00000000 FFFFFFFF 600022E8 00000001 00F7DF40 00FFBA98 00200000 Call backtrace: machine check

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