December 2005 - U-Boot

[U-Boot-Users] [PATCH] Correct register for pci async mode on PPC440EP
by Youngchul Bang 10 Dec '05

10 Dec '05

Hi, Stefan This patch fixes the register for PCI async mode configuration information. Best regards, Youngchul Bang diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index a463053..a26533c 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -57,7 +57,7 @@ int pci_async_enabled(void) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) unsigned long val; - mfsdr(cpc0_strp1, val); + mfsdr(sdr_sdstp1, val); return (val & SDR0_SDSTP1_PAME_MASK); #endif }

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RE: [U-Boot-Users] NAND driver issue
by Dave Ellis 10 Dec '05

10 Dec '05

Thursday, December 08, 2005 11:33 AM Aubrey wrote: > But "nand read" and "nand write" failed because of ECC. So I try to > remove the macro "CONFIG_MTD_NAND_ECC" from the file > "common/cmd_nand.c", now it works. I can run "nand read" and "nand > write" successfully. The data wrote into the NAND flash and read back > is the same. I think the ECC code used to be broken unless CONFIG_MTD_NAND_ECC_JFFS2 is set in your board config file. Dave Ellis ~~~~~~~~~~~~~~~~~~~~~~~~~~ SIXNET - "Leading the Industrial Ethernet Revolution" 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 Email me at: dge(a)sixnetio.com Detailed product info: www.sixnetio.com ~~~~~~~~~~~~~~~~~~~~~~~~~~

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[U-Boot-Users] [PATCH] Enabled time handling on 83xx
by Kumar Gala 09 Dec '05

09 Dec '05

Enabled time handling on 83xx Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> CHANGELOG: * Enable time handling on 83xx Patch by Kumar Gala 09 Dec 2005 --- commit 0e1dbe02634177d369921208bd36cd8c875bc4a6 tree ee3e5b5a6b2e14280509a5f5d1eb4c137e6c73b3 parent 113d17d798e5770ff90bcfd9f7b21e080b91a8c9 author Kumar Gala <galak(a)kernel.crashing.org> Fri, 09 Dec 2005 13:22:03 -0600 committer Kumar Gala <galak(a)kernel.crashing.org> Fri, 09 Dec 2005 13:22:03 -0600 cpu/mpc83xx/interrupts.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c index 53474f6..729de2a 100644 --- a/cpu/mpc83xx/interrupts.c +++ b/cpu/mpc83xx/interrupts.c @@ -43,6 +43,16 @@ struct irq_action { int interrupt_init_cpu (unsigned *decrementer_count) { + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; + + /* Enable e300 time base */ + + immr->sysconf.spcr |= 0x00400000; + return 0; }

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[U-Boot-Users] u-boot debug failure with BDI2000 on MPC8540ads and eval8540 (gdatech's 8540 board)
by emre kara 09 Dec '05

09 Dec '05

Dear All; I have bought a BDI2000 with BDIGDB-85xx s/w. I'll use it for freescale's mpc8540eval board (know as GDA8540) and freescale's MPC8560ads. I can succesfully program the flash, but I can't debug neither linux kernel (2.6.15) nor u-boot(version 1.1.3). We have already running systems included u-boot and linux,so I could (try) to debug both of them. There is a strange behavior while debugging u-boot. Target boots at (loop) state, a few steps later (with ti command or step on gdb),bdi2000 gives a error message "Core status is 0x0041 *** Core is stopped, no restart possible bdi2000" loses control over target and then it reads all the register zero, every time on the same address(0xfffff154) it happes again,any breakpoint greater then this address doesnt work. I have tried it 3 different versions of u-boot (1.1.2-1.1.3-and latest with CVS) programmed on flash, and 2 different hardwares, nothing has changed. Normally, all this u-boot images succcesfully can boot up the target(with reset run command) and all of them are fully functional. Can you please examine the log below? ------------------------------------------------ - TARGET: waiting for target Vcc - TARGET: processing power-up delay - TARGET: processing user reset request - BDI asserts HRESET - Reset JTAG controller passed - JTAG exists check passed - IDCODE is 0x1007001D - SVR is 0x80700020 - PVR is 0x80200020 - Core status is 0x0001 - Platform status is 0x0005 - SAP status is 0x0005 - CCSRBAR is 0x0_ff700000 - BDI scans platform HALT command - Core status is 0x0001 - Platform status is 0x0005 - SAP status is 0x0005 - BDI removes HRESET - BDI writes boot loop to L2SRAM - BDI scans platform RESUME command - TARGET: Target PVR is 0x80200020 - TARGET: resetting target passed - TARGET: processing target startup .... - TARGET: processing target startup passed BDI>conf BDI MAC : 00-0c-01-97-95-07 BDI IP : 192.168.11.101 BDI Subnet : 255.255.255.255 BDI Gateway : 255.255.255.255 Config IP : 192.168.11.1 Config File : ads8560.cfg BDI>i Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : COP halt Current PC : 0xfffffffc Current CR : 0x00000000 Current MSR : 0x00000200 Current LR : 0x00000000 Current CCSRBAR : 0x0_40000000 BDI>bi 0xfffff14c Breakpoint identification is 0 BDI>go - TARGET: stopped BDI>i Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : instruction breakpoint Current PC : 0xfffff14c Current CR : 0x40000000 Current MSR : 0x00000200 Current LR : 0x00000000 Current CCSRBAR : 0x0_40000000 BDI>ti Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : single step Current PC : 0xfffff150 Current CR : 0x40000000 Current MSR : 0x00000200 Current LR : 0x00000000 Current CCSRBAR : 0x0_40000000 BDI>ti Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : single step Current PC : 0xfffff154 Current CR : 0x40000000 Current MSR : 0x00000200 Current LR : 0x00000000 Current CCSRBAR : 0x0_40000000 BDI>ti - Core status is 0x0041 *** Core is stopped, no restart possible # PPC: timeout while waiting for halt BDI> Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : COP freeze Current PC : 0x00000000 Current CR : 0x00000000 Current MSR : 0x00000000 Current LR : 0x00000000 Current CCSRBAR : 0x0_40000000 # Step timeout detected BDI>i Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : COP freeze Current PC : 0x00000000 Current CR : 0x00000000 Current MSR : 0x00000000 Current LR : 0x00000000 Current CCSRBAR : 0x0_40000000 BDI> and system craches until a "reset run" command --------------------------------------------------------------------- What can be cause this problem?. The configuration file of eval8540 is below (taken from ultsol web site). Abatron Model:BDI2000/C SerNo: 97950725 Loader: V1.05 Firmware:V1.04 bdiGDB for MPC85xx Logic:V1.05 PPC6xx/PPC7xx ;bdiGDB configuration file for Metrowerks eval board MPC8540 ;----------------------------------------------------------- ; ; The boot flash data bus is connected with swapped bytes. ; ; CPU D0 D1 ... D6 D7 | D8 D9 ... D14 D15 ; | | ... | | | | ... | | ; | | ... | | | | ... | | ; FLASH D7 D6 ... D1 D0 | D15 D14 ... D9 D8 ; ; ; [INIT] ; init core register ; ; define maximal transfer size ;TSZ4 0x00000000 0xffffffff ; ; Move the L2SRAM to the initial MMU page WM32 0xFF720000 0x68010000 ;L2CTL WM32 0xFF720100 0xFFFC0000 ;L2SRBAR0 WM32 0xFF720000 0xA8010000 ;L2CTL ; ; Clear l2 sram with dma (needed if STARTUP HALT) ;WM32 0xff721110 0x00040000 ;SATR0 SREADTTYPE=Read, don't snoop ;WM32 0xff721114 0xff700004 ;SAR0 Dummy source register ;WM32 0xff721118 0x00050000 ;DATR0 DWRITETTTYPE=Write, snoop local processor ;WM32 0xff721120 0x00040000 ;BCR0 Size ;WM32 0xff721100 0x0f009404 ;MR0 BWC=f,SAHTS=2(4 bytes),SAHE=1,SWSM=Dest,SRW=1,CTM=1,CS=0 ;WM32 0xff72111c 0xfffc0000 ;DAR0 which sets CS=1 ;DELAY 200 ;let DMA complete ; ; load and execute boot code (needed if STARTUP HALT) ;WM32 0xfffffffc 0x48000000 ;loop ;EXEC 0xfffffffc 1000 ; ; load TLB entries, helper code @ 0xfffff000 WM32 0xfffff000 0x7c0007a4 ;tlbwe WM32 0xfffff004 0x7c0004ac ;msync WM32 0xfffff008 0x48000000 ;loop ; ; 1MB TLB1 #1 0x40000000 - 0x400fffff WSPR 624 0x10010000 ;MAS0: WSPR 625 0x80000500 ;MAS1: WSPR 626 0x4000000a ;MAS2: WSPR 627 0x40000015 ;MAS3: WSPR 628 0x00000000 ;MAS4: EXEC 0xfffff000 ; ; 64 MB TLB1 #2 0xc0000000 - 0xc3ffffff WSPR 624 0x10020000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0xc0000008 ;MAS2: WSPR 627 0xc0000015 ;MAS3: EXEC 0xfffff000 ; ; 64 MB TLB1 #3 0x00000000 - 0x03ffffff WSPR 624 0x10030000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0x00000008 ;MAS2: WSPR 627 0x00000015 ;MAS3: EXEC 0xfffff000 ; ; 64 MB TLB1 #4 0x04000000 - 0x07ffffff WSPR 624 0x10040000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0x04000008 ;MAS2: WSPR 627 0x04000015 ;MAS3: EXEC 0xfffff000 ; ; 16 MB TLB1 #5 0xff000000 - 0xffffffff WSPR 624 0x10050000 ;MAS0: WSPR 625 0x80000700 ;MAS1: WSPR 626 0xff80000a ;MAS2: changed WSPR 627 0xff800015 ;MAS3: changed EXEC 0xfffff000 ; ; 16 MB TLB1 #0 0xf0000000 - 0xf0ffffff WSPR 624 0x10000000 ;MAS0: WSPR 625 0x80000700 ;MAS1: WSPR 626 0xf0000008 ;MAS2: WSPR 627 0xf0000015 ;MAS3: EXEC 0xfffff000 ; ; Remove the L2SRAM from the initial MMU page WM32 0xFF720000 0x28010000 ;L2CTL WM32 0xFF720000 0x28000000 ;L2CTL ; ; Move CCSRBAR to 0xfdf00000 WM32 0xff700000 0x000fdf00 ;CCSRBAR to 0xfdf00000 ; ; Initialize LAWBAR's WM32 0xfdf00C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0xfdf00C10 0x80f0001b ;LAWAR0 : DDR/SDRAM 256MB ;WM32 0xfdf00C28 0x000c0000 ;LAWBAR1 : @0xc0000000 ;WM32 0xfdf00C30 0x8040001d ;LAWAR1 : Local Bus 1GB ; ; Setup DDR (Metrowerks eval board, 256MB DDR) WM32 0xfdf02000 0x00000007 ;CS0_BNDS WM32 0xfdf02080 0x80000101 ;CS0_CONFIG WM32 0xfdf02108 0x36342321 ;TIMING_CFG_1 WM32 0xfdf0210C 0x00000800 ;TIMING_CFG_2 WM32 0xfdf02110 0x02000000 ;DDR_SDRAM_CFG WM32 0xfdf02118 0x00000062 ;DDR_SDRAM_MODE WM32 0xfdf02124 0x03d00100 ;DDR_SDRAM_IVAL DELAY 200 WM32 0xfdf02110 0xc2000000 ;DDR_SDRAM_CFG ; ; Setup Flash chip select WM32 0xfdf05000 0xff801001 ;BR0 WM32 0xfdf05004 0xff806f67 ;OR0 ; ; Setup flash programming workspace in L2SRAM ;WM32 0x40020000 0x68010000 ;L2CTL ;WM32 0x40020100 0xf0000000 ;L2SRBAR0 ;WM32 0x40020000 0xA8010000 ;L2CTL ;WSPR 63 0xf0000000 ;IVPR to workspace ;WSPR 415 0x0001500 ;IVOR15 : Debug exception ;WM32 0xf0001500 0x48000000 ;write valid instruction ; ; Setup for program execution WM32 0xfdf20000 0x28010000 ;L2CTL WM32 0xfdf20000 0x28000000 ;L2CTL WSPR 63 0x00000000 ;IVPR to workspace WSPR 406 0x0000700 ;IVOR6 : Program exception WSPR 415 0x0001500 ;IVOR15 : Debug exception WM32 0x00000700 0x48000000 ;write valid instruction WM32 0x00001500 0x48000000 ;write valid instruction ; ; Clear flash Lock-Bits WM16 0xFF800000 0x6000 ;clear Lock-Bits command WM16 0xFF800000 0xD000 DELAY 1000 ;needs up to 0.7 sec WM16 0xFF800000 0xFFFF ;set flash to read mode ; [TARGET] ;***DONE*** MMU XLAT CPUTYPE 8540 ;the CPU type JTAGCLOCK 3 ;use 4 MHz JTAG clock STARTUP LOOP ;use boot loop in L2SRAM ;STARTUP HALT ;halt core while HRESET is asserted BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 200 ;give reset time to complete ;POWERUP 5000 ;start delay after power-up detected in ms POWERUP 100 ;start delay after power-up detected in ms MEMACCESS SAP ;use SAP or CORE for JTAG memory accesses [HOST] IP 192.168.11.1 ;emreFILE E:\cygwin\home\demo\e500\fibo.elf ;emreFORMAT ELF ;emreLOAD MANUAL ;load code MANUAL or AUTO after reset ;emreDUMP D:\SCORE_PRO\BRIDGE_CARD\BDI2000\DUMP\e500.bin [FLASH] CHIPTYPE STRATAX16 CHIPSIZE 0x800000 ;The size of one flash chip in bytes BUSWIDTH 16 SWAP ;The bytes are swapped !!! WORKSPACE 0x00000000 ;workspace in system RAM ;WORKSPACE 0xf0000000 ;workspace in L2SRAM ;FILE E:\cygwin\home\bdidemo\e500\ads8560.cfg ;FORMAT BIN 0xFF800000 ;ERASE 0xFF800000 ;erase sector 0 ;ERASE 0xFF840000 ;erase sector 1 ;ERASE 0xFF880000 ;erase sector 2 ;ERASE 0xFF8C0000 ;erase sector 3 [REGS] FILE $reg8560.def Best Regards Emre KARA ___________________________________________________________ To help you stay safe and secure online, we've developed the all new Yahoo! Security Centre. http://uk.security.yahoo.com

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[U-Boot-Users] NAND driver issue
by Aubrey 09 Dec '05

09 Dec '05

Hi all, I'm trying to enable NAND driver in uboot for my target board. It's a ST nand chip, the part number is nand128w3a(small page, 16M*8bit). After add its data info into the matrix nand_flash_ids[] in the file "include/linux/mtd/nand_ids.h" and add the nand driver interface macros in my board head file, u-boot can find my NAND flash chip. And I can run the command "nand bad" successfully. But "nand read" and "nand write" failed because of ECC. So I try to remove the macro "CONFIG_MTD_NAND_ECC" from the file "common/cmd_nand.c", now it works. I can run "nand read" and "nand write" successfully. The data wrote into the NAND flash and read back is the same. I can make sure that the hardware is no problem. I know ECC is very important and can't be disabled. So, Is it a bug of NAND driver? Or did I miss something? Thanks for your any suggestions and comments. Regards, -Aubrey

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[U-Boot-Users] About SMDK2410 in uboot
by 周宇 08 Dec '05

08 Dec '05

We all know that there two nor flash (AM29LV800BB-90EC (1MB) and E28F128J3A150 (16MB,Unload),)in smdk2410 board. But we only see the init function for AM29LV800BB-90EC chipset. I don't know why the E28F128J3A150 don't want to be initialized. Who can tell why _________________________________________________________________ 与联机的朋友进行交流，请使用 MSN Messenger: http://messenger.msn.com/cn

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RE: [U-Boot-Users] IVPR on E500
by Nuno João (Ext_NBS) 08 Dec '05

08 Dec '05

Hello Kylo, Thank you for the answer. After the relocation done by your patch, IVPR is relocated again, to 0x0, when trap_init() (start.S) is called inside board_init_r(). trap_init() relocates the exception handlers to 0x0. This means that, when you get to the linux kernel boot, IVPR is at the same place as it was before your patch (this init_trap() code is earlier than your patch)... or am I missing something? Thank you and Best Regards On 12/8/05, Kylo Ginsberg <kylo.ginsberg(a)gmail.com> wrote: > That was my patch, but I need to work from memory as I'm at a > different job w/o an E500 at hand. As I recall, the problem was this: > --there is a window during very early linux startup when it has > removed the TLB entries setup by u-boot and is building its own > --using a BDI2000 trying to set breakpoints in this part of the linux code > --the E500 part wants to fetch the debug vector before passing control > to the BDI > --if this fetch goes to an unmapped region of address space, the E500 > is off in the weeds and stops responding to the BDI > Relocating the IVPR to ram at the same time that the rest of the image > is moved to ram addressed this problem. > I don't recall the third piece of code that you mention, so I don't > know how that interacts. (And my attempt to cg-clone u-boot.git gave > me a 404 error for one of the pack files part way through the > download; I'll try again later.) On 12/7/05, Nuno João (Ext_NBS) <nuno.joao-ext_nbs(a)siemens.com> wrote: > I've noticed some E500 related files (start.S and lib-ppc/board.c, > I don't know if others) have been changed with comment > "E500 update: repoint IVPR to RAM when code is relocated". > I don't understand the need for this change. Traps start in flash, > with IVPR set to TEXT_BASE in start.S. Later, this recent patch > relocates them to the same code but now in ram, after u-boot's > relocation. Later in lib_ppc/board.c:board_init_r() they are > then relocated to the beggining of ram (IVPR = 0). > Why do we need this "IVPR dance"? What does the "repoint IVPR do > RAM" patch fixes?

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[U-Boot-Users] Debugging U-boot
by Bashier Machmur 08 Dec '05

08 Dec '05

Hello, I'm using my custom board (PPC 440GX) and working with U-boot1.1.2 and Linux kernel 2.6.12. Now I have problems with debugging. When I start U-boot from Flash, it's working fine. But when I try debugging U-boot with BDI2000, it always hangs on PC: 0x00001300. ppc>go ppc>halt Core number :0 Core state :debug mode Debug entry cause :JTAG stop request Current PC :0x00001300 Current CR :0x22004022 Current MSR :0x00000000 Current LR :0xfffff144 ppc> Thanks for any help, Bashier

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[U-Boot-Users] IVPR on E500
by Nuno João (Ext_NBS) 08 Dec '05

08 Dec '05

Hello All, I've noticed some E500 related files (start.S and lib-ppc/board.c, I don't know if others) have been changed with comment "E500 update: repoint IVPR to RAM when code is relocated". I don't understand the need for this change. Traps start in flash, with IVPR set to TEXT_BASE in start.S. Later, this recent patch relocates them to the same code but now in ram, after u-boot's relocation. Later in lib_ppc/board.c:board_init_r() they are then relocated to the beggining of ram (IVPR = 0). Why do we need this "IVPR dance"? What does the "repoint IVPR do RAM" patch fixes? Thank you All and Best Regards, Nuno

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[U-Boot-Users] troubles
by Alexandr Kuleschov 07 Dec '05

07 Dec '05

Hi people! I work with based on AT91RM9200 board. (SDRAM 16Mbitx16) When i use "#define CONFIG_SKIP_LOWLEVEL_INIT" and "#define CONFIG_SKIP_RELOCATE_UBOOT" then U-BOOT does not work. But if to change a lines in file "/cpu/arm920t/at91rm9200/lowlevel_init.S" : ldr r0, =SMRDATA ldr r1, _MTEXT_BASE sub r0, r0, r1 add r2, r0, #32 //this number valid for me and ldr r0, =SMRDATA1 ldr r1, _MTEXT_BASE sub r0, r0, r1 add r2, r0, #160 //this number valid for me to a line ldr r0, =SMRDATA add r2, r0, #32 //this number valid for me and ldr r0, =SMRDATA1 add r2, r0, #160 //this number valid for me works correctly How to solve a problem? Thank Alexandr ------------------------------------------------------- This SF.net email is sponsored by: Splunk Inc. Do you grep through log files for problems? Stop! Download the new AJAX search engine that makes searching your log files as easy as surfing the web. DOWNLOAD SPLUNK! http://ads.osdn.com/?ad_id=7637&alloc_id=16865&op=click _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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