May 2004 - U-Boot

[U-Boot-Users] booting linux
by Petre Pircalabu 17 May '04

17 May '04

Hello, I have a problem when I'm trying to boot Linux on my platform (PXA255 processor, Strataflash 0x0-0x00800000, SDRAM 0xa0000000- 0xa4000000 and FFUART ). I have compiled the Linux kernel (2.4.19) for my board starting from the CSB226 port. I have created the uImage with the entry point and load address at 0xa0008000. I download over the serial line the image at address 0xa1000000 and after I issued the bootm 0xa1000000 command, the u-boot decompressed the image, but "after starting Linux kernel ..." it hangs. Does anyone encountered this problem? Thanks, Petre

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RE: [U-Boot-Users] How does the stack works in the DCache?
by Woodruff, Richard 17 May '04

17 May '04

I'm not familiar with the port in question, but using the d-cache as temporary memory when external memory is not yet available is a common trick. As long as you don't need more temporary memory then the size of the cache then you can use the cache itself as a temporary store. The cache is probably set up as read/write allocate, to make sure what you write stays in the cache. Even if its just read allocate you could pre allocate a range to make sure you get a hit when you attempt to access that address. Its likely the 4000000 maps to nothing yet, most any address will do, just so long as its marked cacheable. I seem to recall the ppc4xx series had both block mapping ability (forget their names, ittr/dttr/ perhaps) and per page mapping available (mmu). Regards, Richard W. > -----Original Message----- > From: u-boot-users-admin(a)lists.sourceforge.net [mailto:u-boot-users- > admin(a)lists.sourceforge.net] On Behalf Of Frank Young > Sent: Sunday, May 16, 2004 10:38 PM > To: u-boot-users(a)lists.sourceforge.net > Subject: [U-Boot-Users] How does the stack works in the DCache? > > Hello all, > > I am using PPC 405 Walnut with 16M sdram. I got a question regarding the > DCache setting in u-boot cpu/ppc4xx/start.S. I wrote the pseudo-code of > start.S as below: > > (In File cpu/ppc4xx/start.S) > .globl _start > _start: > _start: > clear and set up registers > invalidate I and D caches > Enable 128M cachable regions > set up temporary stack in DCACHE > sdram_init() (cpu/ppc4xx/sdram.c) > > .......... > > I understand the code is trying to set up a stack in DCache. But I didn't > get how the code makes it. Before calling sdram_init(), the stack pointer > is > CFG_INIT_RAM_ADDR = 0x40000000. I suppose this address is not a physical > address and it refers to the address in the DCache. Is that right? But the > CFG_INIT_RAM_ADDR is located in the address space of sdram. So is there > any > address translator in between DCache and CFG_INIT_RAM_ADDR? Or did I miss > anything? I just couldn't figure out how the stack works in DCache... Can > someone give me any clue? Thanks! > > Frank > > _________________________________________________________________ > Is your PC infected? Get a FREE online computer virus scan from McAfee(r) > Security. http://clinic.mcafee.com/clinic/ibuy/campaign.asp?cid=3963 > > > > ------------------------------------------------------- > This SF.Net email is sponsored by: SourceForge.net Broadband > Sign-up now for SourceForge Broadband and get the fastest > 6.0/768 connection for only $19.95/mo for the first 3 months! > http://ads.osdn.com/?ad_id=2562&alloc_id=6184&op=click > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] How does the stack works in the DCache?
by Frank Young 17 May '04

17 May '04

Hello all, I am using PPC 405 Walnut with 16M sdram. I got a question regarding the DCache setting in u-boot cpu/ppc4xx/start.S. I wrote the pseudo-code of start.S as below: (In File cpu/ppc4xx/start.S) .globl _start _start: _start: clear and set up registers invalidate I and D caches Enable 128M cachable regions set up temporary stack in DCACHE sdram_init() (cpu/ppc4xx/sdram.c) .......... I understand the code is trying to set up a stack in DCache. But I didn't get how the code makes it. Before calling sdram_init(), the stack pointer is CFG_INIT_RAM_ADDR = 0x40000000. I suppose this address is not a physical address and it refers to the address in the DCache. Is that right? But the CFG_INIT_RAM_ADDR is located in the address space of sdram. So is there any address translator in between DCache and CFG_INIT_RAM_ADDR? Or did I miss anything? I just couldn't figure out how the stack works in DCache... Can someone give me any clue? Thanks! Frank _________________________________________________________________ Is your PC infected? Get a FREE online computer virus scan from McAfee® Security. http://clinic.mcafee.com/clinic/ibuy/campaign.asp?cid=3963

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[U-Boot-Users] CPM on 8250 board seems stuck.
by Subodh Nijsure 16 May '04

16 May '04

Hello, I have a PPC8250 based on which I am trying to boot u-boot. First I am using 8260 toolchain to compile this image, as 8250 is supposed to be equivalent of 8260. I have configured SCC1 to be the console port. When I step through the code using BDI, I see is the code is stuck in a while loop in serial_putc waiting for the Buffer descriptor ready bit to get cleared in putc function. while ( tbdf->cbd_sc & BD_SC_READY ) ; According to the hardware configuration the CPM should be running at 200 Mhz and core at 300 Mhz. I have CPM factor of 3, , Core Factor 4.5 Now when I reset the SCM by writing to the reset regiser, CPM is supposed to clear the bit when reset is done and I see that CPM is resetting itself correctly. However I am bit stumped as to why the buffer descriptor may not be getting cleared. I have checked the external signal CTS, the Tx should be happening. I have tried all the baud rates. Only thing I have not tried is auto-baud. So yesterday I changed order of init and tried to initialize the I2C first and right after the I2C init tried to perform a read something from a address I know where a I2C device is located, I don't see any activity lines on those pins there either. It appears to me that CPM is "dead". Now how do I prove things either way, that it is not dead or its is working. Any CLUES I would really appreciate them. In case someone does want to take at my config file I have attached it. Anybody here that has done 8250 board, and booted u-boot on it, care to share your config.h file? -Subodh Nijsure

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[U-Boot-Users] sh3 port
by Evgeni Dobrev 16 May '04

16 May '04

Hi, I am interested in porting das U-Boot for the SH3 CPU architecture. Does such an effort already exist ? When not what would be a good starting point? Cheers, evgeni

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[U-Boot-Users] [PATCH] configh
by Robert Schwebel 16 May '04

16 May '04

ChangeLog: * Patch by Robert Schwebel, 14 May 2004: use config.h (which is needed in serial.c for CFG_HZ) Robert -- Dipl.-Ing. Robert Schwebel | http://www.pengutronix.de Pengutronix - Linux Solutions for Science and Industry Handelsregister: Amtsgericht Hildesheim, HRA 2686 Hornemannstraße 12, 31137 Hildesheim, Germany Phone: +49-5121-28619-0 | Fax: +49-5121-28619-4

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RE: [U-Boot-Users] (no subject)
by Vidya S 14 May '04

14 May '04

hi, i am using smc driver for blackfin processor. it working fine. i am not sure of the question u have asked. i mean, i havent done any change other than what has been released by you. i havent added any init in eth.c regards vidya -----Original Message----- From: u-boot-users-admin(a)lists.sourceforge.net [mailto:u-boot-users-admin@lists.sourceforge.net]On Behalf Of Wolfgang Kanovsky Sent: Thursday, May 13, 2004 9:37 PM To: U-Boot-Users Subject: [U-Boot-Users] (no subject) Importance: High Hi anyone here who knows how the CONFIG_DRIVER_SMC91111 is used ..when the chip is on the ISA - BUS mean it is not in the eth.c file for init ( i have configured it in the board.h file ...)? greets Wolfgang K. ------------------------------------------------------- This SF.Net email is sponsored by: SourceForge.net Broadband Sign-up now for SourceForge Broadband and get the fastest 6.0/768 connection for only $19.95/mo for the first 3 months! http://ads.osdn.com/?ad_id=2562&alloc_id=6184&op=click _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] board/x/flash.c required calls
by Daren Hayward 14 May '04

14 May '04

I have a custom board based on the walnut 405, I have managed to get U-Boot up and running on the board until it tries to setup the Flash, I have code that already works with for the flash (in house bootloader) and I need to know what calls are required in flash.c i.e. flash_init(), is there a document containing this information? I have also tried to get CFI to detect the flash, but it is unable to determine the flash type (ATMEL AT49BV322A, operating as 4Mx8) , I have a JTAG programmer that successfully reads the CFI data too. I #defined DEBUG 1 and can see the attempt of CFI to detect the flash, alas no valid data is returned. Cheers Daren

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[U-Boot-Users] Map output...
by Wolfgang Kanovsky 14 May '04

14 May '04

Hi all Can anyone help me too understand the output of the map file .... 0x08fd702b ali512x_set_fdc 0x08fd7278 ali512x_set_rtc 0x08fd74ce __u_boot_cmd_start = . .u_boot_cmd 0x08fd74d0 0x4c8 *(.u_boot_cmd) .u_boot_cmd 0x08fd74d0 0x18 common/libcommon.a(cmd_autoscript.o) 0x08fd74d0 __u_boot_cmd_autoscr .u_boot_cmd 0x08fd74e8 0x18 common/libcommon.a(cmd_bdinfo.o) 0x08fd74e8 __u_boot_cmd_bdinfo .u_boot_cmd 0x08fd7500 0x30 common/libcommon.a(cmd_boot.o) 0x08fd7518 __u_boot_cmd_reset is from the U-Boot.map file of (sc520 board) 0x08fd74ce __u_boot_cmd_start = . should point to ".u_boot_cmd 0x08fd74d0" but it points to itself (2 Bytes Wrong! ) Why could that be ? comes this "offset" from a wrong <board>.lds file with misalignes or wrong alinement ?? second problem : *fill* 0x08fdf6bc 0x4 00 .rodata.str1.32 0x08fdf6c0 0x20b fs/jffs2/libjffs2.a(jffs2_1pass.o) .rel.dyn 0x03f00000 . = 0x3f00000 0x03f00000 _i386boot_romdata_dest = <code 335> (.) .data 0x03f00000 0xcd0 load address 0x08fdf8cb code335 means: the linker can"t find the section holding the code .. same 0x00000cd0 _i386boot_romdata_size = (SIZEOF (.data) + SIZEOF (.got)) 0x03f00cd0 . = ALIGN (0x4) 0x03f00cd0 _i386boot_bss_start = <code 335> (.) .bss 0x03f00ce0 0xadcc *(.bss) .bss 0x03f00ce0 0xa8 lib_i386/libi386.a(board.o) onby i post the board.lds file maybe their is one in here who can help me correct the file or tell me what i made wrong ... thanks a lot Wolfgang K. =================================================================== /* * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, daniel(a)omicron.se. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") OUTPUT_ARCH(i386) ENTRY(_start) SECTIONS { . = 0x8fc0000; /* Where bootcode in the flash is mapped */ .text : { *(.text); } __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; . = ALIGN(4); .rodata : { *(.rodata) *(.rodata.*) } . = 0x3f00000; /* Ram data segment to use (63Mb lastfrom top)*/ _i386boot_romdata_dest = ABSOLUTE(.); .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } _i386boot_romdata_start = LOADADDR(.data); . = ALIGN(4); .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got); . = ALIGN(4); _i386boot_bss_start = ABSOLUTE(.); .bss : { *(.bss) } _i386boot_bss_size = SIZEOF(.bss); /* 16bit realmode trampoline code */ .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) } _i386boot_realmode = LOADADDR(.realmode); _i386boot_realmode_size = SIZEOF(.realmode); /* 16bit BIOS emulation code (just enough to boot Linux) */ .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } _i386boot_bios = LOADADDR(.bios); _i386boot_bios_size = SIZEOF(.bios); /* The load addresses below assumes that the flash * will be mapped so that 0x8ff0000 == 0xffff0000 * at reset time * * The fe00 and ff00 offsets of the start32 and start16 * segments are arbitrary, the just have to be mapped * at reset and the code have to fit. * The fff0 offset of reset is important, however. */ . = 0xfffffe00; .start32 : AT (0x8fffe00) { *(.start32); } . = 0xff00; .start16 : AT (0x8ffff00) { *(.start16); } . = 0xfff0; .reset : AT (0x8fffff0) { *(.reset); } _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); } _

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[U-Boot-Users] U-Boot on LH7A400
by Devraj Mukherjee 14 May '04

14 May '04

Hi there, Is anyone out there using a Sharp LH7A400 (http://logicpd.com) and UBoot. We are new to getting Linux working on this board and are wonderng which boot loader to use. UBoot seems to be the choice :-) if anyone of you are using UBoot on these boards, can you please send us an image of the bootloader so we can give it a shot. Any other resources are welcome, thanks for your time Devraj -- --------------------------------------------------------------------- System Administration Team Eternity Technologies Pty. Ltd. P O Box 5949 Wagga Wagga 2650 NSW AUS Phone/Fax +61-2-69717131 http://eternitytechnologies.com/ ---------------------------------------------------------------------

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