October 2004 - U-Boot

[U-Boot-Users] [PATCH] Option to enable XLB pipelining in MPC5200
by Mark Jonas 11 Oct '04

11 Oct '04

Hello, this patch adds the option CFG_XLB_PIPELINING to cpu/mpc5xxx/cpu_init.c to enable XLB pipelining. This improves FTP performance and is enabled in IceCube by default. Other MPC5200 boards should benefit from this as well. Regards Mark cpu/mpc5xxx/cpu_init.c | 5 +++++ cpu/mpc5xxx/pci_mpc5200.c | 5 ----- include/configs/IceCube.h | 2 ++ 3 files changed, 7 insertions(+), 5 deletions(-) * Patch by Mark Jonas, 31 August 2004: Added option CFG_XLB_PIPELINING to cpu/mpc5xxx/cpu_init.c to enable XLB pipelining. This improves FTP performance and is enabled in IceCube by default.

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[U-Boot-Users] Re: [Pacth]Some fixes on RPXlite DW
by Sam Song 11 Oct '04

11 Oct '04

Sam Song <samsongshu(a)yahoo.com.cn> wrote： > Hi, > > I got a nudge from some folk chatting with Wolfgang > about RESET and did this patch. All for RPXlite_DW > board. > > * Patch by Sam Song, 21 August 2004: > - Add RESET support for RPXlite_DW board > - Adjust CPU:BUS frequency rato 1:1 when core > frequency less than 50MHz OK, I give up this patch for it as updated as follows and all against CVS: * Patch by Sam Song, 31 August 2004: - Updating RPXlite_DW board on RESET/PREBOOT Index: board/RPXlite_dw/README =================================================================== RCS file: /cvsroot/u-boot/u-boot/board/RPXlite_dw/README,v retrieving revision 1.1 diff -p -u -r1.1 README --- board/RPXlite_dw/README 9 Jun 2004 21:04:49 -0000 1.1 +++ board/RPXlite_dw/README 31 Aug 2004 01:58:04 -0000 @@ -2,9 +2,9 @@ After following the step of Yoo. Jonghoon and Wolfgang Denk, I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW. -There are three differences between the Yoo-ported RPXlite and the RPXlite_DW. +There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW. -Board(in U-BOOT) version(in EmbeddedPlanet) CPU SDRAM FLASH +Board(in U-Boot) version(in EmbeddedPlanet) CPU SDRAM FLASH RPXlite RPXlite CW 850 16MB 4MB RPXlite_DW RPXlite DW 823e 64MB 16MB @@ -17,6 +17,7 @@ It has the following three features: The default setting is 48MHz.To get a 64MHz u-boot,just add '64' in make command,like +make distclean make RPXlite_DW_64_config make all @@ -28,19 +29,21 @@ didn't use EEPROM for ENV is that Planet home.Because of the possibility of using two firewares on this board,I didn't 'disturb' EEPROM.To get NVRAM support,you may use the following build command: +make distclean make RPXlite_DW_NVRAM_config make all 3. LCD panel support -To support the Platform better,I added LCD panel(NL6448BC20-08) function.But bewear of -the fact that once you build this support and program it to FLASH,you should make sure -you put workable kernel and ramdisk at the right place in FLASH or through NFS. -Otherwise, you must erase this fireware manually via BDI2000 or ICE tools.So this -function is used for deployment and demo only.Pls look before you leap. +To support the Platform better, I added LCD panel(NL6448BC20-08) function. +For the convenience of debug, CONFIG_PERBOOT was supported. So you just +perss ENTER if you want to get a serial console in boot count down. +Then you can switch to LCD and serial console freely just typing +'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled. To get a LCD support u-boot,you can do the following: +make distclean make RPXlite_DW_LCD_config make all @@ -68,7 +71,7 @@ make RPXlite_DW_64_LCD_config The boot process by "make RPXlite_DW_config" could be: -U-Boot 1.1.1 (Jun 8 2004 - 11:16:30) +U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache Board: RPXlite_DW @@ -84,6 +87,64 @@ u-boot> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +A word on the U-Boot enviroment variable setting and usage : + +In the beginning, you could just need very simple defult environment variable setting, +like[include/configs/RPXlite.h] : + +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "bootm" + +This is enough for kernel NFS test. But as debug process goes on, you would expect +to save some time on environment variable setting and u-boot/kernel updating. +So the default environment variable setting would become more complicated. Just like +the one I did in include/configs/RPXlite_DW.h. + +Two u-boot commands, ku and uu, should be careful to use. They were designed to update +kernel and u-boot image file respectively. You must tftp your image to default address +'100000' and then use them correctly. Yeah, you can create your own command to do this +job. :-) The example u-boot image updating process could be : + +u-boot>t 100000 RPXlite_DW_LCD.bin +Using SCC ETHERNET device +TFTP from server 172.16.115.6; our IP address is 172.16.115.7 +Filename 'RPXlite_DW_LCD.bin'. +Load address: 0x100000 +Loading: ############################# +done +Bytes transferred = 144700 (2353c hex) +u-boot>run uu +Un-Protect Flash Sectors 0-4 in Bank # 1 +Erase Flash Sectors 0-4 in Bank # 1 +.... done +Copy to Flash... done +ff000000: 27051956 552d426f 6f742031 2e312e32 '..VU-Boot 1.1.2 +ff000010: 20284175 67203239 20323030 34202d20 (Aug 29 2004 - +ff000020: 31353a32 303a3238 29000000 00000000 15:20:28)....... +ff000030: 00000000 00000000 00000000 00000000 ................ +ff000040: 00000000 00000000 00000000 00000000 ................ +ff000050: 00000000 00000000 00000000 00000000 ................ +ff000060: 00000000 00000000 00000000 00000000 ................ +ff000070: 00000000 00000000 00000000 00000000 ................ +ff000080: 00000000 00000000 00000000 00000000 ................ +ff000090: 00000000 00000000 00000000 00000000 ................ +ff0000a0: 00000000 00000000 00000000 00000000 ................ +ff0000b0: 00000000 00000000 00000000 00000000 ................ +ff0000c0: 00000000 00000000 00000000 00000000 ................ +ff0000d0: 00000000 00000000 00000000 00000000 ................ +ff0000e0: 00000000 00000000 00000000 00000000 ................ +ff0000f0: 00000000 00000000 00000000 00000000 ................ +u-boot updating finished +u-boot> + +Also for environment updating, 'run eu' could let you erase OLD default environment variable +and then use the working u-boot environment setting. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + I'd like to extend my heartfelt gratitute to kind people for helping me work it out. I would particually thank Wolfgang Denk for his nice help. @@ -93,4 +154,4 @@ Sam Song, samsongshu(a)yahoo.com.cn Institute of Electrical Machinery and Controls Shanghai University -June 8,2004 +August 29,2004 Index: include/configs/RPXlite_DW.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/configs/RPXlite_DW.h,v retrieving revision 1.2 diff -p -u -r1.2 RPXlite_DW.h --- include/configs/RPXlite_DW.h 19 Jun 2004 21:19:13 -0000 1.2 +++ include/configs/RPXlite_DW.h 31 Aug 2004 01:58:21 -0000 @@ -60,18 +60,20 @@ #define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ #ifdef CONFIG_LCD -#define CONFIG_BOOTDELAY 12 /* autoboot after 12 seconds */ +#define CONFIG_BOOTDELAY 6 /* autoboot after 12 seconds */ #else #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #endif +/* pre-boot commands */ +#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" + #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "nfsargs=setenv bootargs console=ttyS0,9600 root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ramargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ - "root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ + "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \ "addip=setenv bootargs $(bootargs) " \ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ ":$(hostname):$(netdev):off panic=1\0" \ @@ -82,9 +84,19 @@ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ "gatewayip=172.16.115.254\0" \ "netmask=255.255.255.0\0" \ - "kernel_addr=ff880000\0" \ - "ramdisk_addr=ff980000\0" \ - "" + "kernel_addr=ff040000\0" \ + "ramdisk_addr=ff200000\0" \ + "ku=era $(kernel_addr) ff1fffff;cp.b 100000 $(kernel_addr) " \ + "$(filesize);md $(kernel_addr);" \ + "echo kernel updating finished\0" \ + "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \ + "$(filesize);md ff000000;" \ + "echo u-boot updating finished\0" \ + "eu=protect off 1:6;era 1:6;reset\0" \ + "lcd=setenv stdout lcd;setenv stdin lcd\0" \ + "ser=setenv stdout serial;setenv stdin serial\0" \ + "verify=no" + #define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -178,6 +190,8 @@ #define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ #endif +#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) + /*----------------------------------------------------------------------- * Cache Configuration */ @@ -249,9 +263,12 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF00 -/* Up to 64MHz system clock, we use 1:2 SYSTEM/BUS ratio */ +/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */ +#if defined(RPXlite_64MHz) #define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */ - +#else +#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ +#endif /*----------------------------------------------------------------------- * PCMCIA stuff *----------------------------------------------------------------------- _________________________________________________________ Do You Yahoo!? 150万曲MP3疯狂搜，带您闯入音乐殿堂 http://music.yisou.com/ 美女明星应有尽有，搜遍美图、艳图和酷图 http://image.yisou.com 1G就是1000兆，雅虎电邮自助扩容！ http://cn.rd.yahoo.com/mail_cn/tag/1g/*http://cn.mail.yahoo.com/event/mail_…

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[U-Boot-Users] [PATCH] Running from SDRAM Detection on omap1510inn
by Michael Bendzick 11 Oct '04

11 Oct '04

Included is a patch that improves the detection scheme in platform.S that the omap1510inn build uses to determine whether or not it is running from SDRAM. The result of the detection is used to determine if the SDRAM configuration registers are safe to change. The previous implementation only made a distinction between running from Flash at 0x0 or SDRAM at 0x10000000. This patch allows U-Boot to run from internal SRAM at 0x20000000 as well and still realize that it can safely configure external SDRAM. Attention 1610 Innovator Users/Owners: Please give this patch a try on your boards as well, as it should work exactly the same. Change log snippet: * Patch by Michael Bendzick, 30 Aug 2004: - Improve platform.S code for omap1510inn that detects whether code is running from SDRAM or not. Patch allows SDRAM to be configured if code is running out of SRAM at 0x20000000. -Michael Bendzick Systems and Software Engineering Logic Product Development www.logicpd.com

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[U-Boot-Users] Re: FW: Wind River SBC8560 Uboot support
by Wolfgang Denk 11 Oct '04

11 Oct '04

In message <FB3BAE941CB9B24782B2DE43D755BD89040CD818(a)ala-mail02.wrs.com> you wrote: > > In accordance with our last correspondence, I have made the following > modifications to the attached patch, u-boot-1.1.1-Wr_SBC85xxPQ3.patch. This > patch will upgrade u-boot-1.1.1 to support WindRiver's SBC8560/8540 > PowerQUICCIII board. Mostly added, thanks. The parts NOT added are as follows: diff -Naur ../u-boot-1.1.1/cpu/mpc85xx/interrupts.c ./cpu/mpc85xx/interrupts.c --- ../u-boot-1.1.1/cpu/mpc85xx/interrupts.c 2003-10-15 19:53:51.000000000 -0400 +++ ./cpu/mpc85xx/interrupts.c 2004-08-27 13:01:50.000000000 -0400 None of the other existing 85xx boards needs functions get_tbl() or set_tbl() like you do. Since interrupt handling is definitely not board dependent I would like to understand why you think you need this stuff while others can do without it. diff -Naur ../u-boot-1.1.1/cpu/mpc85xx/tsec.c ./cpu/mpc85xx/tsec.c --- ../u-boot-1.1.1/cpu/mpc85xx/tsec.c 2004-04-18 17:45:44.000000000 -0400 +++ ./cpu/mpc85xx/tsec.c 2004-08-30 12:04:30.000000000 -0400 ... diff -Naur ../u-boot-1.1.1/cpu/mpc85xx/tsec.h ./cpu/mpc85xx/tsec.h --- ../u-boot-1.1.1/cpu/mpc85xx/tsec.h 2004-04-18 17:45:44.000000000 -0400 +++ ./cpu/mpc85xx/tsec.h 2004-08-27 14:31:49.000000000 -0400 ... Patches don't apply against CVS tree. Please clean up your code and resubmit new patch against top of tree in CVS. diff -Naur ../u-boot-1.1.1/README ./README --- ../u-boot-1.1.1/README 2004-04-23 16:32:05.000000000 -0400 +++ ./README 2004-08-27 13:11:30.000000000 -0400 Please resubmit and keep lists sorted! Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de Nothing ever becomes real until it is experienced. - John Keats

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[U-Boot-Users] [PATCH] Configure omap1510inn board to use drivers/cfi_flash.c
by Michael Bendzick 11 Oct '04

11 Oct '04

Included is a patch to make the TI OMAP 1510 Innovator board make use of the CFI driver and buffered writes, increasing the write speed by a factor of about 10. Change log snippet: * Patch by Michael Bendzick, 30 Aug 2004: - Configure omap1510inn board to use drivers/cfi_flash.c Wolfgang: Note that this patch entirely removes board/omap1510inn/flash.c. If you would prefer to keep this file around for posterity, I could resubmit the patch. -Michael Bendzick Systems and Software Engineering Logic Product Development www.logicpd.com

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[U-Boot-Users] [PATCH] lpd7a40x register defs, include consolidation
by Paul Ruhland 10 Oct '04

10 Oct '04

Wolfgang, I know you dislike large patches with many changes but I am hoping you will accept this. I've changed the register definitions to be in the style preferred by the armlinux folks. Unfortunately, I changed this locally before consolidating the board config includes and improving the SDRAM configuration handling. So I can't really submit the latter changes seperately without many small incremental patches and large headaches on my end. I will do it if you insist since these changes are quite an improvement for these boards...but it may take a while. CHANGELOG * Patch by Paul Ruhland, 29 August 2004 - change register definitions to use the __REG style preferred by the arm linux community - add targets to Makefile for all card engine SDRAM configurations - add support for all SDRAM configurations in board config includes, 'sdram_init', and board config.mk - add CONFIG_LPD7A404 to 'ARM base boards' in toplevel README - add CPLD revision detection to handle hardware variations between card-engine revisions - consolidate existing board config includes into generic 'lpd7a40x-10.h' and 'lpd7a40x.h'... differences between boards are small enough not to warrent seperate files

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[U-Boot-Users] Generating b-records for DragonBall i.MX
by Steven Scholz 10 Oct '04

10 Oct '04

Hi there, I just hacked a simple script that converts u-boot.bin into a text file containg processor init code, SynchFlash programming code and U-Boot data in form of so called b-records. This can be used to programm U-Boot into (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L 0AFE1F3410202E2E2E000000002073756363656564/ 0AFE1F44102E0A0000206661696C656420210A0000/ 0AFE100000 ... MX1ADS Sync-flash Programming Utility v0.5 2002/08/21 Source address (stored in 0x0AFE0000): 0x0A000000 Target address (stored in 0x0AFE0004): 0x0C000000 Size (stored in 0x0AFE0008): 0x0001A320 Press any key to start programming ... Erasing ... Blank checking ... Programming ... Verifying flash ... succeed. Programming finished. So no need for a BDI2000 anymore... ;-) This is working on my MX1ADS eval board. Hope this could be useful for someone. (Maybe we even want to include this into the tools directory.) Steven

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[U-Boot-Users] [PATCH] Nios-II Support (7 of 7)
by Scott McNutt 10 Oct '04

10 Oct '04

-Add support for Altera Nios-II processors. -Add support for Psyent PCI-5441 board. -Add support for Psyent PK1C20 board. Regards, --Scott diff -Naurb u-boot-2004-08-24/MAINTAINERS u-boot-nios2/MAINTAINERS --- u-boot-2004-08-24/MAINTAINERS 2004-07-11 18:37:59.000000000 -0400 +++ u-boot-nios2/MAINTAINERS 2004-08-24 06:07:20.000000000 -0400 @@ -429,6 +429,18 @@ DK1C20 Nios-32 ######################################################################### +# Nios-II Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Scott McNutt <smcnutt(a)psyent.com> + + PCI5441 Nios-II + PK1C20 Nios-II + +######################################################################### # MicroBlaze Systems: # # # # Maintainer Name, Email Address # diff -Naurb u-boot-2004-08-24/MAKEALL u-boot-nios2/MAKEALL --- u-boot-2004-08-24/MAKEALL 2004-08-01 18:48:16.000000000 -0400 +++ u-boot-nios2/MAKEALL 2004-08-24 06:20:27.000000000 -0400 @@ -188,6 +188,12 @@ " ######################################################################### +## Nios-II Systems +######################################################################### + +LIST_nios2="PCI5441 PK1C20" + +######################################################################### ## MicroBlaze Systems ######################################################################### @@ -219,7 +225,7 @@ arm|SA|ARM7|ARM9|pxa|ixp| \ microblaze| \ mips| \ - nios| \ + nios|nios2| \ x86|I486) for target in `eval echo '$LIST_'${arg}` do diff -Naurb u-boot-2004-08-24/Makefile u-boot-nios2/Makefile --- u-boot-2004-08-24/Makefile 2004-08-04 17:56:49.000000000 -0400 +++ u-boot-nios2/Makefile 2004-08-24 06:01:57.000000000 -0400 @@ -72,6 +72,9 @@ ifeq ($(ARCH),nios) CROSS_COMPILE = nios-elf- endif +ifeq ($(ARCH),nios2) +CROSS_COMPILE = nios2-elf- +endif ifeq ($(ARCH),m68k) CROSS_COMPILE = m68k-elf- endif @@ -1443,6 +1446,15 @@ } @./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv +######################################################################### +## Nios-II +######################################################################### + +PK1C20_config : unconfig + @./mkconfig PK1C20 nios2 nios2 pk1c20 psyent + +PCI5441_config : unconfig + @./mkconfig PCI5441 nios2 nios2 pci5441 psyent #======================================================================== # MicroBlaze diff -Naurb u-boot-2004-08-24/nios2_config.mk u-boot-nios2/nios2_config.mk --- u-boot-2004-08-24/nios2_config.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/nios2_config.mk 2004-08-24 05:56:44.000000000 -0400 @@ -0,0 +1,26 @@ +# +# (C) Copyright 2004 +# Psyent Corporation <www.psyent.com> +# Scott McNutt <smcnutt(a)psyent.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ +PLATFORM_CPPFLAGS += -ffixed-r15 diff -Naurb u-boot-2004-08-24/README u-boot-nios2/README --- u-boot-2004-08-24/README 2004-08-02 19:22:59.000000000 -0400 +++ u-boot-nios2/README 2004-08-24 06:24:52.000000000 -0400 @@ -139,6 +139,7 @@ - mpc8260 Files specific to Motorola MPC8260 CPUs - mpc85xx Files specific to Motorola MPC85xx CPUs - nios Files specific to Altera NIOS CPUs + - nios2 Files specific to Altera Nios-II CPUs - ppc4xx Files specific to IBM PowerPC 4xx CPUs - pxa Files specific to Intel XScale PXA CPUs - s3c44b0 Files specific to Samsung S3C44B0 CPUs @@ -244,6 +245,10 @@ ---------------------- CONFIG_MICROBLAZE + Nios-2 based CPUs: + ---------------------- + CONFIG_NIOS2 + - Board Type: Define exactly one of @@ -304,6 +309,11 @@ CONFIG_SUZAKU + Nios-2 based boards: + ------------------------ + + CONFIG_PCI5441 CONFIG_PK1C20 + - CPU Module Type: (if CONFIG_COGENT is defined) Define exactly one of diff -Naurb u-boot-2004-08-24/CREDITS u-boot-nios2/CREDITS --- u-boot-2004-08-24/CREDITS 2004-07-11 15:17:20.000000000 -0400 +++ u-boot-nios2/CREDITS 2004-08-24 06:06:07.000000000 -0400 @@ -286,7 +286,10 @@ N: Scott McNutt E: smcnutt(a)psyent.com -D: Support for Altera Nios-32 CPU, for Nios Cyclone Development Kit (DK-1C20) +D: Support for Altera Nios-32 CPU +D: Support for Altera Nios-II CPU +D: Support for Nios Cyclone Development Kit (DK-1C20) +W: http://www.psyent.com N: Rolf Offermanns E: rof(a)sysgo.de diff -Naurb u-boot-2004-08-24/examples/Makefile u-boot-nios2/examples/Makefile --- u-boot-2004-08-24/examples/Makefile 2004-07-10 17:45:58.000000000 -0400 +++ u-boot-nios2/examples/Makefile 2004-08-24 06:43:02.000000000 -0400 @@ -41,6 +41,10 @@ LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds endif +ifeq ($(ARCH),nios2) +LOAD_ADDR = 0x00800000 -L $(gcclibdir) -T nios2.lds +endif + ifeq ($(ARCH),m68k) LOAD_ADDR = 0x20000 -L $(clibdir) endif diff -Naurb u-boot-2004-08-24/examples/nios2.lds u-boot-nios2/examples/nios2.lds --- u-boot-2004-08-24/examples/nios2.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/examples/nios2.lds 2004-08-24 06:43:40.000000000 -0400 @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-littlenios2") +OUTPUT_ARCH(nios2) +ENTRY(_start) + +SECTIONS +{ + .text : + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + } + . = ALIGN (4); + _etext = .; + PROVIDE (etext = .); + + /* INIT DATA sections - "Small" data (see the gcc -G option) + * is always gp-relative. Here we make all init data sections + * adjacent to simplify the startup code -- and provide + * the global pointer for gp-relative access. + */ + _data = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + } + + . = ALIGN(16); + _gp = .; /* Global pointer addr */ + PROVIDE (gp = .); + + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* UNINIT DATA - Small uninitialized data is first so it's + * adjacent to sdata and can be referenced via gp. The normal + * bss follows. We keep it adjacent to simplify init code. + */ + __bss_start = .; + .sbss : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } + . = ALIGN(4); + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + *(.scommon) + } + . = ALIGN(4); + _end = .; + PROVIDE (end = .); + + /* CMD TABLE - uboot command sections + */ + __uboot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + /* DEBUG -- symbol table, string table, etc. etc. + */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff -Naurb u-boot-2004-08-24/examples/stubs.c u-boot-nios2/examples/stubs.c --- u-boot-2004-08-24/examples/stubs.c 2004-07-10 19:48:42.000000000 -0400 +++ u-boot-nios2/examples/stubs.c 2004-08-24 06:46:53.000000000 -0400 @@ -82,6 +82,21 @@ " jmp %%g0\n" \ " nop \n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x) : "r0"); +#elif defined(CONFIG_NIOS2) +/* + * r15 holds the pointer to the global_data, r8 is call-clobbered + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" movhi r8, %%hi(%0)\n" \ +" ori r8, r0, %%lo(%0)\n" \ +" add r8, r0, r15\n" \ +" ldw r8, 0(r8)\n" \ +" ldw r8, %1(r8)\n" \ +" jmp r8\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r15"); #elif defined(CONFIG_M68K) /* * d7 holds the pointer to the global_data, a0 is a call-clobbered

2 1

[U-Boot-Users] [PATCH] Nios-II Support (6 of 7)
by Scott McNutt 10 Oct '04

10 Oct '04

-Add support for Altera Nios-II processors. -Add support for Psyent PCI-5441 board. -Add support for Psyent PK1C20 board. Regards, --Scott diff -Naurb u-boot-2004-08-24/lib_nios2/board.c u-boot-nios2/lib_nios2/board.c --- u-boot-2004-08-24/lib_nios2/board.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/lib_nios2/board.c 2004-08-24 05:36:48.000000000 -0400 @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2003, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <devices.h> +#include <watchdog.h> +#include <net.h> +#ifdef CONFIG_STATUS_LED +#include <status_led.h> +#endif + + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ + + +extern void malloc_bin_reloc (void); +typedef int (init_fnc_t) (void); + +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +static ulong mem_malloc_start = 0; +static ulong mem_malloc_end = 0; +static ulong mem_malloc_brk = 0; + +/* + * The Malloc area is immediately below the monitor copy in RAM + */ +static void mem_malloc_init (void) +{ + mem_malloc_start = CFG_MALLOC_BASE; + mem_malloc_end = mem_malloc_start + CFG_MALLOC_LEN; + mem_malloc_brk = mem_malloc_start; + memset ((void *) mem_malloc_start, + 0, + mem_malloc_end - mem_malloc_start); +} + +void *sbrk (ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) { + return (NULL); + } + mem_malloc_brk = new; + return ((void *) old); +} + + +/************************************************************************ + * Initialization sequence * + ***********************************************************************/ + +init_fnc_t *init_sequence[] = { + +#if defined(CONFIG_BOARD_EARLY_INIT_F) + board_early_init_f, /* Call board-specific init code early.*/ +#endif + + env_init, + serial_init, + console_init_f, + display_options, + checkcpu, + checkboard, + NULL, /* Terminate this list */ +}; + + +/***********************************************************************/ +void board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + bd_t *bd; + init_fnc_t **init_fnc_ptr; + char *s, *e; + int i; + + /* Pointer is writable since we allocated a register for it. + * Nios treats CFG_GBL_DATA_OFFSET as an address. + */ + gd = (gd_t *)CFG_GBL_DATA_OFFSET; + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + memset( gd, 0, CFG_GBL_DATA_SIZE ); + + gd->bd = (bd_t *)(gd+1); /* At end of global data */ + gd->baudrate = CONFIG_BAUDRATE; + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + + bd = gd->bd; + bd->bi_memstart = CFG_SDRAM_BASE; + bd->bi_memsize = CFG_SDRAM_SIZE; + bd->bi_flashstart = CFG_FLASH_BASE; +#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE) + bd->bi_sramstart= CFG_SRAM_BASE; + bd->bi_sramsize = CFG_SRAM_SIZE; +#endif + bd->bi_baudrate = CONFIG_BAUDRATE; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + WATCHDOG_RESET (); + if ((*init_fnc_ptr) () != 0) { + hang (); + } + } + + WATCHDOG_RESET (); + bd->bi_flashsize = flash_init(); + + WATCHDOG_RESET (); + mem_malloc_init(); + malloc_bin_reloc(); + env_relocate(); + + bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + s = getenv ("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) s = (*e) ? e + 1 : e; + } + + WATCHDOG_RESET (); + devices_init(); + jumptable_init(); + console_init_r(); + + WATCHDOG_RESET (); + interrupt_init (); + + /* main_loop */ + for (;;) { + WATCHDOG_RESET (); + main_loop (); + } +} + + +/***********************************************************************/ + +void hang (void) +{ + disable_interrupts (); + puts("### ERROR ### Please reset board ###\n"); + for (;;); +} diff -Naurb u-boot-2004-08-24/lib_nios2/cache.S u-boot-nios2/lib_nios2/cache.S --- u-boot-2004-08-24/lib_nios2/cache.S 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/lib_nios2/cache.S 2004-08-24 05:36:48.000000000 -0400 @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + + .text + + .global flush_dcache + +flush_dcache: + add r5, r5, r4 + movhi r8, %hi(CFG_DCACHELINE_SIZE) + ori r8, r8, %lo(CFG_DCACHELINE_SIZE) +0: flushd 0(r4) + add r4, r4, r8 + bltu r4, r5, 0b + ret + + + .global flush_icache + +flush_icache: + add r5, r5, r4 + movhi r8, %hi(CFG_ICACHELINE_SIZE) + ori r8, r8, %lo(CFG_ICACHELINE_SIZE) +1: flushi r4 + add r4, r4, r8 + bltu r4, r5, 1b + ret + + .global flush_cache + +flush_cache: + add r5, r5, r4 + mov r9, r4 + mov r10, r5 + + movhi r8, %hi(CFG_DCACHELINE_SIZE) + ori r8, r8, %lo(CFG_DCACHELINE_SIZE) +0: flushd 0(r4) + add r4, r4, r8 + bltu r4, r5, 0b + + mov r4, r9 + mov r5, r10 + movhi r8, %hi(CFG_ICACHELINE_SIZE) + ori r8, r8, %lo(CFG_ICACHELINE_SIZE) +1: flushi r4 + add r4, r4, r8 + bltu r4, r5, 1b + + sync + flushp + ret diff -Naurb u-boot-2004-08-24/lib_nios2/divmod.c u-boot-nios2/lib_nios2/divmod.c --- u-boot-2004-08-24/lib_nios2/divmod.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/lib_nios2/divmod.c 2004-08-24 05:36:48.000000000 -0400 @@ -0,0 +1,101 @@ +/* + * This file is part of GNU CC. + * + * GNU CC is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published + * by the Free Software Foundation; either version 2, or (at your + * option) any later version. + * + * GNU CC is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with GNU CC; see the file COPYING. If not, write + * to the Free Software Foundation, 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + */ + + +#include "math.h" + +USItype udivmodsi4 (USItype num, USItype den, word_type modwanted) +{ + USItype bit = 1; + USItype res = 0; + + while (den < num && bit && !(den & (1L << 31))) { + den <<= 1; + bit <<= 1; + } + while (bit) { + if (num >= den) { + num -= den; + res |= bit; + } + bit >>= 1; + den >>= 1; + } + if (modwanted) + return num; + return res; +} + + +SItype __divsi3 (SItype a, SItype b) +{ + word_type neg = 0; + SItype res; + + if (a < 0) { + a = -a; + neg = !neg; + } + + if (b < 0) { + b = -b; + neg = !neg; + } + + res = udivmodsi4 (a, b, 0); + + if (neg) + res = -res; + + return res; +} + + +SItype __modsi3 (SItype a, SItype b) +{ + word_type neg = 0; + SItype res; + + if (a < 0) { + a = -a; + neg = 1; + } + + if (b < 0) + b = -b; + + res = udivmodsi4 (a, b, 1); + + if (neg) + res = -res; + + return res; +} + + +SItype __udivsi3 (SItype a, SItype b) +{ + return udivmodsi4 (a, b, 0); +} + + +SItype __umodsi3 (SItype a, SItype b) +{ + return udivmodsi4 (a, b, 1); +} diff -Naurb u-boot-2004-08-24/lib_nios2/Makefile u-boot-nios2/lib_nios2/Makefile --- u-boot-2004-08-24/lib_nios2/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/lib_nios2/Makefile 2004-08-24 05:36:48.000000000 -0400 @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = cache.o + +COBJS = board.o divmod.o nios_linux.o mult.o time.o + +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff -Naurb u-boot-2004-08-24/lib_nios2/math.h u-boot-nios2/lib_nios2/math.h --- u-boot-2004-08-24/lib_nios2/math.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/lib_nios2/math.h 2004-08-24 05:36:48.000000000 -0400 @@ -0,0 +1,16 @@ +#define BITS_PER_UNIT 8 + +typedef int HItype __attribute__ ((mode (HI))); +typedef unsigned int UHItype __attribute__ ((mode (HI))); + +typedef int SItype __attribute__ ((mode (SI))); +typedef unsigned int USItype __attribute__ ((mode (SI))); + +typedef int word_type __attribute__ ((mode (__word__))); + +struct SIstruct {HItype low, high;}; + +typedef union { + struct SIstruct s; + SItype ll; +} SIunion; diff -Naurb u-boot-2004-08-24/lib_nios2/mult.c u-boot-nios2/lib_nios2/mult.c --- u-boot-2004-08-24/lib_nios2/mult.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/lib_nios2/mult.c 2004-08-24 05:36:48.000000000 -0400 @@ -0,0 +1,56 @@ +/* + * This file is part of GNU CC. + * + * GNU CC is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published + * by the Free Software Foundation; either version 2, or (at your + * option) any later version. + * + * GNU CC is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with GNU CC; see the file COPYING. If not, write + * to the Free Software Foundation, 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + */ + + +#include <common.h> + +#if !defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) + +#include "math.h" + +USItype __mulsi3 (USItype a, USItype b) +{ + USItype c = 0; + + while (a != 0) { + if (a & 1) + c += b; + a >>= 1; + b <<= 1; + } + + return c; +} + + +UHItype __mulhi3 (UHItype a, UHItype b) +{ + UHItype c = 0; + + while (a != 0) { + if (a & 1) + c += b; + a >>= 1; + b <<= 1; + } + + return c; +} + +#endif /*!defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) */ diff -Naurb u-boot-2004-08-24/lib_nios2/nios_linux.c u-boot-nios2/lib_nios2/nios_linux.c --- u-boot-2004-08-24/lib_nios2/nios_linux.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/lib_nios2/nios_linux.c 2004-08-24 05:36:48.000000000 -0400 @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2003, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +/* TODO + */ +void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ +} diff -Naurb u-boot-2004-08-24/lib_nios2/time.c u-boot-nios2/lib_nios2/time.c --- u-boot-2004-08-24/lib_nios2/time.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/lib_nios2/time.c 2004-08-24 05:36:48.000000000 -0400 @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2003, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> + + +extern void dly_clks( unsigned long ticks ); + +void udelay(unsigned long usec) +{ + /* The Nios core doesn't have a timebase, so we do our + * best for now and call a low-level loop that counts + * cpu clocks. + */ + unsigned long cnt = (CONFIG_SYS_CLK_FREQ/1000000) * usec; + WATCHDOG_RESET (); /* trigger watchdog if needed */ + dly_clks (cnt); +}

2 1

[U-Boot-Users] [PATCH] Nios-II Support (5 of 7)
by Scott McNutt 10 Oct '04

10 Oct '04

-Add support for Altera Nios-II processors. -Add support for Psyent PCI-5441 board. -Add support for Psyent PK1C20 board. Regards, --Scott diff -Naurb u-boot-2004-08-24/include/configs/PCI5441.h u-boot-nios2/include/configs/PCI5441.h --- u-boot-2004-08-24/include/configs/PCI5441.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/include/configs/PCI5441.h 2004-08-24 05:54:30.000000000 -0400 @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*------------------------------------------------------------------------ + * BOARD/CPU + *----------------------------------------------------------------------*/ +#define CONFIG_PCI5441 1 /* PCI-5441 board */ +#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ + +#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ +#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ +#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ + +/*------------------------------------------------------------------------ + * CACHE -- the following will support II/s and II/f. The II/s does not + * have dcache, so the cache instructions will behave as NOPs. + *----------------------------------------------------------------------*/ +#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ +#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ +#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ +#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ + +/*------------------------------------------------------------------------ + * MEMORY BASE ADDRESSES + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ +#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ +#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ + +/*------------------------------------------------------------------------ + * MEMORY ORGANIZATION + * -Monitor at top. + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET + +/*------------------------------------------------------------------------ + * FLASH (AM29LV065D) + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ +#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ + +/*------------------------------------------------------------------------ + * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above + * CFG_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) + +/*------------------------------------------------------------------------ + * CONSOLE + *----------------------------------------------------------------------*/ +#if defined(CONFIG_CONSOLE_JTAG) +#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ +#else +#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */ +#endif + +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ + +/*------------------------------------------------------------------------ + * DEBUG + *----------------------------------------------------------------------*/ +#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ + +/*------------------------------------------------------------------------ + * TIMEBASE -- + * + * The high res timer defaults to 1 msec. Since it includes the period + * registers, we can slow it down to 10 msec using TMRCNT. If the default + * period is acceptable, TMRCNT can be left undefined. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ +#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ +#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) +#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) + +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include <cmd_confdefs.h> + +/*------------------------------------------------------------------------ + * MISC + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* Provide extended help*/ +#define CFG_PROMPT "==> " /* Command prompt */ +#define CFG_CBSIZE 256 /* Console I/O buf size */ +#define CFG_MAXARGS 16 /* Max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ +#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ +#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ +#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 + +#endif /* __CONFIG_H */ diff -Naurb u-boot-2004-08-24/include/configs/PK1C20.h u-boot-nios2/include/configs/PK1C20.h --- u-boot-2004-08-24/include/configs/PK1C20.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/include/configs/PK1C20.h 2004-08-24 05:54:10.000000000 -0400 @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*------------------------------------------------------------------------ + * BOARD/CPU + *----------------------------------------------------------------------*/ +#define CONFIG_PK1C20 1 /* PK1C20 board */ +#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ + +#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ +#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ +#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ + +/*------------------------------------------------------------------------ + * CACHE -- the following will support II/s and II/f. The II/s does not + * have dcache, so the cache instructions will behave as NOPs. + *----------------------------------------------------------------------*/ +#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ +#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ +#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ +#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ + +/*------------------------------------------------------------------------ + * MEMORY BASE ADDRESSES + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ +#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ +#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ +#define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */ +#define CFG_SRAM_SIZE 0x00200000 /* 2 MByte */ + +/*------------------------------------------------------------------------ + * MEMORY ORGANIZATION + * -Monitor at top. + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET + +/*------------------------------------------------------------------------ + * FLASH (AM29LV065D) + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ +#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ + +/*------------------------------------------------------------------------ + * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above + * CFG_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) + +/*------------------------------------------------------------------------ + * CONSOLE + *----------------------------------------------------------------------*/ +#if defined(CONFIG_CONSOLE_JTAG) +#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ +#else +#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */ +#endif + +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ + +/*------------------------------------------------------------------------ + * DEBUG + *----------------------------------------------------------------------*/ +#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ + +/*------------------------------------------------------------------------ + * TIMEBASE -- + * + * The high res timer defaults to 1 msec. Since it includes the period + * registers, we can slow it down to 10 msec using TMRCNT. If the default + * period is acceptable, TMRCNT can be left undefined. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ +#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ +#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) +#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) + +/*------------------------------------------------------------------------ + * STATUS LED -- Provides a simple blinking led. For Nios2 each board + * must implement its own led routines -- leds are, after all, + * board-specific, no? + *----------------------------------------------------------------------*/ +#define CFG_LEDPIO_ADDR 0x00920840 /* LED PIO base addr */ +#define CONFIG_STATUS_LED /* Enable status driver */ + +#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ +#define STATUS_LED_STATE 1 /* Blinking */ +#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ + +/*------------------------------------------------------------------------ + * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... + * and really doesn't need any additional clutter. So I choose the lazy + * way out to avoid changes there -- define the base address to ensure + * cache bypass so there's no need to monkey with inx/outx macros. + *----------------------------------------------------------------------*/ +#define CONFIG_SMC91111_BASE 0x80910300 /* Base addr (bypass) */ +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ + +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.2.21 +#define CONFIG_SERVERIP 192.168.2.16 + +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include <cmd_confdefs.h> + +/*------------------------------------------------------------------------ + * MISC + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* Provide extended help*/ +#define CFG_PROMPT "==> " /* Command prompt */ +#define CFG_CBSIZE 256 /* Console I/O buf size */ +#define CFG_MAXARGS 16 /* Max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ +#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ +#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ +#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 + +#endif /* __CONFIG_H */ diff -Naurb u-boot-2004-08-24/include/image.h u-boot-nios2/include/image.h --- u-boot-2004-08-24/include/image.h 2004-04-18 17:13:45.000000000 -0400 +++ u-boot-nios2/include/image.h 2004-08-24 07:16:51.000000000 -0400 @@ -67,6 +67,7 @@ #define IH_CPU_M68K 12 /* M68K */ #define IH_CPU_NIOS 13 /* Nios-32 */ #define IH_CPU_MICROBLAZE 14 /* MicroBlaze */ +#define IH_CPU_NIOS2 15 /* Nios-II */ /* * Image Types diff -Naurb u-boot-2004-08-24/include/nios2.h u-boot-nios2/include/nios2.h --- u-boot-2004-08-24/include/nios2.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/include/nios2.h 2004-08-24 05:49:58.000000000 -0400 @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __NIOS2_H__ +#define __NIOS2_H__ + +/*------------------------------------------------------------------------ + * Control registers -- use with wrctl() & rdctl() + *----------------------------------------------------------------------*/ +#define CTL_STATUS 0 /* Processor status reg */ +#define CTL_ESTATUS 1 /* Exception status reg */ +#define CTL_BSTATUS 2 /* Break status reg */ +#define CTL_IENABLE 3 /* Interrut enable reg */ +#define CTL_IPENDING 4 /* Interrut pending reg */ + +/*------------------------------------------------------------------------ + * Access to control regs + *----------------------------------------------------------------------*/ +#define _str_(x) #x + +#define rdctl(reg)\ + ({unsigned int val;\ + asm volatile( "rdctl %0, ctl" _str_(reg)\ + : "=r" (val) ); val;}) + +#define wrctl(reg,val)\ + asm volatile( "wrctl ctl" _str_(reg) ",%0"\ + : : "r" (val)) + +/*------------------------------------------------------------------------ + * Control reg bit masks + *----------------------------------------------------------------------*/ +#define STATUS_IE (1<<0) /* Interrupt enable */ +#define STATUS_U (1<<1) /* User-mode */ + +/*------------------------------------------------------------------------ + * Bit-31 Cache bypass -- only valid for data access. When data cache + * is not implemented, bit 31 is ignored for compatibility. + *----------------------------------------------------------------------*/ +#define CACHE_BYPASS(a) ((a) | 0x80000000) +#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) + +#endif /* __NIOS2_H__ */ diff -Naurb u-boot-2004-08-24/include/nios2-io.h u-boot-nios2/include/nios2-io.h --- u-boot-2004-08-24/include/nios2-io.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-nios2/include/nios2-io.h 2004-08-24 05:49:58.000000000 -0400 @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera Nios2 Standard Peripherals + ************************************************************************/ + +#ifndef __NIOS2IO_H__ +#define __NIOS2IO_H__ + +/*------------------------------------------------------------------------ + * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_uart_t { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned divisor; /* Baud rate divisor reg */ + unsigned endofpacket; /* End-of-packet reg */ +}nios_uart_t; + +/* status register */ +#define NIOS_UART_PE (1 << 0) /* parity error */ +#define NIOS_UART_FE (1 << 1) /* frame error */ +#define NIOS_UART_BRK (1 << 2) /* break detect */ +#define NIOS_UART_ROE (1 << 3) /* rx overrun */ +#define NIOS_UART_TOE (1 << 4) /* tx overrun */ +#define NIOS_UART_TMT (1 << 5) /* tx empty */ +#define NIOS_UART_TRDY (1 << 6) /* tx ready */ +#define NIOS_UART_RRDY (1 << 7) /* rx ready */ +#define NIOS_UART_E (1 << 8) /* exception */ +#define NIOS_UART_DCTS (1 << 10) /* cts change */ +#define NIOS_UART_CTS (1 << 11) /* cts */ +#define NIOS_UART_EOP (1 << 12) /* eop detected */ + +/* control register */ +#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ +#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ +#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ +#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ +#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_UART_IE (1 << 8) /* exception int ena */ +#define NIOS_UART_TBRK (1 << 9) /* transmit break */ +#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ +#define NIOS_UART_RTS (1 << 11) /* rts */ +#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ + + +/*------------------------------------------------------------------------ + * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_timer_t { + unsigned status; /* Timer status reg */ + unsigned control; /* Timer control reg */ + unsigned periodl; /* Timeout period low */ + unsigned periodh; /* Timeout period high */ + unsigned snapl; /* Snapshot low */ + unsigned snaph; /* Snapshot high */ +}nios_timer_t; + +/* status register */ +#define NIOS_TIMER_TO (1 << 0) /* Timeout */ +#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ + +/* control register */ +#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ +#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ +#define NIOS_TIMER_START (1 << 2) /* Start timer */ +#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ + + +/*------------------------------------------------------------------------ + * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_pio_t { + unsigned int data; /* Data value at each PIO in/out */ + unsigned int direction; /* Data direct. for each PIO bit */ + unsigned int interruptmask; /* Per-bit IRQ enable/disable */ + unsigned int edgecapture; /* Per-bit sync. edge detect & hold */ +}nios_pio_t; + +/* direction register */ +#define NIOS_PIO_OUT (1) /* PIO bit is output */ +#define NIOS_PIO_IN (0) /* PIO bit is input */ + + +/*------------------------------------------------------------------------ + * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_spi_t { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned reserved; /* (master only) */ + unsigned slaveselect; /* SPI slave select mask (master only) */ +}nios_spi_t; + +/* status register */ +#define NIOS_SPI_ROE (1 << 3) /* rx overrun */ +#define NIOS_SPI_TOE (1 << 4) /* tx overrun */ +#define NIOS_SPI_TMT (1 << 5) /* tx empty */ +#define NIOS_SPI_TRDY (1 << 6) /* tx ready */ +#define NIOS_SPI_RRDY (1 << 7) /* rx ready */ +#define NIOS_SPI_E (1 << 8) /* exception */ + +/* control register */ +#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_SPI_IE (1 << 8) /* exception int ena */ +#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ + +/*------------------------------------------------------------------------ + * ASMI + *----------------------------------------------------------------------*/ +typedef volatile struct nios_asmi_t { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned reserved; + unsigned slavesel; /* Slave select */ + unsigned endofpacket; /* End-of-packet reg */ +}nios_asmi_t; + +/* status register */ +#define NIOS_ASMI_ROE (1 << 3) /* rx overrun */ +#define NIOS_ASMI_TOE (1 << 4) /* tx overrun */ +#define NIOS_ASMI_TMT (1 << 5) /* tx empty */ +#define NIOS_ASMI_TRDY (1 << 6) /* tx ready */ +#define NIOS_ASMI_RRDY (1 << 7) /* rx ready */ +#define NIOS_ASMI_E (1 << 8) /* exception */ +#define NIOS_ASMI_EOP (1 << 9) /* eop detected */ + +/* control register */ +#define NIOS_ASMI_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_ASMI_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_ASMI_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_ASMI_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_ASMI_IE (1 << 8) /* exception int ena */ +#define NIOS_ASMI_IEOP (1 << 9) /* rx eop int ena */ +#define NIOS_ASMI_SSO (1 << 10) /* slave select enable */ + +/*------------------------------------------------------------------------ + * JTAG UART + *----------------------------------------------------------------------*/ +typedef volatile struct nios_jtag_t { + unsigned data; /* Data register */ + unsigned control; /* Control register */ +}nios_jtag_t; + +/* data register */ +#define NIOS_JTAG_RVALID (1<<15) /* Read valid */ +#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */ +#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */ + +/* control register */ +#define NIOS_JTAG_RE (1 << 0) /* read intr enable */ +#define NIOS_JTAG_WE (1 << 1) /* write intr enable */ +#define NIOS_JTAG_RI (1 << 8) /* read intr pending */ +#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/ +#define NIOS_JTAG_AC (1 << 10) /* activity indicator */ +#define NIOS_JTAG_RRDY (1 << 12) /* read available */ +#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ + +/*------------------------------------------------------------------------ + * SYSTEM ID + *----------------------------------------------------------------------*/ +typedef volatile struct nios_sysid_t { + unsigned id; /* The system build id*/ + unsigned timestamp; /* Timestamp */ +}nios_sysid_t; + +#endif /* __NIOS2IO_H__ */ diff -Naurb u-boot-2004-08-24/include/status_led.h u-boot-nios2/include/status_led.h --- u-boot-2004-08-24/include/status_led.h 2004-07-10 18:36:00.000000000 -0400 +++ u-boot-nios2/include/status_led.h 2004-08-24 07:18:07.000000000 -0400 @@ -340,6 +340,9 @@ #elif defined(CONFIG_WRSBC8240) /* XXX empty just to avoid the error */ /************************************************************************/ +#elif defined(CONFIG_NIOS2) +/* XXX empty just to avoid the error */ +/************************************************************************/ #else # error Status LED configuration missing #endif

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