Andy Fleming schrieb:
On Tue, Apr 1, 2008 at 8:33 AM, Andre Schwarz andre.schwarz@matrix-vision.de wrote:
Tor,
after investigating the tsec code I'm wondering how your PHY works in RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into account during tsec_init.
/* Init ECNTRL */ regs->ecntrl = ECNTRL_INIT_SETTINGS;
If you look carefully, you'll notice that ecntrl's RPM bit is read-only. Those bits are configured by POR pin strappings.
sorry, my documentation (MPC8349EARM rev.1) declares this register read-write. Of course it will be configured by the HRCW but can be overwritten afterwards.
If this is not true it's a documentation bug.
You may be more familiar with the UEC, which doesn't automatically detect the link type, but is otherwise fairly similar to the tsec.
What do you mean ? I'm trying to get two VSC8601 RGMII PHYs running on a MPC8343B ...
Andy
regards, Andre
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