January 2025 - U-Boot

[PATCH] Fix neighbor discovery ethernet address saving
by seanedmond＠linux.microsoft.com 01 Jan '25

01 Jan '25

From: Sean Edmond <seanedmond(a)microsoft.com> When a successful neighbor advertisement is received, the ethernet address should be saved for later use to avoid having to redo the neighbor discovery process. For example, with TFTP the address should get saved into "net_server_ethaddr". This is being done correctly with ARP for IPv4, but not for neighbor discovery with IPv6. Signed-off-by: Sean Edmond <seanedmond(a)microsoft.com> --- net/ndisc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ndisc.c b/net/ndisc.c index d1cec0601c8..505515f2d95 100644 --- a/net/ndisc.c +++ b/net/ndisc.c @@ -461,8 +461,8 @@ int ndisc_receive(struct ethernet_hdr *et, struct ip6_hdr *ip6, int len) ndisc_extract_enetaddr(ndisc, neigh_eth_addr); /* save address for later use */ - if (!net_nd_packet_mac) - net_nd_packet_mac = neigh_eth_addr; + if (net_nd_packet_mac) + memcpy(net_nd_packet_mac, neigh_eth_addr, 6); /* modify header, and transmit it */ memcpy(((struct ethernet_hdr *)net_nd_tx_packet)->et_dest, -- 2.42.0

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[PATCH] net: tftpput: reset timeout_count when an ACK is received
by Jerome Forissier 01 Jan '25

01 Jan '25

timeout_count is never reset once a tftpput transfer has started. If for whatever reason timeouts occur frequently, but the server keeps replying nonetheless, the transfer may be needlessly aborted. Reset timer_count on reception of an ACK to avoid this situation. Signed-off-by: Jerome Forissier <jerome.forissier(a)linaro.org> --- net/tftp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/tftp.c b/net/tftp.c index 704b20b4ff8..8d54a83d9c2 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -478,6 +478,7 @@ static void tftp_handler(uchar *pkt, unsigned dest, struct in_addr sip, case TFTP_ACK: #ifdef CONFIG_CMD_TFTPPUT if (tftp_put_active) { + timeout_count = 0; if (tftp_put_final_block_sent) { tftp_complete(); } else { -- 2.43.0

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[PATCH v1 1/2] net: phy: Add driver for Motorcomm YT8531S Gigabit ethernet phy
by Frank Sae 01 Jan '25

01 Jan '25

Add driver for Motorcomm YT8531S Gigabit ethernet phy. Signed-off-by: Frank Sae <Frank.Sae(a)motor-comm.com> --- drivers/net/phy/motorcomm.c | 96 ++++++++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 4d67203ee7..a1d5eac7bf 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Motorcomm 8531 PHY driver. + * Motorcomm YT8511/YT8531/YT8531S/YT8821 PHY driver. * - * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Copyright (C) 2024 Motorcomm Electronic Technology Co., Ltd. */ #include <config.h> @@ -13,6 +13,7 @@ #define PHY_ID_YT8511 0x0000010a #define PHY_ID_YT8531 0x4f51e91b #define PHY_ID_YT8821 0x4f51ea19 +#define PHY_ID_YT8531S 0x4f51e91a #define PHY_ID_MASK GENMASK(31, 0) /* Extended Register's Address Offset Register */ @@ -1114,6 +1115,86 @@ static int yt8821_startup(struct phy_device *phydev) return 0; } +static int yt8531s_config(struct phy_device *phydev) +{ + struct ytphy_plat_priv *priv = phydev->priv; + u16 mask, val; + int ret; + + ret = genphy_config_aneg(phydev); + if (ret < 0) + return ret; + + ytphy_dt_parse(phydev); + switch (priv->clk_out_frequency) { + case YTPHY_DTS_OUTPUT_CLK_DIS: + mask = YT8531_SCR_SYNCE_ENABLE; + val = 0; + break; + case YTPHY_DTS_OUTPUT_CLK_25M: + mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | + YT8531_SCR_CLK_FRE_SEL_125M; + val = YT8531_SCR_SYNCE_ENABLE | + FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, + YT8531_SCR_CLK_SRC_REF_25M); + break; + case YTPHY_DTS_OUTPUT_CLK_125M: + mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | + YT8531_SCR_CLK_FRE_SEL_125M; + val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M | + FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, + YT8531_SCR_CLK_SRC_PLL_125M); + break; + default: + pr_warn("Freq err:%u\n", priv->clk_out_frequency); + return -EINVAL; + } + + ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask, + val); + if (ret < 0) + return ret; + + ret = ytphy_rgmii_clk_delay_config(phydev); + if (ret < 0) + return ret; + + if (priv->flag & AUTO_SLEEP_DISABLED) { + /* disable auto sleep */ + ret = ytphy_modify_ext(phydev, + YT8531_EXTREG_SLEEP_CONTROL1_REG, + YT8531_ESC1R_SLEEP_SW, 0); + if (ret < 0) + return ret; + } + + if (priv->flag & KEEP_PLL_ENABLED) { + /* enable RXC clock when no wire plug */ + ret = ytphy_modify_ext(phydev, + YT8531_CLOCK_GATING_REG, + YT8531_CGR_RX_CLK_EN, 0); + if (ret < 0) + return ret; + } + + return 0; +} + +static int yt8531s_startup(struct phy_device *phydev) +{ + int ret; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + + ret = yt8531_parse_status(phydev); + if (ret) + return ret; + + return 0; +} + U_BOOT_PHY_DRIVER(motorcomm8511) = { .name = "YT8511 Gigabit Ethernet", .uid = PHY_ID_YT8511, @@ -1145,3 +1226,14 @@ U_BOOT_PHY_DRIVER(motorcomm8821) = { .startup = &yt8821_startup, .shutdown = &genphy_shutdown, }; + +U_BOOT_PHY_DRIVER(motorcomm8531S) = { + .name = "YT8531S Gigabit Ethernet Transceiver", + .uid = PHY_ID_YT8531S, + .mask = PHY_ID_MASK, + .features = PHY_GBIT_FEATURES, + .probe = &yt8531_probe, + .config = &yt8531s_config, + .startup = &yt8531s_startup, + .shutdown = &genphy_shutdown, +}; -- 2.34.1

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[PATCH 1/1] net: correct the description of ip_to_string()
by Heinrich Schuchardt 01 Jan '25

01 Jan '25

The output of ip_to_string() is a string. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- include/net-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/net-common.h b/include/net-common.h index b7a519e36db..ed3d0a4a185 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -427,7 +427,7 @@ void string_to_enetaddr(const char *addr, uint8_t *enetaddr); struct in_addr string_to_ip(const char *s); /** - * ip_to_string() - Convert a string to ip address + * ip_to_string() - Convert an IPv4 address to a string * * Implemented in lib/net_utils.c (built unconditionally) * -- 2.45.2

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[PATCH] Bitbanging MDIO driver for DM framework.
by Tom Rini 01 Jan '25

01 Jan '25

From: Markus Gothe <markus.gothe(a)genexis.eu> Linux DTS compatible MDIO bitbanging driver. Both clause 22 and clause 45 MDIO supported and validated. Heavily based on the Linux drivers (more or less the same code base). Signed-off-by: Markus Gothe <markus.gothe(a)genexis.eu> --- drivers/net/Kconfig | 6 + drivers/net/Makefile | 1 + drivers/net/mdio_gpio.c | 313 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 320 insertions(+) create mode 100644 drivers/net/mdio_gpio.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 576cd2d50ad9..5e862158c566 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1007,6 +1007,12 @@ config FSL_ENETC This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. +config MDIO_GPIO_BITBANG + bool "GPIO bitbanging MDIO driver" + depends on DM_MDIO && DM_GPIO + help + Driver for bitbanging MDIO + config MDIO_MUX_I2CREG bool "MDIO MUX accessed as a register over I2C" depends on DM_MDIO_MUX && DM_I2C diff --git a/drivers/net/Makefile b/drivers/net/Makefile index f5ab1f5dedf6..e51a917933eb 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o +obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio_mux_meson_gxl.o diff --git a/drivers/net/mdio_gpio.c b/drivers/net/mdio_gpio.c new file mode 100644 index 000000000000..a2a41f95190c --- /dev/null +++ b/drivers/net/mdio_gpio.c @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GPIO based MDIO bitbang driver. + * + * Copyright 2024 Markus Gothe <markus.gothe(a)genexis.eu> + * + * This file is based on the Linux kernel drivers drivers/net/phy/mdio-gpio.c + * and drivers/net/phy/mdio-bitbang.c which have the following copyrights: + * + * Copyright (c) 2008 CSE Semaphore Belgium. + * by Laurent Pinchart <laurentp(a)cse-semaphore.com> + * + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas(a)teltonika.lt> + * + * Author: Scott Wood <scottwood(a)freescale.com> + * Copyright (c) 2007 Freescale Semiconductor + * + * Copyright (c) 2003 Intracom S.A. + * by Pantelis Antoniou <panto(a)intracom.gr> + * + * 2005 (c) MontaVista Software, Inc. + * Vitaly Bordug <vbordug(a)ru.mvista.com> + */ + +#include <dm.h> +#include <log.h> +#include <miiphy.h> +#include <asm/gpio.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/mdio.h> + +#define MDIO_READ 2 +#define MDIO_WRITE 1 + +#define MDIO_C45 BIT(15) +#define MDIO_C45_ADDR (MDIO_C45 | 0) +#define MDIO_C45_READ (MDIO_C45 | 3) +#define MDIO_C45_WRITE (MDIO_C45 | 1) + +/* Minimum MDC period is 400 ns, plus some margin for error. MDIO_DELAY + * is done twice per period. + */ +#define MDIO_DELAY 250 + +/* The PHY may take up to 300 ns to produce data, plus some margin + * for error. + */ +#define MDIO_READ_DELAY 350 + +#define MDIO_GPIO_MDC 0 +#define MDIO_GPIO_MDIO 1 +#define MDIO_GPIO_MDO 2 + +struct mdio_gpio_priv { + struct gpio_desc mdc, mdio, mdo; +}; + +static void mdio_dir(struct udevice *mdio_dev, int dir) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + if (dm_gpio_is_valid(&priv->mdo)) { + /* Separate output pin. Always set its value to high + * when changing direction. If direction is input, + * assume the pin serves as pull-up. If direction is + * output, the default value is high. + */ + dm_gpio_set_value(&priv->mdo, 1); + return; + } + + if (dir) + dm_gpio_set_dir_flags(&priv->mdio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + else + dm_gpio_set_dir_flags(&priv->mdio, GPIOD_IS_IN); +} + +static int mdio_get(struct udevice *mdio_dev) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + return dm_gpio_get_value(&priv->mdio); +} + +static void mdio_set(struct udevice *mdio_dev, int what) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + if (dm_gpio_is_valid(&priv->mdo)) + dm_gpio_set_value(&priv->mdo, what); + else + dm_gpio_set_value(&priv->mdio, what); +} + +static void mdc_set(struct udevice *mdio_dev, int what) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + dm_gpio_set_value(&priv->mdc, what); +} + +/* MDIO must already be configured as output. */ +static void mdio_gpio_send_bit(struct udevice *mdio_dev, int val) +{ + mdio_set(mdio_dev, val); + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 1); + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 0); +} + +/* MDIO must already be configured as input. */ +static int mdio_gpio_get_bit(struct udevice *mdio_dev) +{ + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 1); + ndelay(MDIO_READ_DELAY); + mdc_set(mdio_dev, 0); + + return mdio_get(mdio_dev); +} + +/* MDIO must already be configured as output. */ +static void mdio_gpio_send_num(struct udevice *mdio_dev, u16 val, int bits) +{ + int i; + + for (i = bits - 1; i >= 0; i--) + mdio_gpio_send_bit(mdio_dev, (val >> i) & 1); +} + +/* MDIO must already be configured as input. */ +static u16 mdio_gpio_get_num(struct udevice *mdio_dev, int bits) +{ + int i; + u16 ret = 0; + + for (i = bits - 1; i >= 0; i--) { + ret <<= 1; + ret |= mdio_gpio_get_bit(mdio_dev); + } + + return ret; +} + +/* Utility to send the preamble, address, and + * register (common to read and write). + */ +static void mdio_gpio_cmd(struct udevice *mdio_dev, int op, u8 phy, u8 reg) +{ + int i; + + mdio_dir(mdio_dev, 1); + + /* + * Send a 32 bit preamble ('1's) with an extra '1' bit for good + * measure. The IEEE spec says this is a PHY optional + * requirement. The AMD 79C874 requires one after power up and + * one after a MII communications error. This means that we are + * doing more preambles than we need, but it is safer and will be + * much more robust. + */ + for (i = 0; i < 32; i++) + mdio_gpio_send_bit(mdio_dev, 1); + + /* + * Send the start bit (01) and the read opcode (10) or write (01). + * Clause 45 operation uses 00 for the start and 11, 10 for + * read/write. + */ + mdio_gpio_send_bit(mdio_dev, 0); + if (op & MDIO_C45) + mdio_gpio_send_bit(mdio_dev, 0); + else + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, (op >> 1) & 1); + mdio_gpio_send_bit(mdio_dev, (op >> 0) & 1); + + mdio_gpio_send_num(mdio_dev, phy, 5); + mdio_gpio_send_num(mdio_dev, reg, 5); +} + +/* + * In clause 45 mode all commands are prefixed by MDIO_ADDR to specify the + * lower 16 bits of the 21 bit address. This transfer is done identically to a + * MDIO_WRITE except for a different code. To enable clause 45 mode or + * MII_ADDR_C45 into the address. Theoretically clause 45 and normal devices + * can exist on the same bus. Normal devices should ignore the MDIO_ADDR + * phase. + */ +static int mdio_gpio_cmd_addr(struct udevice *mdio_dev, int phy, u32 dev_addr, u32 reg) +{ + mdio_gpio_cmd(mdio_dev, MDIO_C45_ADDR, phy, dev_addr); + + /* send the turnaround (10) */ + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, 0); + + mdio_gpio_send_num(mdio_dev, reg, 16); + + mdio_dir(mdio_dev, 0); + mdio_gpio_get_bit(mdio_dev); + + return dev_addr; +} + +static int mdio_gpio_read(struct udevice *mdio_dev, int addr, int devad, int reg) +{ + int ret, i; + + if (devad != MDIO_DEVAD_NONE) { + reg = mdio_gpio_cmd_addr(mdio_dev, addr, devad, reg); + mdio_gpio_cmd(mdio_dev, MDIO_C45_READ, addr, reg); + } else { + mdio_gpio_cmd(mdio_dev, MDIO_READ, addr, reg); + } + + mdio_dir(mdio_dev, 0); + + /* check the turnaround bit: the PHY should be driving it to zero. + */ + if (mdio_gpio_get_bit(mdio_dev) != 0) { + /* PHY didn't drive TA low -- flush any bits it + * may be trying to send. + */ + for (i = 0; i < 32; i++) + mdio_gpio_get_bit(mdio_dev); + + return 0xffff; + } + + ret = mdio_gpio_get_num(mdio_dev, 16); + mdio_gpio_get_bit(mdio_dev); + + return ret; +} + +static int mdio_gpio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val) +{ + if (devad != MDIO_DEVAD_NONE) { + reg = mdio_gpio_cmd_addr(mdio_dev, addr, devad, reg); + mdio_gpio_cmd(mdio_dev, MDIO_C45_WRITE, addr, reg); + } else { + mdio_gpio_cmd(mdio_dev, MDIO_WRITE, addr, reg); + } + + /* send the turnaround (10) */ + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, 0); + + mdio_gpio_send_num(mdio_dev, val, 16); + + mdio_dir(mdio_dev, 0); + mdio_gpio_get_bit(mdio_dev); + + return 0; +} + +static const struct mdio_ops mdio_gpio_ops = { + .read = mdio_gpio_read, + .write = mdio_gpio_write, + .reset = NULL, +}; + +/* + * Name the device, we use the device tree node name. + * This can be overwritten by MDIO class code if device-name property is + * present. + */ +static int mdio_gpio_bind(struct udevice *mdio_dev) +{ + if (ofnode_valid(dev_ofnode(mdio_dev))) + device_set_name(mdio_dev, ofnode_get_name(dev_ofnode(mdio_dev))); + + return 0; +} + +static int mdio_gpio_probe(struct udevice *mdio_dev) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + int ret = 0; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDC, &priv->mdc, GPIOD_IS_OUT); + if (ret) + return ret; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDIO, &priv->mdio, GPIOD_IS_IN); + if (ret) + return ret; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDO, &priv->mdo, GPIOD_IS_OUT); + if (ret && ret != -ENOENT) + return ret; + + return 0; +} + +static const struct udevice_id mdio_gpio_ids[] = { + { .compatible = "virtual,mdio-gpio" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(gpio_mdio) = { + .name = "gpio_mdio", + .id = UCLASS_MDIO, + .of_match = mdio_gpio_ids, + .bind = mdio_gpio_bind, + .probe = mdio_gpio_probe, + .ops = &mdio_gpio_ops, + .plat_auto = sizeof(struct mdio_perdev_priv), + .priv_auto = sizeof(struct mdio_gpio_priv), +}; -- 2.34.1

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[PATCH] Revert "net: phy: marvell 88e151x: Fix handling of bare RGMII interface type"
by Rufus Segar 01 Jan '25

01 Jan '25

From 2f97d889cecfa2ba06652469765f31c70a68e867 Mon Sep 17 00:00:00 2001 From: Rufus Segar <rufuss(a)carallon.com> Date: Tue, 3 Dec 2024 14:35:10 +0000 Subject: [PATCH] Revert "net: phy: marvell 88e151x: Fix handling of bare RGMII interface type" This reverts commit 431be621c6cbc72efd1d45fa36686a682cbb470a. This change is erroneous, the RX/TX delay should only be added when in RGMII-ID mode. RGMII mode should have no RX/TX delay. --- drivers/net/phy/marvell.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index b0a0b7fcb3..08608a99b9 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -461,9 +461,7 @@ static int m88e151x_config(struct phy_device *phydev) reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY; - if (phydev->interface == PHY_INTERFACE_MODE_RGMII || - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) reg |= MIIM_88E151x_RGMII_RXTX_DELAY; else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) reg |= MIIM_88E151x_RGMII_RX_DELAY; -- 2.47.0

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[PATCH v2] net: tftpboot: clear timeout_count on every successful block
by Mikhail Kshevetskiy 01 Jan '25

01 Jan '25

We have a some boards that rarely starts networking abnormally, so there are many timeouts during file transfer. In the same time there is a normal transfer between timeouts. In this case we can continue transfer (instead of connection aborting) by just clearing timeout counter on every successfull block. This patch does not affect the case when several timeouts happen one after another. The transfer will be aborted. Thus the transfer will be continued in the case of unstable link, but will be aborted in the case of inaccessible server. Feature downside: it may greatly slowdown (instead of abort) file transfer in the case of unstable link. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy(a)iopsys.eu> --- Changes v2: * update patch description --- net/tftp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/tftp.c b/net/tftp.c index 704b20b4ff8..8f948204a6f 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -498,6 +498,7 @@ static void tftp_handler(uchar *pkt, unsigned dest, struct in_addr sip, tftp_state = STATE_DATA; tftp_remote_port = src; } + timeout_count = 0; tftp_send(); /* Send next data block */ } } @@ -657,6 +658,7 @@ static void tftp_handler(uchar *pkt, unsigned dest, struct in_addr sip, net_set_state(NETLOOP_FAIL); break; } + timeout_count = 0; if (len < tftp_block_size) { tftp_send(); -- 2.45.2

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[PATCH v2] arm64: dts: renesas: Deduplicate extalr_clk bootph-all
by Marek Vasut 01 Jan '25

01 Jan '25

Most R-Car Gen3 and Gen4 systems require extalr_clk very early in the boot process. Currently the extalr_clk { bootph-all } DT property to indicate this clock should be available early is set in each SoC U-Boot DT extras file. Deduplicate this assignment to new common r8a779x-rcar64-u-boot.dtsi file. Note that R-Car Gen3 R8A77990 E3 and R8A77995 D3 do not require extalr_clk early, therefore these SoCs still include plain r8a779x-u-boot.dtsi in their U-Boot DT extras . Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Chris Paterson <chris.paterson2(a)renesas.com> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj(a)bp.renesas.com> Cc: Marek Vasut <marek.vasut+renesas(a)mailbox.org> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)lists.denx.de --- V2: Rebase on u-boot/next --- arch/arm/dts/r8a774a1-u-boot.dtsi | 6 +----- arch/arm/dts/r8a774b1-u-boot.dtsi | 6 +----- arch/arm/dts/r8a774c0-u-boot.dtsi | 2 +- arch/arm/dts/r8a774e1-u-boot.dtsi | 6 +----- arch/arm/dts/r8a77951-u-boot.dtsi | 6 +----- arch/arm/dts/r8a77960-u-boot.dtsi | 6 +----- arch/arm/dts/r8a77965-u-boot.dtsi | 6 +----- arch/arm/dts/r8a77970-u-boot.dtsi | 6 +----- arch/arm/dts/r8a77980-u-boot.dtsi | 6 +----- arch/arm/dts/r8a779a0-u-boot.dtsi | 6 +----- arch/arm/dts/r8a779f0-u-boot.dtsi | 6 +----- arch/arm/dts/r8a779g0-u-boot.dtsi | 6 +----- arch/arm/dts/r8a779x-rcar64-u-boot.dtsi | 12 ++++++++++++ 13 files changed, 24 insertions(+), 56 deletions(-) create mode 100644 arch/arm/dts/r8a779x-rcar64-u-boot.dtsi diff --git a/arch/arm/dts/r8a774a1-u-boot.dtsi b/arch/arm/dts/r8a774a1-u-boot.dtsi index 3530eeb2718..bd91a963cd6 100644 --- a/arch/arm/dts/r8a774a1-u-boot.dtsi +++ b/arch/arm/dts/r8a774a1-u-boot.dtsi @@ -5,8 +5,4 @@ * Copyright (C) 2021 Renesas Electronics Corporation */ -#include "r8a779x-u-boot.dtsi" - -&extalr_clk { - bootph-all; -}; +#include "r8a779x-rcar64-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi b/arch/arm/dts/r8a774b1-u-boot.dtsi index 07aeabc46b4..38a82f065c0 100644 --- a/arch/arm/dts/r8a774b1-u-boot.dtsi +++ b/arch/arm/dts/r8a774b1-u-boot.dtsi @@ -5,8 +5,4 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779x-u-boot.dtsi" - -&extalr_clk { - bootph-all; -}; +#include "r8a779x-rcar64-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774c0-u-boot.dtsi b/arch/arm/dts/r8a774c0-u-boot.dtsi index 4572c22f6c1..91d14536e48 100644 --- a/arch/arm/dts/r8a774c0-u-boot.dtsi +++ b/arch/arm/dts/r8a774c0-u-boot.dtsi @@ -6,7 +6,7 @@ * */ -#include "r8a779x-u-boot.dtsi" +#include "r8a779x-rcar64-u-boot.dtsi" / { soc { diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi b/arch/arm/dts/r8a774e1-u-boot.dtsi index 2202731ccb3..f314b2b0cf8 100644 --- a/arch/arm/dts/r8a774e1-u-boot.dtsi +++ b/arch/arm/dts/r8a774e1-u-boot.dtsi @@ -5,8 +5,4 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include "r8a779x-u-boot.dtsi" - -&extalr_clk { - bootph-all; -}; +#include "r8a779x-rcar64-u-boot.dtsi" diff --git a/arch/arm/dts/r8a77951-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index c16c5116592..768d633ded0 100644 --- a/arch/arm/dts/r8a77951-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -5,11 +5,7 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut(a)gmail.com> */ -#include "r8a779x-u-boot.dtsi" - -&extalr_clk { - bootph-all; -}; +#include "r8a779x-rcar64-u-boot.dtsi" / { soc { diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi index 2245be2aa76..db062f8e8c7 100644 --- a/arch/arm/dts/r8a77960-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-u-boot.dtsi @@ -5,11 +5,7 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut(a)gmail.com> */ -#include "r8a779x-u-boot.dtsi" - -&extalr_clk { - bootph-all; -}; +#include "r8a779x-rcar64-u-boot.dtsi" / { soc { diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index f39acc237d3..d67e94e318b 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -5,11 +5,7 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut(a)gmail.com> */ -#include "r8a779x-u-boot.dtsi" - -&extalr_clk { - bootph-all; -}; +#include "r8a779x-rcar64-u-boot.dtsi" / { soc { diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi index 7900c641ba1..8dfa56c2f13 100644 --- a/arch/arm/dts/r8a77970-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-u-boot.dtsi @@ -5,11 +5,7 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut(a)gmail.com> */ -#include "r8a779x-u-boot.dtsi" - -&extalr_clk { - bootph-all; -}; +#include "r8a779x-rcar64-u-boot.dtsi" / { soc { diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi b/arch/arm/dts/r8a77980-u-boot.dtsi index aa7e058c585..088839907c2 100644 --- a/arch/arm/dts/r8a77980-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-u-boot.dtsi @@ -5,11 +5,7 @@ * Copyright (C) 2019 Marek Vasut <marek.vasut(a)gmail.com> */ -#include "r8a779x-u-boot.dtsi" - -&extalr_clk { - bootph-all; -}; +#include "r8a779x-rcar64-u-boot.dtsi" / { soc { diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi b/arch/arm/dts/r8a779a0-u-boot.dtsi index 2b6d6ef05dc..f506a666518 100644 --- a/arch/arm/dts/r8a779a0-u-boot.dtsi +++ b/arch/arm/dts/r8a779a0-u-boot.dtsi @@ -5,7 +5,7 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include "r8a779x-u-boot.dtsi" +#include "r8a779x-rcar64-u-boot.dtsi" / { soc { @@ -19,7 +19,3 @@ }; }; }; - -&extalr_clk { - bootph-all; -}; diff --git a/arch/arm/dts/r8a779f0-u-boot.dtsi b/arch/arm/dts/r8a779f0-u-boot.dtsi index 0f98c09fc52..08d32fef2b9 100644 --- a/arch/arm/dts/r8a779f0-u-boot.dtsi +++ b/arch/arm/dts/r8a779f0-u-boot.dtsi @@ -5,7 +5,7 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779x-u-boot.dtsi" +#include "r8a779x-rcar64-u-boot.dtsi" / { soc { @@ -22,7 +22,3 @@ }; }; }; - -&extalr_clk { - bootph-all; -}; diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index 2e731b628b3..10051c9dbfe 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -5,7 +5,7 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779x-u-boot.dtsi" +#include "r8a779x-rcar64-u-boot.dtsi" / { binman: binman { @@ -139,10 +139,6 @@ bootph-all; }; -&extalr_clk { - bootph-all; -}; - &hscif0 { bootph-all; }; diff --git a/arch/arm/dts/r8a779x-rcar64-u-boot.dtsi b/arch/arm/dts/r8a779x-rcar64-u-boot.dtsi new file mode 100644 index 00000000000..b59cc7deca7 --- /dev/null +++ b/arch/arm/dts/r8a779x-rcar64-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot on R-Car 64bit SoC + * + * Copyright (C) 2024 Marek Vasut <marek.vasut+renesas(a)mailbox.org> + */ + +#include "r8a779x-u-boot.dtsi" + +&extalr_clk { + bootph-all; +}; -- 2.45.2

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[PATCH v2 1/3] arm64: Convert core type check macros into inline functions
by Marek Vasut 01 Jan '25

01 Jan '25

Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent. Reviewed-by: Paul Barker <paul.barker.ct(a)bp.renesas.com> Reviewed-by: Peter Robinson <pbrobinson(a)gmail.com> Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Biju Das <biju.das.jz(a)bp.renesas.com> Cc: Chris Paterson <chris.paterson2(a)renesas.com> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj(a)bp.renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Cc: Paul Barker <paul.barker.ct(a)bp.renesas.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)lists.denx.de --- V2: - Rebase on u-boot/next - Add RB from Paul and Peter --- arch/arm/include/asm/armv8/cpu.h | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index 40d54dc85ab..aa1470bb72d 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -3,11 +3,11 @@ * Copyright 2018 NXP */ -#define MIDR_PARTNUM_CORTEX_A35 0xD04 -#define MIDR_PARTNUM_CORTEX_A53 0xD03 -#define MIDR_PARTNUM_CORTEX_A72 0xD08 -#define MIDR_PARTNUM_SHIFT 0x4 -#define MIDR_PARTNUM_MASK (0xFFF << 0x4) +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) static inline unsigned int read_midr(void) { @@ -18,9 +18,15 @@ static inline unsigned int read_midr(void) return val; } -#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) -#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) -#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) +#define is_cortex_a(__n) \ + static inline int is_cortex_a##__n(void) \ + { \ + unsigned int midr = read_midr(); \ + midr &= MIDR_PARTNUM_MASK; \ + midr >>= MIDR_PARTNUM_SHIFT; \ + return midr == MIDR_PARTNUM_CORTEX_A##__n; \ + } + +is_cortex_a(35) +is_cortex_a(53) +is_cortex_a(72) -- 2.45.2

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[PATCH v2 0/3] Add 'trace wipe'
by Jerome Forissier 01 Jan '25

01 Jan '25

This short series adds the 'trace wipe' command which clears the trace buffer, allowing to re-start a capture from scratch. Jerome Forissier (3): trace: add support for 'trace wipe' test: test_trace.py: test 'trace wipe' trace: document 'trace wipe' cmd/trace.c | 5 ++++ doc/develop/trace.rst | 11 +++++++++ include/trace.h | 2 ++ lib/trace.c | 47 ++++++++++++++++++++++++++----------- test/py/tests/test_trace.py | 30 +++++++++++++++++++++++ 5 files changed, 81 insertions(+), 14 deletions(-) v2: - Change 'trace clear' to 'trace wipe' - Add doc patch - Minor edits to the patch descriptions v1: - Added patch: 'test: test_trace.py: test "trace clear" command' v0: - Sent as a single patch: https://lists.denx.de/pipermail/u-boot/2024-December/574148.html -- 2.43.0

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