January 2025 - U-Boot

[PATCH v2] rockchip: rk3308-rock-s0: Fix SD-card boot on v1.1 hw revision
by Jonas Karlman 12 Jan '25

12 Jan '25

BootROM leave GPIO4_D6 configured as SDMMC_PWREN function and DW MMC driver set PWREN high in dwmci_init(). However, HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. For HW revision v1.2 the state of GPIO4_D6 has no impact. Upstream linux-rockchip maintainer tree has merged a patch "arm64: dts: rockchip: Fix sdmmc access on rk3308-rock-s0 v1.1 boards" for v6.14 to fix this issue. Add the upstream vmmc-supply regulator in board u-boot.dtsi and enable required Kconfig options to set GPIO4_D6 low to fix reading sdmmc on v1.1 hw revision. The regulator-3v3-vcc-sd and sdmmc-2030 nodes along with the vmmc-supply prop can be dropped once dts/upstream sync v6.14 DTs. Fixes: 25438c40a007 ("board: rockchip: Add Radxa ROCK S0") Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz(a)cherry.de> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> --- v2: - Rebased to fix clean apply on master - Collect r-b tags This matches pending Linux commit 26c100232b09 ("arm64: dts: rockchip: Fix sdmmc access on rk3308-rock-s0 v1.1 boards") targeting v6.14: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/co… --- arch/arm/dts/rk3308-rock-s0-u-boot.dtsi | 43 +++++++++++++++++++++++++ configs/rock-s0-rk3308_defconfig | 2 ++ 2 files changed, 45 insertions(+) diff --git a/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi b/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi index 84ca2ee0d5fb..7de8c9b59ca7 100644 --- a/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi @@ -2,11 +2,50 @@ #include "rk3308-u-boot.dtsi" +/ { + /* + * HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. + * This is modeled as an always-on active low fixed regulator. + */ + vcc_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_2030>; + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; +}; + &emmc_pwren { bootph-pre-ram; bootph-some-ram; }; +&gpio4 { + bootph-pre-ram; +}; + +&pinctrl { + sdmmc { + sdmmc_2030: sdmmc-2030 { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + vmmc-supply = <&vcc_sd>; +}; + +&sdmmc_2030 { + bootph-pre-ram; +}; + &uart0 { bootph-all; clock-frequency = <24000000>; @@ -16,6 +55,10 @@ bootph-all; }; +&vcc_sd { + bootph-pre-ram; +}; + &vdd_core { regulator-init-microvolt = <1015000>; }; diff --git a/configs/rock-s0-rk3308_defconfig b/configs/rock-s0-rk3308_defconfig index 0a46e7bb1871..063e0b921d73 100644 --- a/configs/rock-s0-rk3308_defconfig +++ b/configs/rock-s0-rk3308_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-s0" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y @@ -53,6 +54,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_BAUDRATE=1500000 -- 2.47.1

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[PATCH v3] rockchip: rk3288: Use rk3288-cru.h from dts/upstream
by Jonas Karlman 12 Jan '25

12 Jan '25

clock/rk3288-cru.h in include/dt-bindings is almost identical to the version in dts/upstream, remove the copy from include/dt-bindings to only use the version from dts/upstream. One clk, SCLK_MAC_PLL, is not part of the upstream bindings, this clk is not used by upstream, in-tree or vendor DTs and can safely be dropped. No functional change to board DTs is intended with this removal. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> --- v3: No change, drop merged patches v2: Collect r-b tag --- include/dt-bindings/clock/rk3288-cru.h | 381 ------------------------- 1 file changed, 381 deletions(-) delete mode 100644 include/dt-bindings/clock/rk3288-cru.h diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h deleted file mode 100644 index 453f66718c6b..000000000000 --- a/include/dt-bindings/clock/rk3288-cru.h +++ /dev/null @@ -1,381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner <heiko(a)sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_SDIO1 70 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_PS2C 74 -#define SCLK_NANDC0 75 -#define SCLK_NANDC1 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S0 82 -#define SCLK_SPDIF 83 -#define SCLK_SPDIF8CH 84 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_TIMER6 91 -#define SCLK_HSADC 92 -#define SCLK_OTGPHY0 93 -#define SCLK_OTGPHY1 94 -#define SCLK_OTGPHY2 95 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_LCDC_PWM0 100 -#define SCLK_LCDC_PWM1 101 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_ISP_JPE 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S0_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_SDIO1_DRV 116 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_SDIO1_SAMPLE 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M_SRC 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_CRYPTO 125 -#define SCLK_MIPIDSI_24M 126 -#define SCLK_VIP_OUT 127 - -#define SCLK_MAC_PLL 150 -#define SCLK_MAC 151 -#define SCLK_MACREF_OUT 152 - -#define DCLK_VOP0 190 -#define DCLK_VOP1 191 - -/* aclk gates */ -#define ACLK_GPU 192 -#define ACLK_DMAC1 193 -#define ACLK_DMAC2 194 -#define ACLK_MMU 195 -#define ACLK_GMAC 196 -#define ACLK_VOP0 197 -#define ACLK_VOP1 198 -#define ACLK_CRYPTO 199 -#define ACLK_RGA 200 -#define ACLK_RGA_NIU 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NIU 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NIU 206 -#define ACLK_HEVC 207 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_GPIO4 324 -#define PCLK_GPIO5 325 -#define PCLK_GPIO6 326 -#define PCLK_GPIO7 327 -#define PCLK_GPIO8 328 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM 350 -#define PCLK_RKPWM 351 -#define PCLK_PS2C 352 -#define PCLK_TIMER 353 -#define PCLK_TZPC 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_DSI1 357 -#define PCLK_MIPI_CSI 358 -#define PCLK_LVDS_PHY 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO2_H2P 361 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL0 364 -#define PCLK_PUBL0 365 -#define PCLK_DDRUPCTL1 366 -#define PCLK_PUBL1 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 -#define PCLK_EFUSE1024 370 -#define PCLK_ISP_IN 371 - -/* hclk gates */ -#define HCLK_GPS 448 -#define HCLK_OTG0 449 -#define HCLK_USBHOST0 450 -#define HCLK_USBHOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_NANDC1 454 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_SDIO1 458 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S0 462 -#define HCLK_SPDIF 463 -#define HCLK_SPDIF8CH 464 -#define HCLK_VOP0 465 -#define HCLK_VOP1 466 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NIU 472 -#define HCLK_VIP 473 -#define HCLK_VIO2_H2P 474 -#define HCLK_HEVC 475 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE2 2 -#define SRST_CORE3 3 -#define SRST_CORE0_PO 4 -#define SRST_CORE1_PO 5 -#define SRST_CORE2_PO 6 -#define SRST_CORE3_PO 7 -#define SRST_PDCORE_STRSYS 8 -#define SRST_PDBUS_STRSYS 9 -#define SRST_L2C 10 -#define SRST_TOPDBG 11 -#define SRST_CORE0_DBG 12 -#define SRST_CORE1_DBG 13 -#define SRST_CORE2_DBG 14 -#define SRST_CORE3_DBG 15 - -#define SRST_PDBUG_AHB_ARBITOR 16 -#define SRST_EFUSE256 17 -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_TIMER 22 -#define SRST_I2S0 23 -#define SRST_SPDIF 24 -#define SRST_TIMER0 25 -#define SRST_TIMER1 26 -#define SRST_TIMER2 27 -#define SRST_TIMER3 28 -#define SRST_TIMER4 29 -#define SRST_TIMER5 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_GPIO5 37 -#define SRST_GPIO6 38 -#define SRST_GPIO7 39 -#define SRST_GPIO8 40 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_CCP 71 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_NANDC1 78 - -#define SRST_TZPC 80 -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIO1_NIU_AXI 103 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP 111 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO_H2P 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDSI1 116 -#define SRST_MIPICSI 117 -#define SRST_LVDS_PHY 118 -#define SRST_LVDS_CON 119 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_SDIO1 130 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBHOST1_AHB 138 -#define SRST_USBHOST1_PHY 139 -#define SRST_USBHOST1_CON 140 -#define SRST_USB_ADP 141 -#define SRST_ACC_EFUSE 142 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_PD_CORE_MP_AXI 147 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_LCDC_PWM1 150 -#define SRST_VIO0_H2P_BRG 151 -#define SRST_VIO1_H2P_BRG 152 -#define SRST_RGA_H2P_BRG 153 -#define SRST_HEVC 154 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_DDRPHY0_CTRL 164 -#define SRST_DDRPHY1 165 -#define SRST_DDRPHY1_APB 166 -#define SRST_DDRCTRL1 167 -#define SRST_DDRCTRL1_APB 168 -#define SRST_DDRPHY1_CTRL 169 -#define SRST_DDRMSCH0 170 -#define SRST_DDRMSCH1 171 -#define SRST_CRYPTO 174 -#define SRST_C2C_HOST 175 - -#define SRST_LCDC1_AXI 176 -#define SRST_LCDC1_AHB 177 -#define SRST_LCDC1_DCLK 178 -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_PS2C 187 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 -#define SRST_TSP_CLKIN1 190 -#define SRST_TSP_27M 191 - -#endif -- 2.47.1

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[PATCH v2 0/1] SoCFPGA: Add watchdog mode setting for Agilex 5
by muhammad.hazim.izzat.zamri＠intel.com 12 Jan '25

12 Jan '25

From: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri(a)intel.com> This patch is to introduce another watchdog mode setting in Agilex 5 as additional watchdog4 has been introduced. This is to enable the debug mode when the CPU is paused by the user. This patch has been tested on Agilex 5 devkit with QSPI boot (UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger). Muhammad Hazim Izzat Zamri (1): arm: socfpga:agilex5: Fix system manager watchdog mode setting arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.26.2

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[RFC PATCH 0/2] Integrate OP-TEE into the RISC-V boot flow
by Yu-Chien Peter Lin 11 Jan '25

11 Jan '25

This patch series adds support for integrating OP-TEE OS into the RISC-V boot flow. It allows specifying the load address of the OP-TEE binary and updates binman to include the OP-TEE OS image. Yu-Chien Peter Lin (2): riscv: Add CONFIG_SPL_OPTEE_LOAD_ADDR riscv: dts: binman.dtsi: Include OP-TEE OS image arch/riscv/Kconfig | 6 ++++++ arch/riscv/dts/binman.dtsi | 26 ++++++++++++++++++++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) -- 2.39.3

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Pull request: u-boot-rockchip-20250110
by Kever Yang 11 Jan '25

11 Jan '25

Hi Tom, Please pull the updates for rockchip platform: - Add boards: rk3566: FriendlyARM NanoPi R3S rk3588s: Radxa ROCK 5C, rk3588: Khadas Edge2 - Migrate to OF_UPSTREAM: rk3066a/rk3188; rk3288: tinker, miqi, firefly; - Migrate to TPL: rk3399 kevin and bob; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/24129 Thanks, - Kever The following changes since commit 38a371110308ebeb277e20531a7b698b7981bbfa: Merge tag 'tpm-master-07012025' of https://source.denx.de/u-boot/custodians/u-boot-tpm (2025-01-09 11:11:27 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20250110 for you to fetch changes up to 34df868161e470e5de04db059daa90f12e824693: rockchip: rk3308: Implement checkboard() to print SoC variant (2025-01-10 15:17:26 +0800) ---------------------------------------------------------------- Cristian Ciocaltea (1): arm64: dts: rockchip: Add HDMI0 node to rk3588 Daniel Semkowicz (1): board: theobroma-systems: Update TF-A setup steps for RK3588 boards FUKAUMI Naoki (3): arm64: dts: rockchip: add Radxa ROCK 5C rockchip: Add support for Radxa ROCK 5C rockchip: rk3399: expand space for decompressed kernel Heiko Stuebner (1): clk: rockchip: rk3588: fix mask define for aclk_vop_root Jacobe Zang (1): board: rockchip: add Khadas Edge2 RK3588 board Johan Jonker (2): rockchip: use OF_UPSTREAM for rk3066a/rk3188 rockchip: rk3066a/rk3188: use includes from dts/upstream Jonas Karlman (56): rockchip: rk3288: Use rk3288-power.h from dts/upstream rockchip: clk: rk3288: Drop use of SCLK_MAC_PLL rockchip: rk3288: Use rk3288.dtsi from dts/upstream rockchip: rk3288: Fix bootph prop for vop nodes board: rockchip: rk3288-tinker: Add myself as reviewer to MAINTAINERS rockchip: rk3288-tinker: Sort u-boot.dtsi nodes alphabetically rockchip: rk3288-tinker: Only include required DT nodes in TPL rockchip: rk3288-tinker: Drop unused vcc_sd regulator from SPL rockchip: rk3288-tinker: Include mmc nodes in pre-reloc for env load rockchip: rk3288-tinker: Set cpuid and serial env var rockchip: rk3288-tinker: Sync defconfig options from rk3288-tinker-s rockchip: rk3288-tinker: Use common bss and stack addresses rockchip: rk3288-tinker: Drop use of silent console and late boardinfo rockchip: rk3288-tinker: Drop USE_PREBOOT Kconfig option rockchip: rk3288-tinker: Migrate to OF_UPSTREAM rockchip: rk3288-tinker: Fix slow Ethernet initializion rockchip: rk3288-tinker: Change to use FIT rockchip: rk3288-miqi: Sort u-boot.dtsi nodes alphabetically rockchip: rk3288-miqi: Remove unused work led node from xPL rockchip: rk3288-miqi: Set ethaddr env based on cpuid rockchip: rk3288-miqi: Use TPL with common bss and stack addresses rockchip: rk3288-miqi: Include required DT nodes in xPL rockchip: rk3288-miqi: Include sdmmc regulator in SPL rockchip: rk3288-miqi: Drop use of silent console and late boardinfo rockchip: rk3288-miqi: Drop USE_PREBOOT Kconfig option rockchip: rk3288-miqi: Migrate to OF_UPSTREAM rockchip: rk3288-miqi: Fix slow Ethernet initializion rockchip: rk3288-miqi: Change to use FIT rockchip: rk3288-firefly: Drop unused SPL_LED related code rockchip: rk3288-firefly: Sort u-boot.dtsi nodes alphabetically rockchip: rk3288-firefly: Set ethaddr env based on cpuid rockchip: rk3288-firefly: Use common bss and stack addresses rockchip: rk3288-firefly: Include required DT nodes in xPL rockchip: rk3288-firefly: Include sdmmc regulator in SPL rockchip: rk3288-firefly: Drop use of silent console and late boardinfo rockchip: rk3288-firefly: Drop USE_PREBOOT Kconfig option rockchip: rk3288-firefly: Migrate to OF_UPSTREAM rockchip: rk3288-firefly: Fix slow Ethernet initializion rockchip: rk3288-firefly: Change to use FIT rockchip: rk3399: Fix TPL build of bob and kevin rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset prop rockchip: rk3399-gru: Move SPI flash payload offset for bob and kevin rockchip: rk3399-gru: Fix include of TPL in u-boot.rom image rockchip: rk3399-gru: Use TPL with common bss and stack addresses rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom image rockchip: rk3399: Drop common Kconfig options already implied rockchip: rk3399-gru: Remove unused nodes from xPL control FDT rockchip: rk3399-gru: Enable dcache and signature validation in SPL rockchip: rk3399-gru: Use SDMA mode to read from eMMC rockchip: rk3399-gru: Include pinctrl and regulators in SPL rockchip: rk3399: Drop unneeded bob and kevin board specific code rockchip: rk3588-nanopc-t6-lts: Add missing board -u-boot.dtsi rockchip: rk3399-rock-pi-4: Fix Synchronous Abort rockchip: rk356x: Implement checkboard() to print SoC variant rockchip: rk3588: Implement checkboard() to print SoC variant rockchip: rk3308: Implement checkboard() to print SoC variant Paul Kocialkowski (3): rockchip: rk3399-roc-pc: Hook sysreset gpio to enable full reset rockchip: rk3399-rockpro64: Hook sysreset gpio to enable full reset rockchip: rk3399-rockpro64: Disable bootstage instrumentation config Sam Edwards (1): arm64: dts: rockchip: Split up RK3588's PCIe pinctrls Tianling Shen (7): arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S arm64: dts: rockchip: replace deprecated snps, reset props for NanoPi R3S arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi R3S arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S board: rockchip: add FriendlyElec NanoPi R3S arch/arm/dts/Makefile | 10 - arch/arm/dts/rk3066a-mk808.dts | 241 --- arch/arm/dts/rk3066a-u-boot.dtsi | 20 - arch/arm/dts/rk3066a.dtsi | 880 --------- arch/arm/dts/rk3188-radxarock.dts | 389 ---- arch/arm/dts/rk3188-u-boot.dtsi | 17 - arch/arm/dts/rk3188.dtsi | 815 -------- arch/arm/dts/rk3288-firefly-u-boot.dtsi | 91 +- arch/arm/dts/rk3288-firefly.dts | 43 - arch/arm/dts/rk3288-firefly.dtsi | 491 ----- arch/arm/dts/rk3288-miqi-u-boot.dtsi | 83 +- arch/arm/dts/rk3288-miqi.dts | 16 - arch/arm/dts/rk3288-miqi.dtsi | 417 ---- arch/arm/dts/rk3288-tinker-s-u-boot.dtsi | 13 +- arch/arm/dts/rk3288-tinker-s.dts | 29 - arch/arm/dts/rk3288-tinker-u-boot.dtsi | 53 +- arch/arm/dts/rk3288-tinker.dts | 33 - arch/arm/dts/rk3288-tinker.dtsi | 533 ----- arch/arm/dts/rk3288-u-boot.dtsi | 13 +- arch/arm/dts/rk3288.dtsi | 2035 -------------------- arch/arm/dts/rk3399-gru-u-boot.dtsi | 29 +- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 8 + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 8 + arch/arm/dts/rk3399-u-boot.dtsi | 14 +- arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi | 8 + arch/arm/dts/rk356x-u-boot.dtsi | 4 + arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi | 3 + arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi | 11 + arch/arm/dts/rk3588s-u-boot.dtsi | 4 + arch/arm/dts/rk3xxx.dtsi | 488 ----- arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 +- arch/arm/mach-rockchip/Kconfig | 2 + arch/arm/mach-rockchip/rk3288/Kconfig | 10 +- arch/arm/mach-rockchip/rk3308/rk3308.c | 16 + arch/arm/mach-rockchip/rk3399/Kconfig | 12 - arch/arm/mach-rockchip/rk3399/rk3399.c | 23 +- arch/arm/mach-rockchip/rk3568/rk3568.c | 61 + arch/arm/mach-rockchip/rk3588/Kconfig | 44 + arch/arm/mach-rockchip/rk3588/rk3588.c | 52 + board/firefly/firefly-rk3288/MAINTAINERS | 1 + board/firefly/firefly-rk3288/Makefile | 7 - board/firefly/firefly-rk3288/firefly-rk3288.c | 46 - board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS | 3 +- board/khadas/khadas-edge2-rk3588s/Kconfig | 12 + board/khadas/khadas-edge2-rk3588s/MAINTAINERS | 6 + board/mqmaker/miqi_rk3288/MAINTAINERS | 1 - board/radxa/rock-5c-rk3588s/Kconfig | 12 + board/radxa/rock-5c-rk3588s/MAINTAINERS | 7 + board/radxa/rockpi4-rk3399/rockpi4-rk3399.c | 2 + board/rockchip/evb_rk3568/MAINTAINERS | 7 + board/rockchip/tinker_rk3288/MAINTAINERS | 7 +- board/rockchip/tinker_rk3288/tinker-rk3288.c | 2 +- configs/chromebook_bob_defconfig | 24 +- configs/chromebook_kevin_defconfig | 24 +- configs/firefly-rk3288_defconfig | 39 +- configs/khadas-edge2-rk3588s_defconfig | 215 +++ configs/miqi-rk3288_defconfig | 43 +- configs/mk808_defconfig | 4 +- configs/nanopi-r3s-rk3566_defconfig | 75 + configs/rock-5c-rk3588s_defconfig | 84 + configs/rock_defconfig | 4 +- configs/rockpro64-rk3399_defconfig | 3 - configs/tinker-rk3288_defconfig | 41 +- configs/tinker-s-rk3288_defconfig | 38 +- doc/board/rockchip/rockchip.rst | 3 + doc/board/theobroma-systems/jaguar_rk3588.rst | 6 +- doc/board/theobroma-systems/tiger_rk3588.rst | 6 +- drivers/clk/rockchip/clk_rk3288.c | 8 +- .../src/arm64/rockchip/rk3566-nanopi-r3s.dts | 554 ++++++ .../src/arm64/rockchip/rk3588-base-pinctrl.dtsi | 271 ++- dts/upstream/src/arm64/rockchip/rk3588-base.dtsi | 41 + .../src/arm64/rockchip/rk3588s-rock-5a.dts | 6 +- .../src/arm64/rockchip/rk3588s-rock-5c.dts | 920 +++++++++ include/configs/khadas-edge2-rk3588s.h | 15 + include/configs/rk3399_common.h | 16 +- include/configs/rock-5c-rk3588s.h | 15 + include/dt-bindings/clock/rk3066a-cru.h | 31 - include/dt-bindings/clock/rk3188-cru-common.h | 261 --- include/dt-bindings/clock/rk3188-cru.h | 47 - include/dt-bindings/power/rk3066-power.h | 22 - include/dt-bindings/power/rk3188-power.h | 24 - include/dt-bindings/power/rk3288-power.h | 32 - 82 files changed, 2760 insertions(+), 7246 deletions(-) delete mode 100644 arch/arm/dts/rk3066a-mk808.dts delete mode 100644 arch/arm/dts/rk3066a.dtsi delete mode 100644 arch/arm/dts/rk3188-radxarock.dts delete mode 100644 arch/arm/dts/rk3188.dtsi delete mode 100644 arch/arm/dts/rk3288-firefly.dts delete mode 100644 arch/arm/dts/rk3288-firefly.dtsi delete mode 100644 arch/arm/dts/rk3288-miqi.dts delete mode 100644 arch/arm/dts/rk3288-miqi.dtsi delete mode 100644 arch/arm/dts/rk3288-tinker-s.dts delete mode 100644 arch/arm/dts/rk3288-tinker.dts delete mode 100644 arch/arm/dts/rk3288-tinker.dtsi delete mode 100644 arch/arm/dts/rk3288.dtsi create mode 100644 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi delete mode 100644 arch/arm/dts/rk3xxx.dtsi delete mode 100644 board/firefly/firefly-rk3288/Makefile delete mode 100644 board/firefly/firefly-rk3288/firefly-rk3288.c create mode 100644 board/khadas/khadas-edge2-rk3588s/Kconfig create mode 100644 board/khadas/khadas-edge2-rk3588s/MAINTAINERS create mode 100644 board/radxa/rock-5c-rk3588s/Kconfig create mode 100644 board/radxa/rock-5c-rk3588s/MAINTAINERS create mode 100644 configs/khadas-edge2-rk3588s_defconfig create mode 100644 configs/nanopi-r3s-rk3566_defconfig create mode 100644 configs/rock-5c-rk3588s_defconfig create mode 100644 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts create mode 100644 include/configs/khadas-edge2-rk3588s.h create mode 100644 include/configs/rock-5c-rk3588s.h delete mode 100644 include/dt-bindings/clock/rk3066a-cru.h delete mode 100644 include/dt-bindings/clock/rk3188-cru-common.h delete mode 100644 include/dt-bindings/clock/rk3188-cru.h delete mode 100644 include/dt-bindings/power/rk3066-power.h delete mode 100644 include/dt-bindings/power/rk3188-power.h delete mode 100644 include/dt-bindings/power/rk3288-power.h

2 1

Please pull u-boot-watchdog/master
by Stefan Roese 11 Jan '25

11 Jan '25

Hi Tom, please pull the following watchdog patches: ---------------------------------------------------------------- - rti: support SPL (or re-start) (Alexander) - rti: drop hack manipulating WDT clock rate (Alexander) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=380&view=results Thanks, Stefan The following changes since commit 6d41f0a39d6423c8e57e92ebbe9f8c0333a63f72: Prepare v2025.01 (2025-01-06 18:54:44 -0600) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-watchdog.git for you to fetch changes up to 5964f24f15473709fb9d897230c3f20e998c88ca: watchdog: rti: drop hack manipulating WDT clock rate (2025-01-07 10:29:58 +0100) ---------------------------------------------------------------- Alexander Sverdlin (2): watchdog: rti: support SPL (or re-start) watchdog: rti: drop hack manipulating WDT clock rate drivers/watchdog/rti_wdt.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-)

2 1

[PATCH v2 00/33] upl: Prerequite patches for updated spec
by Simon Glass 10 Jan '25

10 Jan '25

The current UPL spec[1] has been tidied up and improved over the last year, since U-Boot's original UPL support was written. This series includes some prerequisite patches needed for the real UPL patches. It is split from [2] [1] git@github.com:UniversalPayload/spec.git commit 3f1450d [2] https://patchwork.ozlabs.org/project/uboot/list/?series=438574&state=* Changes in v2: - Fix 'Emable' typo - Enable the command in cmd/Kconfig instead - Fix unbalanced {} - Add new patch to move x86 tables to use SZ macros - Use 4K instead of 4KB - Add new patch to enable bloblist on x86 - Split this into its own function - Split prerequisite patches into their own series Raymond Mao (1): bloblist: add api to get blob with size Simon Glass (32): bloblist: Drop BSD license bloblist: Make BLOBLIST_ALLOC the default abuf: Provide a way to get the buffer address abuf: Allow use in host tools abuf: Provide a constant buffer cpu: Provide a way to get the physical-address size serial: Support info() method in ns16550 xPL with UPL mkimage: Update map_to_sysmem() to match its prototype x86: Enable meminfo command x86: Show the timestamp counter with bdinfo ofnode: Use 4K for a default tree-size ofnode: Indicate when out of space in a few places ofnode: Update of_add_subnode() to indicate name is alloced boot: Rename fit_image_get_data() boot: Rename fit_image_get_data_and_size() boot: Update fit_image_get_emb_data to use abuf boot: Use fit_image_get_data() to get data boot: Update fit_image_get_data() to use abuf test: Fix inpected typo in upl test emulation: fdt: Relax condition for OF_HAS_PRIOR_STAGE emulation: Use bloblist to hold tables x86: Create more space for SPL with qemu-x86_64 pci: video: Set up the pixel-format field x86: Show an error if video fails x86: Support jumping to a UPL image x86: Enable UPL handoff for SPL x86: Move tables to use SZ macros x86: Align the SMBIOS table to a 4K boundary x86: emulation: Enable bloblist dm: core: Clarify behaviour of ofnode_name_eq() dm: core: Provide ofnode_name_eq_unit() to accept a unit address dm: core: Provide ofnode_find_subnode_unit() arch/arm/cpu/armv8/sec_firmware.c | 13 ++-- arch/arm/mach-k3/r5/sysfw-loader.c | 11 ++- arch/x86/include/asm/cpu.h | 9 --- arch/x86/lib/bdinfo.c | 3 + arch/x86/lib/bootm.c | 18 ++++- arch/x86/lib/spl.c | 12 +++- arch/x86/lib/tables.c | 11 ++- boot/image-board.c | 11 ++- boot/image-fit.c | 98 +++++++++----------------- cmd/Kconfig | 4 +- cmd/ximg.c | 14 ++-- common/Kconfig | 15 ++-- common/bloblist.c | 19 ++++- common/spl/spl_fit.c | 8 ++- common/splash_source.c | 18 +---- common/update.c | 7 +- configs/chromebook_bob_defconfig | 1 + configs/chromebook_coral_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/chromebook_samus_tpl_defconfig | 1 + configs/qemu-x86_64_defconfig | 6 +- configs/qemu-x86_defconfig | 2 + configs/qemu_arm64_defconfig | 2 + configs/qemu_arm_defconfig | 2 + drivers/core/ofnode.c | 67 ++++++++++++++---- drivers/misc/qfw_acpi.c | 37 +++++++++- drivers/misc/qfw_smbios.c | 45 ++++++------ drivers/pci/pci_rom.c | 3 + drivers/serial/ns16550.c | 2 +- drivers/video/bochs.c | 1 + drivers/video/video-uclass.c | 1 + dts/Kconfig | 2 +- include/abuf.h | 25 +++++++ include/bloblist.h | 20 +++++- include/cpu.h | 14 ++++ include/dm/ofnode.h | 35 +++++++-- include/image.h | 39 ++++++++-- include/video.h | 2 + lib/Kconfig | 1 + lib/Makefile | 5 ++ lib/abuf.c | 21 +++++- test/common/Makefile | 4 ++ test/dm/core.c | 20 ++++++ test/dm/ofnode.c | 19 +++++ test/lib/abuf.c | 26 ++++++- test/py/tests/test_upl.py | 2 +- tools/Makefile | 3 +- tools/fit_image.c | 8 +-- tools/image-host.c | 23 +++--- tools/mkimage.h | 2 +- 50 files changed, 507 insertions(+), 207 deletions(-) -- 2.34.1

3 59

[PATCH 00/18] x86: Improve operation under QEMU
by Simon Glass 10 Jan '25

10 Jan '25

U-Boot can start and boot an OS in both qemu-x86 and qemu-x86_64 but it is not perfect. With both builds, executing the VESA ROM causes an intermittent hang, at least on some AMD CPUs. With qemu-x86_64 kvm cannot be used since the move to long mode (64-bit) is done in a way that works on real hardware but not with QEMU. This means that performance is 4-5x slower than it could be, at least on my CPU. We can work around the first problem by using Bochs, which is anyway a better choice than VESA for QEMU. But this results in the Ubuntu installer failing to boot via EFI. It isn't clear whether this due to a problem with the UEFI GOP, or something else. It hangs before the Ubuntu logo appears. So this series is unfinished. I thought it best to post what is here in the hope that others can help work out the kinks. Simon Glass (18): scripts: Add a script for building and booting QEMU x86: Expand x86_64 early memory RFC: x86: qemu: Switch to bochs display x86: qemu: Enable dhrystone x86: qemu: Avoid accessing BSS too early x86: Drop mpspec from the SPL build x86: Add some log categories x86: Drop use of CONFIG_REALMODE_DEBUG x86: Avoid clearing the VESA display x86: Add 64-bit entries to the GDT x86: Use defines for the cache flags x86: spl: Drop duplicate CPU init x86: Drop the message about features missing in 64-bit x86: Include stdbool.h in interrupt header x86: Tidy up the GDT size in start/16.S x86: Disable paging before changing to long mode x86: Use the same GDT when jumping to long mode x86: Use a simple jump into long mode MAINTAINERS | 8 ++ arch/x86/cpu/i386/call64.S | 35 +++---- arch/x86/cpu/i386/cpu.c | 18 +++- arch/x86/cpu/qemu/qemu.c | 20 ++-- arch/x86/cpu/start.S | 4 +- arch/x86/cpu/start16.S | 3 +- arch/x86/include/asm/interrupt.h | 1 + arch/x86/include/asm/processor.h | 5 +- arch/x86/lib/Makefile | 2 + arch/x86/lib/bios.c | 27 +++-- arch/x86/lib/bios_interrupts.c | 8 +- arch/x86/lib/i8259.c | 2 + arch/x86/lib/spl.c | 4 +- configs/qemu-x86_64_defconfig | 10 +- configs/qemu-x86_defconfig | 6 +- doc/board/emulation/index.rst | 1 + doc/board/emulation/script.rst | 61 +++++++++++ scripts/build-qemu.sh | 175 +++++++++++++++++++++++++++++++ 18 files changed, 331 insertions(+), 59 deletions(-) create mode 100644 doc/board/emulation/script.rst create mode 100755 scripts/build-qemu.sh -- 2.34.1

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[PATCH] riscv: spacemit: k1: probe dram size during boot phase.
by Huan Zhou 10 Jan '25

10 Jan '25

--- This patch introduce improvement for get dram size on bananapi BPI-F3, retrieving the dram size dynamically. Have tested on bananapi BPIF3 4G and jupiter 8G. Signed-off-by: Huan Zhou <me(a)per1cycle.org> --- arch/riscv/cpu/k1/dram.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c index c477c15cbfb19f0e3a0ee72985b602f5bda352d7..095217f2a4c053f7477d62c0776bcb51e623db47 100644 --- a/arch/riscv/cpu/k1/dram.c +++ b/arch/riscv/cpu/k1/dram.c @@ -4,17 +4,53 @@ */ #include <asm/global_data.h> +#include <asm/io.h> #include <config.h> +#include <bitfield.h> #include <fdt_support.h> #include <linux/sizes.h> +#define DDR_BASE 0xC0000000 DECLARE_GLOBAL_DATA_PTR; +static inline u32 map_format_size(u32 val) +{ + u32 tmp; + + if (val & 0x1 == 0) + return 0; + + tmp = bitfield_extract(val, 16, 5); + switch (tmp) { + case 0xd: + return 512; + case 0xe: + return 1024; + case 0xf: + return 2048; + case 0x10: + return 4096; + case 0x11: + return 8192; + default: + pr_info("Invalid DRAM density %x\n", val); + return 0; + } +} + +u32 ddr_get_density(void) +{ + u32 cs0_size = map_format_size(readl((void *)DDR_BASE + 0x200)); + u32 cs1_size = map_format_size(readl((void *)DDR_BASE + 0x208)); + u32 ddr_size = cs0_size + cs1_size; + + return ddr_size; +} + int dram_init(void) { gd->ram_base = CFG_SYS_SDRAM_BASE; - /* TODO get ram size from ddr controller */ - gd->ram_size = SZ_4G; + gd->ram_size = (u64)ddr_get_density() * SZ_1M; return 0; } --- base-commit: 19fc0b7f7d907119a13e9c207991899f0817f8fc change-id: 20250108-get-dram-size-65cf59a15201 Best regards, -- Huan Zhou <me(a)per1cycle.org>

7 12

[PATCH 00/12] rockchip: rk3399: Migrate to use TPL on bob and kevin
by Jonas Karlman 10 Jan '25

10 Jan '25

This is a continuation of an RFC [1] sent back in August. All Rockchip aarch64 boards, beside bob and kevin, use TPL to initialize DRAM and SPL to load FIT with U-Boot proper and TF-A. Bob and kevin currently does not use TPL and instead initialize DRAM in SPL and directly after tries to load a FIT with only U-Boot proper. This series migrate bob and kevin to also use TPL to uniform TPL/SPL use for all Rockchip aarch64 boards. Features and changes in this series: - Use of Rockchip aarch64 common bss and stack addresses - SHA256 checksum/signature check of FIT images in SPL - Use of dcache to speed up checksum check in SPL - SDMA use for eMMC access to speed up read/write in U-Boot proper - FIT location moved from 0x40000 to 0xE0000 in SPI flash Changes sinc RFC: - Include pinctrl props and enable regulators based on DT in SPL - Drop bob and kevin board specific code from common rk3399.c Please note that I do not have any bob or kevin so this has only been compile tested and the original RFC [1] was runtime tested by Simon. [1] https://patchwork.ozlabs.org/patch/1967517/ Jonas Karlman (12): rockchip: rk3399: Fix TPL build of bob and kevin rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset prop rockchip: rk3399-gru: Move SPI flash payload offset for bob and kevin rockchip: rk3399-gru: Fix include of TPL in u-boot.rom image rockchip: rk3399-gru: Use TPL with common bss and stack addresses rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom image rockchip: rk3399: Drop common Kconfig options already implied rockchip: rk3399-gru: Remove unused nodes from xPL control FDT rockchip: rk3399-gru: Enable dcache and signature validation in SPL rockchip: rk3399-gru: Use SDMA mode to read from eMMC rockchip: rk3399-gru: Include pinctrl and regulators in SPL rockchip: rk3399: Drop unneeded bob and kevin board specific code arch/arm/dts/rk3399-gru-u-boot.dtsi | 29 ++++++++++++++++++++++++-- arch/arm/dts/rk3399-u-boot.dtsi | 14 +++++++++++-- arch/arm/mach-rockchip/rk3399/Kconfig | 12 ----------- arch/arm/mach-rockchip/rk3399/rk3399.c | 23 +------------------- configs/chromebook_bob_defconfig | 23 ++++++-------------- configs/chromebook_kevin_defconfig | 23 ++++++-------------- 6 files changed, 52 insertions(+), 72 deletions(-) -- 2.47.1

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