January 2025 - U-Boot

[PATCH v2 0/3] Initial support for PXA1908 and samsung-coreprimevelte
by Duje Mihanović 24 Jan '25

24 Jan '25

Hello, This series adds initial support for Marvell's PXA1908 ARM64 SoC and Samsung's Galaxy Core Prime VE LTE, a smartphone based on said SoC. On this board, U-Boot is used as a secondary bootloader to work around certain quirks of the factory S-Boot. Signed-off-by: Duje Mihanović <duje.mihanovic(a)skole.hr> --- Changes in v2: - Drop arm,armv8 compatible from CPU nodes to match upstream - Add intel,xscale-uart compatible to NS16550 and use it in serial nodes to match upstream - Add include guards to include/configs/pxa1908.h - Disable CONFIG_DISPLAY_CPUINFO and CONFIG_CPU - Rebase on v2025.01-rc5 - Link to v1: https://lore.kernel.org/r/20241227-coreprimevelte-v1-0-ac8243eee4e6@skole.hr --- Duje Mihanović (3): serial: ns16550: Add Intel XScale support arm: mmp: add initial support for PXA1908 SoC board: samsung: add initial support for coreprimevelte board MAINTAINERS | 8 ++ arch/arm/Kconfig | 11 +++ arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/pxa1908-samsung-coreprimevelte.dts | 74 +++++++++++++++++ arch/arm/dts/pxa1908.dtsi | 106 ++++++++++++++++++++++++ arch/arm/mach-mmp/Kconfig | 12 +++ arch/arm/mach-mmp/Makefile | 1 + arch/arm/mach-mmp/board.c | 82 ++++++++++++++++++ arch/arm/mach-mmp/mmu.c | 30 +++++++ board/samsung/coreprimevelte/Kconfig | 12 +++ board/samsung/coreprimevelte/MAINTAINERS | 6 ++ configs/coreprimevelte_defconfig | 18 ++++ drivers/serial/ns16550.c | 1 + include/configs/pxa1908.h | 18 ++++ 15 files changed, 382 insertions(+) --- base-commit: 4be40460758057b9a85b0303dc072c108813cdf6 change-id: 20241226-coreprimevelte-1c26acfb58db Best regards, -- Duje Mihanović <duje.mihanovic(a)skole.hr>

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[PATCH v4 00/20] imx: add i.MX95 support
by Alice Guo 24 Jan '25

24 Jan '25

Changes in v4: - split the SCMI pin controller driver and SCMI agent code - update i.MX95 SoC and clock related code, board basic support code and so on according to comments - move the function that loads ATF and tee.bin to spl_imx_container.c - add document for i.MX95 image container format Signed-off-by: Alice Guo <alice.guo(a)nxp.com> --- Alice Guo (8): pinctrl: nxp: add a pin controller driver based on SCMI pin control protocol firmware: scmi: add pin control protocol support to SCMI agent clk: scmi: check the clock state/parent/rate control permissions sandbox: add SCMI clock control permissions to sandbox imx: Kconfig: IMX8_ROMAPI is not configured for i.MX95 binman: add a new entry type for packing DDR PHY firmware images tools: imx8image: add i.MX95 support doc: imx: add document for i.MX95 Image Container Format Peng Fan (6): mailbox: add i.MX95 Messaging Unit (MU) driver scmi_protocols: add SCMI misc protocol protocol_id and message_id for getting the ROM passover data scmi_protocols: add SCMI Performance domain management protocol message IDs clk: scmi: add the command CLOCK_PARENT_SET scmi: add the macro SCMI_MSG imx9: scmi: add i.MX95 SoC and clock related code Teo Hall (1): imx: add V2X container support on i.MX95 Viorel Suman (1): firmware: scmi: smt: Interrupt communication enable Ye Li (4): scmi_protocols: update struct scmi_base_discover_list_protocols_out spl: imx: use trampoline buffer to load images to secure region imx9: add i.MX95 Kconfig and Makefile imx95_evk: add i.MX95 19x19 EVK board basic support MAINTAINERS | 1 + arch/arm/dts/imx95-19x19-evk-u-boot.dtsi | 68 +++ arch/arm/dts/imx95-u-boot.dtsi | 157 +++++ arch/arm/include/asm/arch-imx/cpu.h | 2 + arch/arm/include/asm/arch-imx9/clock.h | 10 + arch/arm/include/asm/arch-imx9/imx-regs.h | 5 + arch/arm/include/asm/arch-imx9/sys_proto.h | 1 + arch/arm/include/asm/mach-imx/sys_proto.h | 39 ++ arch/arm/mach-imx/Kconfig | 2 +- arch/arm/mach-imx/image-container.c | 63 +- arch/arm/mach-imx/imx9/Kconfig | 14 + arch/arm/mach-imx/imx9/Makefile | 9 +- arch/arm/mach-imx/imx9/scmi/Makefile | 6 + arch/arm/mach-imx/imx9/scmi/clock.c | 105 ++++ arch/arm/mach-imx/imx9/scmi/clock_scmi.c | 135 +++++ arch/arm/mach-imx/imx9/scmi/container.cfg | 10 + arch/arm/mach-imx/imx9/scmi/imximage.cfg | 15 + arch/arm/mach-imx/imx9/scmi/soc.c | 827 ++++++++++++++++++++++++++ arch/sandbox/include/asm/scmi_test.h | 4 +- board/freescale/imx95_evk/Kconfig | 12 + board/freescale/imx95_evk/MAINTAINERS | 6 + board/freescale/imx95_evk/Makefile | 11 + board/freescale/imx95_evk/imx95_19x19_evk.env | 90 +++ board/freescale/imx95_evk/imx95_evk.c | 54 ++ board/freescale/imx95_evk/spl.c | 72 +++ common/spl/Kconfig | 6 + common/spl/spl_imx_container.c | 41 +- configs/imx95_19x19_evk_defconfig | 177 ++++++ doc/board/nxp/imx95_evk.rst | 114 ++++ doc/board/nxp/index.rst | 1 + doc/imx/imx95_container.txt | 136 +++++ drivers/clk/clk_scmi.c | 191 +++++- drivers/firmware/scmi/Kconfig | 6 + drivers/firmware/scmi/sandbox-scmi_agent.c | 56 +- drivers/firmware/scmi/scmi_agent-uclass.c | 11 + drivers/firmware/scmi/smt.c | 3 + drivers/firmware/scmi/smt.h | 10 + drivers/mailbox/Kconfig | 7 + drivers/mailbox/Makefile | 1 + drivers/mailbox/imx-mailbox.c | 417 +++++++++++++ drivers/pinctrl/nxp/Kconfig | 13 + drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imx.c | 7 +- drivers/pinctrl/nxp/pinctrl-imx.h | 11 + drivers/pinctrl/nxp/pinctrl-scmi.c | 136 +++++ include/configs/imx95_evk.h | 27 + include/imx8image.h | 19 +- include/scmi_agent-uclass.h | 2 + include/scmi_agent.h | 11 + include/scmi_protocols.h | 105 +++- tools/binman/entries.rst | 10 + tools/binman/etype/nxp_header_ddrfw.py | 32 + tools/binman/ftest.py | 11 + tools/binman/test/346_nxp_ddrfw_imx95.dts | 24 + tools/imx8image.c | 143 ++++- tools/imx9_image.sh | 8 + 56 files changed, 3390 insertions(+), 65 deletions(-) --- base-commit: d6da3dbaef57fc1d319b6b552efa009e2489d7d9 change-id: 20250114-imx95-ac8bbccd71e5 Best regards, -- Alice Guo <alice.guo(a)oss.nxp.com>

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Pull request: SoCFPGA changes for u-boot-socfpga-next-20250124
by Chee, Tien Fong 24 Jan '25

24 Jan '25

Dear Tom, Please pull the SoCFPGA changes for next from u-boot-socfpga, containing: 1. Bug fixed for doorbell in secure device manager mailbox driver 2. Enhancement on SoCFPGA dwc_eth_xgmac driver 3. Enhancement on DW MAC driver 4. Improved the error message and status for SoC64 device FPGA configuration driver 5. Updated existing watchdog in system manager to support new SM device Best regards, Tien Fong The following changes since commit 2eed5a1ff36217372e19f7513bd07077fc76718a: Merge https://source.denx.de/u-boot/custodians/u-boot-snapdragon (2025-01-22 11:23:35 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-socfpga.git tags/u-boot-socfpga-next-20250124 for you to fetch changes up to 60d96038d7ca9681e926a22789613a983ff9bf9a: fpga: intel_sdm_mb: add support for query SDM config error and status (2025-01-24 09:56:34 +0800) ---------------------------------------------------------------- Alif Zakuan Yuslaimi (1): arch: arm: mach-socfpga: Mailbox buffer and SDM doorbell improvement Boon Khai Ng (4): net: dwc_eth_xgmac_socfpga: Add support for rgmii-id mode. net: dwc_eth_xgmac: Add device name for the error message. net: dwc_eth_xgmac_socfpga: Add support for distinct mac-mode and phy mode. fpga: intel_sdm_mb: add support for query SDM config error and status Muhammad Hazim Izzat Zamri (1): arm: socfpga:agilex5: Fix system manager watchdog mode setting Rufus Segar (1): net: designware: socfpga: Add RGMII-ID support arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 218 +++++++++++++++++++++ arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 2 +- arch/arm/mach-socfpga/mailbox_s10.c | 16 +- drivers/fpga/intel_sdm_mb.c | 641 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/net/dwc_eth_xgmac.c | 82 +++++--- drivers/net/dwc_eth_xgmac_socfpga.c | 27 ++- drivers/net/dwmac_socfpga.c | 3 + 7 files changed, 940 insertions(+), 49 deletions(-)

2 1

[PATCH] xilinx: Enable mkfwumdata tool for a/b update
by Michal Simek 24 Jan '25

24 Jan '25

Build mkfwumdata tool by default for building ab mdata structure. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- configs/amd_versal2_virt_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index a7d8b035a714..57a6a06df7cd 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -157,3 +157,4 @@ CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_TPM=y # CONFIG_OPTEE_LIB is not set +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index dd6e3ca34660..70e73ac7ad45 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -171,3 +171,4 @@ CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_TPM=y +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 05ead1a41b4d..c0721b65fd48 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -249,3 +249,4 @@ CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_TPM=y CONFIG_SPL_GZIP=y +CONFIG_TOOLS_MKFWUMDATA=y -- 2.43.0

1 0

[PATCH 00/13] rockchip: Add initial support for RK3528
by Jonas Karlman 24 Jan '25

24 Jan '25

This series add initial support for the Rockchip RK3528 SoC. Clk, pinctrl and rng drivers have been imported from vendor U-Boot with minor adjustments and fixes. Upstream DT for RK3528 is at a very basic state at the moment and this series instead add a few missing nodes to -u-boot.dtsi files to have a bootable system. Features tested on a ArmSoM Sige1: - SD-card boot - eMMC boot Features tested on a Radxa E20C v1.104: - SD-card boot - eMMC boot Features tested on a Radxa ROCK 2A v1.202: - SD-card boot Boot log on a ArmSoM Sige1: DDR 44ec2e0a51 huan.he 24/07/12-14:38:48,fwver: v1.10 [...] out U-Boot SPL 2025.01 (Jan 23 2025 - 20:16:33 +0000) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK INFO: Preloader serial: 0 NOTICE: BL31: v2.3():v2.3-857-g059b3c586:derrick.huang, fwver: v1.18 NOTICE: BL31: Built : 17:43:24, Nov 18 2024 INFO: rk_otp_init finish! INFO: ARM GICv2 driver initialized INFO: nonboot_cpus_off: clst_st=0xc0e, core_st=0xe1e0 boot_cpu=0 INFO: dfs DDR fsp_param[0].freq_mhz= 1056MHz INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz INFO: idle_st=0x0, pd_st=0x0 INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 1 INFO: rk_otp_init finish! INFO: RK3528 SoC (0x101) INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9 U-Boot 2025.01 (Jan 23 2025 - 20:16:33 +0000) Model: Generic RK3528 SoC: RK3528A DRAM: 2 GiB Core: 98 devices, 20 uclasses, devicetree: separate MMC: mmc@ffbf0000: 0, mmc@ffc30000: 1 Loading Environment from nowhere... OK In: serial@ff9f0000 Out: serial@ff9f0000 Err: serial@ff9f0000 Hit any key to stop autoboot: 0 => This series depends on the pending merge of devicetree-rebasing v6.13-dts tag. Jonas Karlman (8): arch: arm: rockchip: Add initial support for RK3528 ram: rockchip: Add basic support for RK3528 mmc: rockchip_sdhci: Extend variant configuration mmc: rockchip_sdhci: Add initial support for RK3528 mmc: rockchip_sdhci: Gate clock for glitch free phase switching arm: dts: rockchip: Add rk3528-u-boot.dtsi board: rockchip: Add minimal generic RK3528 board board: rockchip: Add Radxa E20C Joseph Chen (2): clk: rockchip: Add support for RK3528 arm: dts: rockchip: Add rk3528-pinctrl.dtsi Lin Jinhan (1): rng: rockchip: Add support for rkrng variant Steven Liu (1): pinctrl: rockchip: Add support for RK3528 Yifeng Zhao (1): rockchip: mkimage: Add support for RK3528 arch/arm/dts/rk3528-generic-u-boot.dtsi | 31 + arch/arm/dts/rk3528-generic.dts | 20 + arch/arm/dts/rk3528-pinctrl.dtsi | 1397 +++++++++++++ arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 31 + arch/arm/dts/rk3528-u-boot.dtsi | 249 +++ arch/arm/include/asm/arch-rk3528/boot0.h | 9 + arch/arm/include/asm/arch-rk3528/gpio.h | 9 + arch/arm/include/asm/arch-rockchip/clock.h | 7 + .../include/asm/arch-rockchip/cru_rk3528.h | 388 ++++ arch/arm/mach-rockchip/Kconfig | 50 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3528/Kconfig | 15 + arch/arm/mach-rockchip/rk3528/MAINTAINERS | 11 + arch/arm/mach-rockchip/rk3528/Makefile | 5 + arch/arm/mach-rockchip/rk3528/clk_rk3528.c | 16 + arch/arm/mach-rockchip/rk3528/rk3528.c | 104 + arch/arm/mach-rockchip/rk3528/syscon_rk3528.c | 19 + arch/arm/mach-rockchip/sdram.c | 3 +- configs/generic-rk3528_defconfig | 39 + configs/radxa-e20c-rk3528_defconfig | 35 + doc/board/rockchip/rockchip.rst | 13 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_pll.c | 23 +- drivers/clk/rockchip/clk_rk3528.c | 1744 +++++++++++++++++ drivers/mmc/rockchip_sdhci.c | 39 +- drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl-rk3528.c | 292 +++ drivers/ram/rockchip/Makefile | 1 + drivers/ram/rockchip/sdram_rk3528.c | 33 + drivers/rng/rockchip_rng.c | 73 + include/configs/rk3528_common.h | 42 + include/dt-bindings/clock/rk3528-cru.h | 751 +++++++ tools/rkcommon.c | 1 + 33 files changed, 5443 insertions(+), 10 deletions(-) create mode 100644 arch/arm/dts/rk3528-generic-u-boot.dtsi create mode 100644 arch/arm/dts/rk3528-generic.dts create mode 100644 arch/arm/dts/rk3528-pinctrl.dtsi create mode 100644 arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi create mode 100644 arch/arm/dts/rk3528-u-boot.dtsi create mode 100644 arch/arm/include/asm/arch-rk3528/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3528/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3528.h create mode 100644 arch/arm/mach-rockchip/rk3528/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3528/MAINTAINERS create mode 100644 arch/arm/mach-rockchip/rk3528/Makefile create mode 100644 arch/arm/mach-rockchip/rk3528/clk_rk3528.c create mode 100644 arch/arm/mach-rockchip/rk3528/rk3528.c create mode 100644 arch/arm/mach-rockchip/rk3528/syscon_rk3528.c create mode 100644 configs/generic-rk3528_defconfig create mode 100644 configs/radxa-e20c-rk3528_defconfig create mode 100644 drivers/clk/rockchip/clk_rk3528.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3528.c create mode 100644 drivers/ram/rockchip/sdram_rk3528.c create mode 100644 include/configs/rk3528_common.h create mode 100644 include/dt-bindings/clock/rk3528-cru.h -- 2.48.1

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[PATCH] xilinx: Enable meminfo command with mapping
by Michal Simek 24 Jan '25

24 Jan '25

Enable meminfo command to be able to see where things are mapped. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- configs/amd_versal2_virt_defconfig | 2 ++ configs/microblaze-generic_defconfig | 2 ++ configs/xilinx_versal_net_virt_defconfig | 2 ++ configs/xilinx_versal_virt_defconfig | 2 ++ configs/xilinx_zynq_virt_defconfig | 2 ++ configs/xilinx_zynqmp_virt_defconfig | 2 ++ 6 files changed, 12 insertions(+) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 22dad1b7076b..a7d8b035a714 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -30,6 +30,8 @@ CONFIG_SYS_PROMPT="versal2> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 2e618d81544d..87756cb26df5 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_GPIO=y CONFIG_CMD_SAVES=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index b40f7b7f8556..081ad424a9aa 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index ccbd33ee1cf7..dd6e3ca34660 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index ed3d10194857..c2422c5b4dcf 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -56,6 +56,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_THOR_RESET_OFF=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index b13079cdf707..05ead1a41b4d 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -63,6 +63,8 @@ CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_THOR_RESET_OFF=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y -- 2.43.0

1 0

[PATCH 0/2] rockchip: sdram: Fix issues observed on RK3576
by Jonas Karlman 24 Jan '25

24 Jan '25

Most Rockchip AArch64 SoCs have start of DRAM at 0x0. However, the RK3576 instead has start of DRAM at 0x40000000 and can extend continuous beyond the 4 GiB mark. This series fixes two issues observed on a Rockchip RK3576 board testing Heiko's RK3576 series [1]. [1] https://patchwork.ozlabs.org/cover/2013854/ Jonas Karlman (2): rockchip: sdram: Allow the first bank to extend beyond 4 GiB rockchip: sdram: Fix reserve of 2 MiB at start of DRAM arch/arm/mach-rockchip/sdram.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) -- 2.48.1

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[PATCH] net: mediatek: fix coding style of AN8855 switch driver
by Weijie Gao 24 Jan '25

24 Jan '25

This patch fixed the following coding style suggested by checkpatch.pl: 1. Use tab instead of space 2. Use BIT() instead of << 3. Use mdelay for long time delay 4. Remove useless parenthesises Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- drivers/net/mtk_eth/an8855.c | 89 ++++++++++++++++++------------------ 1 file changed, 44 insertions(+), 45 deletions(-) diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c index 4bd7506a58b..25a98e0f935 100644 --- a/drivers/net/mtk_eth/an8855.c +++ b/drivers/net/mtk_eth/an8855.c @@ -22,7 +22,7 @@ #define AN8855_FORCE_MODE_LNK BIT(31) #define AN8855_FORCE_MODE 0xb31593f0 -#define AN8855_PORT_CTRL_BASE (0x10208000) +#define AN8855_PORT_CTRL_BASE 0x10208000 #define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + (p) * 0x200 + (r)) #define AN8855_PORTMATRIX_REG(p) AN8855_PORT_CTRL_REG(p, 0x44) @@ -46,7 +46,7 @@ #define AN8855_CKGCR 0x10213e1c -#define AN8855_SCU_BASE 0x10000000 +#define AN8855_SCU_BASE 0x10000000 #define AN8855_RG_RGMII_TXCK_C (AN8855_SCU_BASE + 0x1d0) #define AN8855_RG_GPIO_LED_MODE (AN8855_SCU_BASE + 0x0054) #define AN8855_RG_GPIO_LED_SEL(i) (AN8855_SCU_BASE + (0x0058 + ((i) * 4))) @@ -66,23 +66,23 @@ #define AN8855_RG_HSGMII_PCS_CTROL_1 (AN8855_HSGMII_CSR_PCS_BASE + 0xa00) #define AN8855_RG_AN_SGMII_MODE_FORCE (AN8855_HSGMII_CSR_PCS_BASE + 0xa24) -#define AN8855_MULTI_SGMII_CSR_BASE 0x10224000 -#define AN8855_SGMII_STS_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x018) +#define AN8855_MULTI_SGMII_CSR_BASE 0x10224000 +#define AN8855_SGMII_STS_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x018) #define AN8855_MSG_RX_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x100) -#define AN8855_MSG_RX_LIK_STS_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x514) -#define AN8855_MSG_RX_LIK_STS_2 (AN8855_MULTI_SGMII_CSR_BASE + 0x51c) +#define AN8855_MSG_RX_LIK_STS_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x514) +#define AN8855_MSG_RX_LIK_STS_2 (AN8855_MULTI_SGMII_CSR_BASE + 0x51c) #define AN8855_PHY_RX_FORCE_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x520) -#define AN8855_XFI_CSR_PCS_BASE 0x10225000 +#define AN8855_XFI_CSR_PCS_BASE 0x10225000 #define AN8855_RG_USXGMII_AN_CONTROL_0 (AN8855_XFI_CSR_PCS_BASE + 0xbf8) #define AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 -#define AN8855_RG_RATE_ADAPT_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x000) +#define AN8855_RG_RATE_ADAPT_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x000) #define AN8855_RATE_ADP_P0_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x100) -#define AN8855_MII_RA_AN_ENABLE (AN8855_MULTI_PHY_RA_CSR_BASE + 0x300) +#define AN8855_MII_RA_AN_ENABLE (AN8855_MULTI_PHY_RA_CSR_BASE + 0x300) #define AN8855_QP_DIG_CSR_BASE 0x1022a000 -#define AN8855_QP_CK_RST_CTRL_4 (AN8855_QP_DIG_CSR_BASE + 0x310) +#define AN8855_QP_CK_RST_CTRL_4 (AN8855_QP_DIG_CSR_BASE + 0x310) #define AN8855_QP_DIG_MODE_CTRL_0 (AN8855_QP_DIG_CSR_BASE + 0x324) #define AN8855_QP_DIG_MODE_CTRL_1 (AN8855_QP_DIG_CSR_BASE + 0x330) @@ -90,7 +90,7 @@ #define AN8855_PON_RXFEDIG_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x100) #define AN8855_PON_RXFEDIG_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x124) -#define AN8855_SS_LCPLL_PWCTL_SETTING_2 (AN8855_QP_PMA_TOP_BASE + 0x208) +#define AN8855_SS_LCPLL_PWCTL_SETTING_2 (AN8855_QP_PMA_TOP_BASE + 0x208) #define AN8855_SS_LCPLL_TDC_FLT_2 (AN8855_QP_PMA_TOP_BASE + 0x230) #define AN8855_SS_LCPLL_TDC_FLT_5 (AN8855_QP_PMA_TOP_BASE + 0x23c) #define AN8855_SS_LCPLL_TDC_PCW_1 (AN8855_QP_PMA_TOP_BASE + 0x248) @@ -101,7 +101,7 @@ #define AN8855_PLL_CTRL_3 (AN8855_QP_PMA_TOP_BASE + 0x40c) #define AN8855_PLL_CTRL_4 (AN8855_QP_PMA_TOP_BASE + 0x410) #define AN8855_PLL_CK_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x414) -#define AN8855_RX_DLY_0 (AN8855_QP_PMA_TOP_BASE + 0x614) +#define AN8855_RX_DLY_0 (AN8855_QP_PMA_TOP_BASE + 0x614) #define AN8855_RX_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x630) #define AN8855_RX_CTRL_5 (AN8855_QP_PMA_TOP_BASE + 0x63c) #define AN8855_RX_CTRL_6 (AN8855_QP_PMA_TOP_BASE + 0x640) @@ -118,7 +118,7 @@ #define AN8855_RG_QP_CDR_PR_CKREF_DIV1 (AN8855_QP_ANA_CSR_BASE + 0x18) #define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE (AN8855_QP_ANA_CSR_BASE + 0x1c) #define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF (AN8855_QP_ANA_CSR_BASE + 0x20) -#define AN8855_RG_QP_TX_MODE_16B_EN (AN8855_QP_ANA_CSR_BASE + 0x28) +#define AN8855_RG_QP_TX_MODE_16B_EN (AN8855_QP_ANA_CSR_BASE + 0x28) #define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL (AN8855_QP_ANA_CSR_BASE + 0x3c) #define AN8855_RG_QP_PLL_SDM_ORD (AN8855_QP_ANA_CSR_BASE + 0x40) @@ -135,49 +135,49 @@ #define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) #define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) -#define PHY_PMA_CTRL (0x340) +#define PHY_PMA_CTRL 0x340 #define PHY_DEV1F 0x1f #define PHY_LED_ON_CTRL(i) (0x24 + ((i) * 2)) -#define LED_ON_EN (1 << 15) -#define LED_ON_POL (1 << 14) -#define LED_ON_EVT_MASK (0x7f) +#define LED_ON_EN BIT(15) +#define LED_ON_POL BIT(14) +#define LED_ON_EVT_MASK 0x7f /* LED ON Event */ -#define LED_ON_EVT_FORCE (1 << 6) -#define LED_ON_EVT_LINK_HD (1 << 5) -#define LED_ON_EVT_LINK_FD (1 << 4) -#define LED_ON_EVT_LINK_DOWN (1 << 3) -#define LED_ON_EVT_LINK_10M (1 << 2) -#define LED_ON_EVT_LINK_100M (1 << 1) -#define LED_ON_EVT_LINK_1000M (1 << 0) +#define LED_ON_EVT_FORCE BIT(6) +#define LED_ON_EVT_LINK_HD BIT(5) +#define LED_ON_EVT_LINK_FD BIT(4) +#define LED_ON_EVT_LINK_DOWN BIT(3) +#define LED_ON_EVT_LINK_10M BIT(2) +#define LED_ON_EVT_LINK_100M BIT(1) +#define LED_ON_EVT_LINK_1000M BIT(0) #define PHY_LED_BLK_CTRL(i) (0x25 + ((i) * 2)) -#define LED_BLK_EVT_MASK (0x3ff) +#define LED_BLK_EVT_MASK 0x3ff /* LED Blinking Event */ -#define LED_BLK_EVT_FORCE (1 << 9) -#define LED_BLK_EVT_10M_RX_ACT (1 << 5) -#define LED_BLK_EVT_10M_TX_ACT (1 << 4) -#define LED_BLK_EVT_100M_RX_ACT (1 << 3) -#define LED_BLK_EVT_100M_TX_ACT (1 << 2) -#define LED_BLK_EVT_1000M_RX_ACT (1 << 1) -#define LED_BLK_EVT_1000M_TX_ACT (1 << 0) +#define LED_BLK_EVT_FORCE BIT(9) +#define LED_BLK_EVT_10M_RX_ACT BIT(5) +#define LED_BLK_EVT_10M_TX_ACT BIT(4) +#define LED_BLK_EVT_100M_RX_ACT BIT(3) +#define LED_BLK_EVT_100M_TX_ACT BIT(2) +#define LED_BLK_EVT_1000M_RX_ACT BIT(1) +#define LED_BLK_EVT_1000M_TX_ACT BIT(0) #define PHY_LED_BCR (0x21) -#define LED_BCR_EXT_CTRL (1 << 15) -#define LED_BCR_CLK_EN (1 << 3) -#define LED_BCR_TIME_TEST (1 << 2) -#define LED_BCR_MODE_MASK (3) -#define LED_BCR_MODE_DISABLE (0) +#define LED_BCR_EXT_CTRL BIT(15) +#define LED_BCR_CLK_EN BIT(3) +#define LED_BCR_TIME_TEST BIT(2) +#define LED_BCR_MODE_MASK 3 +#define LED_BCR_MODE_DISABLE 0 -#define PHY_LED_ON_DUR (0x22) -#define LED_ON_DUR_MASK (0xffff) +#define PHY_LED_ON_DUR 0x22 +#define LED_ON_DUR_MASK 0xffff -#define PHY_LED_BLK_DUR (0x23) -#define LED_BLK_DUR_MASK (0xffff) +#define PHY_LED_BLK_DUR 0x23 +#define LED_BLK_DUR_MASK 0xffff -#define PHY_LED_BLINK_DUR_CTRL (0x720) +#define PHY_LED_BLINK_DUR_CTRL 0x720 /* Definition of LED */ #define LED_ON_EVENT (LED_ON_EVT_LINK_1000M | \ @@ -993,7 +993,7 @@ static int an8855_setup(struct mtk_eth_switch_priv *swpriv) /* Switch soft reset */ an8855_reg_write(priv, AN8855_SYS_CTRL_REG, AN8855_SW_SYS_RST); - udelay(100000); + mdelay(100); an8855_reg_read(priv, AN8855_PKG_SEL, &val); if ((val & 0x7) == PAG_SEL_AN8855H) { @@ -1003,8 +1003,7 @@ static int an8855_setup(struct mtk_eth_switch_priv *swpriv) /* Invert for LED activity change */ an8855_reg_read(priv, AN8855_RG_GPIO_L_INV, &val); for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { - if ((led_cfg[id].pol == LED_HIGH) && - (led_cfg[id].en == 1)) + if (led_cfg[id].pol == LED_HIGH && led_cfg[id].en == 1) val |= 0x1 << id; } an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, (val | 0x1)); -- 2.34.1

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mkenvimage CRC does not match the CRC of fw_setenv
by Floyd Brown 24 Jan '25

24 Jan '25

When I run the same file against both utilities, they do not produce the same CRC. The CRC of fw_setenv matches what uboot has when the environment is created inside the image. Is this a known issue? If so, I am sorry to bring it up (but maybe remove mkenvimage...) Thanks

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[PATCH 0/3] MediaTek ethernet driver refactor and updates
by Weijie Gao 24 Jan '25

24 Jan '25

This patch series will split the switch initialization code from mtk_eth driver into their own files and then add new SoC and switch support. Weijie Gao (3): net: mediatek: split ethernet switch code from mtk_eth.c net: mediatek: add support for MediaTek MT7987 SoC net: mediatek: add support for Airoha AN8855 ethernet switch drivers/net/Kconfig | 21 +- drivers/net/Makefile | 2 +- drivers/net/mtk_eth/Kconfig | 39 + drivers/net/mtk_eth/Makefile | 10 + drivers/net/mtk_eth/an8855.c | 1096 +++++++++++++++++++++++++++ drivers/net/mtk_eth/mt7530.c | 281 +++++++ drivers/net/mtk_eth/mt7531.c | 293 +++++++ drivers/net/mtk_eth/mt753x.c | 262 +++++++ drivers/net/mtk_eth/mt753x.h | 286 +++++++ drivers/net/mtk_eth/mt7988.c | 160 ++++ drivers/net/{ => mtk_eth}/mtk_eth.c | 981 ++++-------------------- drivers/net/{ => mtk_eth}/mtk_eth.h | 301 ++------ 12 files changed, 2631 insertions(+), 1101 deletions(-) create mode 100644 drivers/net/mtk_eth/Kconfig create mode 100644 drivers/net/mtk_eth/Makefile create mode 100644 drivers/net/mtk_eth/an8855.c create mode 100644 drivers/net/mtk_eth/mt7530.c create mode 100644 drivers/net/mtk_eth/mt7531.c create mode 100644 drivers/net/mtk_eth/mt753x.c create mode 100644 drivers/net/mtk_eth/mt753x.h create mode 100644 drivers/net/mtk_eth/mt7988.c rename drivers/net/{ => mtk_eth}/mtk_eth.c (62%) rename drivers/net/{ => mtk_eth}/mtk_eth.h (59%) -- 2.34.1

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