September 2024 - U-Boot

[PATCH 00/10] arm64: zynqmp: DT schema alignments
by Michal Simek 20 Sep '24

20 Sep '24

Hi, I am sending some patches to fix issues reported by dt-schema checking. Thanks, Michal Michal Simek (10): arm64: zynqmp: Fix status property for m-a2197 boards arm64: zynqmp: Align gpio hogs with dt-schema xilinx: Fix axi and mmc node names in mini configuration arm64: zynqmp: Fix gpio-line-name size for m-a2197 platforms arm64: zynqmp: Fix comment style around gpio line-names arm64: zynqmp: fix i2c mux bus description for m-a2197 platforms arm64: zynqmp: Align mini-qspi DT with dt-schema arm64: zynqmp: Define phy-mode in zcu1275-revB arm64: zynqmp: Use generic spi@ name in zcu111-revA arm64: zynqmp: Rename ina226-vccint-io-bram-ps nodes arch/arm/dts/versal-mini-emmc0.dts | 2 +- arch/arm/dts/versal-mini-emmc1.dts | 2 +- arch/arm/dts/versal-mini-ospi.dtsi | 2 +- arch/arm/dts/versal-mini-qspi.dtsi | 2 +- arch/arm/dts/zynq-cse-nand.dts | 2 +- arch/arm/dts/zynq-cse-nor.dts | 2 +- arch/arm/dts/zynq-cse-qspi.dtsi | 2 +- arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 16 ++++++++-------- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 16 ++++++++-------- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 16 ++++++++-------- arch/arm/dts/zynqmp-mini-emmc0.dts | 4 ++-- arch/arm/dts/zynqmp-mini-emmc1.dts | 4 ++-- arch/arm/dts/zynqmp-mini-nand.dts | 2 +- arch/arm/dts/zynqmp-mini-qspi.dts | 16 ++++++++-------- .../zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso | 8 ++++---- .../zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso | 8 ++++---- .../zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso | 8 ++++---- .../zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso | 8 ++++---- .../zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso | 8 ++++---- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 10 +++++----- arch/arm/dts/zynqmp-sc-revB.dts | 2 +- arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso | 8 ++++---- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revB.dts | 1 + arch/arm/dts/zynqmp-zcu208-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu216-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu670-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu670-revB.dts | 2 +- 30 files changed, 84 insertions(+), 83 deletions(-) -- 2.43.0

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[PATCH] arm64: zynqmp: Define only one revision in zcu106-rev1.0
by Michal Simek 20 Sep '24

20 Sep '24

zcu106 rev1.0 is sw compatible with revA but only one revision should be listed in compatible string that's why remove revA and keep only rev1.0. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-zcu106-rev1.0.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts index a9b5826a777d..f1ec314fdefc 100644 --- a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts @@ -11,6 +11,6 @@ / { model = "ZynqMP ZCU106 Rev1.0"; - compatible = "xlnx,zynqmp-zcu106-rev1.0", "xlnx,zynqmp-zcu106-revA", + compatible = "xlnx,zynqmp-zcu106-rev1.0", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; }; -- 2.43.0

1 1

[PATCH] net: gem: Remove undocumented is-internal-pcspma dt flag
by Michal Simek 20 Sep '24

20 Sep '24

Generic understanding/consideration is that phy-mode as sgmi means that the internal PCS(Physical Coding Sublayer) should be enabled by default. Xilinx GEM implementation allows configuration GEM (gmii mode) + PL PCS PMA (sgmii mode, Physical Medum Attachment) but in this case phy-mode should be setup as gmii. The reason for this assumption is that phy-mode should be described based on GEM configuration not based on mode coming out of PHY. Also Linux kernel automatically setting up PCSSEL bit when phy mode is sgmii without a need to specified additional DT propety. All our DTSes with sgmii phy mode have this flag enabled that's why there is no need/reason to just duplicate information. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-dlc21-revA.dts | 1 - arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 1 - arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 1 - arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 1 - arch/arm/dts/zynqmp-vpk120-revA.dts | 1 - drivers/net/zynq_gem.c | 9 ++------- 9 files changed, 2 insertions(+), 15 deletions(-) diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 59cf22d0eb98..293d8e97b63a 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -87,7 +87,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 0b97fa3f28ac..4e0587fd441a 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -155,7 +155,6 @@ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; - is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index e3228fc98f0c..c439f778ca46 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -80,7 +80,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; - is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index d3070b0062e9..ae52e8e996a5 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -90,7 +90,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index ce7c5eb6d346..6349a0e10877 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -195,7 +195,6 @@ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; - is-internal-pcspma; assigned-clock-rates = <250000000>; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 0a0cbd2b69ae..b0d737d3caf0 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -216,7 +216,6 @@ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; - is-internal-pcspma; assigned-clock-rates = <250000000>; }; diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index b626d1aacf58..7849f8c540bf 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -117,7 +117,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index e0632883e4ec..4768fac71d02 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -118,7 +118,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ mdio: mdio { #address-cells = <1>; diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index fe7d10844507..461805ae53ff 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -228,7 +228,6 @@ struct zynq_gem_priv { struct clk tx_clk; struct clk pclk; u32 max_speed; - bool int_pcs; bool dma_64bit; u32 clk_en_info; struct reset_ctl_bulk resets; @@ -504,8 +503,7 @@ static int zynq_gem_init(struct udevice *dev) * Set SGMII enable PCS selection only if internal PCS/PMA * core is used and interface is SGMII. */ - if (priv->interface == PHY_INTERFACE_MODE_SGMII && - priv->int_pcs) { + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | ZYNQ_GEM_NWCFG_PCS_SEL; } @@ -529,8 +527,7 @@ static int zynq_gem_init(struct udevice *dev) writel(nwcfg, &regs->nwcfg); #ifdef CONFIG_ARM64 - if (priv->interface == PHY_INTERFACE_MODE_SGMII && - priv->int_pcs) { + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { /* * Disable AN for fixed link configuration, enable otherwise. * Must be written after PCS_SEL is set in nwconfig, @@ -992,8 +989,6 @@ static int zynq_gem_of_to_plat(struct udevice *dev) return -EINVAL; priv->interface = pdata->phy_interface; - priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); - priv->clk_en_info = dev_get_driver_data(dev); return 0; -- 2.43.0

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[PATCH] mmc: zynq_sdhci: Remove device_is_compatible() function
by Padmarao Begari 20 Sep '24

20 Sep '24

There are lot of device_is_compatible() present in the driver. Remove them and replace with a variables "SDHCI_COMPATIBLE_SDHCI_89A" and "SDHCI_COMPATIBLE_VERSAL_NET_EMMC" with match data. This change saves the space and reduce the execution time. Signed-off-by: Padmarao Begari <padmarao.begari(a)amd.com> --- drivers/mmc/zynq_sdhci.c | 39 ++++++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 28d2b456fb..24d0556cd3 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -105,6 +105,19 @@ struct arasan_sdhci_priv { struct reset_ctl_bulk resets; }; +enum arasan_sdhci_compatible { + SDHCI_COMPATIBLE_SDHCI_89A, + SDHCI_COMPATIBLE_VERSAL_NET_EMMC, +}; + +static bool arasan_sdhci_is_compatible(struct udevice *dev, + enum arasan_sdhci_compatible family) +{ + enum arasan_sdhci_compatible compat = dev_get_driver_data(dev); + + return compat == family; +} + /* For Versal platforms zynqmp_mmio_write() won't be available */ __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) { @@ -422,7 +435,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) mdelay(1); - if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + if (arasan_sdhci_is_compatible(mmc->dev, SDHCI_COMPATIBLE_SDHCI_89A)) arasan_zynqmp_dll_reset(host, priv->node_id); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); @@ -470,7 +483,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) udelay(1); - if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + if (arasan_sdhci_is_compatible(mmc->dev, SDHCI_COMPATIBLE_SDHCI_89A)) arasan_zynqmp_dll_reset(host, priv->node_id); /* Enable only interrupts served by the SD controller */ @@ -858,7 +871,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing); if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && - device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) { ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase); if (ret) return ret; @@ -869,7 +882,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL) || IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || IS_ENABLED(CONFIG_ARCH_VERSAL2)) && - device_is_compatible(dev, "xlnx,versal-8.9a")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) { ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase); if (ret) return ret; @@ -879,7 +892,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) return ret; } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || IS_ENABLED(CONFIG_ARCH_VERSAL2)) && - device_is_compatible(dev, "xlnx,versal-net-emmc")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC)) { if (mmc->clock >= MIN_PHY_CLK_HZ) if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN) iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL; @@ -933,7 +946,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) int i; if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && - device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i]; clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i]; @@ -948,7 +961,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) if ((IS_ENABLED(CONFIG_ARCH_VERSAL) || IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || IS_ENABLED(CONFIG_ARCH_VERSAL2)) && - device_is_compatible(dev, "xlnx,versal-8.9a")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = versal_iclk_phases[i]; clk_data->clk_phase_out[i] = versal_oclk_phases[i]; @@ -957,7 +970,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || IS_ENABLED(CONFIG_ARCH_VERSAL2)) && - device_is_compatible(dev, "xlnx,versal-net-emmc")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC)) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i]; clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i]; @@ -1101,7 +1114,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host = priv->host; #if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE) - if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { + if (arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) { ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_SD_CONFIG); if (!ret) { @@ -1111,7 +1124,7 @@ static int arasan_sdhci_probe(struct udevice *dev) } } #endif - if (device_is_compatible(dev, "xlnx,versal-net-emmc")) + if (arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC)) priv->internal_phy_reg = true; ret = clk_get_by_index(dev, 0, &clk); @@ -1145,7 +1158,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks |= SDHCI_QUIRK_NO_1_8_V; if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) && - device_is_compatible(dev, "xlnx,versal-net-emmc")) + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC)) host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400; plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ; @@ -1228,8 +1241,8 @@ static int arasan_sdhci_bind(struct udevice *dev) } static const struct udevice_id arasan_sdhci_ids[] = { - { .compatible = "arasan,sdhci-8.9a" }, - { .compatible = "xlnx,versal-net-emmc" }, + { .compatible = "arasan,sdhci-8.9a", .data = SDHCI_COMPATIBLE_SDHCI_89A }, + { .compatible = "xlnx,versal-net-emmc", .data = SDHCI_COMPATIBLE_VERSAL_NET_EMMC }, { } }; -- 2.25.1

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[PATCH] board: xilinx: Remove conditional check for Microblaze
by Padmarao Begari 20 Sep '24

20 Sep '24

U-Boot is not picking boot.scr script address from device tree rather it's using default address for Microblaze platform, and it's picking for other platforms. Remove conditional check for Microblaze platform, so that u-boot pick up boot.scr script address for all platforms from device tree. Signed-off-by: Padmarao Begari <padmarao.begari(a)amd.com> --- board/xilinx/common/board.c | 39 +++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 0b43407b9e..a217b39df6 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -426,28 +426,25 @@ int board_late_init_xilinx(void) struct xilinx_board_description *desc; phys_size_t bootm_size = gd->ram_top - gd->ram_base; u64 bootscr_flash_offset, bootscr_flash_size; - - if (!IS_ENABLED(CONFIG_MICROBLAZE)) { - ulong scriptaddr; - u64 bootscr_address; - u64 bootscr_offset; - - /* Fetch bootscr_address/bootscr_offset from DT and update */ - if (!ofnode_read_bootscript_address(&bootscr_address, - &bootscr_offset)) { - if (bootscr_offset) - ret |= env_set_hex("scriptaddr", - gd->ram_base + - bootscr_offset); - else - ret |= env_set_hex("scriptaddr", - bootscr_address); - } else { - /* Update scriptaddr(bootscr offset) from env */ - scriptaddr = env_get_hex("scriptaddr", 0); + ulong scriptaddr; + u64 bootscr_address; + u64 bootscr_offset; + + /* Fetch bootscr_address/bootscr_offset from DT and update */ + if (!ofnode_read_bootscript_address(&bootscr_address, + &bootscr_offset)) { + if (bootscr_offset) ret |= env_set_hex("scriptaddr", - gd->ram_base + scriptaddr); - } + gd->ram_base + + bootscr_offset); + else + ret |= env_set_hex("scriptaddr", + bootscr_address); + } else { + /* Update scriptaddr(bootscr offset) from env */ + scriptaddr = env_get_hex("scriptaddr", 0); + ret |= env_set_hex("scriptaddr", + gd->ram_base + scriptaddr); } if (!ofnode_read_bootscript_flash(&bootscr_flash_offset, -- 2.25.1

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About fsl-espi driver
by Yusuf Kaya 20 Sep '24

20 Sep '24

Hello, Firstly thanks for your contribution to u-boot. When i look at the driver(fsl_espi.c), it has some flaws ? Because when ı want to receive 6-bytes from the slave device, spi master also sends 6-bytes to the spi slave. This is happening in espi_xfer functionality. I just wonder it is a mistake or not ? Thanks in advance.

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[PATCH] arm64: zynqmp: Fix status property for m-a2197 boards
by Michal Simek 20 Sep '24

20 Sep '24

Status property should be missing or okay or disabled but not just disable. dt-validate is reporting it too. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 83b8a98d80ca..38be5a0f96f1 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -101,7 +101,7 @@ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ - status = "disable"; + status = "disabled"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index dd37b726d3dc..3c04da1c5fbe 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -97,7 +97,7 @@ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ - status = "disable"; + status = "disabled"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 811cebafe9e6..7439a2f872e5 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -97,7 +97,7 @@ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ - status = "disable"; + status = "disabled"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; -- 2.43.0

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[PATCH] arm64: zynqmp: Add missing vc7_xin fixed clock to sc-vpk180-revA
by Michal Simek 20 Sep '24

20 Sep '24

Add missing vc7_xin fixed clock as clock input for some clock generators. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-sc-vpk180-revA.dtso | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso index 18625933ad3d..ba5484573c99 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso @@ -16,6 +16,12 @@ &{/} { compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA", "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; + + vc7_xin: vc7-xin { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <50000000>; + }; }; &i2c0 { -- 2.43.0

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[PATCH v2 0/2] fdtoverlay related changes
by Prasad Kummari 20 Sep '24

20 Sep '24

Changes in v2: - Corrected commit description. Prasad Kummari (2): kbuild: cherry-pick kbuild fdtoverlay changes from linux arm64: zynqmp: Remove overlays and add new dtb entries for ZynqMP arch/arm/dts/Makefile | 78 +++++++++++++++++++++++++++++++++--------- scripts/Kbuild.include | 4 +++ scripts/Makefile.build | 1 + scripts/Makefile.lib | 27 +++++++++++++++ 4 files changed, 93 insertions(+), 17 deletions(-) -- 2.25.1

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[PATCH v2 00/13] ufs: enhancements to support Qualcomm UFS controllers
by Neil Armstrong 20 Sep '24

20 Sep '24

This serie regroups all the fixes and base enhancements required to support the Qualcomm UFS controllers in U-Boot. This syncs headers & defines from Linux, and includes 2 set of fixes that were sent separately: - ufs: core: remove link_startup_again logic - ufs: properly fix cache operations Without those 2 sets, UFS cannot initialize on Qualcomm controlers since v5, and a numerous of Cache issues makes any UFS controller fail to initialize. Since UFS core hasn't changed for a while, and since UFS is core technology for the Qualcomm SoCs, I volunteer maintaininig the UFS subsystem if Bhupesh & Neha Malcom Francis are ok with that. It has been reported to show regressions on: - TI K3 platforms (j721s2, j721e, j7200, j784s4) [1] - AMD platform (amd_versal2_virt_defconfig) [2] [1] https://lore.kernel.org/all/38f599a8-7094-4a04-8ff6-96fc8b9d168a@ti.com/ [2] https://lore.kernel.org/all/SA1PR12MB869713CA620F99077B75EF0E98632@SA1PR12M… Signed-off-by: Neil Armstrong <neil.armstrong(a)linaro.org> --- Changes in v2: - Added review and tested-by tags - Updated patch 12 message with more explanations - Synced patch 9 again with Linux 6.11 - Updated patches 7, 8, 9 and 10 with informations about the origins of the changes - Link to v1: https://lore.kernel.org/r/20240910-topic-ufs-enhancements-v1-0-3ee0bffacc64… --- Bhupesh Sharma (5): ufs/ufs.h: Add definition of 'ufshcd_rmwl()' ufs: Clear UECPA once due to LINERESET has happened during LINK_STARTUP ufs: Sync possible UFS Quirks with Linux UFS driver ufs: Add missing memory barriers ufs: Fix debug message in 'ufs_start' Marek Vasut (2): ufs: Add UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS ufs: Add UFSHCD_QUIRK_HIBERN_FASTAUTO Neil Armstrong (6): ufs: allocate descriptors with size aligned with DMA_MINALIGN ufs: fix dcache flush and invalidate range calculation ufs: split flush and invalidate to only invalidate when required ufs: use dcache helpers for scsi_cmd data and only invalidate if necessary ufs: core: remove link_startup_again logic MAINTAINERS: Add myself to the list of UFS maintainers MAINTAINERS | 1 + drivers/ufs/ufs.c | 98 ++++++++++++++++----------- drivers/ufs/ufs.h | 199 ++++++++++++++++++++++++++++++++++++++++++++++++------ 3 files changed, 239 insertions(+), 59 deletions(-) --- base-commit: 24961c0e0444d3ed534ffc6a173e6ea636ca116b change-id: 20240910-topic-ufs-enhancements-fe8ef9ce39d8 Best regards, -- Neil Armstrong <neil.armstrong(a)linaro.org>

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