May 2024 - U-Boot

[PATCH] ARM: dts: renesas: Reserve space in 64bit R-Car DTs
by Marek Vasut 20 May '24

20 May '24

Reserve 4 kiB of space in 64bit R-Car DTs when those DTs are compiled to permit patching in OpTee-OS /firmware node, /reserved-memory node, possibly also additional /memory@ nodes and RPC node by TFA. This duplicates behavior in arch/arm/dts/Makefile with OF_UPSTREAM. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Sumit Garg <sumit.garg(a)linaro.org> Cc: Tom Rini <trini(a)konsulko.com> --- dts/upstream/src/arm64/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/dts/upstream/src/arm64/Makefile b/dts/upstream/src/arm64/Makefile index 9a8f6aa3584..26a83d3d29d 100644 --- a/dts/upstream/src/arm64/Makefile +++ b/dts/upstream/src/arm64/Makefile @@ -7,6 +7,10 @@ targets += $(dtb-y) # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 +ifdef CONFIG_RCAR_64 +DTC_FLAGS += -R 4 -p 0x1000 +endif + PHONY += dtbs dtbs: $(addprefix $(obj)/, $(dtb-y)) @: -- 2.43.0

2 1

[Agilex7 M-series Platform Enablement v1 00/16]
by tingting.meng＠intel.com 20 May '24

20 May '24

From: Tingting Meng <tingting.meng(a)intel.com> Intel Agilex7 M-Series is the highest peformance FPGA targeted for compute and memory-intensive application,this series is built using intel 7 process technology and expands upon I-Series device feature, offering in-package high bandwidth memory (HBM), memory interfaces for DDR5 SDRAM, and a hard memory Network-on-Chip (NoC) to maximize memory bandwidth. The series of patches include adding clock driver, IOSSM mailbox driver, UIBSSM mailbox driver, DDR driver and HBM driver needed for Agilex 7 M-Series platform enablement and supports linux boot from SD card. This series patches based on master branch https://source.denx.de/u-boot/u-boot Complete compilation check on different devices, ran checkpatch and tested on board Siew Chin Lim (1): include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile Sin Hui Kho (1): ddr: altera: soc64: Restructure SDRAM firewall function Teik Heng Chong (5): arch: arm: mach-socfpga: Improve help info. clk: altera: Add clock support for Agilex7 M-series ddr: altera: Add uibssm mailbox for Agilex7 M-series ddr: altera: soc64: Clean up bit-shift by zero bit ddr: altera: soc64: Fix dram size calculation in clamshell mode Wan Yee Lau (9): arch: arm: dts: Add dts and dtsi for new platform Agilex7 M-series arch: arm: mach-socfpga: Add Agilex7 M-series mach-socfgpa enablement arch: arm: mach-socfpga: Update handoff settings for Agilex7 M-series include: configs: Add config header file for Agilex7 M-series ddr: altera: Add iossm mailbox for Agilex7 M-series ddr: altera: Add DDR driver for Agilex7 M-series arch: arm: mach-socfpga: Update kconfig for new platform Agilex7 M-series arch: arm: dts: Update Makefile for new platform Agilex7 M-series configs: Add defconfig for Agilex7 M-series arch/arm/Kconfig | 7 +- arch/arm/dts/Makefile | 1 + .../dts/socfpga_agilex7m_socdk-u-boot.dtsi | 80 +++ arch/arm/dts/socfpga_agilex7m_socdk.dts | 185 +++++ arch/arm/dts/socfpga_soc64_u-boot.dtsi | 127 ++++ arch/arm/mach-socfpga/Kconfig | 19 + arch/arm/mach-socfpga/Makefile | 18 + .../include/mach/base_addr_soc64.h | 6 +- .../mach-socfpga/include/mach/clock_manager.h | 2 +- .../mach-socfpga/include/mach/handoff_soc64.h | 14 +- arch/arm/mach-socfpga/include/mach/misc.h | 3 +- .../include/mach/system_manager_soc64.h | 7 +- arch/arm/mach-socfpga/misc.c | 6 +- arch/arm/mach-socfpga/spl_agilex7m.c | 98 +++ arch/arm/mach-socfpga/wrap_handoff_soc64.c | 4 + board/intel/agilex7m-socdk/MAINTAINERS | 7 + board/intel/agilex7m-socdk/Makefile | 7 + board/intel/agilex7m-socdk/socfpga.c | 4 + configs/socfpga_agilex7m_sdmmc_defconfig | 114 ++++ drivers/clk/altera/Makefile | 1 + drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/iossm_mailbox.c | 637 ++++++++++++++++++ drivers/ddr/altera/iossm_mailbox.h | 182 +++++ drivers/ddr/altera/sdram_agilex7m.c | 527 +++++++++++++++ drivers/ddr/altera/sdram_soc64.c | 42 +- drivers/ddr/altera/sdram_soc64.h | 40 +- drivers/ddr/altera/uibssm_mailbox.c | 311 +++++++++ drivers/ddr/altera/uibssm_mailbox.h | 117 ++++ include/configs/socfpga_agilex7m_socdk.h | 12 + 29 files changed, 2551 insertions(+), 30 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex7m_socdk.dts create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi create mode 100644 arch/arm/mach-socfpga/spl_agilex7m.c create mode 100644 board/intel/agilex7m-socdk/MAINTAINERS create mode 100644 board/intel/agilex7m-socdk/Makefile create mode 100644 board/intel/agilex7m-socdk/socfpga.c create mode 100644 configs/socfpga_agilex7m_sdmmc_defconfig create mode 100644 drivers/ddr/altera/iossm_mailbox.c create mode 100644 drivers/ddr/altera/iossm_mailbox.h create mode 100644 drivers/ddr/altera/sdram_agilex7m.c create mode 100644 drivers/ddr/altera/uibssm_mailbox.c create mode 100644 drivers/ddr/altera/uibssm_mailbox.h create mode 100644 include/configs/socfpga_agilex7m_socdk.h -- 2.25.1

3 20

[PATCH 1/2 v4] board: starfive: support Pine64 Star64 board
by H Bell 20 May '24

20 May '24

Similar to the Milk-V Mars, The Star64 board contains few differences to the VisionFive 2 boards, so can be part of the same U-boot build. Signed-off-by: Henry Bell <dmoo_dv(a)protonmail.com> Cc: ycliang(a)andestech.com Cc: heinrich.schuchardt(a)canonical.com --- Changes since v1 - Fix typos on naming - Create pine64_star64 struct to be populated with PHY values once confirmed Changes since v2 - Set delays to 0 - Add missing 10/100/1000 clocks across the two devices - Set all uA values to 2910 Changes since v3 - Rebase against d678a59d2d --- board/starfive/visionfive2/spl.c | 91 +++++++++++++++++++ .../visionfive2/starfive_visionfive2.c | 4 + 2 files changed, 95 insertions(+) diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index b555189556..becc178c38 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -86,6 +86,45 @@ static const struct starfive_vf2_pro starfive_verb[] = { "tx-internal-delay-ps", "0"}, }; +static const struct starfive_vf2_pro star64_pine64[] = { + {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, + {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, + + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-adj-enabled", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-10-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-100-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-1000-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,rx-clk-drv-microamp", "2910"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,rx-data-drv-microamp", "2910"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "rx-internal-delay-ps", "0"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "tx-internal-delay-ps", "0"}, + + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,tx-clk-adj-enabled", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,tx-clk-10-inverted", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,tx-clk-100-inverted", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-1000-inverted", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,rx-clk-drv-microamp", "2910"}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,rx-data-drv-microamp", "2910"}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "rx-internal-delay-ps", "0"}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "tx-internal-delay-ps", "0"}, +}; + void spl_fdt_fixup_mars(void *fdt) { static const char compat[] = "milkv,mars\0starfive,jh7110"; @@ -250,6 +289,56 @@ void spl_fdt_fixup_version_b(void *fdt) } } +void spl_fdt_fixup_star64(void *fdt) +{ + static const char compat[] = "pine64,star64\0starfive,jh7110"; + u32 phandle; + u8 i; + int offset; + int ret; + + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", + "Pine64 Star64"); + + /* gmac0 */ + offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); + phandle = fdt_get_phandle(fdt, offset); + offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); + + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", + JH7110_AONCLK_GMAC0_RMII_RTX); + + /* gmac1 */ + offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); + phandle = fdt_get_phandle(fdt, offset); + offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); + + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", + JH7110_SYSCLK_GMAC1_RMII_RTX); + + for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) { + offset = fdt_path_offset(fdt, star64_pine64[i].path); + + if (star64_pine64[i].value) + ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name, + dectoul(star64_pine64[i].value, NULL)); + else + ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name); + + if (ret) { + pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name); + break; + } + } +} + void spl_perform_fixups(struct spl_image_info *spl_image) { u8 version; @@ -278,6 +367,8 @@ void spl_perform_fixups(struct spl_image_info *spl_image) spl_fdt_fixup_version_b(spl_image->fdt_addr); break; }; + } else if (!strncmp(product_id, "STAR64", 6)) { + spl_fdt_fixup_star64(spl_image->fdt_addr); } else { pr_err("Unknown product %s\n", product_id); }; diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index 6be5348962..f6114602f8 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -27,6 +27,8 @@ DECLARE_GLOBAL_DATA_PTR; "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" #define FDTFILE_VISIONFIVE2_1_3B \ "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb" +#define FDTFILE_PINE64_STAR64 \ + "starfive/jh7110-pine64-star64.dtb" /* enable U74-mc hart1~hart4 prefetcher */ static void enable_prefetcher(void) @@ -87,6 +89,8 @@ static void set_fdtfile(void) fdtfile = FDTFILE_VISIONFIVE2_1_3B; break; } + } else if (!strncmp(product_id, "STAR64", 6)) { + fdtfile = FDTFILE_PINE64_STAR64; } else { log_err("Unknown product\n"); return; -- 2.44.0

1 0

[PATCH v2 0/8] ECC Series
by Santhosh Kumar K 20 May '24

20 May '24

Hello, This series is to: Add support for Inline ECC in DDR for AM64X, AM62X, AM62AX, AM62PX, J721S2 and J784S4 devices. (1/8) Enable ECC priming with BIST engine (2/8) Add a function to store base address and size of RAM's banks in a 64-bit device private data (3/8) Setup the ECC region start and range (4/8) Enable ECC 1-bit error, 2-bit error and multiple-bit error interrupts (5/8) Add CONFIG_K3_INLINE_ECC (6/8) Set NR_DRAM_BANKS to 2 (7/8) Pull Redundant DDR functions to a common location and Fixup DDR size when ECC is enabled (8/8) Add ss_cfg reg entry Changes since v1: Add support for J7* devices. v1: https://lore.kernel.org/u-boot/20240131060213.1128024-1-s-k6@ti.com/T/#m19d… Test Results: https://gist.github.com/santhosh21/53c6f285640c4b6dfb3420d84975d12a This series contains changes that grab the memory node from the DTS to set/modify DRAM bank sizes. A kernel patch has been sent [1] setting the required nodes to be available at bootloader stage. This patch series can be merged only after the DTS changes have been reflected in U-Boot either via OF_UPSTREAM (for devices that have moved to it) or via a sync to U-Boot patch. [1] https://lore.kernel.org/all/20240506110203.3230255-1-n-francis@ti.com/ Thanks and Regards, Santhosh. Georgi Vlaev (1): ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming Neha Malcom Francis (2): drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC configs: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2 Santhosh Kumar K (5): ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue ram: k3-ddrss: Setup ECC region start and range ram: k3-ddrss: Enable ECC interrupts board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled arm: dts: k3-*-ddr: Add ss_cfg reg entry arch/arm/dts/k3-am62a-ddr.dtsi | 7 +- arch/arm/dts/k3-j721s2-ddr.dtsi | 12 +- arch/arm/dts/k3-j784s4-ddr.dtsi | 24 ++-- board/ti/am62ax/evm.c | 17 +-- board/ti/am62px/evm.c | 18 +-- board/ti/am62x/evm.c | 63 ++-------- board/ti/am64x/evm.c | 73 ++--------- board/ti/am65x/evm.c | 29 +---- board/ti/common/Makefile | 1 + board/ti/common/k3-ddr-init.c | 89 +++++++++++++ board/ti/common/k3-ddr-init.h | 15 +++ board/ti/j721e/evm.c | 29 +---- board/ti/j721s2/evm.c | 35 ++---- board/ti/j784s4/evm.c | 17 +-- configs/j7200_evm_r5_defconfig | 1 + configs/j721e_evm_r5_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + configs/j784s4_evm_r5_defconfig | 1 + drivers/ram/Kconfig | 11 ++ drivers/ram/k3-ddrss/k3-ddrss.c | 214 +++++++++++++++++++++++++++----- 20 files changed, 391 insertions(+), 267 deletions(-) create mode 100644 board/ti/common/k3-ddr-init.c create mode 100644 board/ti/common/k3-ddr-init.h -- 2.34.1

3 10

[PATCH v3 0/3] cyclic/watchdog patches
by Rasmus Villemoes 19 May '24

19 May '24

A bit of a mixed bag. I've been wanting to submit something like 3/3 for a while. So when I stumbled on Marek's patch https://lore.kernel.org/u-boot/20240316201416.211480-1-marek.vasut+renesas@… , I got reminded of that plan, and I think that patch could be more readable if we adopt this model. While actually doing those mostly mechanical changes, I stumbled on two separate issues that probably want fixing regardless of the fate of 3/3. Mostly just compile-tested, and now also checked that at least the sandbox test runs succesfully. v3: Also update the unit test according to the new API. v2: Add R-bs from Stefan. Fixup whitespace in the doc/ part. Rebase to current master (676903c1b97), fixing trivial conflict with 301bac6047c8. Rasmus Villemoes (3): cyclic: stop strdup'ing name in cyclic_register() wdt-uclass: prevent multiple cyclic_register calls cyclic: make clients embed a struct cyclic_info in their own data structure board/Marvell/octeon_nic23/board.c | 9 ++++--- cmd/cyclic.c | 12 ++++------ common/cyclic.c | 24 +++++-------------- doc/develop/cyclic.rst | 26 ++++++++++++-------- drivers/watchdog/wdt-uclass.c | 38 ++++++++++++++++-------------- include/cyclic.h | 36 ++++++++++++++-------------- test/common/cyclic.c | 19 +++++++++------ 7 files changed, 83 insertions(+), 81 deletions(-) -- 2.40.1.1.g1c60b9335d

1 3

[PATCH 2/2 v3] board: starfive: support Pine64 Star64 board
by H Bell 19 May '24

19 May '24

Add documentation files Signed-off-by: Henry Bell <dmoo_dv(a)protonmail.com> Cc: ycliang(a)andestech.com Cc: heinrich.schuchardt(a)canonical.com --- Changes since v1 - New patch Changes since v2 - Remove extra params to - Clarification on boot section - Add entry on MAC adresses and how to correct them --- doc/board/starfive/index.rst | 1 + doc/board/starfive/pine64_star64.rst | 136 +++++++++++++++++++++++++++ 2 files changed, 137 insertions(+) create mode 100644 doc/board/starfive/pine64_star64.rst diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst index 2762bf74c1..f05f8a0765 100644 --- a/doc/board/starfive/index.rst +++ b/doc/board/starfive/index.rst @@ -7,4 +7,5 @@ StarFive :maxdepth: 1 milk-v_mars.rst + pine64_star64 visionfive2 diff --git a/doc/board/starfive/pine64_star64.rst b/doc/board/starfive/pine64_star64.rst new file mode 100644 index 0000000000..567d1207ba --- /dev/null +++ b/doc/board/starfive/pine64_star64.rst @@ -0,0 +1,136 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Pine64 Star64 +=========== + +U-Boot for the Star64 uses the same U-Boot binaries as the VisionFive 2 board. +In U-Boot SPL the actual board is detected and the device-tree patched +accordingly. + +Building +~~~~~~~~ + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE=<riscv64 toolchain prefix> + +The M-mode software OpenSBI provides the supervisor binary interface (SBI) and +is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot. +Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use +a current release. + +.. code-block:: console + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=generic FW_TEXT_START=0x40000000 + +Now build the U-Boot SPL and U-Boot proper. + +.. code-block:: console + + cd <U-Boot-dir> + make starfive_visionfive2_defconfig + make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin + +This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well +as the FIT image (u-boot.itb) with OpenSBI and U-Boot. + +Device-tree selection +~~~~~~~~~~~~~~~~~~~~~ + +U-Boot will set variable $fdtfile to starfive/jh7110-pine64-star64.dtb. + +To overrule this selection the variable can be set manually and saved in the +environment + +:: + + setenv fdtfile my_device-tree.dtb + env save + +or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to +provide a default value. + +Boot source selection +~~~~~~~~~~~~~~~~~~~~~ + +The board provides the DIP switches (marked S1804) adjacent to the 40pin GPIO +Bus for boot selection. The ``L`` (0) and ``H`` (1) silk screening to the side +of the should be used to determine state (not the ``ON/ONKE`` markings +physically on the component). ``GPIO_0`` is channel 2 on the switch, while +``GPIO_1`` is channel 1. + ++ (QSPI) Flash: 00 ``??`` ++ SD: 01 ``??`` ++ EMMC: 10 ``??`` ++ UART: 11 ``??`` + +Preparing the SD-Card +~~~~~~~~~~~~~~~~~~~~~ + +The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the +partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free +to choose any partition number. + +With the default configuration U-Boot SPL loads the U-Boot FIT image +(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2). +When formatting it is recommended to use GUID +BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition. + +The FIT image (u-boot.itb) is a combination of OpenSBI's fw_dynamic.bin, +u-boot-nodtb.bin and the device tree blob. + +Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch) + +.. code-block:: bash + + sudo sgdisk --clear \ + --set-alignment=2 \ + --new=1:4096:8191 --change-name=1:spl --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985\ + --new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172 \ + --new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \ + /dev/sdb + +Copy U-Boot to the SD card + +.. code-block:: bash + + sudo dd if=u-boot-spl.bin.normal.out of=/dev/sdb1 + sudo dd if=u-boot.itb of=/dev/sdb2 + + sudo mount /dev/sdb3 /mnt/ + sudo cp u-boot-spl.bin.normal.out /mnt/ + sudo cp u-boot.itb /mnt/ + sudo cp Image.gz /mnt/ + sudo cp initramfs.cpio.gz /mnt/ + sudo cp jh7110-starfive-visionfive-2.dtb /mnt/ + sudo umount /mnt + +Booting +~~~~~~~ + +Once you plugin the sdcard and power up, you should see the U-Boot prompt. + +MAC address issues +~~~~~~~~~~~~~~~~~~ + +The Star64 does not currently ship with unique serial numbers per-device. +Devices tested (all 4GiB RAM) have the same serial number of +``STAR64V1-2310-D004E000-00000005`` and the mac addresses of +``6c:cf:39:00:75:61`` (lower) and ``6c:cf:39:00:75:62`` (upper) port will be +assigned. Shipped models also have the EEPROM set as write protected, so it +cannot be changed using ``mac`` commands. + +The MAC addresses may be "set" as follows by writing as a custom config to SPI +(Change the last 3 bytes of MAC addreses as appropriate): + +:: + + env set ethaddr 6c:cf:39:00:75:63 + env set eth1addr 6c:cf:39:00:75:64 + env save + reset -- 2.44.0

1 0

[PATCH 1/2 v3] board: starfive: support Pine64 Star64 board
by H Bell 19 May '24

19 May '24

Similar to the Milk-V Mars, The Star64 board contains few differences to the VisionFive 2 boards, so can be part of the same U-boot build. Signed-off-by: Henry Bell <dmoo_dv(a)protonmail.com> Cc: ycliang(a)andestech.com Cc: heinrich.schuchardt(a)canonical.com --- Changes since v1 - Fix typos on naming - Create pine64_star64 struct to be populated with PHY values once confirmed Changes since v2 - Set delays to 0 - Add missing 10/100/1000 clocks across the two devices - Set all uA values to 2910 --- board/starfive/visionfive2/spl.c | 91 +++++++++++++++++++ .../visionfive2/starfive_visionfive2.c | 4 + 2 files changed, 95 insertions(+) diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index ca61b5be22..ad30c06f99 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -86,6 +86,45 @@ static const struct starfive_vf2_pro starfive_verb[] = { "tx-internal-delay-ps", "0"}, }; +static const struct starfive_vf2_pro star64_pine64[] = { + {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, + {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, + + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-adj-enabled", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-10-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-100-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-1000-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,rx-clk-drv-microamp", "2910"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,rx-data-drv-microamp", "2910"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "rx-internal-delay-ps", "0"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "tx-internal-delay-ps", "0"}, + + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,tx-clk-adj-enabled", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,tx-clk-10-inverted", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,tx-clk-100-inverted", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-1000-inverted", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,rx-clk-drv-microamp", "2910"}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,rx-data-drv-microamp", "2910"}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "rx-internal-delay-ps", "0"}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "tx-internal-delay-ps", "0"}, +}; + void spl_fdt_fixup_mars(void *fdt) { static const char compat[] = "milkv,mars\0starfive,jh7110"; @@ -226,6 +265,56 @@ void spl_fdt_fixup_version_b(void *fdt) } } +void spl_fdt_fixup_star64(void *fdt) +{ + static const char compat[] = "pine64,star64\0starfive,jh7110"; + u32 phandle; + u8 i; + int offset; + int ret; + + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", + "Pine64 Star64"); + + /* gmac0 */ + offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); + phandle = fdt_get_phandle(fdt, offset); + offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); + + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", + JH7110_AONCLK_GMAC0_RMII_RTX); + + /* gmac1 */ + offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); + phandle = fdt_get_phandle(fdt, offset); + offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); + + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", + JH7110_SYSCLK_GMAC1_RMII_RTX); + + for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) { + offset = fdt_path_offset(fdt, star64_pine64[i].path); + + if (star64_pine64[i].value) + ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name, + dectoul(star64_pine64[i].value, NULL)); + else + ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name); + + if (ret) { + pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name); + break; + } + } +} + void spl_perform_fixups(struct spl_image_info *spl_image) { u8 version; @@ -252,6 +341,8 @@ void spl_perform_fixups(struct spl_image_info *spl_image) spl_fdt_fixup_version_b(spl_image->fdt_addr); break; }; + } else if (!strncmp(product_id, "STAR64", 6)) { + spl_fdt_fixup_star64(spl_image->fdt_addr); } else { pr_err("Unknown product %s\n", product_id); }; diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index a86bca533b..1e7c41f01b 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -23,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR; "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" #define FDTFILE_VISIONFIVE2_1_3B \ "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb" +#define FDTFILE_PINE64_STAR64 \ + "starfive/jh7110-pine64-star64.dtb" /* enable U74-mc hart1~hart4 prefetcher */ static void enable_prefetcher(void) @@ -78,6 +80,8 @@ static void set_fdtfile(void) fdtfile = FDTFILE_VISIONFIVE2_1_3B; break; } + } else if (!strncmp(product_id, "STAR64", 6)) { + fdtfile = FDTFILE_PINE64_STAR64; } else { log_err("Unknown product\n"); return; -- 2.44.0

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Pull request efi-2024-07-rc3
by Heinrich Schuchardt 18 May '24

18 May '24

Dear Tom, The following changes since commit 3be9f399e911cfc437a37ac826441f1d96da1c9b: Init virtio before loading ENV from EXT4 or FAT (2024-05-17 13:18:43 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2024-07-rc3 for you to fetch changes up to 41145d93556e3f1d38e5147f4a6fc65610229ab4: doc: process.rst: Document device tree resync rules (2024-05-18 10:36:59 +0200) Gitlab CI reported no issues: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/20753 ---------------------------------------------------------------- Pull request efi-2024-07-rc3 Documentation: * improve netconsole documenation * document device tree resync rules UEFI: * correct handling of signed variable append ---------------------------------------------------------------- Fiona Klute (2): doc: Detailed example for netconsole setup doc: Update netconsole examples, mention stderr Tom Rini (2): doc: process.rst: Use subsubheading for "Phases of the Development Process" doc: process.rst: Document device tree resync rules Weizhao Ouyang (1): efi_loader: Fix EFI_VARIABLE_APPEND_WRITE hash check doc/develop/devicetree/control.rst | 9 +++-- doc/develop/process.rst | 21 ++++++++--- doc/usage/netconsole.rst | 49 +++++++++++++++++++++----- lib/efi_loader/efi_variable.c | 6 ++-- test/py/tests/test_efi_secboot/conftest.py | 10 ++++++ test/py/tests/test_efi_secboot/test_authvar.py | 4 +-- test/py/tests/test_efi_secboot/test_signed.py | 10 +++--- 7 files changed, 83 insertions(+), 26 deletions(-)

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[PATCH 0/3] sandbox: HOST_ARCH improvements
by Jiaxun Yang 18 May '24

18 May '24

Hi all, This series is in respond to a review comment [1] I got from Heinrich. It moved detection of HOST_ARCH to Kconfig, which allows us to control options based on HOST_ARCH. It further improved detection and configuration of SDL2 so that it can work with cross toolchain provided sysroot. Tested on x86_64, cross compile and loosely tesed with qemu-user on riscv64, arm, aarch64. Thanks [1]: https://lore.kernel.org/u-boot/2CD8D385-F0A9-4A1B-827D-1C55CD7E32ED@gmx.de/ Signed-off-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com> --- Jiaxun Yang (3): sandbox: Move HOST_ARCH detection to Kconfig EFI: Make EFI loader depend sandbox HOST_ARCH sandbox: Use pkg-config to detect and config sdl2 Makefile | 27 ++--------------------- arch/sandbox/Kconfig | 25 ++++++++++++++++++++- arch/sandbox/config.mk | 17 +++++++------- arch/sandbox/lib/crt0_sandbox_efi.S | 14 ++++++------ arch/sandbox/lib/reloc_sandbox_efi.c | 14 ++++++------ doc/arch/sandbox/sandbox.rst | 6 ----- include/efi_default_filename.h | 14 ++++++------ include/host_arch.h | 26 ---------------------- lib/efi_loader/Kconfig | 7 ++++-- lib/efi_selftest/efi_selftest_miniapp_exception.c | 6 ++--- 10 files changed, 63 insertions(+), 93 deletions(-) --- base-commit: ad7dce5abd49ef3b5c93da5303e15449c8c162b4 change-id: 20240517-sandbox-hostarch-kconfig-a56a5f80b70d Best regards, -- Jiaxun Yang <jiaxun.yang(a)flygoat.com>

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[PATCH v2 1/2] doc: Detailed example for netconsole setup
by Fiona Klute 18 May '24

18 May '24

This adds details that I would have liked to have readily available, in particular how to activate the network interface before enabling netconsole, and how to integrate netconsole so you can use the U-Boot prompt. Signed-off-by: Fiona Klute <fiona.klute(a)gmx.de> --- Changes in v2: * Include stderr redirection * Use 4 spaces instead of tabs for code block to avoid overflowing lines doc/usage/netconsole.rst | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/doc/usage/netconsole.rst b/doc/usage/netconsole.rst index 2aa3b9ccc5..647f0c220b 100644 --- a/doc/usage/netconsole.rst +++ b/doc/usage/netconsole.rst @@ -18,7 +18,9 @@ broadcast address and port 6666 are used. If it is set to an IP address of 0 (or 0.0.0.0) then no messages are sent to the network. The source / listening port can be configured separately by setting the 'ncinport' environment variable and the destination port can be -configured by setting the 'ncoutport' environment variable. +configured by setting the 'ncoutport' environment variable. Note that +you need to set up the network interface (e.g. using DHCP) before it +can be used for network console. For example, if your server IP is 192.168.1.1, you could use:: @@ -107,3 +109,32 @@ as follows: Note that unlike the U-Boot implementation the Linux netconsole is unidirectional, i. e. you have console output only in Linux. + +Setup via environment +--------------------- + +If persistent environment is enabled in your U-Boot configuration, you +can configure the network console using the environment. For example:: + + => env set autoload no + => env set hostname "u-boot" + => env set bootdelay 5 + => env set nc 'dhcp; env set stdout nc; env set stderr nc; env set stdin nc' + => env set ncip 192.168.1.1 + => env set preboot "${preboot}; run nc;" + => env save + => reset + +``autoload no`` tells the ``dhcp`` command to configure the network +interface without trying to load an image. ``hostname "u-boot"`` sets +the hostname to be sent in DHCP requests, so they are easy to +recognize in the DHCP server log. The command in ``nc`` calls ``dhcp`` +to make sure the network interface is set up before enabling +netconsole. + +Adding ``nc`` to ``preboot`` tells U-Boot to activate netconsole +before trying to find any boot options, so you can interact with it if +desired. + +``env save`` stores the settings persistently, and ``reset`` then +triggers a fresh start that will use the changed settings. -- 2.43.0

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