May 2024 - U-Boot

[PATCH] tools: docker: Drop the git user name and email configuration
by Bin Meng 10 Oct '24

10 Oct '24

Since commit b45ab9ca6621 ("CI: Update to QEMU 8.0.3"), the manual patch applying was removed, hence there is no need to do a git user name and email configuration. Signed-off-by: Bin Meng <bmeng(a)tinylab.org> --- tools/docker/Dockerfile | 3 --- 1 file changed, 3 deletions(-) diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index c4a2596b48..c12ed0fd9b 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -179,9 +179,6 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ RUN git clone https://gitlab.com/qemu-project/qemu.git /tmp/qemu && \ cd /tmp/qemu && \ git checkout v8.0.3 && \ - # config user.name and user.email to make 'git am' happy - git config user.name u-boot && \ - git config user.email u-boot(a)denx.de && \ ./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,m68k-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \ make -j$(nproc) all install && \ rm -rf /tmp/qemu -- 2.34.1

3 3

[PATCH] doc: coreboot: Update stale graphics enabling instructions
by Bin Meng 10 Oct '24

10 Oct '24

From: Bin Meng <bmeng.cn(a)gmail.com> With latest coreboot (e.g.: v4.22.01), the instructions to enable graphics support has changed. Refresh the doc. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- doc/board/coreboot/coreboot.rst | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index f2c6452b5b..8408461617 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -32,10 +32,9 @@ of _x86boot_start (in arch/x86/cpu/start.S). If you want to use ELF as the coreboot payload, change U-Boot configuration to use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. -To enable video you must enable these options in coreboot: +To enable video you must enable CONFIG_GENERIC_LINEAR_FRAMEBUFFER in coreboot: - - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) - - Keep VESA framebuffer + - Devices->Display->Framebuffer mode->Linear "high resolution" framebuffer At present it seems that for Minnowboard Max, coreboot does not pass through the video information correctly (it always says the resolution is 0x0). This @@ -184,9 +183,9 @@ boot as a coreboot payload, based on a known-good build of coreboot. To update the `coreboot.rom` file which is used: -#. Build coreboot with `CONFIG_LINEAR_FRAMEBUFFER=y`. If using `make menuconfig` - this is under - `Devices ->Display->Framebuffer mode->Linear "high resolution" framebuffer`. +#. Build coreboot with `CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y`. If using + `make menuconfig`, this is under + `Devices->Display->Framebuffer mode->Linear "high resolution" framebuffer`. #. Compress the resulting `coreboot.rom`:: -- 2.34.1

2 1

[PATCH 0/4] spi: Various Kconfig fixes
by John Watts 10 Oct '24

10 Oct '24

I'm doing some SPI work so I tried to compile all the drivers on my sunxi board to try and avoid some regressions. This failed, so here are some fixes for this. Signed-off-by: John Watts <contact(a)jookia.org> --- John Watts (4): spi: Kconfig: Add some required arch depends for drivers spi: mtk_spim: Remove completion.h include spi: ca_sflash: Add missing dm include spi: rockchip_sfc: Select BOUNCE_BUFFER drivers/spi/Kconfig | 17 +++++++++++++++++ drivers/spi/ca_sflash.c | 1 + drivers/spi/mtk_spim.c | 1 - 3 files changed, 18 insertions(+), 1 deletion(-) --- base-commit: 174ac987655c888017c82df1883c0c2ea0dc2495 change-id: 20240427-spikconfig-2417bbcf4c14 Best regards, -- John Watts <contact(a)jookia.org>

2 6

[PATCH] mtd: spi-nor: scale up timeout for full-chip erase
by Venkatesh Yadav Abbarapu 20 Sep '24

20 Sep '24

This patch fixes timeout issues seen on large NOR flash. For full-chip erase, where we use the SPINOR_OP_CHIP_ERASE (0xc7) opcode. Use a different timeout for full-chip erase than for other commands. [Ported from Linux kernel commit 09b6a377687b ("mtd: spi-nor: scale up timeout for full-chip erase") ] Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/mtd/spi/spi-nor-core.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9a1801ba93..171c68787c 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -45,6 +45,12 @@ #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) +/* + * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up + * for larger flash + */ +#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) + #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) struct sfdp_parameter_header { @@ -832,6 +838,20 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor) DEFAULT_READY_WAIT_JIFFIES); } +static int spi_nor_erase_chip_wait_till_ready(struct spi_nor *nor, unsigned long size) +{ + /* + * Scale the timeout linearly with the size of the flash, with + * a minimum calibrated to an old 2MB flash. We could try to + * pull these from CFI/SFDP, but these values should be good + * enough for now. + */ + unsigned long timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, + CHIP_ERASE_2MB_READY_WAIT_JIFFIES * + (unsigned long)(size / SZ_2M)); + return spi_nor_wait_till_ready_with_timeout(nor, timeout); +} + #ifdef CONFIG_SPI_FLASH_BAR /* * This "clean_bar" is necessary in a situation when one was accessing @@ -966,7 +986,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor = mtd_to_spi_nor(mtd); bool addr_known = false; - u32 addr, len, rem; + u32 addr, len, rem, max_size; int ret, err; dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, @@ -980,6 +1000,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) addr = instr->addr; len = instr->len; + max_size = instr->len; instr->state = MTD_ERASING; addr_known = true; @@ -1012,7 +1033,13 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) addr += ret; len -= ret; - ret = spi_nor_wait_till_ready(nor); + if (max_size == mtd->size && + !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { + ret = spi_nor_erase_chip_wait_till_ready(nor, mtd->size); + } else { + ret = spi_nor_wait_till_ready(nor); + } + if (ret) goto erase_err; } -- 2.25.1

3 3

[PATCH v4 0/6] rpi5: initial support
by Ivan T. Ivanov 19 Sep '24

19 Sep '24

Hi, These patches are slight update for patches posted earlier here[1]. They are adding basic support for RPi5 and are based on v2 series from Dmitry Malkin[2]. What changed: * Initial memory map now includes whole first 1GB of DRAM. At runtime, the firmware will adjust this size depending on whether an HDMI cable is plugged in or not. If there is HDMI monitor connected it will reserve framebufer memory region and will add simple-framebuffer device into devicetree. * Dynamically calculate bits per pixel in video driver. This works on all prevous RPi's models that I have. * I am dropping PCIe patch for now. I made some progress on porting changes from vendor Linux tree to U-Boot. Unfortunatly testing it is little bit tricky. They are many devices behind PCIe, but more or less all of them requires missing either "reset-controller" or "clock-controller" or "pin-controller" drivers. I was able to probe "cdns,macb" device, but access to ethernet PHY over MDIO bus is stucking. Then I ported "raspberrypi,rp1-adc" driver from vendor Linux tree, but it requires missing clock. And on top of that machine that I used for developing this crashed and I lost my PCIe changes :-|. Anyway. These patches allows me to boot current openSUSE Tumbleweed without modification. I can see serial console log and boot process on HDMI connected monitor. I think these patches should be enough for start. Please consider for inclusion. Thanks, Ivan [1] https://lore.kernel.org/all/20231218210341.30073-1-iivanov@suse.de/ [2] https://lore.kernel.org/all/CAKRNjQ0dsWozGo4n8g58m4cCEk3n=qx1R+L24WBgpo-iP1… Dmitry Malkin (2): rpi5: add initial memory map for bcm2712 rpi5: Use devicetree as alternative way to read IO base addresses Ivan T. Ivanov (4): rpi5: Use devicetree to retrieve board revision bcm2835: Dynamically calculate bytes per pixel parameter mmc: bcmstb: Add support for bcm2712 SD controller configs: rpi_arm64: enable SDHCI BCMSTB driver arch/arm/mach-bcm283x/include/mach/base.h | 5 +- arch/arm/mach-bcm283x/include/mach/mbox.h | 3 +- arch/arm/mach-bcm283x/include/mach/sdhci.h | 3 +- arch/arm/mach-bcm283x/include/mach/timer.h | 3 +- arch/arm/mach-bcm283x/include/mach/wdog.h | 3 +- arch/arm/mach-bcm283x/init.c | 74 ++++++++- board/raspberrypi/rpi/rpi.c | 22 ++- configs/rpi_arm64_defconfig | 1 + drivers/mmc/bcmstb_sdhci.c | 173 ++++++++++++++++++++- drivers/video/bcm2835.c | 18 ++- 10 files changed, 282 insertions(+), 23 deletions(-) -- 2.35.3

5 18

[PATCH 1/2] mtd: spi-nor-core: allow overriding 4-byte OPCODE support
by Robert Marko 12 Sep '24

12 Sep '24

Currently, the only way to indicate 4-byte OPCODE support is by setting the SPI_NOR_4B_OPCODES feature flag for each JEDEC ID in spi_nor_ids[]. However, its becoming increasingly common practice for vendors to reuse the same JEDEC ID for new revisions of current parts. For example Winbond W25Q256FV does not fully support 4-byte OPCODE-s while newer W25Q256JV revision does fully support them but they share the same JEDEC ID thus currently its not possible to advertise support for 4-byte OPCODE-s on W25Q256JV. Luckily for us, there usually is a way to differentiate between parts with the same JEDEC ID by differences in SFDP tables, so in order to be able to apply a fixup after they are parsed lets add a feature flag that we can override. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> --- drivers/mtd/spi/spi-nor-core.c | 6 ++++-- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f86003ca8c..7615ba602f 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3879,7 +3879,7 @@ static int spi_nor_init(struct spi_nor *nor) if (nor->addr_width == 4 && !(nor->info->flags & SPI_NOR_OCTAL_DTR_READ) && (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) && - !(nor->info->flags & SPI_NOR_4B_OPCODES)) { + !(nor->flags & SNOR_F_4B_OPCODES)) { /* * If the RESET# pin isn't hooked up properly, or the system * otherwise doesn't perform a reset command in the boot @@ -4118,6 +4118,8 @@ int spi_nor_scan(struct spi_nor *nor) nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; if (info->flags & USE_CLSR) nor->flags |= SNOR_F_USE_CLSR; + if (info->flags & SPI_NOR_4B_OPCODES) + nor->flags |= SNOR_F_4B_OPCODES; if (info->flags & SPI_NOR_NO_ERASE) mtd->flags |= MTD_NO_ERASE; @@ -4156,7 +4158,7 @@ int spi_nor_scan(struct spi_nor *nor) /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || - info->flags & SPI_NOR_4B_OPCODES) + nor->flags & SNOR_F_4B_OPCODES) spi_nor_set_4byte_opcodes(nor, info); #else /* Configure the BAR - discover bank cmds and read current bank */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d1dbf3eadb..80e56cf308 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -294,6 +294,7 @@ enum spi_nor_option_flags { SNOR_F_BROKEN_RESET = BIT(6), SNOR_F_SOFT_RESET = BIT(7), SNOR_F_IO_MODE_EN_VOLATILE = BIT(8), + SNOR_F_4B_OPCODES = BIT(9), }; struct spi_nor; -- 2.44.0

3 5

[PATCH 1/1] clk: sifive: avoid declaring static variables in includes
by Heinrich Schuchardt 09 Sep '24

09 Sep '24

The existing code is unnecessarily convoluted: Arrays __prci_init_clocks_fu[5|7]40 are initialized with data. In separate includes fu[5|7]40-prci.h the size of the arrays is provided as constants. By moving the structures prci_clk_fu[5|7]40 to the respective code modules we can directly use ARRAY_SIZE() to access the size of the data used for initialization. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- drivers/clk/sifive/fu540-prci.c | 7 ++++++- drivers/clk/sifive/fu540-prci.h | 22 ---------------------- drivers/clk/sifive/fu740-prci.c | 7 ++++++- drivers/clk/sifive/fu740-prci.h | 22 ---------------------- drivers/clk/sifive/sifive-prci.c | 3 +-- drivers/clk/sifive/sifive-prci.h | 4 ++++ 6 files changed, 17 insertions(+), 48 deletions(-) delete mode 100644 drivers/clk/sifive/fu540-prci.h delete mode 100644 drivers/clk/sifive/fu740-prci.h diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index ceb2c6fab0d..e55a26ab8fd 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -58,7 +58,7 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { }; /* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu540[] = { +static struct __prci_clock __prci_init_clocks_fu540[] = { [PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -83,3 +83,8 @@ struct __prci_clock __prci_init_clocks_fu540[] = { .ops = &sifive_fu540_prci_tlclksel_clk_ops, }, }; + +const struct prci_clk_desc prci_clk_fu540 = { + .clks = __prci_init_clocks_fu540, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), +}; diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h deleted file mode 100644 index 113301107da..00000000000 --- a/drivers/clk/sifive/fu540-prci.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Zong Li - * Pragnesh Patel - */ - -#ifndef __SIFIVE_CLK_FU540_PRCI_H -#define __SIFIVE_CLK_FU540_PRCI_H - -#include "sifive-prci.h" - -#define NUM_CLOCK_FU540 4 - -extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; - -static const struct prci_clk_desc prci_clk_fu540 = { - .clks = __prci_init_clocks_fu540, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), -}; - -#endif /* __SIFIVE_CLK_FU540_PRCI_H */ diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 5edc864e4bd..4274b215d2f 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -102,7 +102,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = { }; /* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu740[] = { +static struct __prci_clock __prci_init_clocks_fu740[] = { [FU740_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -156,3 +156,8 @@ struct __prci_clock __prci_init_clocks_fu740[] = { .pwd = &__prci_pcieaux_data, } }; + +const struct prci_clk_desc prci_clk_fu740 = { + .clks = __prci_init_clocks_fu740, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), +}; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h deleted file mode 100644 index b74f0789061..00000000000 --- a/drivers/clk/sifive/fu740-prci.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Zong Li - * Pragnesh Patel - */ - -#ifndef __SIFIVE_CLK_FU740_PRCI_H -#define __SIFIVE_CLK_FU740_PRCI_H - -#include "sifive-prci.h" - -#define NUM_CLOCK_FU740 9 - -extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; - -static const struct prci_clk_desc prci_clk_fu740 = { - .clks = __prci_init_clocks_fu740, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), -}; - -#endif /* __SIFIVE_CLK_FU740_PRCI_H */ diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index c8fb6002907..603a176d06a 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -34,8 +34,7 @@ #include <linux/math64.h> #include <dt-bindings/clock/sifive-fu740-prci.h> -#include "fu540-prci.h" -#include "fu740-prci.h" +#include "sifive-prci.h" /* * Private functions diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 5ce33d61846..b391698081d 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -320,4 +320,8 @@ unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable); +/* Clock driver data */ +extern const struct prci_clk_desc prci_clk_fu540; +extern const struct prci_clk_desc prci_clk_fu740; + #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ -- 2.43.0

3 2

[PATCH] video: Add parentheses around VNBYTES() macro
by Dan Carpenter 06 Sep '24

06 Sep '24

The VNBYTES() macro needs to have parentheses to prevent some (harmless) macro expansion bugs. The VNBYTES() macro is used like this: VID_TO_PIXEL(x) * VNBYTES(vid_priv->bpix) The * operation is done before the / operation. It still ends up with the same results, but it's not ideal. Signed-off-by: Dan Carpenter <dan.carpenter(a)linaro.org> --- include/video.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/video.h b/include/video.h index 9729fa348aa5..b364bf91825f 100644 --- a/include/video.h +++ b/include/video.h @@ -58,7 +58,7 @@ enum video_log2_bpp { * Convert enum video_log2_bpp to bytes and bits. Note we omit the outer * brackets to allow multiplication by fractional pixels. */ -#define VNBYTES(bpix) (1 << (bpix)) / 8 +#define VNBYTES(bpix) ((1 << (bpix)) / 8) #define VNBITS(bpix) (1 << (bpix)) -- 2.39.2

4 6

[PATCH] power: regulator: tps6287x: Add driver for TPS6287x step down convertors
by Keerthy 06 Sep '24

06 Sep '24

Add driver for TPS6287x step down convertors Data sheet: https://www.ti.com/lit/ds/slvsgc5a/slvsgc5a.pdf Signed-off-by: Keerthy <j-keerthy(a)ti.com> --- drivers/power/regulator/Kconfig | 18 ++ drivers/power/regulator/Makefile | 1 + drivers/power/regulator/tps6287x_regulator.c | 172 +++++++++++++++++++ 3 files changed, 191 insertions(+) create mode 100644 drivers/power/regulator/tps6287x_regulator.c diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 102ec7bc5f..db4b40c35e 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -375,6 +375,15 @@ config DM_REGULATOR_TPS80031 features for TPS80031/TPS80032 PMICs. The driver implements get/set api for: value and enable. +config DM_REGULATOR_TPS6287X + bool "Enable driver for TPS6287x Power Regulator" + depends on DM_REGULATOR + help + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. + config DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators" depends on DM_REGULATOR && PMIC_STPMIC1 @@ -394,6 +403,15 @@ config DM_REGULATOR_ANATOP regulators. It is recommended that this option be enabled on i.MX6 platform. +config SPL_DM_REGULATOR_TPS6287X + bool "Enable driver for TPS6287x Power Regulator" + depends on SPL_DM_REGULATOR + help + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. + config SPL_DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators in SPL" depends on SPL_DM_REGULATOR && PMIC_STPMIC1 diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index f79932d833..6335e5566d 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS65911) += tps65911_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS6287X) += tps6287x_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS80031) += tps80031_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o diff --git a/drivers/power/regulator/tps6287x_regulator.c b/drivers/power/regulator/tps6287x_regulator.c new file mode 100644 index 0000000000..6d18571919 --- /dev/null +++ b/drivers/power/regulator/tps6287x_regulator.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + * Keerthy <j-keerthy(a)ti.com> + */ + +#include <dm.h> +#include <i2c.h> +#include <dm/device_compat.h> +#include <power/regulator.h> + +#define TPS6287X_REG_VSET 0x0 +#define TPS6287X_REG_CONTROL1 0x1 +#define TPS6287X_REG_CONTROL2 0x2 +#define TPS6287X_REG_CONTROL3 0x3 +#define TPS6287X_REG_STATUS 0x4 +#define TPS6287X_REG_VSET_VSET_MASK 0xff +#define TPS6287X_REG_CONTROL2_VRANGE_MASK 0xc + +struct tps6287x_regulator_config { + u32 vmin; + u32 vmax; +}; + +struct tps6287x_regulator_pdata { + u8 vsel_offset; + struct udevice *i2c; + struct tps6287x_regulator_config *config; +}; + +static struct tps6287x_regulator_config tps6287x_data = { + .vmin = 400000, + .vmax = 3350000, +}; + +static int tps6287x_regulator_set_value(struct udevice *dev, int uV) +{ + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + u8 regval, vset; + int ret; + + if (uV < pdata->config->vmin || uV > pdata->config->vmax) + return -EINVAL; + /* + * Based on the value of VRANGE bit field of CONTROL2 reg the range + * varies. + */ + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, &regval, 1); + if (ret) { + dev_err(dev, "CTRL2 reg read failed: %d\n", ret); + return ret; + } + + regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK; + regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1; + + /* + * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV + * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV + * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV + * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV + */ + switch (regval) { + case 0: + vset = (uV - 400000) / 1250; + break; + case 1: + vset = (uV - 400000) / 2500; + break; + case 2: + vset = (uV - 400000) / 5000; + break; + case 3: + vset = (uV - 800000) / 10000; + break; + default: + pr_err("%s: invalid regval %d\n", dev->name, regval); + return -EINVAL; + } + + return dm_i2c_write(pdata->i2c, TPS6287X_REG_VSET, &vset, 1); +} + +static int tps6287x_regulator_get_value(struct udevice *dev) +{ + u8 regval, vset; + int uV; + int ret; + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + + /* + * Based on the value of VRANGE bit field of CONTROL2 reg the range + * varies. + */ + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, &regval, 1); + if (ret) { + dev_err(dev, "i2c read failed: %d\n", ret); + return ret; + } + + regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK; + regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1; + + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_VSET, &vset, 1); + if (ret) { + dev_err(dev, "i2c VSET read failed: %d\n", ret); + return ret; + } + + /* + * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV + * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV + * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV + * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV + */ + switch (regval) { + case 0: + uV = 400000 + vset * 1250; + break; + case 1: + uV = 400000 + vset * 2500; + break; + case 2: + uV = 400000 + vset * 5000; + break; + case 3: + uV = 800000 + vset * 10000; + break; + default: + pr_err("%s: invalid regval %d\n", dev->name, regval); + return -EINVAL; + } + + return uV; +} + +static int tps6287x_regulator_probe(struct udevice *dev) +{ + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + int ret, slave_id; + + pdata->config = (void *)dev_get_driver_data(dev); + + slave_id = devfdt_get_addr_index(dev, 0); + + ret = i2c_get_chip(dev->parent, slave_id, 1, &pdata->i2c); + if (ret) { + dev_err(dev, "i2c dev get failed.\n"); + return ret; + } + + return 0; +} + +static const struct dm_regulator_ops tps6287x_regulator_ops = { + .get_value = tps6287x_regulator_get_value, + .set_value = tps6287x_regulator_set_value, +}; + +static const struct udevice_id tps6287x_regulator_ids[] = { + { .compatible = "ti,tps62873", .data = (ulong)&tps6287x_data }, + { }, +}; + +U_BOOT_DRIVER(tps6287x_regulator) = { + .name = "tps6287x_regulator", + .id = UCLASS_REGULATOR, + .ops = &tps6287x_regulator_ops, + .of_match = tps6287x_regulator_ids, + .plat_auto = sizeof(struct tps6287x_regulator_pdata), + .probe = tps6287x_regulator_probe, +}; -- 2.17.1

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[PATCH] power: regulator: Fix error code in regulator_list_autoset()
by Dan Carpenter 06 Sep '24

06 Sep '24

This condition has a bitwise & vs logical && typo so it only preserves odd number error codes. Fixes: 3b880757abca ("dm: regulator: uclass driver code cleanup") Signed-off-by: Dan Carpenter <dan.carpenter(a)linaro.org> --- drivers/power/regulator/regulator-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 77d101f262e2..de2bb3b1cd88 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -390,7 +390,7 @@ int regulator_list_autoset(const char *list_platname[], ret = regulator_autoset_by_name(list_platname[i], &dev); if (ret != -EMEDIUMTYPE && verbose) regulator_show(dev, ret); - if (ret & !error) + if (ret && !error) error = ret; if (list_devp) -- 2.43.0

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