March 2024 - U-Boot

[PATCH] power: regulator: Fix error code in regulator_list_autoset()
by Dan Carpenter 06 Sep '24

06 Sep '24

This condition has a bitwise & vs logical && typo so it only preserves odd number error codes. Fixes: 3b880757abca ("dm: regulator: uclass driver code cleanup") Signed-off-by: Dan Carpenter <dan.carpenter(a)linaro.org> --- drivers/power/regulator/regulator-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 77d101f262e2..de2bb3b1cd88 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -390,7 +390,7 @@ int regulator_list_autoset(const char *list_platname[], ret = regulator_autoset_by_name(list_platname[i], &dev); if (ret != -EMEDIUMTYPE && verbose) regulator_show(dev, ret); - if (ret & !error) + if (ret && !error) error = ret; if (list_devp) -- 2.43.0

3 2

[PATCH v2] mmc: sdhci-cadence: Add support for Cadence sdmmc v6
by Kuan Lim Lee 06 Sep '24

06 Sep '24

Cadence SDMMC v6 controller has a lot of changes on initialize compared to v4 controller. PHY is needed by v6 controller. Signed-off-by: Kuan Lim Lee <kuanlim.lee(a)starfivetech.com> Co-developed-by: Alex Soo <yuklin.soo(a)starfivetech.com> Signed-off-by: Wei Liang Lim <weiliang.lim(a)starfivetech.com> --- Changes in v2 - Rename file sdhci-cadence6-phy.c to sdhci-cadence6.c - Remove CONFIG_MMC_SDHCI_CADENCE_V6 - Rewrite code of v6 configuration part - Add sdhci_cdns6_phy_init() function --- drivers/mmc/Makefile | 1 + drivers/mmc/sdhci-cadence.c | 63 ++------ drivers/mmc/sdhci-cadence.h | 69 ++++++++ drivers/mmc/sdhci-cadence6.c | 294 +++++++++++++++++++++++++++++++++++ 4 files changed, 376 insertions(+), 51 deletions(-) create mode 100644 drivers/mmc/sdhci-cadence.h create mode 100644 drivers/mmc/sdhci-cadence6.c diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 2c65c4765a..136f06600a 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o +obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence6.o obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 327a05ad11..a5533af045 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -17,56 +17,7 @@ #include <linux/libfdt.h> #include <mmc.h> #include <sdhci.h> - -/* HRS - Host Register Set (specific to Cadence) */ -#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ -#define SDHCI_CDNS_HRS04_ACK BIT(26) -#define SDHCI_CDNS_HRS04_RD BIT(25) -#define SDHCI_CDNS_HRS04_WR BIT(24) -#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16) -#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8) -#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0) - -#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ -#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) -#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8) -#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0) -#define SDHCI_CDNS_HRS06_MODE_SD 0x0 -#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 -#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 -#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 -#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 -#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 - -/* SRS - Slot Register Set (SDHCI-compatible) */ -#define SDHCI_CDNS_SRS_BASE 0x200 - -/* PHY */ -#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 -#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 -#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 -#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 -#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 -#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 -#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 -#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 -#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 -#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b -#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c -#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d - -/* - * The tuned val register is 6 bit-wide, but not the whole of the range is - * available. The range 0-42 seems to be available (then 43 wraps around to 0) - * but I am not quite sure if it is official. Use only 0 to 39 for safety. - */ -#define SDHCI_CDNS_MAX_TUNING_LOOP 40 - -struct sdhci_cdns_plat { - struct mmc_config cfg; - struct mmc mmc; - void __iomem *hrs_addr; -}; +#include "sdhci-cadence.h" struct sdhci_cdns_phy_cfg { const char *property; @@ -163,6 +114,9 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host *host) tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06); + + if (device_is_compatible(mmc->dev, "cdns,sd6hc")) + sdhci_cdns6_phy_adj(mmc->dev, plat, mode); } static const struct sdhci_ops sdhci_cdns_ops = { @@ -176,6 +130,9 @@ static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, u32 tmp; int i, ret; + if (device_is_compatible(plat->mmc.dev, "cdns,sd6hc")) + return sdhci_cdns6_set_tune_val(plat, val); + if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val))) return -EINVAL; @@ -282,7 +239,10 @@ static int sdhci_cdns_probe(struct udevice *dev) if (ret) return ret; - ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev)); + if (device_is_compatible(dev, "cdns,sd6hc")) + ret = sdhci_cdns6_phy_init(dev, plat); + else + ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev)); if (ret) return ret; @@ -301,6 +261,7 @@ static int sdhci_cdns_probe(struct udevice *dev) static const struct udevice_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc" }, { .compatible = "cdns,sd4hc" }, + { .compatible = "cdns,sd6hc" }, { /* sentinel */ } }; diff --git a/drivers/mmc/sdhci-cadence.h b/drivers/mmc/sdhci-cadence.h new file mode 100644 index 0000000000..c20efd899a --- /dev/null +++ b/drivers/mmc/sdhci-cadence.h @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> + */ + +#ifndef SDHCI_CADENCE_H_ +#define SDHCI_CADENCE_H_ + +/* HRS - Host Register Set (specific to Cadence) */ +/* PHY access port */ +#define SDHCI_CDNS_HRS04 0x10 +/* Cadence V4 HRS04 Description*/ +#define SDHCI_CDNS_HRS04_ACK BIT(26) +#define SDHCI_CDNS_HRS04_RD BIT(25) +#define SDHCI_CDNS_HRS04_WR BIT(24) +#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16) +#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8) +#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0) + +#define SDHCI_CDNS_HRS05 0x14 + +/* eMMC control */ +#define SDHCI_CDNS_HRS06 0x18 +#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) +#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8) +#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0) +#define SDHCI_CDNS_HRS06_MODE_SD 0x0 +#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 +#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 + +/* SRS - Slot Register Set (SDHCI-compatible) */ +#define SDHCI_CDNS_SRS_BASE 0x200 + +/* Cadence V4 PHY Setting*/ +#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 +#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 +#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 +#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 +#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 +#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 +#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b +#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c +#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d + +/* + * The tuned val register is 6 bit-wide, but not the whole of the range is + * available. The range 0-42 seems to be available (then 43 wraps around to 0) + * but I am not quite sure if it is official. Use only 0 to 39 for safety. + */ +#define SDHCI_CDNS_MAX_TUNING_LOOP 40 + +struct sdhci_cdns_plat { + struct mmc_config cfg; + struct mmc mmc; + void __iomem *hrs_addr; +}; + +int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode); +int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat); +int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val); + +#endif diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c new file mode 100644 index 0000000000..ea0857e655 --- /dev/null +++ b/drivers/mmc/sdhci-cadence6.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-or-platform_driver +/* + * Copyright (C) 2023 Starfive. + * Author: Kuan Lim Lee <kuanlim.lee(a)starfivetech.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/global_data.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/bug.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/sizes.h> +#include <linux/libfdt.h> +#include <mmc.h> +#include <sdhci.h> +#include "sdhci-cadence.h" + +/* IO Delay Information */ +#define SDHCI_CDNS_HRS07 0X1C +#define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16) +#define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0) + +/* PHY Control and Status */ +#define SDHCI_CDNS_HRS09 0x24 +#define SDHCI_CDNS_HRS09_RDDATA_EN BIT(16) +#define SDHCI_CDNS_HRS09_RDCMD_EN BIT(15) +#define SDHCI_CDNS_HRS09_EXTENDED_WR_MODE BIT(3) +#define SDHCI_CDNS_HRS09_EXTENDED_RD_MODE BIT(2) +#define SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE BIT(1) +#define SDHCI_CDNS_HRS09_PHY_SW_RESET BIT(0) + +/* SDCLK adjustment */ +#define SDHCI_CDNS_HRS10 0x28 +#define SDHCI_CDNS_HRS10_HCSDCLKADJ GENMASK(19, 16) + +/* CMD/DAT output delay */ +#define SDHCI_CDNS_HRS16 0x40 + +/* PHY Special Function Registers */ +/* register to control the DQ related timing */ +#define PHY_DQ_TIMING_REG_ADDR 0x2000 + +/* register to control the DQS related timing */ +#define PHY_DQS_TIMING_REG_ADDR 0x2004 + +/* register to control the gate and loopback control related timing */ +#define PHY_GATE_LPBK_CTRL_REG_ADDR 0x2008 + +/* register to control the Master DLL logic */ +#define PHY_DLL_MASTER_CTRL_REG_ADDR 0x200C + +/* register to control the Slave DLL logic */ +#define PHY_DLL_SLAVE_CTRL_REG_ADDR 0x2010 +#define PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY GENMASK(31, 24) +#define PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY GENMASK(7, 0) + +#define SDHCI_CDNS6_PHY_CFG_NUM 4 +#define SDHCI_CDNS6_CTRL_CFG_NUM 4 + +struct sdhci_cdns6_phy_cfg { + const char *property; + u32 val; +}; + +struct sdhci_cdns6_ctrl_cfg { + const char *property; + u32 val; +}; + +static struct sdhci_cdns6_phy_cfg sd_ds_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-sd-ds", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-sd-ds", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-sd-ds", 0x00000000, }, + { "cdns,phy-dq-timing-delay-sd-ds", 0x00000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_sdr_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-semmc-sdr", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-sdr", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-sdr", 0x00000000, }, + { "cdns,phy-dq-timing-delay-emmc-sdr", 0x00000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_ddr_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-emmc-ddr", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-ddr", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-ddr", 0x00000000, }, + { "cdns,phy-dq-timing-delay-emmc-ddr", 0x10000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_hs200_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-emmc-hs200", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-hs200", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-hs200", 0x00DADA00, }, + { "cdns,phy-dq-timing-delay-emmc-hs200", 0x00000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_hs400_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-emmc-hs400", 0x00280004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-hs400", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-hs400", 0x00DAD800, }, + { "cdns,phy-dq-timing-delay-emmc-hs400", 0x00000001, }, +}; + +static struct sdhci_cdns6_ctrl_cfg sd_ds_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-sd-ds", 0x0001800C, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-sd-ds", 0x00020000, }, + { "cdns,ctrl-hrs16-slave-ctrl-sd-ds", 0x00000000, }, + { "cdns,ctrl-hrs07-timing-delay-sd-ds", 0x00080000, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_sdr_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-sdr", 0x0001800C, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-sdr", 0x00030000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-sdr", 0x00000000, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-sdr", 0x00080000, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_ddr_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-ddr", 0x0001800C, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-ddr", 0x00020000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-ddr", 0x11000001, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-ddr", 0x00090001, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_hs200_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-hs200", 0x00018000, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-hs200", 0x00080000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-hs200", 0x00000000, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-hs200", 0x00090000, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_hs400_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-hs400", 0x00018000, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-hs400", 0x00080000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-hs400", 0x11000000, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-hs400", 0x00080000, }, +}; + +static u32 sdhci_cdns6_read_phy_reg(struct sdhci_cdns_plat *plat, u32 addr) +{ + writel(addr, plat->hrs_addr + SDHCI_CDNS_HRS04); + return readl(plat->hrs_addr + SDHCI_CDNS_HRS05); +} + +static void sdhci_cdns6_write_phy_reg(struct sdhci_cdns_plat *plat, u32 addr, u32 val) +{ + writel(addr, plat->hrs_addr + SDHCI_CDNS_HRS04); + writel(val, plat->hrs_addr + SDHCI_CDNS_HRS05); +} + +static int sdhci_cdns6_reset_phy_dll(struct sdhci_cdns_plat *plat, bool reset) +{ + void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS09; + u32 tmp; + int ret; + + tmp = readl(reg); + tmp &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET; + + /* Switch On DLL Reset */ + if (reset) + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, 0); + else + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, 1); + + writel(tmp, reg); + + /* After reset, wait until HRS09.PHY_INIT_COMPLETE is set to 1 within 3000us*/ + if (!reset) { + ret = readl_poll_timeout(reg, tmp, (tmp & SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE), + 3000); + } + + return ret; +} + +int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode) +{ + DECLARE_GLOBAL_DATA_PTR; + struct sdhci_cdns6_phy_cfg *sdhci_cdns6_phy_cfgs; + struct sdhci_cdns6_ctrl_cfg *sdhci_cdns6_ctrl_cfgs; + const fdt32_t *prop; + u32 tmp; + int i, ret; + + switch (mode) { + case SDHCI_CDNS_HRS06_MODE_SD: + sdhci_cdns6_phy_cfgs = sd_ds_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = sd_ds_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_SDR: + sdhci_cdns6_phy_cfgs = emmc_sdr_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_sdr_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_DDR: + sdhci_cdns6_phy_cfgs = emmc_ddr_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_ddr_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_HS200: + sdhci_cdns6_phy_cfgs = emmc_hs200_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_hs200_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_HS400: + sdhci_cdns6_phy_cfgs = emmc_hs400_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_hs400_ctrl_cfgs; + break; + default: + return -EINVAL; + } + + for (i = 0; i < SDHCI_CDNS6_PHY_CFG_NUM; i++) { + prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + sdhci_cdns6_phy_cfgs[i].property, NULL); + if (prop) + sdhci_cdns6_phy_cfgs[i].val = *prop; + } + + for (i = 0; i < SDHCI_CDNS6_CTRL_CFG_NUM; i++) { + prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + sdhci_cdns6_ctrl_cfgs[i].property, NULL); + if (prop) + sdhci_cdns6_ctrl_cfgs[i].val = *prop; + } + + /* Switch On the DLL Reset */ + sdhci_cdns6_reset_phy_dll(plat, true); + + sdhci_cdns6_write_phy_reg(plat, PHY_DQS_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[0].val); + sdhci_cdns6_write_phy_reg(plat, PHY_GATE_LPBK_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[1].val); + sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[2].val); + + /* Switch Off the DLL Reset */ + ret = sdhci_cdns6_reset_phy_dll(plat, false); + if (ret) { + printf("sdhci_cdns6_reset_phy is not completed\n"); + return ret; + } + + /* Set PHY DQ TIMING control register */ + sdhci_cdns6_write_phy_reg(plat, PHY_DQ_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[3].val); + + /* Set HRS09 register */ + tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS09); + tmp &= ~(SDHCI_CDNS_HRS09_EXTENDED_WR_MODE | + SDHCI_CDNS_HRS09_EXTENDED_RD_MODE | + SDHCI_CDNS_HRS09_RDDATA_EN | + SDHCI_CDNS_HRS09_RDCMD_EN); + tmp |= sdhci_cdns6_ctrl_cfgs[0].val; + writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS09); + + /* Set HRS10 register */ + tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS10); + tmp &= ~SDHCI_CDNS_HRS10_HCSDCLKADJ; + tmp |= sdhci_cdns6_ctrl_cfgs[1].val; + writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS10); + + /* Set HRS16 register */ + writel(sdhci_cdns6_ctrl_cfgs[2].val, plat->hrs_addr + SDHCI_CDNS_HRS16); + + /* Set HRS07 register */ + writel(sdhci_cdns6_ctrl_cfgs[3].val, plat->hrs_addr + SDHCI_CDNS_HRS07); + + return 0; +} + +int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat) +{ + return sdhci_cdns6_phy_adj(dev, plat, SDHCI_CDNS_HRS06_MODE_SD); +} + +int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val) +{ + u32 tmp, tuneval; + + tuneval = (val * 256) / SDHCI_CDNS_MAX_TUNING_LOOP; + + tmp = sdhci_cdns6_read_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR); + tmp &= ~(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY | + PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY); + tmp |= FIELD_PREP(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY, tuneval) | + FIELD_PREP(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY, tuneval); + sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, tmp); + + return 0; +} -- 2.34.1

3 2

[PATCH v4] mmc: Poll CD in case cyclic framework is enabled
by Marek Vasut 05 Sep '24

05 Sep '24

In case the cyclic framework is enabled, poll the card detect of already initialized cards and deinitialize them in case they are removed. Since the card initialization is a longer process and card initialization is done on first access to an uninitialized card anyway, avoid initializing newly detected uninitialized cards in the cyclic callback. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> --- V2: Move the cyclic registration/unregistration into mmc init/deinit V3: Replace if (CONFIG_IS_ENABLED(CYCLIC)...) with #if as the former does not work with structure members V4: Stuff the code with CONFIG_IS_ENABLED() variants to avoid #ifdefs --- drivers/mmc/mmc.c | 32 ++++++++++++++++++++++++++++++++ include/mmc.h | 3 +++ 2 files changed, 35 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index eb5010c1465..e90ffd5dcd1 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2985,6 +2985,20 @@ static int mmc_complete_init(struct mmc *mmc) return err; } +static void __maybe_unused mmc_cyclic_cd_poll(void *ctx) +{ + struct mmc *m = ctx; + + if (!m->has_init) + return; + + if (mmc_getcd(m)) + return; + + mmc_deinit(m); + m->has_init = 0; +} + int mmc_init(struct mmc *mmc) { int err = 0; @@ -3007,6 +3021,19 @@ int mmc_init(struct mmc *mmc) if (err) pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start)); + if (CONFIG_IS_ENABLED(CYCLIC, (!mmc->cyclic), (NULL))) { + /* Register cyclic function for card detect polling */ + CONFIG_IS_ENABLED(CYCLIC, + (mmc->cyclic = cyclic_register(mmc_cyclic_cd_poll, + 100 * 1000, + mmc->cfg->name, mmc))); + if (CONFIG_IS_ENABLED(CYCLIC, (!mmc->cyclic), (NULL))) { + printf("Failed to register %s CD poll function\n", + mmc->cfg->name); + err = -EINVAL; + } + } + return err; } @@ -3014,6 +3041,11 @@ int mmc_deinit(struct mmc *mmc) { u32 caps_filtered; + if (CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic), (NULL))) { + cyclic_unregister(CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic), NULL)); + CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic = NULL)); + } + if (!CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) && !CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) && !CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)) diff --git a/include/mmc.h b/include/mmc.h index 1022db3ffa7..706566fa1ad 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -14,6 +14,7 @@ #include <linux/sizes.h> #include <linux/compiler.h> #include <linux/dma-direction.h> +#include <cyclic.h> #include <part.h> struct bd_info; @@ -739,6 +740,8 @@ struct mmc { u8 hs400_tuning; enum bus_mode user_speed_mode; /* input speed mode from user */ + + CONFIG_IS_ENABLED(CYCLIC, (struct cyclic_info *cyclic)); }; #if CONFIG_IS_ENABLED(DM_MMC) -- 2.43.0

3 6

[PATCH 00/14] event: Replace some more init hooks
by Simon Glass 07 Aug '24

07 Aug '24

This series replaces some more of the init hooks in board_f.c and board_r.c with events. Notably it converts last_state_init() over. It also provides a 'simple' event spy, which takes no arguments. It turns out that this is quite a common case, so it is worth optimising for this, to reduce code size, before events become too commonly used. Finally, it introduces a way of emitting an event in an initcall, instead of calling a function. This is likely to be used at least as often as the functions, as we convert more of these initcalls. As part of this, the initcall code is brought back into a C file. Somehow the compiler has changed or something else, so that this does not confer any benefits now. For boards with EVENT enabled, this unfortunately results in small growth, e.g. for firefly: aarch64: (for 1/1 boards) all +114.0 data +16.0 rodata +22.0 text +76.0 arm: (for 1/1 boards) all +82.0 rodata +18.0 text +64.0 For boards without EVENT enabled the growth is smaller, e.g. nokia_rx51: arm: (for 1/1 boards) all +32.0 data +8.0 rodata -8.0 text +32.0 I cannot find a good way to avoid the latter, other than macro magic with an embedded comma (to completely remove an event entry), which seems nasty. Simon Glass (14): event: Support a simple spy record Revert "initcall: Move to inline function" initcall: Factor out reloc_off calculation initcall: Adjust the loop logic initcall: Adjust the failure message and return value event: Export event_type_name() initcall: Support emitting events initcall: Support manual relocation event: Convert existing spy records to simple event: Rename EVENT_SPY to EVENT_SPY_FULL event: Update documentation for simple spy x86: Convert arch_fsp_init() to use events freescale: Drop call to init_func_vid() in the init sequence event: Use an event to replace last_stage_init() arch/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/spl.c | 5 + arch/arm/mach-imx/imx8/cpu.c | 4 +- arch/arm/mach-imx/imx8m/soc.c | 4 +- arch/arm/mach-imx/imx8ulp/soc.c | 7 +- arch/arm/mach-imx/imx9/soc.c | 4 +- arch/arm/mach-omap2/am33xx/board.c | 4 +- arch/arm/mach-omap2/hwinit-common.c | 12 +- arch/mips/mach-mtmips/cpu.c | 6 +- arch/mips/mach-pic32/cpu.c | 12 +- arch/nios2/cpu/cpu.c | 4 +- arch/riscv/cpu/cpu.c | 4 +- arch/riscv/include/asm/system.h | 2 +- arch/riscv/lib/spl.c | 2 +- arch/sandbox/cpu/start.c | 7 +- arch/x86/cpu/baytrail/cpu.c | 4 +- arch/x86/cpu/broadwell/cpu.c | 4 +- arch/x86/cpu/coreboot/coreboot.c | 7 +- arch/x86/cpu/cpu.c | 10 +- arch/x86/cpu/efi/payload.c | 4 +- arch/x86/cpu/ivybridge/cpu.c | 4 +- arch/x86/cpu/quark/quark.c | 30 +++-- arch/x86/lib/fsp1/fsp_common.c | 1 + arch/x86/lib/fsp2/fsp_common.c | 5 - arch/x86/lib/fsp2/fsp_init.c | 4 +- board/CZ.NIC/turris_mox/turris_mox.c | 4 +- board/Marvell/mvebu_armada-37xx/board.c | 5 +- board/Marvell/octeon_nic23/board.c | 4 +- board/Marvell/octeontx2/board.c | 4 +- board/cortina/presidio-asic/presidio.c | 4 +- board/emulation/qemu-ppce500/qemu-ppce500.c | 4 +- board/freescale/ls1088a/ls1088a.c | 3 +- board/freescale/lx2160a/lx2160a.c | 2 + board/gdsys/a38x/controlcenterdc.c | 31 +++-- board/gdsys/mpc8308/gazerbeam.c | 4 +- board/ge/bx50v3/bx50v3.c | 4 +- board/google/chromebook_coral/coral.c | 4 +- board/keymile/km83xx/km83xx.c | 4 +- board/keymile/kmcent2/kmcent2.c | 7 +- .../keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 10 +- board/phytium/durian/durian.c | 4 +- board/phytium/pomelo/pomelo.c | 4 +- board/starfive/visionfive2/spl.c | 2 +- boot/vbe_request.c | 2 +- boot/vbe_simple_os.c | 2 +- common/Kconfig | 1 + common/board_f.c | 21 +--- common/board_r.c | 20 ++-- common/event.c | 13 ++- configs/bayleybay_defconfig | 1 - configs/cherryhill_defconfig | 1 - configs/chromebook_coral_defconfig | 1 - configs/chromebook_link64_defconfig | 1 - configs/chromebook_link_defconfig | 1 - configs/chromebook_samus_defconfig | 1 - configs/chromebook_samus_tpl_defconfig | 1 - configs/chromebox_panther_defconfig | 1 - ...-qeval20-qa3-e3845-internal-uart_defconfig | 1 - configs/conga-qeval20-qa3-e3845_defconfig | 1 - configs/coreboot64_defconfig | 1 - configs/coreboot_defconfig | 1 - configs/cougarcanyon2_defconfig | 1 - configs/crownbay_defconfig | 1 - configs/dfi-bt700-q7x-151_defconfig | 1 - configs/edison_defconfig | 1 - configs/efi-x86_app32_defconfig | 1 - configs/efi-x86_app64_defconfig | 1 - configs/efi-x86_payload32_defconfig | 1 - configs/efi-x86_payload64_defconfig | 1 - configs/galileo_defconfig | 1 - configs/minnowmax_defconfig | 1 - configs/qemu-x86_64_defconfig | 3 +- configs/qemu-x86_defconfig | 1 - configs/som-db5800-som-6867_defconfig | 1 - ...able-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 - .../theadorable-x86-conga-qa3-e3845_defconfig | 1 - configs/theadorable-x86-dfi-bt700_defconfig | 1 - doc/develop/event.rst | 23 +++- drivers/cpu/microblaze_cpu.c | 4 +- include/event.h | 72 +++++++++++- include/init.h | 15 --- include/initcall.h | 72 +++++------- lib/Makefile | 1 + lib/fwu_updates/fwu.c | 4 +- lib/initcall.c | 109 ++++++++++++++++++ scripts/event_dump.py | 12 +- test/common/event.c | 22 ++++ test/py/tests/test_event_dump.py | 3 +- test/py/tests/test_trace.py | 11 +- 89 files changed, 431 insertions(+), 261 deletions(-) create mode 100644 lib/initcall.c -- 2.42.0.rc1.204.g551eb34607-goog

4 19

[PATCH v4] board: phytec: phycore-imx93: Add phyBOARD-Segin-i.MX93 support
by Mathieu Othacehe 03 Aug '24

03 Aug '24

Add initial support for the PHYTEC phyBOARD-Segin-i.MX93 board based on the PHYTEC phyCORE-i.MX93 SoM. Supported features: - 1GB LPDDR4 RAM - eMMC - external SD - FEC Ethernet - debug UART - watchdog Signed-off-by: Mathieu Othacehe <othacehe(a)gnu.org> --- Hello, This new revision fixes the remarks of Primoz. The configuration is now aligned on the savedefconfig output. The FEC Ethernet is also tested to be working if this patch is in: https://patchwork.ozlabs.org/project/uboot/patch/20240130124337.497748-1-pr… The proposed patch has been rebased on top of 6faba41. Thanks, Mathieu v3: https://lists.denx.de/pipermail/u-boot/2024-January/544493.html arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi | 293 ++++ arch/arm/dts/imx93-phyboard-segin.dts | 117 ++ arch/arm/dts/imx93-phycore-som.dtsi | 126 ++ arch/arm/mach-imx/imx9/Kconfig | 6 + board/phytec/phycore_imx93/Kconfig | 13 + board/phytec/phycore_imx93/MAINTAINERS | 10 + board/phytec/phycore_imx93/Makefile | 14 + board/phytec/phycore_imx93/lpddr4_timing.c | 1546 +++++++++++++++++ board/phytec/phycore_imx93/phycore-imx93.c | 42 + board/phytec/phycore_imx93/phycore_imx93.env | 73 + board/phytec/phycore_imx93/spl.c | 148 ++ configs/imx93-phyboard-segin_defconfig | 138 ++ doc/board/phytec/imx93-phyboard-segin.rst | 61 + doc/board/phytec/index.rst | 1 + include/configs/phycore_imx93.h | 28 + 16 files changed, 2618 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi create mode 100644 arch/arm/dts/imx93-phyboard-segin.dts create mode 100644 arch/arm/dts/imx93-phycore-som.dtsi create mode 100644 board/phytec/phycore_imx93/Kconfig create mode 100644 board/phytec/phycore_imx93/MAINTAINERS create mode 100644 board/phytec/phycore_imx93/Makefile create mode 100644 board/phytec/phycore_imx93/lpddr4_timing.c create mode 100644 board/phytec/phycore_imx93/phycore-imx93.c create mode 100644 board/phytec/phycore_imx93/phycore_imx93.env create mode 100644 board/phytec/phycore_imx93/spl.c create mode 100644 configs/imx93-phyboard-segin_defconfig create mode 100644 doc/board/phytec/imx93-phyboard-segin.rst create mode 100644 include/configs/phycore_imx93.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 50f35e3db3f..1a20031b063 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1130,7 +1130,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ dtb-$(CONFIG_ARCH_IMX9) += \ imx93-11x11-evk.dtb \ - imx93-var-som-symphony.dtb + imx93-var-som-symphony.dtb \ + imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb \ diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi new file mode 100644 index 00000000000..8bf28c2de87 --- /dev/null +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Christoph Stoidner <c.stoidner(a)phytec.de> + * + * Product homepage: + * phyBOARD-Segin carrier board is reused for the i.MX93 design. + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6… + */ + +#include "imx93-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +&reg_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_cd { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_default { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc2 { + bootph-pre-ram; + bootph-some-ram; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&wdog3 { + bootph-all; + bootph-pre-ram; +}; + +/* + * The two nodes below won't be needed once nxp,pca9451a + * support is added to the Linux kernel. + */ +&iomuxc { + pinctrl_lpi2c3: lpi2c3grp { + bootph-pre-ram; + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pmic: pmicgrp { + bootph-pre-ram; + fsl,pins = < + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e + >; + }; +}; + +&lpi2c3 { + bootph-pre-ram; + bootph-some-ram; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + pmic@25 { + bootph-pre-ram; + bootph-some-ram; + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + regulators { + bootph-pre-ram; + bootph-some-ram; + buck1: BUCK1 { + regulator-name = "VDD_SOC"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "VDDQ_0V6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3_BUCK"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "VDD_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "PMIC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx93-phyboard-segin.dts b/arch/arm/dts/imx93-phyboard-segin.dts new file mode 100644 index 00000000000..85fb188b057 --- /dev/null +++ b/arch/arm/dts/imx93-phyboard-segin.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov(a)phytec.de>, Christoph Stoidner <c.stoidner(a)phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe(a)gmail.com> + * + * Product homepage: + * phyBOARD-Segin carrier board is reused for the i.MX93 design. + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6… + */ +/dts-v1/; + +#include "imx93-phycore-som.dtsi" + +/{ + model = "PHYTEC phyBOARD-Segin-i.MX93"; + compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", + "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SD"; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + no-1-8-v; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + vmmc-supply = <&reg_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_default: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff --git a/arch/arm/dts/imx93-phycore-som.dtsi b/arch/arm/dts/imx93-phycore-som.dtsi new file mode 100644 index 00000000000..88c2657b50e --- /dev/null +++ b/arch/arm/dts/imx93-phycore-som.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov(a)phytec.de>, Christoph Stoidner <c.stoidner(a)phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe(a)gmail.com> + * + * Product homepage: + * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ + */ + +#include <dt-bindings/leds/common.h> + +#include "imx93.dtsi" + +/{ + model = "PHYTEC phyCORE-i.MX93"; + compatible = "phytec,imx93-phycore-som", "fsl,imx93"; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* Ethernet */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <&ethphy1>; + fsl,magic-packet; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>, <50000000>; + status = "okay"; + + mdio: mdio { + clock-frequency = <5000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* Watchdog */ +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e + MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; +}; diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 961d6f527ab..b79485f1f75 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -37,9 +37,15 @@ config TARGET_IMX93_VAR_SOM select IMX93 select IMX9_LPDDR4X +config TARGET_PHYCORE_IMX93 + bool "phycore_imx93" + select IMX93 + select IMX9_LPDDR4X + endchoice source "board/freescale/imx93_evk/Kconfig" +source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" endif diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig new file mode 100644 index 00000000000..a70104cb798 --- /dev/null +++ b/board/phytec/phycore_imx93/Kconfig @@ -0,0 +1,13 @@ + +if TARGET_PHYCORE_IMX93 + +config SYS_BOARD + default "phycore_imx93" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_imx93" + +endif diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS new file mode 100644 index 00000000000..9e91a29dc31 --- /dev/null +++ b/board/phytec/phycore_imx93/MAINTAINERS @@ -0,0 +1,10 @@ +phyCORE-i.MX93 +M: Mathieu Othacehe <m.othacehe(a)gmail.com> +W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ +S: Maintained +F: arch/arm/dts/imx93-phyboard-segin.dts +F: arch/arm/dts/imx93-phycore-som.dtsi +F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +F: board/phytec/phycore_imx93/ +F: configs/imx93-phyboard-segin_defconfig +F: include/configs/phycore_imx93.h diff --git a/board/phytec/phycore_imx93/Makefile b/board/phytec/phycore_imx93/Makefile new file mode 100644 index 00000000000..ce35326a156 --- /dev/null +++ b/board/phytec/phycore_imx93/Makefile @@ -0,0 +1,14 @@ +# +# Copyright 2022 NXP +# Copyright (C) 2023 PHYTEC Messtechnik GmbH +# Christoph Stoidner <c.stoidner(a)phytec.de> +# Copyright (C) 2024 Mathieu Othacehe <m.othacehe(a)gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += phycore-imx93.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o lpddr4_timing.o +endif diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx93/lpddr4_timing.c new file mode 100644 index 00000000000..2111972a40e --- /dev/null +++ b/board/phytec/phycore_imx93/lpddr4_timing.c @@ -0,0 +1,1546 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 NXP + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Christoph Stoidner <c.stoidner(a)phytec.de> + * + * Code generated with DDR Tool v1.0.0. + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x4080}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, + +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24A0421B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F263233}, + {0x4e30010C, 0x0005E18B}, + {0x4e300124, 0x1C770000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x00FE00FE}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2215}, + {0x4e300304, 0x00FE2213}, + {0x4e300308, 0x0A3C0E3C}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0xF2}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x2}, + {0x110a3, 0x3}, + {0x110a4, 0x4}, + {0x110a5, 0x5}, + {0x110a6, 0x6}, + {0x110a7, 0x7}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x2002e, 0x2}, + {0x90204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x20056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x200fa, 0x2}, + {0x20019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x1}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, + +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x2002e, 0x0}, + {0x90204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x20056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x200fa, 0x0}, + {0x20019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, + +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0xf2}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0xf2}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0xf236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0xf236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0xf2}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0xf2}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0xf236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0xf236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x75}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, + +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + + }, + + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, + +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c new file mode 100644 index 00000000000..085c8e195a6 --- /dev/null +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner <c.stoidner(a)phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe(a)gmail.com> + */ + +#include <asm/arch-imx9/ccm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-imx9/imx93_pins.h> +#include <asm/arch/clock.h> +#include <asm/global_data.h> +#include <asm/mach-imx/boot_mode.h> +#include <env.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + switch (get_boot_device()) { + case SD2_BOOT: + env_set_ulong("mmcdev", 1); + break; + case MMC1_BOOT: + env_set_ulong("mmcdev", 0); + break; + default: + break; + } + + return 0; +} diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx93/phycore_imx93.env new file mode 100644 index 00000000000..27bfadfa140 --- /dev/null +++ b/board/phytec/phycore_imx93/phycore_imx93.env @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +image=Image +console=ttyLP0 +fdt_addr=0x83000000 +fdto_addr=0x830c0000 +bootenv_addr=0x83500000 +fdt_file=CONFIG_DEFAULT_FDT_FILE +ip_dyn=yes +bootenv=bootenv.txt +mmc_load_bootenv=fatload mmc ${mmcdev}:${mmcpart} ${bootenv_addr} ${bootenv} +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcpart=1 +mmcroot=2 +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} earlycon + root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmc_load_overlay=fatload mmc ${mmcdev}:${mmcpart} ${fdto_addr} ${overlay} +mmc_apply_overlays= + fdt address ${fdt_addr}; + for overlay in ${overlays}; + do; + if run mmc_load_overlay; then + fdt resize ${filesize}; + fdt apply ${fdto_addr}; + fi; + done; +mmcboot= + echo Booting from mmc ...; + if run mmc_load_bootenv; then + env import -t ${bootenv_addr} ${filesize}; + fi; + run mmcargs; + if run loadfdt; then + run mmc_apply_overlays; + booti ${loadaddr} - ${fdt_addr}; + else + echo WARN: Cannot load the DT; + fi; +nfsroot=/nfs +netargs=setenv bootargs console=${console},${baudrate} earlycon + root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +net_load_bootenv=${get_cmd} ${bootenv_addr} ${bootenv} +net_load_overlay=${get_cmd} ${fdto_addr} ${overlay} +net_apply_overlays= + fdt address ${fdt_addr}; + for overlay in ${overlays}; + do; + if run net_load_overlay; then + fdt resize ${filesize}; + fdt apply ${fdto_addr}; + fi; + done; +netboot= + echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if run net_load_bootenv; then + env import -t ${bootenv_addr} ${filesize}; + fi; + ${get_cmd} ${loadaddr} ${image}; + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + run net_apply_overlays; + booti ${loadaddr} - ${fdt_addr}; + else + echo WARN: Cannot load the DT; + fi; diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c new file mode 100644 index 00000000000..da4b9e53594 --- /dev/null +++ b/board/phytec/phycore_imx93/spl.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner <c.stoidner(a)phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe(a)gmail.com> + */ + +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/trdc.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/sections.h> +#include <hang.h> +#include <init.h> +#include <log.h> +#include <power/pmic.h> +#include <power/pca9450.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Will be part of drivers/power/regulator/pca9450.c + * when pca9451a support is added. + */ +#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5) + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + val = ret; + + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) { + /* 0.8v for Low drive mode */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x10); + } + } else { + /* 0.9v for Over drive mode */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x14); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + } + } + + /* set standby voltage to 0.65v */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + + return 0; +} + +extern int imx9_probe_mu(void *ctx, struct event *event); +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(NULL, NULL); + if (ret) { + printf("Fail to init ELE API\n"); + } else { + printf("SOC: 0x%x\n", gd->arch.soc_rev); + printf("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init(); + + power_init_board(); + + if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + set_arm_core_max_clk(); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig new file mode 100644 index 00000000000..91a24c3456d --- /dev/null +++ b/configs/imx93-phyboard-segin_defconfig @@ -0,0 +1,138 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x20000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="phycore_imx93" +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-phyboard-segin" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_AHAB_BOOT=y +CONFIG_TARGET_PHYCORE_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x20519dd0 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x720000 +CONFIG_CMD_DEKBLOB=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_REMAKE_ELF=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" +CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2051a000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_CLK_IMX93=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_GPIO_HOG=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y diff --git a/doc/board/phytec/imx93-phyboard-segin.rst b/doc/board/phytec/imx93-phyboard-segin.rst new file mode 100644 index 00000000000..da8772ecd5c --- /dev/null +++ b/doc/board/phytec/imx93-phyboard-segin.rst @@ -0,0 +1,61 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +phyBOARD-Segin-i.MX93 +===================== + +U-Boot for the phyBOARD-Segin-i.MX93. + +Quick Start +----------- + +- Get and Build the ARM Trusted firmware +- Get the DDR firmware +- Get ahab-container.img +- Build U-Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.8 + +.. code-block:: bash + + $ unset LDFLAGS + $ make PLAT=imx93 bl31 + $ cp build/imx93/release/bl31.bin $(srctree) + +Get the DDR firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin + $ chmod +x firmware-imx-8.21.bin + $ ./firmware-imx-8.21.bin + $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree) + +Get ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.10.bin + $ chmod +x firmware-sentinel-0.10.bin + $ ./firmware-sentinel-0.10.bin + $ cp firmware-sentinel-0.10/mx93a0-ahab-container.img $(srctree) + +Build U-Boot +------------ + +.. code-block:: bash + + $ make imx93-phyboard-segin_defconfig + $ make + +Burn the flash.bin to MicroSD card offset 32KB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index 965d40de4d4..fea0b076202 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -7,6 +7,7 @@ PHYTEC :maxdepth: 2 imx8mm-phygate-tauri-l + imx93-phyboard-segin phycore-am62x phycore-imx8mm phycore-imx8mp diff --git a/include/configs/phycore_imx93.h b/include/configs/phycore_imx93.h new file mode 100644 index 00000000000..07364dff403 --- /dev/null +++ b/include/configs/phycore_imx93.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Christoph Stoidner <c.stoidner(a)phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe(a)gmail.com> + */ + +#ifndef __PHYCORE_IMX93_H +#define __PHYCORE_IMX93_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif /* __PHYCORE_IMX93_H */ -- 2.41.0

5 4

[PATCH] clk: Fix error message in clk_get_bulk
by Jan Kiszka 02 Aug '24

02 Aug '24

From: Jan Kiszka <jan.kiszka(a)siemens.com> Fix a logical inversion of the printed text. Signed-off-by: Jan Kiszka <jan.kiszka(a)siemens.com> --- drivers/clk/clk-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index ed6e60bc484..78d8ea94c65 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -180,7 +180,7 @@ int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) bulk_get_err: err = clk_release_all(bulk->clks, bulk->count); if (err) - debug("%s: could release all clocks for %p\n", + debug("%s: could not release all clocks for %p\n", __func__, dev); return ret; -- 2.35.3

4 3

[PATCH v2 0/8] Add support for Qualcomm SA8155-ADP board
by Volodymyr Babchuk 27 Jul '24

27 Jul '24

This patch series adds support for Qualcomm SA8155-ADP development board. Main motivation for this series is to allow running virtualization software on this board and U-Boot is a good way to break Qualcomm's boot chain at EL2 with more convenient ways for uploading and running the code. With this patches applied it is possible to upload and run Xen on this board. KVM probably should work too. I added myself as a maintainer for this board, but my abilities to maintain it are quite limited as I have no access to Qualcomm documentation. I used mostly Linux drivers as the source for device-specific information, like register addresses and offsets. If anyone wants to maintain this, I will gladly agree. This is the second version of the series. It is now rebased onto qcom-next branch. Changes in v2: - New patch in v2 - Clear loopback bit explicitly - Reworked qcom_cc_bind() function - Added timeout to qcom_power_set() - Minor fixes in register names and formatting - Renamed GPLL7_MAIN to just GPLL7 (while I like idea to use Linux naming convention, such rework needs to be done in a separate commit) - Removed unnecessary include - Fixed GDSCR register values for couple of devices - Enable GPLL7 only when RGMII clock is enabled - Rebased onto qcom-next branch - Removed unnecessary files thanks to generic qualcomm board support - Enabled CONFIG_REMAKE_ELF (this removes one extra step in the readme) Volodymyr Babchuk (8): qcom: board: validate fdt before trying to use it clk: qcom: clear div mask before assigning a new divider net: dw_eth_qos: add support for Qualcomm SM8150 SoC clk: qcom: add support for power domains uclass clk: qcom: add driver for SM8150 SoC pinctrl: qcom: pass pin number to get_function_mux callback pinctrl: qcom: add driver for SM8150 SoC board: add support for Qualcomm SA8155P-ADP board arch/arm/dts/sa8155p-adp-u-boot.dtsi | 30 ++ arch/arm/mach-snapdragon/board.c | 5 +- board/qualcomm/sa8155p-adp/MAINTAINERS | 5 + configs/sa8155p_adp_defconfig | 35 ++ doc/board/qualcomm/index.rst | 1 + doc/board/qualcomm/sa8155p-adp.rst | 87 ++++ drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-qcom.c | 131 +++++- drivers/clk/qcom/clock-qcom.h | 7 + drivers/clk/qcom/clock-sm8150.c | 237 ++++++++++ drivers/net/dwc_eth_qos.c | 4 + drivers/net/dwc_eth_qos.h | 2 + drivers/net/dwc_eth_qos_qcom.c | 46 +- drivers/pinctrl/qcom/Kconfig | 7 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-apq8016.c | 3 +- drivers/pinctrl/qcom/pinctrl-apq8096.c | 3 +- drivers/pinctrl/qcom/pinctrl-ipq4019.c | 3 +- drivers/pinctrl/qcom/pinctrl-qcom.c | 4 +- drivers/pinctrl/qcom/pinctrl-qcom.h | 3 +- drivers/pinctrl/qcom/pinctrl-qcs404.c | 3 +- drivers/pinctrl/qcom/pinctrl-sdm845.c | 3 +- drivers/pinctrl/qcom/pinctrl-sm8150.c | 589 +++++++++++++++++++++++++ 24 files changed, 1186 insertions(+), 32 deletions(-) create mode 100644 arch/arm/dts/sa8155p-adp-u-boot.dtsi create mode 100644 board/qualcomm/sa8155p-adp/MAINTAINERS create mode 100644 configs/sa8155p_adp_defconfig create mode 100644 doc/board/qualcomm/sa8155p-adp.rst create mode 100644 drivers/clk/qcom/clock-sm8150.c create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c -- 2.43.0

4 31

[PATCH] riscv: dts: jh7110: Enable PLL node in SPL
by Bo Gan 19 Jul '24

19 Jul '24

Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on OSC clock (24Mhz). As a result, all peripherals have to run at a much lower frequency, and loading from sdcard/emmc is slow. Thus, enabling PLL node in dts to fix this. Signed-off-by: Bo Gan <ganboing(a)gmail.com> --- arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 2f560e7..c09d5c9 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -93,6 +93,10 @@ bootph-pre-ram; }; +&pllclk { + bootph-pre-ram; +}; + &S7_0 { status = "okay"; }; -- 2.7.4

4 10

[PATCH v2 0/2] sunxi, usb: UDC/DM gadget model support
by Sam Edwards 15 Jul '24

15 Jul '24

Happy Thursday, U-Boot list! Here is attempt 2 at making this USB controller driver compatible with DM's gadget model, following what most of the other musb variants do. v2 removes the unwanted printfs in the probe func, per feedback from Marek. I received no other feedback against v1 of this patch. Cheers, Sam Sam Edwards (2): usb: musb-new: sunxi: remove unwanted printfs usb: musb-new: sunxi: make compatible with UDC/DM gadget model drivers/usb/musb-new/sunxi.c | 52 +++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 21 deletions(-) -- 2.39.2

3 9

[PATCH v2 0/7] rockchip: Add GMAC support for RK3568 and RK3588
by Jonas Karlman 11 Jul '24

11 Jul '24

This series adds a glue driver, dwc_eth_qos_rockchip, to support GMAC on RK356x and RK3588. rk_gmac_ops used in this series has been ported from mainline linux. Patch 1-3 does some minor cleanup in dwc_eth_qos driver. Patch 4 add glue driver with RK3568 support. Patch 5 add support for RK3588 to glue driver. Patch 6-7 update defconfigs to enable use of the new driver. Changes in v2: - Add comment about ported code intentionally left close to 1:1 with linux - Add lubancat-2-rk3568_defconfig changes - Add rock5b-rk3588_defconfig changes - Collect r-b tags Dependencies: - "rockchip: Port IO-domain driver for RK3568 from linux" [1] dhcp and ping commands has been tested on the followin devices: - RK3566: Quartz64 Model A and SOQuartz on Blade - RK3568: ROCK 3 Model A - RK3588: ROCK 5 Model A This series can also be found at [2]. [1] https://patchwork.ozlabs.org/cover/1823769/ [2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-gmac-v2 Jonas Karlman (7): net: dwc_eth_qos: Drop unused rx_pkt from eqos_priv net: dwc_eth_qos: Return error code when start fails net: dwc_eth_qos: Stop spam of RX packet not available message net: dwc_eth_qos: Add glue driver for GMAC on Rockchip RK3568 net: dwc_eth_qos_rockchip: Add support for RK3588 configs: rockchip: Enable ethernet driver on RK356x boards configs: rockchip: Enable ethernet driver on RK3588 boards configs/evb-rk3568_defconfig | 6 +- configs/evb-rk3588_defconfig | 5 +- configs/lubancat-2-rk3568_defconfig | 3 + configs/nanopi-r5s-rk3568_defconfig | 3 + configs/neu6a-io-rk3588_defconfig | 2 - configs/neu6b-io-rk3588_defconfig | 2 - configs/odroid-m1-rk3568_defconfig | 3 + configs/quartz64-a-rk3566_defconfig | 3 + configs/quartz64-b-rk3566_defconfig | 3 + configs/radxa-cm3-io-rk3566_defconfig | 6 +- configs/rock-3a-rk3568_defconfig | 5 +- configs/rock5a-rk3588s_defconfig | 5 +- configs/rock5b-rk3588_defconfig | 3 +- configs/soquartz-blade-rk3566_defconfig | 3 + configs/soquartz-cm4-rk3566_defconfig | 3 + configs/soquartz-model-a-rk3566_defconfig | 3 + drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 33 +- drivers/net/dwc_eth_qos.h | 3 +- drivers/net/dwc_eth_qos_rockchip.c | 522 ++++++++++++++++++++++ 21 files changed, 590 insertions(+), 35 deletions(-) create mode 100644 drivers/net/dwc_eth_qos_rockchip.c -- 2.42.0

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