October 2024 - U-Boot

[PATCH] spi: davinci: Drop the preload of TX buffer before read/writes operations
by Bastien Curutchet 03 Oct '24

03 Oct '24

A write to the TX buffer is performed before entering the loop to "avoid clock starvation". This sometimes results in subsequent writes in davinci_spi_xfer_data() to occur while the TXFULL bit is asserted, leading to write failures. Remove the preload of the TX buffer. Signed-off-by: Bastien Curutchet <bastien.curutchet(a)bootlin.com> --- Hi all, I've ran into write failures to flash on my platform based on the DAVINCI/OMAP L138. This patch fixes it. drivers/spi/davinci_spi.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 25f5e9fdeb..07c46b8b66 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -129,9 +129,6 @@ static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len, while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) ; - /* preload the TX buffer to avoid clock starvation */ - writel(data1_reg_val, &ds->regs->dat1); - /* keep reading 1 byte until only 1 byte left */ while ((len--) > 1) *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val); @@ -159,12 +156,6 @@ static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len, while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) ; - /* preload the TX buffer to avoid clock starvation */ - if (len > 2) { - writel(data1_reg_val | *txp++, &ds->regs->dat1); - len--; - } - /* keep writing 1 byte until only 1 byte left */ while ((len--) > 1) davinci_spi_xfer_data(ds, data1_reg_val | *txp++); -- 2.46.0

2 1

[PATCH] Add mkimage secp521r1 ECDSA curve support
by Joakim Tjernlund 03 Oct '24

03 Oct '24

Signed-off-by: Joakim Tjernlund <joakim.tjernlund(a)infinera.com> --- include/u-boot/ecdsa.h | 1 + lib/ecdsa/ecdsa-libcrypto.c | 2 +- tools/image-sig-host.c | 7 +++++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/include/u-boot/ecdsa.h b/include/u-boot/ecdsa.h index 53490c6b287..8f9f5e7d6e7 100644 --- a/include/u-boot/ecdsa.h +++ b/include/u-boot/ecdsa.h @@ -65,5 +65,6 @@ int ecdsa_verify(struct image_sign_info *info, /** @} */ #define ECDSA256_BYTES (256 / 8) +#define ECDSA521_BYTES ((521 + 7) / 8) #endif diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c index 5fa9be10b4b..403dfe0b97c 100644 --- a/lib/ecdsa/ecdsa-libcrypto.c +++ b/lib/ecdsa/ecdsa-libcrypto.c @@ -108,7 +108,7 @@ static size_t ecdsa_key_size_bytes(const EC_KEY *key) const EC_GROUP *group; group = EC_KEY_get0_group(key); - return EC_GROUP_order_bits(group) / 8; + return (EC_GROUP_order_bits(group) + 7) / 8; } static int default_password(char *buf, int size, int rwflag, void *u) diff --git a/tools/image-sig-host.c b/tools/image-sig-host.c index d0133aec4c8..21b4fa5d39d 100644 --- a/tools/image-sig-host.c +++ b/tools/image-sig-host.c @@ -76,6 +76,13 @@ struct crypto_algo crypto_algos[] = { .add_verify_data = ecdsa_add_verify_data, .verify = ecdsa_verify, }, + { + .name = "secp521r1", + .key_len = ECDSA521_BYTES, + .sign = ecdsa_sign, + .add_verify_data = ecdsa_add_verify_data, + .verify = ecdsa_verify, + }, }; struct padding_algo padding_algos[] = { -- 2.44.2

4 6

[PATCH v2] fs: Fix SPL build if SPL_FS_LOADER is enabled and FS_LOADER is disabled
by Francesco Dolcini 03 Oct '24

03 Oct '24

From: Hiago De Franco <hiago.franco(a)toradex.com> When SPL_FS_LOADER is set to y and FS_LOADER is not enabled, the SPL build fails with the following errors: AR spl/boot/built-in.o LD spl/u-boot-spl arm-none-linux-gnueabihf-ld.bfd: drivers/misc/fs_loader.o: in function `fw_get_filesystem_firmware': /u-boot/drivers/misc/fs_loader.c:162: undefined reference to `fs_set_blk_dev' arm-none-linux-gnueabihf-ld.bfd: /home/frh/tdx/src/u-boot/drivers/misc/ fs_loader.c:185: undefined reference to `fs_read' arm-none-linux-gnueabihf-ld.bfd: drivers/misc/fs_loader.o: in function `select_fs_dev': /u-boot/drivers/misc/fs_loader.c:89: undefined reference to `fs_set_blk_dev_with_part' make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make: *** [Makefile:2055: spl/u-boot-spl] Error 2 Fix it by replacing the FS_LOADER with SPL_FS_LOADER in the Makefile, so the fs.c with the necessary function definitions are compiled. Fixes: b071a07743d4 ("drivers: misc: Makefile: Enable fs_loader compilation at SPL Level") Suggested-by: Francesco Dolcini <francesco.dolcini(a)toradex.com> Signed-off-by: Hiago De Franco <hiago.franco(a)toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini(a)toradex.com> --- v2: fix sandbox_noinst_defconfig and config SPL_BLK_FS --- configs/sandbox_noinst_defconfig | 1 + drivers/block/Kconfig | 2 +- fs/Makefile | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index f37230151a05..9ddb606f8f9b 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -186,6 +186,7 @@ CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_FS_LOADER=y +CONFIG_SPL_FS_LOADER=y CONFIG_MMC_SANDBOX=y CONFIG_DM_MTD=y CONFIG_MTD_CONCAT=y diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 48529a6982f5..5283d8981e09 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -109,7 +109,7 @@ config EFI_MEDIA config SPL_BLK_FS bool "Load images from filesystems on block devices" - depends on SPL_BLK + depends on SPL_BLK && SPL_FS_LOADER help Use generic support to load images from fat/ext filesystems on different types of block devices such as NVMe. diff --git a/fs/Makefile b/fs/Makefile index 7b05c79e0ccf..a3ee0a361d3d 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -5,7 +5,7 @@ # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_FS_LOADER) += fs.o +obj-$(CONFIG_SPL_FS_LOADER) += fs.o obj-$(CONFIG_SPL_FS_FAT) += fat/ obj-$(CONFIG_SPL_FS_EXT4) += ext4/ obj-$(CONFIG_SPL_FS_CBFS) += cbfs/ -- 2.39.5

2 1

[PATCH] board: ti: j722s: Update Resource Management configs
by Vaishnav Achath 03 Oct '24

03 Oct '24

Update J722S Resource Management configs to the latest output generated by K3 Resource Partitioning tool. Main change includes allocating more BCDMA channels to A53 for CSI2RX to support 4 x CSIRX capture instance simultaneously. Signed-off-by: Vaishnav Achath <vaishnav.a(a)ti.com> --- Test logs (CSI capture + RM config dump): https://gist.github.com/vachath/7b37cd288ef16ad8a2ac6ff5710d1e9a board/ti/j722s/rm-cfg.yaml | 48 ++++++++++++++++++++++----------- board/ti/j722s/tifs-rm-cfg.yaml | 28 +++++++++++++------ 2 files changed, 53 insertions(+), 23 deletions(-) diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml index 21ca30104c..e32beb8479 100644 --- a/board/ti/j722s/rm-cfg.yaml +++ b/board/ti/j722s/rm-cfg.yaml @@ -244,7 +244,7 @@ rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 1160 + resasg_entries_size: 1184 reserved: 0 resasg_entries: - @@ -1017,13 +1017,13 @@ rm-cfg: reserved: 0 - start_resource: 8 - num_resource: 12 + num_resource: 32 type: 12750 host_id: 12 reserved: 0 - - start_resource: 20 - num_resource: 20 + start_resource: 8 + num_resource: 32 type: 12750 host_id: 38 reserved: 0 @@ -1035,13 +1035,13 @@ rm-cfg: reserved: 0 - start_resource: 0 - num_resource: 12 + num_resource: 32 type: 12769 host_id: 12 reserved: 0 - - start_resource: 12 - num_resource: 20 + start_resource: 0 + num_resource: 32 type: 12769 host_id: 38 reserved: 0 @@ -1053,10 +1053,22 @@ rm-cfg: reserved: 0 - start_resource: 0 - num_resource: 8 + num_resource: 2 type: 12810 host_id: 12 reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 12810 + host_id: 20 + reserved: 0 + - + start_resource: 4 + num_resource: 2 + type: 12810 + host_id: 22 + reserved: 0 - start_resource: 22 num_resource: 18 @@ -1065,21 +1077,27 @@ rm-cfg: reserved: 0 - start_resource: 12288 - num_resource: 64 + num_resource: 56 type: 12813 host_id: 12 reserved: 0 - - start_resource: 12352 - num_resource: 64 + start_resource: 12344 + num_resource: 48 type: 12813 - host_id: 38 + host_id: 20 reserved: 0 - - start_resource: 12416 - num_resource: 88 + start_resource: 12392 + num_resource: 48 type: 12813 - host_id: 128 + host_id: 22 + reserved: 0 + - + start_resource: 12440 + num_resource: 64 + type: 12813 + host_id: 38 reserved: 0 - start_resource: 1536 diff --git a/board/ti/j722s/tifs-rm-cfg.yaml b/board/ti/j722s/tifs-rm-cfg.yaml index 5e8d7e0444..4a2af0ebca 100644 --- a/board/ti/j722s/tifs-rm-cfg.yaml +++ b/board/ti/j722s/tifs-rm-cfg.yaml @@ -244,7 +244,7 @@ tifs-rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 976 + resasg_entries_size: 992 reserved: 0 resasg_entries: - @@ -897,13 +897,13 @@ tifs-rm-cfg: reserved: 0 - start_resource: 8 - num_resource: 12 + num_resource: 32 type: 12750 host_id: 12 reserved: 0 - - start_resource: 20 - num_resource: 20 + start_resource: 8 + num_resource: 32 type: 12750 host_id: 38 reserved: 0 @@ -915,13 +915,13 @@ tifs-rm-cfg: reserved: 0 - start_resource: 0 - num_resource: 12 + num_resource: 32 type: 12769 host_id: 12 reserved: 0 - - start_resource: 12 - num_resource: 20 + start_resource: 0 + num_resource: 32 type: 12769 host_id: 38 reserved: 0 @@ -933,10 +933,22 @@ tifs-rm-cfg: reserved: 0 - start_resource: 0 - num_resource: 8 + num_resource: 2 type: 12810 host_id: 12 reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 12810 + host_id: 20 + reserved: 0 + - + start_resource: 4 + num_resource: 2 + type: 12810 + host_id: 22 + reserved: 0 - start_resource: 22 num_resource: 18 -- 2.34.1

3 2

[PATCH v2 0/3] Add Android 14 bootflow support for AM62X and AM62P board
by Guillaume La Roque 03 Oct '24

03 Oct '24

Ths patchset add support of Android 14 with boot image version 4 for : - AM62X-SK EVM: https://www.ti.com/tool/SK-AM62B - BeaglePlay: https://beagleplay.org/ - AM62PX-SK EVM: https://www.ti.com/tool/SK-AM62P-LP Android Images use to test this series are on the Official TI website: - AM62x/BeaglePlay: https://www.ti.com/tool/PROCESSOR-SDK-AM62X - AM62PX: https://www.ti.com/tool/PROCESSOR-SDK-AM62P Signed-off-by: Guillaume La Roque <glaroque(a)baylibre.com> --- Changes in v2: - Remove uneeded part in android fragment - Update commit message. - Link to v1: https://lore.kernel.org/r/20240902-sitaraupstream-v1-0-0c478c33c08b@baylibr… --- Guillaume La Roque (1): board: ti: am62x_evm: Add android bootflow Mattijs Korpershoek (2): board: beagle: beagleplay: Add android bootflow support board: ti: am62px: Add android bootflow support board/beagle/beagleplay/beagleplay.env | 30 ++++++++++++++++++++++++++++++ board/ti/am62px/am62px.env | 5 +++++ board/ti/am62x/am62x.env | 5 +++++ configs/am62x_a53_android.config | 21 +++++++++++++++++++++ doc/board/ti/am62x_sk.rst | 14 ++++++++++++++ include/env/ti/android.env | 31 +++++++++++++++++++++++++++++++ 6 files changed, 106 insertions(+) --- base-commit: 57949a99b7bd0aa21abbde1ffa7e50e5d9e10a4e change-id: 20240830-sitaraupstream-5b18f3b9824f Best regards, -- Guillaume La Roque <glaroque(a)baylibre.com>

5 8

[PATCH 1/2] bootm: adjust the print format
by Dario Binacchi 03 Oct '24

03 Oct '24

All three addresses printed are in hexadecimal format, but only the first two have the "0x" prefix. The patch aligns the format of the "end" address with the other two by adding the "0x" prefix. Signed-off-by: Dario Binacchi <dario.binacchi(a)amarulasolutions.com> --- boot/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot/bootm.c b/boot/bootm.c index 480f8e6a0e6e..951e549f19ff 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -703,7 +703,7 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) /* Handle BOOTM_STATE_LOADOS */ if (relocated_addr != load) { - printf("Moving Image from 0x%lx to 0x%lx, end=%lx\n", + printf("Moving Image from 0x%lx to 0x%lx, end=0x%lx\n", load, relocated_addr, relocated_addr + image_size); memmove((void *)relocated_addr, load_buf, image_size); -- 2.43.0

6 13

[PATCH v2 0/4] dm: core: fix several debug messages and migrate debug() to dm_warn
by Quentin Schulz 03 Oct '24

03 Oct '24

Fix a few misleading or incorrect debug messages and prompt text for a Kconfig symbol. Migrate debug() messages to use dm_warn() instead so that we can print them without selecting DM_DEBUG which does too much (e.g. makes assert() reset U-boot if it fails). Tested on top of next branch but it applies without complaints on top of master as well, so up to you to which branch to merge it. Signed-off-by: Quentin Schulz <quentin.schulz(a)cherry.de> --- Changes in v2: - add missing dm/util.h header includes - Link to v1: https://lore.kernel.org/r/20240610-misc-20240610-v1-0-6914f1725dd4@cherry.de --- Quentin Schulz (4): dm: core: fix misleading debug message when matching compatible dm: core: fix signedness in debug messages dm: core: migrate debug() messages to use dm_warn dm: core: fix typo in SPL_DM_WARN prompt text drivers/core/Kconfig | 2 +- drivers/core/device.c | 2 +- drivers/core/fdtaddr.c | 7 +++-- drivers/core/lists.c | 7 ++--- drivers/core/of_access.c | 51 +++++++++++++++--------------- drivers/core/of_addr.c | 41 ++++++++++++------------ drivers/core/of_extra.c | 33 ++++++++++---------- drivers/core/ofnode.c | 81 ++++++++++++++++++++++++------------------------ drivers/core/regmap.c | 57 +++++++++++++++++----------------- drivers/core/root.c | 14 ++++----- drivers/core/uclass.c | 4 +-- 11 files changed, 152 insertions(+), 147 deletions(-) --- base-commit: f9886bc60f42d5bcfcfa4e474af7dc230400b6be change-id: 20240610-misc-20240610-f9dce050186b Best regards, -- Quentin Schulz <quentin.schulz(a)cherry.de>

6 15

[PATCH 1/1] Squashed 'dts/upstream/' changes from 20e0f0897ea2..3347eecf3408
by Tom Rini 02 Oct '24

02 Oct '24

3347eecf3408 Merge tag 'v6.11-dts-raw' [snip] git-subtree-dir: dts/upstream git-subtree-split: 3347eecf3408998fa7136c8789322cc99646ceab --- [snip] 1503 files changed, 78440 insertions(+), 20166 deletions(-) I have massively editing this down because the relevant information here is that we are merging to v6.11-dts from the devicetree-rebasing tree.

1 1

[PATCH 0/4] clk/qcom: implement clk dump callback
by Caleb Connolly 02 Oct '24

02 Oct '24

Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks. This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly. == Usage == Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of qcom-<soc>.c. If your SoC doesn't yet define the debug data for clocks, it can be added using the Linux driver as a reference. The "clk dump" command should print the states of all the gates, GPLLs and RCGs for your SoC. == Glossary == RCG: Root Clock Generator * Takes in some fairly arbitrary high freq clock (configurable clock source and options for taking just even pulses and other things) * Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary 8 or 16-bit values (depending on the RCG), and d is a number (with support for .5 offsets). GPLL: Global Phase Locked Loop * Crystal as input * integer multiplier + exponent part (2^-40) Gate: Simple on/off clock * Put between RCGs and the peripherals they power * Required to allow for correct power sequencing If you do the maths manually using the equations from "clk dump", the numbers should roughly line up by they're likely to be out by a handful of MHz. They output is formatted so that it can be pasted directly into the python interpreter. == Example output == => clk dump Rate Usecnt Name ------------------------------------------ 38400000 0 |-- xo-board 32764 0 |-- sleep-clk qcom_clk qcom_clk: Gate Clocks: GCC_AGGRE_USB3_SEC_AXI_CLK : GCC_CFG_NOC_USB3_SEC_AXI_CLK : GCC_QUPV3_WRAP0_S0_CLK : GCC_QUPV3_WRAP0_S1_CLK : GCC_QUPV3_WRAP0_S2_CLK : GCC_QUPV3_WRAP0_S3_CLK : GCC_QUPV3_WRAP0_S4_CLK : GCC_QUPV3_WRAP0_S5_CLK : GCC_QUPV3_WRAP0_S6_CLK : GCC_QUPV3_WRAP0_S7_CLK : GCC_QUPV3_WRAP1_S0_CLK : GCC_QUPV3_WRAP1_S1_CLK : ON GCC_QUPV3_WRAP1_S3_CLK : GCC_QUPV3_WRAP1_S4_CLK : GCC_QUPV3_WRAP1_S5_CLK : GCC_QUPV3_WRAP1_S6_CLK : GCC_QUPV3_WRAP1_S7_CLK : GCC_QUPV3_WRAP_0_M_AHB_CLK : GCC_QUPV3_WRAP_0_S_AHB_CLK : GCC_QUPV3_WRAP_1_M_AHB_CLK : ON GCC_QUPV3_WRAP_1_S_AHB_CLK : ON GCC_SDCC2_AHB_CLK : ON GCC_SDCC2_APPS_CLK : ON GCC_SDCC4_AHB_CLK : GCC_SDCC4_APPS_CLK : GCC_UFS_CARD_AHB_CLK : GCC_UFS_CARD_AXI_CLK : GCC_UFS_CARD_CLKREF_CLK : ON GCC_UFS_CARD_ICE_CORE_CLK : GCC_UFS_CARD_PHY_AUX_CLK : GCC_UFS_CARD_RX_SYMBOL_0_CLK : GCC_UFS_CARD_RX_SYMBOL_1_CLK : GCC_UFS_CARD_TX_SYMBOL_0_CLK : GCC_UFS_CARD_UNIPRO_CORE_CLK : GCC_UFS_MEM_CLKREF_CLK : ON GCC_UFS_PHY_AHB_CLK : ON GCC_UFS_PHY_AXI_CLK : ON GCC_UFS_PHY_ICE_CORE_CLK : ON GCC_UFS_PHY_PHY_AUX_CLK : ON GCC_UFS_PHY_RX_SYMBOL_0_CLK : ON GCC_UFS_PHY_RX_SYMBOL_1_CLK : ON GCC_UFS_PHY_TX_SYMBOL_0_CLK : ON GCC_UFS_PHY_UNIPRO_CORE_CLK : ON GCC_USB30_PRIM_MASTER_CLK : ON GCC_USB30_PRIM_MOCK_UTMI_CLK : ON GCC_USB30_PRIM_SLEEP_CLK : ON GCC_USB30_SEC_MASTER_CLK : GCC_USB30_SEC_MOCK_UTMI_CLK : GCC_USB30_SEC_SLEEP_CLK : GCC_USB3_PRIM_CLKREF_CLK : ON GCC_USB3_PRIM_PHY_AUX_CLK : ON GCC_USB3_PRIM_PHY_COM_AUX_CLK : ON GCC_USB3_PRIM_PHY_PIPE_CLK : ON GCC_USB3_SEC_CLKREF_CLK : ON GCC_USB3_SEC_PHY_AUX_CLK : GCC_USB3_SEC_PHY_PIPE_CLK : GCC_USB3_SEC_PHY_COM_AUX_CLK : GCC_USB_PHY_CFG_AHB2PHY_CLK : ON GPLL clocks: | GPLL | LOCKED | XO_BOARD | PLL_L | ALPHA | +--------+--------+-----------+------------+----------------+ | GPLL0 | X | 19200000 * (0x1f + 0x0 * 2 ** -40 )/ 1000000 | GPLL1 | X | 19200000 * (0x37 + 0x0 * 2 ** -40 ) / 1000000 | GPLL2 | | 19200000 * (0x14 + 0x0 * 2 ** -40 ) / 1000000 | GPLL3 | | 19200000 * (0x30 + 0x0 * 2 ** -40 )/ 1000000 | GPLL4 | X | 19200000 * (0x29 + 0x0 * 2 ** -40 ) / 1000000 | GPLL5 | | 19200000 * (0x30 + 0x0 * 2 ** -40 ) / 1000000 | GPLL6 | | 19200000 * (0x0 + 0x0 * 2 ** -40 )/ 1000000 RCGs: | NAME | ON | SRC | OUT_FREQ = input_freq * (m/n) * (1/d) | [CMD REG ] | +----------------------------------+----+-----+---------------------------------------+--------------+ GCC_USB30_PRIM_MASTER | X | 1 | input_freq * ( 1/ 1) * (1/4.5) | [0x00000000] GCC_USB30_PRIM_MOCK_UTMI | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_USB3_PRIM_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_USB30_SEC_MASTER | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_USB30_SEC_MOCK_UTMI | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_USB3_SEC_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_SDCC2_APPS | X | 5 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] GCC_SDCC4_APPS | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_CORE_2X | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_QUPV3_WRAP0_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S1 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S2 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S1 | X | 6 | input_freq * ( 384/15625) * (1/1 ) | [0x00000000] GCC_QUPV3_WRAP1_S2 | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_QUPV3_WRAP1_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_0_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_1_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_PHY_REFGEN | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_UFS_CARD_AXI | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_UFS_CARD_ICE_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_CARD_UNIPRO_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_CARD_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_PHY_AXI | X | 1 | input_freq * ( 1/ 1) * (1/3 ) | [0x00000000] GCC_UFS_PHY_ICE_CORE | X | 1 | input_freq * ( 1/ 1) * (1/2 ) | [0x00000000] GCC_UFS_PHY_UNIPRO_CORE | X | 1 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] GCC_UFS_PHY_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] --- Caleb Connolly (4): clk/qcom: implement clk dump clk/qcom: sdm845: add dump data clk/qcom: sm6115: add debug data clk/qcom: sm8250: add debug data drivers/clk/qcom/clock-qcom.c | 117 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 6 +++ drivers/clk/qcom/clock-sdm845.c | 93 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-sm6115.c | 63 ++++++++++++++++++++++ drivers/clk/qcom/clock-sm8250.c | 115 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 394 insertions(+) --- change-id: 20240819-b4-qcom-clk-dump-e25a0198f6c0 base-commit: b7d5ce05b1b52136af09cf34541c6a91079a4b86 // Caleb (they/them)

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[PATCH] Revert "gpio: qcom_pmic: add a quirk to skip GPIO configuration"
by Caleb Connolly 02 Oct '24

02 Oct '24

This reverts commit 19f000b72b2fa7e4540f7cdb91287aff594239bd. The bug in writing was caused by a long-standing error in the SPMI driver which has since been fixed - c2de620d64d4 ("spmi: msm: fix version 5 support"). We can safely enable writing GPIO configuration now. Signed-off-by: Caleb Connolly <caleb.connolly(a)linaro.org> --- Tested on SDM845/pm8998 (OnePlus 6) --- drivers/gpio/qcom_pmic_gpio.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 80fee841ee3f..f2ef4e5ce144 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -68,19 +68,8 @@ #define REG_EN_CTL 0x46 #define REG_EN_CTL_ENABLE (1 << 7) -/** - * pmic_gpio_match_data - platform specific configuration - * - * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them. - * This is a workaround for an unknown bug on some platforms where trying to write the - * GPIO configuration registers causes the board to hang. - */ -enum pmic_gpio_quirks { - QCOM_PMIC_QUIRK_READONLY = (1 << 0), -}; - struct qcom_pmic_gpio_data { uint32_t pid; /* Peripheral ID on SPMI bus */ bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */ u32 pin_count; @@ -127,15 +116,10 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset, bool input, int value) { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); uint32_t gpio_base = plat->pid + REG_OFFSET(offset); - ulong quirks = dev_get_driver_data(dev); int ret = 0; - /* Some PMICs don't like their GPIOs being configured */ - if (quirks & QCOM_PMIC_QUIRK_READONLY) - return 0; - /* Disable the GPIO */ ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, REG_EN_CTL_ENABLE, 0); if (ret < 0) @@ -277,9 +261,8 @@ static const struct dm_gpio_ops qcom_gpio_ops = { static int qcom_gpio_bind(struct udevice *dev) { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); - ulong quirks = dev_get_driver_data(dev); struct udevice *child; struct driver *drv; int ret; @@ -291,9 +274,9 @@ static int qcom_gpio_bind(struct udevice *dev) /* Bind the GPIO driver as a child of the PMIC. */ ret = device_bind_with_driver_data(dev, drv, dev->name, - quirks, dev_ofnode(dev), &child); + 0, dev_ofnode(dev), &child); if (ret) return log_msg_ret("bind", ret); dev_set_plat(child, plat); @@ -360,13 +343,13 @@ static int qcom_gpio_probe(struct udevice *dev) static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ - { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, + { .compatible = "qcom,pm8998-gpio" }, { .compatible = "qcom,pms405-gpio" }, - { .compatible = "qcom,pm6125-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, - { .compatible = "qcom,pm8150-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, - { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, + { .compatible = "qcom,pm6125-gpio" }, + { .compatible = "qcom,pm8150-gpio" }, + { .compatible = "qcom,pm8550-gpio" }, { } }; U_BOOT_DRIVER(qcom_pmic_gpio) = { -- 2.46.0

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