October 2024 - U-Boot

[PATCH V2 1/5] mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API
by Peng Fan (OSS) 05 Oct '24

05 Oct '24

From: Peng Fan <peng.fan(a)nxp.com> With partition reset supported for i.MX8QM/QXP/95 and etc, when linux mmc runtime suspended, the mmc clks are gated off. While at same time system controller reset Cortex-A cores because of various reasons( WDOG timeout and etc), with SPL run again, only enable PER clk is not enough, also need to enable AHB/IPG clk, here use clk bulk API to enable all the clocks. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- V2: Update commit log and use clk bulk API per Fabio. drivers/mmc/fsl_esdhc_imx.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 03de7dcd505..0ced796ff49 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -148,6 +148,7 @@ struct fsl_esdhc_priv { struct fsl_esdhc *esdhc_regs; unsigned int sdhc_clk; struct clk per_clk; + struct clk_bulk clk_bulk; unsigned int clock; unsigned int mode; #if !CONFIG_IS_ENABLED(DM_MMC) @@ -1521,14 +1522,21 @@ static int fsl_esdhc_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(CLK) /* Assigned clock already set clock */ - ret = clk_get_by_name(dev, "per", &priv->per_clk); + ret = clk_get_bulk(dev, &priv->clk_bulk); if (ret) { - printf("Failed to get per_clk\n"); + dev_err(dev, "Failed to get clks: %d\n", ret); return ret; } - ret = clk_enable(&priv->per_clk); + + ret = clk_enable_bulk(&priv->clk_bulk); if (ret) { - printf("Failed to enable per_clk\n"); + dev_err(dev, "Failed to enable clks: %d\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "per", &priv->per_clk); + if (ret) { + printf("Failed to get per_clk\n"); return ret; } -- 2.35.3

3 7

[PATCH v2] gpio: adp5585: Add SPL config for ADP5585 driver
by alice.guo＠oss.nxp.com 05 Oct '24

05 Oct '24

From: Ye Li <ye.li(a)nxp.com> So we can disable to build ADP5585 in SPL to save size Signed-off-by: Ye Li <ye.li(a)nxp.com> Signed-off-by: Alice Guo <alice.guo(a)nxp.com> Reviewed-by: Peng Fan <peng.fan(a)nxp.com> --- Changes for v2: - added my Signed-off-by drivers/gpio/Kconfig | 6 ++++++ drivers/gpio/Makefile | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 3996333fe8..1e5711663e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -700,4 +700,10 @@ config RZG2L_GPIO Support the gpio functionality of the pin function controller (PFC) on the Renesas RZ/G2L SoC family. +config SPL_ADP5585_GPIO + bool "ADP5585 GPIO driver in SPL" + depends on SPL_DM_GPIO && SPL_I2C + help + Support ADP5585 GPIO expander in SPL. + endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index da0faf0524..56c20e4c63 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -76,5 +76,5 @@ obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o obj-$(CONFIG_FTGPIO010) += ftgpio010.o -obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o +obj-$(CONFIG_$(SPL_)ADP5585_GPIO) += adp5585_gpio.o obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o -- 2.34.1

2 2

[PATCH] arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM PicoITX
by Marek Vasut 05 Oct '24

05 Oct '24

Add support for DH electronics i.MX8M Plus DHCOM SoM on PicoITX carrier board. This system is populated with serial console, EQoS ethernet, eMMC, SD, SPI NOR, LEDs and USB 3.0 host used in USB 2.0 mode on PicoITX. Matching Linux kernel patch has been posted: https://lore.kernel.org/imx/20240928234949.357893-2-marex@denx.de/ Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi | 6 + arch/arm/dts/imx8mp-dhcom-picoitx.dts | 152 ++++++++++ configs/imx8mp_dhcom_picoitx_defconfig | 273 ++++++++++++++++++ 4 files changed, 432 insertions(+) create mode 100644 arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-dhcom-picoitx.dts create mode 100644 configs/imx8mp_dhcom_picoitx_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cdb90f1d358..d69b53ce8f7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -972,6 +972,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ + imx8mp-dhcom-picoitx.dtb \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ imx8mq-pico-pi.dtb \ diff --git a/arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi new file mode 100644 index 00000000000..4e95cd0e483 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023-2024 Marek Vasut <marex(a)denx.de> + */ + +#include "imx8mp-dhcom-u-boot.dtsi" diff --git a/arch/arm/dts/imx8mp-dhcom-picoitx.dts b/arch/arm/dts/imx8mp-dhcom-picoitx.dts new file mode 100644 index 00000000000..285aaa5b6c0 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-picoitx.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023-2024 Marek Vasut <marex(a)denx.de> + * + * DHCOM iMX8MP variant: + * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E-SD-RTC-T-RGB-I-01D2 + * DHCOM PCB number: 660-200 or newer + * PicoITX PCB number: 487-600 or newer + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "imx8mp-dhcom-som.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM PicoITX"; + compatible = "dh,imx8mp-dhcom-picoitx", "dh,imx8mp-dhcom-som", + "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_YELLOW>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; +}; + +&eqos { /* First ethernet */ + pinctrl-0 = <&pinctrl_eqos_rmii>; + phy-handle = <&ethphy0f>; + phy-mode = "rmii"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>; +}; + +&ethphy0g { /* Micrel KSZ9131RNXI */ + status = "disabled"; +}; + +&ethphy0f { /* SMSC LAN8740Ai */ + status = "okay"; +}; + +&fec { + status = "disabled"; +}; + +&flexcan1 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "DHCOM-G", "", "", "", + "", "DHCOM-I", "PicoITX-HW0", "PicoITX-HW2", + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "PicoITX-HW1", "", "", "", "", + "", "", "", "", "DHCOM-INT", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "SOM-HW1", "", "", "", "", + "", "", "", "PicoITX-Out2", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "PicoITX-In2", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", + "", "", "PicoITX-In1", "PicoITX-Out1", + "", "", "", "", "", "", "", ""; +}; + +/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */ +&pcie_phy { + status = "disabled"; +}; + +&pcie { + status = "disabled"; +}; + +/* No WiFi/BT chipset on this SoM variant. */ +&uart2 { + bluetooth { + status = "disabled"; + }; +}; + +/* USB_OTG port is not routed out on PicoITX. */ +&usb3_0 { + status = "disabled"; +}; + +&usb_dwc3_0 { + status = "disabled"; +}; + +&usb3_1 { + fsl,over-current-active-low; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; +}; + +/* No WiFi/BT chipset on this SoM variant. */ +&usdhc1 { + status = "disabled"; +}; + +&iomuxc { + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * I: yellow led + */ + pinctrl-0 = <&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j + &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_m + &pinctrl_dhcom_n &pinctrl_dhcom_o &pinctrl_dhcom_p + &pinctrl_dhcom_q &pinctrl_dhcom_r &pinctrl_dhcom_s + &pinctrl_dhcom_int>; +}; diff --git a/configs/imx8mp_dhcom_picoitx_defconfig b/configs/imx8mp_dhcom_picoitx_defconfig new file mode 100644 index 00000000000..4d8ce2dba4b --- /dev/null +++ b/configs/imx8mp_dhcom_picoitx_defconfig @@ -0,0 +1,273 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xFE0000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-picoitx" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y +CONFIG_DM_RESET=y +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 +CONFIG_SPL_STACK=0x96fc00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x96fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL=y +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_DEBUG_UART_BASE=0x30860000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_ENV_OFFSET_REDUND=0xFF0000 +CONFIG_IMX_BOOTAUX=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000 +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +CONFIG_SYS_BOOTM_LEN=0x8000000 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset" +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-picoitx.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2081 +CONFIG_CONSOLE_MUX=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +# CONFIG_SPL_FIT_IMAGE_TINY is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=16384 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_SHA1SUM=y +CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MBR=y +CONFIG_CMD_MMC=y +CONFIG_CMD_BKOPS_ENABLE=y +CONFIG_MMC_SPEED_MODE_SET=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_READ=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_UUID=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_SMC=y +CONFIG_HASH_VERIFY=y +CONFIG_CMD_BTRFS=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_MTDIDS_DEFAULT="nor0=flash@0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)" +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE_AUTO=y +CONFIG_ENV_SPI_MAX_HZ=80000000 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y +CONFIG_IMX8M_DRAM_INLINE_ECC=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_TIMEOUT=y +CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +# CONFIG_INPUT is not set +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_PHY_SMSC=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_SPL_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y +CONFIG_DM_RTC=y +CONFIG_RTC_M41T62=y +CONFIG_CONS_INDEX=2 +CONFIG_DM_SERIAL=y +# CONFIG_SPL_DM_SERIAL is not set +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="DH electronics" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_FUNCTION_ACM=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y +CONFIG_IMX_WATCHDOG=y -- 2.45.2

2 2

[PATCH v2] arm64: dts: imx8mp: Add DH i.MX8MP DHCOM SoM on DRC02 carrier board
by Marek Vasut 05 Oct '24

05 Oct '24

Add support for DH electronics i.MX8MP DHCOM SoM on DRC02 carrier board. This system is populated with two ethernet ports, two CANs, RS485 and RS232, USB, capacitive buttons and an OLED display. Matching Linux kernel patch has been posted: https://lore.kernel.org/imx/20240925160343.84388-2-marex@denx.de/ Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de --- V2: Fill in lore link to kernel DT submission --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi | 6 + arch/arm/dts/imx8mp-dhcom-drc02.dts | 230 ++++++++++++++++ configs/imx8mp_dhcom_drc02_defconfig | 277 ++++++++++++++++++++ 4 files changed, 514 insertions(+) create mode 100644 arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-dhcom-drc02.dts create mode 100644 configs/imx8mp_dhcom_drc02_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b3fe3f3c535..cdb90f1d358 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -968,6 +968,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \ imx8mp-debix-model-a.dtb \ + imx8mp-dhcom-drc02.dtb \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ diff --git a/arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi new file mode 100644 index 00000000000..8a23b117d9a --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Marek Vasut <marex(a)denx.de> + */ + +#include "imx8mp-dhcom-u-boot.dtsi" diff --git a/arch/arm/dts/imx8mp-dhcom-drc02.dts b/arch/arm/dts/imx8mp-dhcom-drc02.dts new file mode 100644 index 00000000000..b3ab6e94508 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-drc02.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Marek Vasut <marex(a)denx.de> + * + * DHCOM iMX8MP variant: + * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E2-CAN2-RTC-I-01D2 + * DHCOM PCB number: 660-100 or newer + * DRC02 PCB number: 568-100 or newer + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx8mp-dhcom-som.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM on DRC02"; + compatible = "dh,imx8mp-dhcom-drc02", "dh,imx8mp-dhcom-som", + "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; +}; + +&eqos { /* First ethernet */ + pinctrl-0 = <&pinctrl_eqos_rmii>; + phy-handle = <&ethphy0f>; + phy-mode = "rmii"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>; +}; + +&ethphy0g { /* Micrel KSZ9131RNXI */ + status = "disabled"; +}; + +&ethphy0f { /* SMSC LAN8740Ai */ + status = "okay"; +}; + +&fec { /* Second ethernet */ + pinctrl-0 = <&pinctrl_fec_rmii>; + phy-handle = <&ethphy1f>; + phy-mode = "rmii"; + status = "okay"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>, <0>; +}; + +&ethphy1f { /* SMSC LAN8740Ai */ + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "DRC02-In1", "", "", "", "", "DHCOM-I", "DRC02-HW2", "DRC02-HW0", + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the i.MX8 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <13 0>; /* GPIO Q */ + line-name = "rs485-rx-en"; + output-low; + }; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "DHCOM-O", "DHCOM-N", "", "SOM-HW1", "", "", "", "", + "", "", "", "", "DRC02-In2", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "SOM-HW0", "", + "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", + "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "SOM-HW1", "", "", "", "", + "", "", "", "DRC02-Out2", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "DHCOM-C", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "DHCOM-E", "DRC02-Out1", + "", "", "", "", "", "", "", ""; +}; + +&i2c3 { + /* Resistive touch controller not populated on this one SoM variant. */ + touchscreen@49 { + status = "disabled"; + }; +}; + +&pcie_phy { + status = "disabled"; +}; + +&pcie { + status = "disabled"; +}; + +/* Console UART */ +&pinctrl_uart1 { + fsl,pins = < + /* No pull-ups on DRC02, enable in-SoC pull-ups */ + MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x149 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x149 + >; +}; + +&pinctrl_uart3 { + fsl,pins = < + /* No pull-ups on DRC02, enable in-SoC pull-ups */ + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x149 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x149 + >; +}; + +&uart1 { + /* + * Due to the use of CAN2 the signals for CAN2 Tx and Rx are routed to + * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs + * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS. + */ + /delete-property/ uart-has-rtscts; + cts-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* GPIO M */ + pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; + pinctrl-names = "default"; + rts-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ +}; + +&uart3 { + /* + * On DRC02 this UART is used as RS485 interface and RS485_TX_En is + * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property + * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via + * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 + * node above. + */ + /delete-property/ uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + pinctrl-0 = <&pinctrl_uart3 &pinctrl_dhcom_p &pinctrl_dhcom_q>; + pinctrl-names = "default"; + rts-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* GPIO P */ +}; + +/* No WiFi/BT chipset on this SoM variant. */ +&uart2 { + bluetooth { + status = "disabled"; + }; +}; + +/* USB_OTG port is not routed out on DRC02. */ +&usb3_0 { + status = "disabled"; +}; + +&usb_dwc3_0 { + status = "disabled"; +}; + +/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */ +&usb3_1 { + fsl,disable-port-power-control; + fsl,permanently-attached; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; +}; + +/* No WiFi/BT chipset on this SoM variant. */ +&usdhc1 { + status = "disabled"; +}; + +&iomuxc { + /* + * GPIO I is connected to UART1_RTS + * GPIO M is connected to UART1_CTS + * GPIO P is connected to RS485_TX_En + * GPIO Q is connected to RS485_RX_En + */ + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j + &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_n + &pinctrl_dhcom_o &pinctrl_dhcom_r &pinctrl_dhcom_s + &pinctrl_dhcom_int>; +}; diff --git a/configs/imx8mp_dhcom_drc02_defconfig b/configs/imx8mp_dhcom_drc02_defconfig new file mode 100644 index 00000000000..7c684d3bea5 --- /dev/null +++ b/configs/imx8mp_dhcom_drc02_defconfig @@ -0,0 +1,277 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xFE0000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-drc02" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y +CONFIG_DM_RESET=y +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 +CONFIG_SPL_STACK=0x96fc00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x96fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL=y +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_DEBUG_UART_BASE=0x30860000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_ENV_OFFSET_REDUND=0xFF0000 +CONFIG_IMX_BOOTAUX=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000 +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +CONFIG_SYS_BOOTM_LEN=0x8000000 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="" +CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-drc02.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2081 +CONFIG_CONSOLE_MUX=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +# CONFIG_SPL_FIT_IMAGE_TINY is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=16384 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_SHA1SUM=y +CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MBR=y +CONFIG_CMD_MMC=y +CONFIG_CMD_BKOPS_ENABLE=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_READ=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_UUID=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_SMC=y +CONFIG_HASH_VERIFY=y +CONFIG_CMD_BTRFS=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_MTDIDS_DEFAULT="nor0=flash@0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)" +CONFIG_MMC_SPEED_MODE_SET=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE_AUTO=y +CONFIG_ENV_SPI_MAX_HZ=80000000 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y +CONFIG_SPL_DM=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y +CONFIG_IMX8M_DRAM_INLINE_ECC=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_TIMEOUT=y +CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +# CONFIG_INPUT is not set +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ANEG_TIMEOUT=20000 +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_PHY_SMSC=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PHY_IMX8M_PCIE=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_SPL_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y +CONFIG_DM_RTC=y +CONFIG_RTC_M41T62=y +CONFIG_CONS_INDEX=2 +CONFIG_DM_SERIAL=y +# CONFIG_SPL_DM_SERIAL is not set +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="DH electronics" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_FUNCTION_ACM=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y +CONFIG_IMX_WATCHDOG=y -- 2.45.2

2 2

[PATCH] sandbox: i2c: Make sure phandle dependency is probed
by Marek Vasut 05 Oct '24

05 Oct '24

This driver depends on i2c emulator via DT phandle. Make sure the dependency is probed before this driver is probed, not when it is first used during transfer. This fixes the following i2c_emul_find() error: " $ ./u-boot -Dc "" ... i2c_emul_find() No emulators for device 'sandbox_pmic' sandbox_pmic_write() write error to device: 0000000018c568d0 register: 0x0! out_set_value() PMIC write failed: -5 i2c_emul_find() No emulators for device 'sandbox_pmic' sandbox_pmic_write() write error to device: 0000000018c568d0 register: 0x0! out_set_value() PMIC write failed: -5 ... " Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Heiko Schocher <hs(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)lists.denx.de --- drivers/i2c/sandbox_i2c.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c index 74bb5e93397..9a39ac14fb4 100644 --- a/drivers/i2c/sandbox_i2c.c +++ b/drivers/i2c/sandbox_i2c.c @@ -80,6 +80,14 @@ static int sandbox_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, return ops->xfer(emul, msg, nmsgs); } +static int sandbox_i2c_probe(struct udevice *dev) +{ + struct udevice *emul; + + return uclass_get_device_by_phandle(UCLASS_I2C_EMUL, dev, + "sandbox,emul", &emul); +} + static const struct dm_i2c_ops sandbox_i2c_ops = { .xfer = sandbox_i2c_xfer, }; @@ -95,4 +103,5 @@ U_BOOT_DRIVER(sandbox_i2c) = { .of_match = sandbox_i2c_ids, .ops = &sandbox_i2c_ops, .priv_auto = sizeof(struct sandbox_i2c_priv), + .probe = sandbox_i2c_probe, }; -- 2.45.2

2 3

RE: [PATCH v1 00/12] Support OF_UPSTREAM for StarFive JH7110
by Hal Feng 05 Oct '24

05 Oct '24

> On 01.10.24 01:56, Heinrich Schuchardt wrote: > On 30.09.24 17:59, Hal Feng wrote: > > This patchset add OF_STREAM support for StarFive JH7110 based boards. > > All the JH7110 based boards can use the DT from upstreaming linux kernel. > > The v1.3b board device tree is set as the default device tree. > > > > This patchset should be applied after the DT from dts/upstream/ > > updating to the latest version. > > Hello Hal, > > Thanks a lot for making the move to upstream device-trees for JH7110 based > boards. > > With the current patchset you suggest to specify the relevant device-tree > when building, e.g. > > make > OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin \ > DEVICE_TREE=starfive/jh7110-milkv-mars > > Another approach would be to build all device-trees into U-Boot and use the > EEPROM information to select the correct one at runtime. > > This approach is selected by Wandboard defconfig and other boards by > specifying CONFIG_MULTI_DTB_FIT and CONFIG_OF_LIST. The choice of the > device-tree is made in board_fit_config_name_match(). > > The advantage from the standpoint of a Linux distro would be that one distro > image can be provided that will run on all JH7110 boards. That is a good idea. I will try to do this after my five-day vacation. By the way, I wanna know whether jh7110-milkv-mars-cm.dts and jh7110-milkv-mars-cm-lite.dts are in the process of upstreaming? I don't see them in the kernel mainline. Thanks for your suggestions. Best regards, Hal

2 1

[PATCH 1/3] dts: Deduplicate dtbs target
by Marek Vasut 05 Oct '24

05 Oct '24

The dtbs: target is almost identical in all architecture Makefiles. All architecture Makefiles include scripts/Makefile.dts . Deduplicate the dtbs: target into scripts/Makefile.dts . No functional change. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Caleb Connolly <caleb.connolly(a)linaro.org> Cc: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Cc: Jonas Karlman <jonas(a)kwiboo.se> Cc: Lothar Rubusch <l.rubusch(a)gmail.com> Cc: Michal Simek <michal.simek(a)amd.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Cc: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Sumit Garg <sumit.garg(a)linaro.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de --- arch/arc/dts/Makefile | 9 +-------- arch/arm/dts/Makefile | 8 -------- arch/m68k/dts/Makefile | 9 +-------- arch/microblaze/dts/Makefile | 9 +-------- arch/mips/dts/Makefile | 8 -------- arch/nios2/dts/Makefile | 9 +-------- arch/powerpc/dts/Makefile | 8 -------- arch/riscv/dts/Makefile | 9 +-------- arch/sandbox/dts/Makefile | 9 +-------- arch/sh/dts/Makefile | 8 -------- arch/x86/dts/Makefile | 8 -------- arch/xtensa/dts/Makefile | 8 -------- dts/upstream/src/arm/Makefile | 8 -------- dts/upstream/src/arm64/Makefile | 8 -------- dts/upstream/src/xtensa/Makefile | 8 -------- scripts/Makefile.dts | 8 ++++++++ 16 files changed, 14 insertions(+), 120 deletions(-) diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index 532a8131c59..fe6ad7b849a 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -10,12 +10,5 @@ dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cdb90f1d358..5976ebd09fc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1304,16 +1304,8 @@ dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 DTC_FLAGS_imx8mp-dhcom-som-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb *.dtbo *_HS diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index 7988522eb98..8b354b9c570 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -20,12 +20,5 @@ dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile index 427a8f9aaca..9be902d3bb1 100644 --- a/arch/microblaze/dts/Makefile +++ b/arch/microblaze/dts/Makefile @@ -4,12 +4,5 @@ dtb-y += $(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)).dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 14fbce597b9..752e771514f 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -39,13 +39,5 @@ dtb-$(CONFIG_SOC_SERVAL) += serval_pcb105.dtb serval_pcb106.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/nios2/dts/Makefile b/arch/nios2/dts/Makefile index 2b29fa90f6c..d77db9762a1 100644 --- a/arch/nios2/dts/Makefile +++ b/arch/nios2/dts/Makefile @@ -4,12 +4,5 @@ dtb-y += $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%).dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 321c644804e..766b0c05951 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -35,13 +35,5 @@ dtb-$(CONFIG_TARGET_CMPCPRO) += cmpcpro.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index c4c44057bad..f3dfd751cb4 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -15,12 +15,5 @@ dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index f810b4752f5..1c9fb4a4566 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -10,12 +10,5 @@ dtb-$(CONFIG_CMD_EXTENSION) += overlay0.dtbo overlay1.dtbo include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb *.dtbo diff --git a/arch/sh/dts/Makefile b/arch/sh/dts/Makefile index 144fd3e7d22..e9153e42534 100644 --- a/arch/sh/dts/Makefile +++ b/arch/sh/dts/Makefile @@ -2,13 +2,5 @@ dtb-y += sh7751-r2dplus.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb *_HS diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index cd77f4c4e81..9a46726e026 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -24,12 +24,4 @@ dtb-y += bayleybay.dtb \ include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - DTC_FLAGS += -R 4 -p $(if $(CONFIG_EFI_APP),0x8000,0x1000) - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/xtensa/dts/Makefile b/arch/xtensa/dts/Makefile index c22c50ac4e5..aa582b85e5c 100644 --- a/arch/xtensa/dts/Makefile +++ b/arch/xtensa/dts/Makefile @@ -4,12 +4,4 @@ dtb-$(CONFIG_XTENSA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - DTC_FLAGS += - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/dts/upstream/src/arm/Makefile b/dts/upstream/src/arm/Makefile index 9a8f6aa3584..c86a2be5d85 100644 --- a/dts/upstream/src/arm/Makefile +++ b/dts/upstream/src/arm/Makefile @@ -2,13 +2,5 @@ include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := */*.dtb */*.dtbo diff --git a/dts/upstream/src/arm64/Makefile b/dts/upstream/src/arm64/Makefile index 26a83d3d29d..b6db0dc6b26 100644 --- a/dts/upstream/src/arm64/Makefile +++ b/dts/upstream/src/arm64/Makefile @@ -2,17 +2,9 @@ include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 ifdef CONFIG_RCAR_64 DTC_FLAGS += -R 4 -p 0x1000 endif - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := */*.dtb */*.dtbo diff --git a/dts/upstream/src/xtensa/Makefile b/dts/upstream/src/xtensa/Makefile index 2a81acb32bc..c86a2be5d85 100644 --- a/dts/upstream/src/xtensa/Makefile +++ b/dts/upstream/src/xtensa/Makefile @@ -2,13 +2,5 @@ include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb *.dtbo */*.dtb */*.dtbo diff --git a/scripts/Makefile.dts b/scripts/Makefile.dts index 790f3c508f1..1fe142f2bbf 100644 --- a/scripts/Makefile.dts +++ b/scripts/Makefile.dts @@ -14,3 +14,11 @@ dtb-vendor_dts := $(patsubst %.dts,%.dtb,$(wildcard $(dt_dir)/$(subst ",,$(CONFI dtb-y += $(subst $(dt_dir)/,,$(dtb-vendor_dts)) endif + +targets += $(dtb-y) + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb *.dtbo */*.dtb */*.dtbo *_HS -- 2.45.2

4 14

[PATCH] ARM: stm32: Update MAINTAINERS file globs for STM32MP DHSOM
by Marek Vasut 05 Oct '24

05 Oct '24

Update the MAINTAINERS file glob to cover all of STM32MP DHSOM related files. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- board/dhelectronics/dh_stm32mp1/MAINTAINERS | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS b/board/dhelectronics/dh_stm32mp1/MAINTAINERS index 865588f5b8b..d6c33c15aac 100644 --- a/board/dhelectronics/dh_stm32mp1/MAINTAINERS +++ b/board/dhelectronics/dh_stm32mp1/MAINTAINERS @@ -2,8 +2,7 @@ DH_STM32MP1_PDK2 BOARD M: Marek Vasut <marex(a)denx.de> L: u-boot(a)dh-electronics.com S: Maintained -F: arch/arm/dts/stm32mp15xx-dhcom* +F: arch/arm/dts/stm32mp*dhco* F: board/dhelectronics/dh_stm32mp1/ -F: configs/stm32mp15_dhcom_basic_defconfig -F: configs/stm32mp15_dhcor_basic_defconfig +F: configs/stm32*_dhco*defconfig F: include/configs/stm32mp15_dh_dhsom.h -- 2.45.2

2 2

[PATCH 0/3] Anbernic RGxx3 Bootloader Fixes
by Chris Morgan 04 Oct '24

04 Oct '24

From: Chris Morgan <macromorgan(a)hotmail.com> Update the Anbernic RGxx3 "device" to use upstream device-trees, add logic to detect a different vdd_cpu regulator, and implement a fix to allow the panel auto-detection to run when using mainline A-TF. Note that *Linux* still cannot use mainline A-TF because of the missing SCMI clock and reset functionality, but this patch series at least ensures that this board can once Linux is ready. Chris Morgan (3): board: rockchip: Convert Anbernic RGxx3 to OF_UPSTREAM board: rockchip: Add vdd_cpu reg fixup for RGXX3 Series board: rockchip: Fix panel detection for mainline A-TF .../dts/rk3566-anbernic-rg353p-u-boot.dtsi | 34 ++ .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 52 --- arch/arm/dts/rk3566-anbernic-rgxx3.dts | 28 -- board/anbernic/rgxx3_rk3566/MAINTAINERS | 4 +- board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 372 +++++++++++++++--- configs/anbernic-rgxx3-rk3566_defconfig | 12 +- 6 files changed, 354 insertions(+), 148 deletions(-) create mode 100644 arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi delete mode 100644 arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi delete mode 100644 arch/arm/dts/rk3566-anbernic-rgxx3.dts -- 2.34.1

3 9

[PULL] Please pull qcom/qcom-next
by Caleb Connolly 04 Oct '24

04 Oct '24

Various improvements and fixes for Qualcomm * Initial UFS PHY driver * Support for SM8150 (clock and pinctrl) * Allow writing configuration to PMIC GPIOs again * Support for configuring "special" pins (e.g. UFS reset or sdhc pins) * Support for "clk dump" command to decode various clocks. CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/22527 --- The following changes since commit 00292c6b39b3f7dcb34e8c3ae6ef276ac862a146: Merge tag 'u-boot-dfu-next-20241003' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next (2024-10-03 16:09:40 -0600) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-snapdragon.git qcom-next for you to fetch changes up to 04584089e12e34aa91ef06aeb91b1550facb0312: clk/qcom: sm8250: add debug data (2024-10-04 14:57:04 +0200) ---------------------------------------------------------------- Bhupesh Sharma (2): phy: qcom: Import QMP phy related header files from Linux phy: qcom: Add QMP UFS PHY driver Caleb Connolly (5): Revert "gpio: qcom_pmic: add a quirk to skip GPIO configuration" clk/qcom: implement clk dump clk/qcom: sdm845: add dump data clk/qcom: sm6115: add debug data clk/qcom: sm8250: add debug data Julius Lehmann (3): clk: qcom: add driver for SM8150 SoC pinctrl: qcom: add driver for SM8150 SoC config: qcom: add sm8150 to qcom_defconfig Neil Armstrong (2): gpio: msm: add support for special pins pinctr: qcom: sm8250: add special pins pins configuration data configs/qcom_defconfig | 2 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-qcom.c | 119 +++ drivers/clk/qcom/clock-qcom.h | 6 + drivers/clk/qcom/clock-sdm845.c | 93 ++ drivers/clk/qcom/clock-sm6115.c | 63 ++ drivers/clk/qcom/clock-sm8150.c | 319 ++++++ drivers/clk/qcom/clock-sm8250.c | 115 ++ drivers/gpio/msm_gpio.c | 101 +- drivers/gpio/qcom_pmic_gpio.c | 27 +- drivers/phy/qcom/Kconfig | 6 + drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v2.h | 25 + drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v3.h | 21 + drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v4.h | 31 + drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v5.h | 32 + drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v6.h | 38 + drivers/phy/qcom/phy-qcom-qmp-pcs-v2.h | 43 + drivers/phy/qcom/phy-qcom-qmp-pcs-v3.h | 145 +++ drivers/phy/qcom/phy-qcom-qmp-pcs-v4.h | 135 +++ drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v3.h | 111 ++ drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v4.h | 123 +++ drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v6.h | 89 ++ drivers/phy/qcom/phy-qcom-qmp-qserdes-com.h | 140 +++ drivers/phy/qcom/phy-qcom-qmp-qserdes-pll.h | 69 ++ .../phy/qcom/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 52 + drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v3.h | 68 ++ drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v4.h | 233 ++++ drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx.h | 205 ++++ drivers/phy/qcom/phy-qcom-qmp-ufs.c | 1116 ++++++++++++++++++++ drivers/phy/qcom/phy-qcom-qmp.h | 115 ++ drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8150.c | 156 +++ drivers/pinctrl/qcom/pinctrl-sm8250.c | 42 +- 36 files changed, 3824 insertions(+), 36 deletions(-) create mode 100644 drivers/clk/qcom/clock-sm8150.c create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v2.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v3.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v4.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v5.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v6.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-v2.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-v3.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-v4.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v3.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v4.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v6.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-com.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-pll.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-ufs-v6.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v3.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v4.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-ufs.c create mode 100644 drivers/phy/qcom/phy-qcom-qmp.h create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c

2 1