October 2024 - U-Boot

[PATCH v2 0/2] Add support for Cool Pi GenBook
by Andy Yan 23 Oct '24

23 Oct '24

Support for Cool Pi GenBook is landing Linux 6.12-rc1, so also add the support for u-boot here. Changes in v2: - Cherry pick it from https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebas… - split the dts to a separate commit - rename to genbook_cm5_rk3588 - move readme to doc/board, and write as reStructuredText format - alphabetically reorder - update doc/board/rockchip Andy Yan (2): arm64: dts: rockchip: Add support for rk3588 based Cool Pi CM5 GenBook board: rockchip: Add support for rk3588 GenBook .../dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi | 70 ++++ arch/arm/mach-rockchip/rk3588/Kconfig | 19 + board/coolpi/genbook_cm5_rk3588/Kconfig | 12 + board/coolpi/genbook_cm5_rk3588/MAINTAINERS | 7 + configs/coolpi-genbook-cm5-rk3588_defconfig | 104 ++++++ doc/board/coolpi/genbook_cm5_rk3588.rst | 69 ++++ doc/board/coolpi/index.rst | 9 + doc/board/rockchip/rockchip.rst | 1 + .../rockchip/rk3588-coolpi-cm5-genbook.dts | 349 ++++++++++++++++++ include/configs/genbook-cm5-rk3588.h | 28 ++ 10 files changed, 668 insertions(+) create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi create mode 100644 board/coolpi/genbook_cm5_rk3588/Kconfig create mode 100644 board/coolpi/genbook_cm5_rk3588/MAINTAINERS create mode 100644 configs/coolpi-genbook-cm5-rk3588_defconfig create mode 100644 doc/board/coolpi/genbook_cm5_rk3588.rst create mode 100644 doc/board/coolpi/index.rst create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts create mode 100644 include/configs/genbook-cm5-rk3588.h -- 2.34.1

2 4

[PATCH] watchdog: davinci: add support for DaVinci DM644x/DM646x processors
by Marcus Folkesson 23 Oct '24

23 Oct '24

Watchdog driver for DaVinci DM644x/DM646x processors. Signed-off-by: Marcus Folkesson <marcus.folkesson(a)gmail.com> --- MAINTAINERS | 5 ++ drivers/watchdog/Kconfig | 9 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/davinci_wdt.c | 151 +++++++++++++++++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 drivers/watchdog/davinci_wdt.c diff --git a/MAINTAINERS b/MAINTAINERS index 8dcce886b8..53aac8a0c3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -854,6 +854,11 @@ F: cmd/cyclic.c F: common/cyclic.c F: include/cyclic.h +DAVINCI WATCHDOG +M: Marcus Folkesson <marcus.folkesson(a)gmail.com> +S: Maintained +F: drivers/watchdog/davinci_wdt.c + DFU M: Lukasz Majewski <lukma(a)denx.de> S: Maintained diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b5ac8f7f50..e38acb0fe2 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -161,6 +161,15 @@ config WDT_CORTINA This driver support all CPU ISAs supported by Cortina Access CAxxxx SoCs. +config WDT_DAVINCI + tristate "DaVinci watchdog timer support" + depends on WDT + depends on ARCH_DAVINCI || ARCH_KEYSTONE + select WATCHDOG_CORE + help + Support for the watchdog timer in the DaVinci DM644x/DM646x + or Keystone processors. + config WDT_GPIO bool "External gpio watchdog support" depends on WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 446d961d7d..ab454924c3 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o +obj-$(CONFIG_WDT_DAVINCI) += davinci_wdt.o obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c new file mode 100644 index 0000000000..e822621fd3 --- /dev/null +++ b/drivers/watchdog/davinci_wdt.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Watchdog driver for DaVinci DM644x/DM646x processors + * + * Copyright 2024 Marcus Folkesson <marcus.folkesson(a)gmail.com> + */ + +#include <asm/global_data.h> +#include <asm/io.h> +#include <common.h> +#include <clk.h> +#include <dm/device.h> +#include <dm/fdtaddr.h> +#include <dm/read.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <linux/err.h> +#include <log.h> +#include <watchdog.h> +#include <wdt.h> + +/* Timer register set definition */ +#define PID12 (0x0) +#define EMUMGT (0x4) +#define TIM12 (0x10) +#define TIM34 (0x14) +#define PRD12 (0x18) +#define PRD34 (0x1C) +#define TCR (0x20) +#define TGCR (0x24) +#define WDTCR (0x28) + +/* TCR bit definitions */ +#define ENAMODE12 GENMASK(7, 6) +#define ENAMODE12_DISABLED (0) +#define ENAMODE12_ONESHOT (1) +#define ENAMODE12_PERIODIC (2) + +/* TGCR bit definitions */ +#define TIM12RS_UNRESET BIT(0) +#define TIM34RS_UNRESET BIT(1) +#define TIMMODE GENMASK(3, 2) +#define TIMMODE_64BIT_WDOG (2) + +/* WDTCR bit definitions */ +#define WDEN BIT(14) +#define WDFLAG BIT(15) +#define WDKEY_SEQ0 (0xa5c6 << 16) +#define WDKEY_SEQ1 (0xda7e << 16) + +DECLARE_GLOBAL_DATA_PTR; + +struct davinci_wdt_priv { + void __iomem *reg; + unsigned long clk_rate; +}; + +static int davinci_wdt_reset(struct udevice *dev) +{ + struct davinci_wdt_priv *priv = dev_get_priv(dev); + + /* put watchdog in service state */ + writel(WDKEY_SEQ0 | WDEN, priv->reg + WDTCR); + /* put watchdog in active state */ + writel(WDKEY_SEQ1 | WDEN, priv->reg + WDTCR); + + return 0; +} + +static int davinci_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + u32 tgcr; + u32 timer_margin; + struct davinci_wdt_priv *priv = dev_get_priv(dev); + + /* disable, internal clock source */ + writel(0, priv->reg + TCR); + + /* reset timer, set mode to 64-bit watchdog, and unreset */ + writel(0, priv->reg + TGCR); + tgcr = FIELD_PREP(TIMMODE, TIMMODE_64BIT_WDOG) | TIM12RS_UNRESET | TIM34RS_UNRESET; + writel(tgcr, priv->reg + TGCR); + + /* clear counter regs */ + writel(0, priv->reg + TIM12); + writel(0, priv->reg + TIM34); + + /* set timeout period */ + timeout = timeout / 1000; + timer_margin = (((u64)timeout * priv->clk_rate) & 0xffffffff); + writel(timer_margin, priv->reg + PRD12); + timer_margin = (((u64)timeout * priv->clk_rate) >> 32); + writel(timer_margin, priv->reg + PRD34); + + /* enable run continuously */ + writel(FIELD_PREP(ENAMODE12, ENAMODE12_PERIODIC), priv->reg + TCR); + + return davinci_wdt_reset(dev); +} + +static int davinci_wdt_expire_now(struct udevice *dev, ulong flags) +{ + davinci_wdt_start(dev, 0, flags); + + return 0; +} + +static int davinci_wdt_probe(struct udevice *dev) +{ + debug("%s: Probing wdt%u (davinci-wdt)\n", __func__, dev_seq(dev)); + + return 0; +} + +static int davinci_wdt_of_to_plat(struct udevice *dev) +{ + struct davinci_wdt_priv *priv = dev_get_priv(dev); + struct clk clk; + + priv->reg = (void __iomem *)dev_read_addr(dev); + if (IS_ERR(priv->reg)) + return PTR_ERR(priv->reg); + + if (!clk_get_by_index(dev, 0, &clk)) + priv->clk_rate = clk_get_rate(&clk); + else + priv->clk_rate = 24000000; + + return 0; +} + +static const struct wdt_ops davinci_wdt_ops = { + .start = davinci_wdt_start, + .reset = davinci_wdt_reset, + .expire_now = davinci_wdt_expire_now, +}; + +static const struct udevice_id davinci_wdt_ids[] = { + { .compatible = "ti,davinci-wdt" }, + {} +}; + +U_BOOT_DRIVER(davinci_wdt) = { + .name = "davinci_wdt", + .id = UCLASS_WDT, + .of_match = davinci_wdt_ids, + .probe = davinci_wdt_probe, + .priv_auto = sizeof(struct davinci_wdt_priv), + .of_to_plat = davinci_wdt_of_to_plat, + .ops = &davinci_wdt_ops, +}; -- 2.46.0

2 1

[PATCH] watchdog: introduce separate SPL symbol for WDT_GPIO
by Rasmus Villemoes 23 Oct '24

23 Oct '24

Currently, enabling WDT_GPIO on a board which uses SPL, but does not have SPL_WDT, SPL_DM_GPIO or SPL_OF_CONTROL enabled, breaks the build. Make it possible to use the WDT_GPIO driver on such boards by introducing a separate symbol controlling whether the driver is built for SPL. Make it default to WDT_GPIO such that boards that already have it enabled and all the SPL prerequisites satisfied will continue to have it in SPL. Signed-off-by: Rasmus Villemoes <ravi(a)prevas.dk> --- drivers/watchdog/Kconfig | 9 +++++++++ drivers/watchdog/Makefile | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0c3e9913318..18028269b9e 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -178,6 +178,15 @@ config WDT_GPIO doc/device-tree-bindings/watchdog/gpio-wdt.txt for information on how to describe the watchdog in device tree. +config SPL_WDT_GPIO + bool "External gpio watchdog support in SPL" + depends on SPL_WDT + depends on SPL_DM_GPIO + depends on SPL_OF_REAL + default WDT_GPIO + help + Support for external watchdog fed by toggling a gpio in SPL. + config WDT_MAX6370 bool "MAX6370 watchdog timer support" depends on WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 7b39adcf0ff..a450c33b3ad 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -30,7 +30,7 @@ obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o -obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o +obj-$(CONFIG_$(SPL_TPL_)WDT_GPIO) += gpio_wdt.o obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o obj-$(CONFIG_WDT_MCF) += mcf_wdt.o obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o -- 2.46.2

3 3

[PATCH 00/13] disentangling cyclic API from schedule()
by Rasmus Villemoes 23 Oct '24

23 Oct '24

These patches are part of a longer-term plan to properly deal with the HW_WATCHDOG vs WATCHDOG dichotomy, and getting rid of the legacy HW_WATCHDOG concept completely. As part of that, clean up which headers include other headers. While schedule(), the artist formerly known as WATCHDOG_RESET(), is obviously called all over the tree, very few TUs make use of the cyclic API (cyclic_register etc.). And there's really no reason at all for global_data.h to include cyclic.h - except that some places implicitly rely on getting their declaration of schedule() through that include. So this introduces a separate mostly trivial header that just serves to declare schedule(). Then we can get rid of things that include cyclic.h just to get that declaration. A next, mostly mechanical step, could be to change almost all includes of watchdog.h (which most TUs that used to have a WATCHDOG_RESET() invocation has) to u-boot/schedule.h, because again, most of those TUs are not really concerned with implementing init_func_watchdog_init or need to call it. But that is for later. CI seems happy: https://github.com/u-boot/u-boot/pull/673 Rasmus Villemoes (13): doc: cyclic: remove reference to WATCHDOG_RESET cyclic: introduce u-boot/schedule.h led: include cyclic.h in led_sw_blink.c m68k: asm/ptrace.h: include linux/types.h fs/cramfs: use schedule instead of cyclic_run as callback test: dm: wdt: replace cyclic_run() by schedule() cyclic: make cyclic_run static watchdog.h: change include of cyclic.h to u-boot/schedule.h lib/sha*: include u-boot/schedule.h instead of cyclic.h i2c: rzg2l: include u-boot/schedule.h ddr: altera: include u-boot/schedule.h boot: cedit: include u-boot/schedule.h global_data.h: remove unnecesary include of cyclic.h arch/m68k/include/asm/ptrace.h | 2 ++ boot/cedit.c | 1 + common/cyclic.c | 3 ++- doc/develop/cyclic.rst | 10 +++++----- drivers/ddr/altera/sdram_n5x.c | 1 + drivers/ddr/altera/sdram_soc64.c | 1 + drivers/i2c/rz_riic.c | 1 + drivers/led/led_sw_blink.c | 1 + fs/cramfs/uncompress.c | 4 ++-- include/asm-generic/global_data.h | 1 - include/cyclic.h | 24 +----------------------- include/u-boot/schedule.h | 24 ++++++++++++++++++++++++ include/watchdog.h | 2 +- lib/sha1.c | 2 +- lib/sha256.c | 2 +- lib/sha512.c | 2 +- test/dm/wdt.c | 10 +++++----- 17 files changed, 50 insertions(+), 41 deletions(-) create mode 100644 include/u-boot/schedule.h -- 2.46.2

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[PATCH] drivers: watchdog: Add DaVinci's watchdog support
by Bastien Curutchet 23 Oct '24

23 Oct '24

Add support for the DaVinci's watchdog timer Signed-off-by: Bastien Curutchet <bastien.curutchet(a)bootlin.com> --- drivers/watchdog/Kconfig | 7 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/davinci_wdt.c | 131 +++++++++++++++++++++++++++++++++ 3 files changed, 139 insertions(+) create mode 100644 drivers/watchdog/davinci_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0c3e991331..a1c50b3f1f 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -169,6 +169,13 @@ config WDT_CORTINA This driver support all CPU ISAs supported by Cortina Access CAxxxx SoCs. +config WDT_DAVINCI + bool "DaVinci watchdog timer support" + depends on WDT + help + Select this to enable the watchdog timer for DaVinci SoCs such as the + OMAP-L138. + config WDT_GPIO bool "External gpio watchdog support" depends on WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 7b39adcf0f..ad3053998a 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o +obj-$(CONFIG_WDT_DAVINCI) += davinci_wdt.o obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c new file mode 100644 index 0000000000..fa8d7842e9 --- /dev/null +++ b/drivers/watchdog/davinci_wdt.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DaVinci Watchdog driver + * + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <wdt.h> + +/* Control Register */ +#define DAVINCI_WDT_ID 0x00 +#define DAVINCI_WDT_TIM12 0x10 +#define DAVINCI_WDT_TIM34 0x14 +#define DAVINCI_WDT_PRD12 0x18 +#define DAVINCI_WDT_PRD34 0x1C +#define DAVINCI_WDT_TCR 0x20 +#define DAVINCI_WDT_TGCR 0x24 +#define DAVINCI_WDT_WDTCR 0x28 + +#define DAVINCI_TCR_CONT_EN BIT(7) + +#define DAVINCI_TGCR_PLUSEN BIT(4) +#define DAVINCI_TGCR_WDT_MODE BIT(3) +#define DAVINCI_TGCR_TIM34RS BIT(1) +#define DAVINCI_TGCR_TIM12RS BIT(0) + +#define DAVINCI_WDTCR_INVALID_KEY (0x5555 << 16) +#define DAVINCI_WDTCR_WDKEY0 (0xA5C6 << 16) +#define DAVINCI_WDTCR_WDKEY1 (0xDA7E << 16) +#define DAVINCI_WDTCR_WDFLAG BIT(15) +#define DAVINCI_WDTCR_WDEN BIT(14) + +#define DEFAULT_THRESHOLD 0xA03200000 + +struct davinci_wdt_priv { + void __iomem *base; + struct clk *ref_clk; +}; + +static int davinci_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct davinci_wdt_priv *priv = dev_get_priv(dev); + ulong rate = clk_get_rate(priv->ref_clk); + u64 threshold; + + if (!rate) + threshold = DEFAULT_THRESHOLD; + else + threshold = rate * timeout_ms / 1000; + + /* Reset control registers */ + writel(0, priv->base + DAVINCI_WDT_TCR); + writel(0, priv->base + DAVINCI_WDT_TGCR); + + /* Enable watchdog mode and timers */ + writel(DAVINCI_TGCR_WDT_MODE | DAVINCI_TGCR_TIM12RS | DAVINCI_TGCR_TIM34RS, + priv->base + DAVINCI_WDT_TGCR); + + /* Reset counters */ + writel(0, priv->base + DAVINCI_WDT_TIM12); + writel(0, priv->base + DAVINCI_WDT_TIM34); + + /* Set timeout threshold */ + writel(threshold & 0xFFFFFFFF, priv->base + DAVINCI_WDT_PRD12); + writel(threshold >> 32, priv->base + DAVINCI_WDT_PRD34); + + /* Enable counter */ + writel(DAVINCI_TCR_CONT_EN, priv->base + DAVINCI_WDT_TCR); + + /* Go to watchdog's active state */ + writel(DAVINCI_WDTCR_WDEN | DAVINCI_WDTCR_WDKEY0, priv->base + DAVINCI_WDT_WDTCR); + writel(DAVINCI_WDTCR_WDEN | DAVINCI_WDTCR_WDKEY1, priv->base + DAVINCI_WDT_WDTCR); + + return 0; +} + +static int davinci_wdt_expire_now(struct udevice *dev, ulong flags) +{ + struct davinci_wdt_priv *priv = dev_get_priv(dev); + + writel(DAVINCI_WDTCR_INVALID_KEY, priv->base + DAVINCI_WDT_WDTCR); + + return 0; +} + +static int davinci_wdt_restart(struct udevice *dev) +{ + struct davinci_wdt_priv *priv = dev_get_priv(dev); + + writel(DAVINCI_WDTCR_WDEN | DAVINCI_WDTCR_WDKEY0, priv->base + DAVINCI_WDT_WDTCR); + writel(DAVINCI_WDTCR_WDEN | DAVINCI_WDTCR_WDKEY1, priv->base + DAVINCI_WDT_WDTCR); + + return 0; +} + +static int davinci_wdt_probe(struct udevice *dev) +{ + struct davinci_wdt_priv *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EFAULT; + + priv->ref_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(priv->ref_clk)) + return PTR_ERR(priv->ref_clk); + + return 0; +} + +static const struct wdt_ops davinci_wdt_ops = { + .start = davinci_wdt_start, + .reset = davinci_wdt_restart, + .expire_now = davinci_wdt_expire_now, +}; + +static const struct udevice_id davinci_wdt_ids[] = { + {.compatible = "ti,davinci-wdt"}, + {} +}; + +U_BOOT_DRIVER(davinci_wdt) = { + .name = "davinci_wdt", + .id = UCLASS_WDT, + .probe = davinci_wdt_probe, + .of_match = davinci_wdt_ids, + .ops = &davinci_wdt_ops, + .priv_auto = sizeof(struct davinci_wdt_priv), +}; -- 2.46.0

2 2

[PATCH] watchdog: gpio_wdt: add support for stoppable devices
by Rasmus Villemoes 23 Oct '24

23 Oct '24

Back when I added this driver in commit 2ac8490412c9, I wrote The corresponding linux driver apparently has support for some watchdog circuits which can be disabled by tri-stating the gpio, but I have never actually encountered such a chip in the wild; That has changed now; I have a board with just such a watchdog on my desk currently. Add support for that. - For a hw_algo="toggle" device, the gpio is requested as output if the always-running flag is set, otherwise as input. - The ->start() method is updated to change the direction to output when required (i.e. it is not always-running). - The ->stop() method is implemented, but of course reports failure if always-running. As I still haven't met any hw_algo="level" devices, I'm not entirely sure how they fit in, but I'm borrowing logic from the corresponding linux driver: - In ->probe(), such devices always request the gpio as GPIOD_IS_OUT. - In ->stop(), the linux driver has an "eternal ping" comment and sets the gpio to (logic) high. Signed-off-by: Rasmus Villemoes <ravi(a)prevas.dk> --- drivers/watchdog/gpio_wdt.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/watchdog/gpio_wdt.c b/drivers/watchdog/gpio_wdt.c index 2920c2c751f..e889861e917 100644 --- a/drivers/watchdog/gpio_wdt.c +++ b/drivers/watchdog/gpio_wdt.c @@ -45,14 +45,32 @@ static int gpio_wdt_start(struct udevice *dev, u64 timeout, ulong flags) if (priv->always_running) return 0; - return -ENOSYS; + dm_gpio_set_dir_flags(&priv->gpio, GPIOD_IS_OUT); + gpio_wdt_reset(dev); + + return 0; +} + +static int gpio_wdt_stop(struct udevice *dev) +{ + struct gpio_wdt_priv *priv = dev_get_priv(dev); + + if (priv->always_running) + return -EOPNOTSUPP; + + if (priv->hw_algo == HW_ALGO_TOGGLE) + dm_gpio_set_dir_flags(&priv->gpio, GPIOD_IS_IN); + else + dm_gpio_set_value(&priv->gpio, 1); + + return 0; } static int dm_probe(struct udevice *dev) { struct gpio_wdt_priv *priv = dev_get_priv(dev); - int ret; const char *algo = dev_read_string(dev, "hw_algo"); + int ret, flags; if (!algo) return -EINVAL; @@ -64,7 +82,9 @@ static int dm_probe(struct udevice *dev) return -EINVAL; priv->always_running = dev_read_bool(dev, "always-running"); - ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_OUT); + flags = priv->always_running || priv->hw_algo == HW_ALGO_LEVEL ? + GPIOD_IS_OUT : GPIOD_IS_IN; + ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, flags); if (ret < 0) { dev_err(dev, "Request for wdt gpio failed: %d\n", ret); return ret; @@ -78,6 +98,7 @@ static int dm_probe(struct udevice *dev) static const struct wdt_ops gpio_wdt_ops = { .start = gpio_wdt_start, + .stop = gpio_wdt_stop, .reset = gpio_wdt_reset, }; -- 2.46.2

2 5

[PATCH 1/2] fdt: Correct condition for receiving bloblist
by Simon Glass 23 Oct '24

23 Oct '24

The condition for receiving a bloblist from TPL is reversed. This was only noticed are the other fixes landed. Fix it. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- lib/fdtdec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index b0655988029..60e28173c03 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1677,7 +1677,7 @@ int fdtdec_setup(void) */ if (CONFIG_IS_ENABLED(BLOBLIST) && (xpl_prev_phase() != PHASE_TPL || - !IS_ENABLED(CONFIG_TPL_BLOBLIST))) { + IS_ENABLED(CONFIG_TPL_BLOBLIST))) { ret = bloblist_maybe_init(); if (!ret) { gd->fdt_blob = bloblist_find(BLOBLISTT_CONTROL_FDT, 0); -- 2.43.0

3 4

[PATCH 0/6] Add OPP_LOW support for J7200
by Aniket Limaye 23 Oct '24

23 Oct '24

This series adds OPP_LOW spec data in k3_avs driver and enables a config option to select the OPP_LOW performance point. AVS test logs (CONFIG_K3_OPP_LOW enabled and dummy efuse value): https://gist.github.com/aniket-l/3bdb454d2416e1900dce795ce6090507 J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance Points as per (7.5 Operating Performance Points) section in the Datasheet [0]. - A72SS/MSMC at 2 GHz/1GHz operation must use OPP_NOM. - A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW voltage (though OPP_LOW voltage is recommended to reduce power consumption). The actual OPP voltage for the device is read from the efuse and updated in k3_avs_probe(). The default j7200 devicetree and k3_avs driver set OPP_NOM spec frequency and voltage. In the board init file, if K3_OPP_LOW config is enabled, Check if OPP_LOW AVS voltage read from efuse is valid and update frequency and voltage as per the OPP_LOW spec. [0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet) Reid Tonking (6): arm: dts: k3-j7200-r5-common: Add msmc clk to a72 node misc: k3_avs: Add OPP_LOW voltage and frequency to vd_data misc: k3_avs: Add k3_check_opp function arm: mach-k3: j721e-init.c: J7200: Add support for CONFIG_K3_OPP_LOW configs: j7200_evm_r5_defconfig: Define K3_OPP_LOW DONOTMERGE: For testing only .../arm/dts/k3-j7200-r5-common-proc-board.dts | 10 ++-- arch/arm/mach-k3/Kconfig | 6 +++ arch/arm/mach-k3/j721e/j721e_init.c | 54 ++++++++++++++++++- configs/j7200_evm_r5_defconfig | 1 + drivers/misc/k3_avs.c | 36 +++++++++++++ include/k3-avs.h | 2 + 6 files changed, 103 insertions(+), 6 deletions(-) -- 2.34.1

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[PATCH] arm64: zynqmp: fix tcm initialization for mini u-boot
by Padmarao Begari 23 Oct '24

23 Oct '24

Fix the issue introduced by commit fed064477c2c ("arm64: zynqmp: Print an error for split to lock mode switch"). The mini u-boot is hanging, because of the tcm is not initialized. The mini u-boot is using the tcm to reserve the mmu table and currently it is not initialized, so allowing u-boot to initialize the tcm. Signed-off-by: Padmarao Begari <padmarao.begari(a)amd.com> --- arch/arm/mach-zynqmp/cpu.c | 7 +++++-- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index b24c1631479..6c43063bf23 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -112,7 +112,7 @@ u64 get_page_table_size(void) return 0x14000; } -#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) void tcm_init(u8 mode) { int ret; @@ -134,7 +134,10 @@ void tcm_init(u8 mode) #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU int arm_reserve_mmu(void) { - tcm_init(TCM_LOCK); + puts("WARNING: Initializing TCM overwrites TCM content\n"); + initialize_tcm(TCM_LOCK); + memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); + gd->arch.tlb_size = PGTABLE_SIZE; gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index b3396db28f0..9af3ab5d6b6 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -51,7 +51,7 @@ unsigned int zynqmp_get_silicon_version(void); int check_tcm_mode(bool mode); void initialize_tcm(bool mode); void mem_map_fill(void); -#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) void tcm_init(u8 mode); #endif -- 2.25.1

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[PATCH v2] amd: Disable LMB, BOOTM, MTD and EFI loader for mini configurations
by Michal Simek 23 Oct '24

23 Oct '24

Mini configurations don't need these features that's why disable them. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- Changes in v2: - Get back MTD for amd_versal2_mini_ospi_defconfig because of missing spi_mem_dtr_supports_op and spi_mem_default_supports_op configs/amd_versal2_mini_defconfig | 3 +++ configs/amd_versal2_mini_ospi_defconfig | 3 +++ configs/amd_versal2_mini_qspi_defconfig | 4 +++- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig index 0dd2305bfb2d..f2444308fb97 100644 --- a/configs/amd_versal2_mini_defconfig +++ b/configs/amd_versal2_mini_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y +# CONFIG_EFI_LOADER is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -35,6 +36,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="versal2> " # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set @@ -75,3 +77,4 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y # CONFIG_GZIP is not set +# CONFIG_LMB is not set diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig index 2242960392f5..4ae5ae19b84c 100644 --- a/configs/amd_versal2_mini_ospi_defconfig +++ b/configs/amd_versal2_mini_ospi_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_LOAD_ADDR=0xBBF80000 CONFIG_DEBUG_UART=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y +# CONFIG_EFI_LOADER is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -33,6 +34,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="versal2> " # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set @@ -82,3 +84,4 @@ CONFIG_HAS_CQSPI_REF_CLK=y CONFIG_CQSPI_REF_CLK=200000000 CONFIG_CADENCE_OSPI_VERSAL=y # CONFIG_GZIP is not set +# CONFIG_LMB is not set diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig index 3360c1546a20..b1d966a56c68 100644 --- a/configs/amd_versal2_mini_qspi_defconfig +++ b/configs/amd_versal2_mini_qspi_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_LOAD_ADDR=0xBBF80000 CONFIG_DEBUG_UART=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y +# CONFIG_EFI_LOADER is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -33,6 +34,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="versal2> " # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set @@ -62,7 +64,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_I2C is not set # CONFIG_INPUT is not set # CONFIG_MMC is not set -CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_LOCK is not set CONFIG_SPI_FLASH_STMICRO=y @@ -77,3 +78,4 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_ZYNQMP_GQSPI=y # CONFIG_GZIP is not set +# CONFIG_LMB is not set -- 2.43.0

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