September 2023 - U-Boot

[PATCH] usb: host: ohci-generic: Make usage of clock/reset bulk() API
by Fabrice Gasnier 04 Sep '23

04 Sep '23

Make usage of clock and reset bulk API in order to simplify the code Signed-off-by: Fabrice Gasnier <fabrice.gasnier(a)foss.st.com> --- drivers/usb/host/ohci-generic.c | 92 +++++++++++---------------------- 1 file changed, 29 insertions(+), 63 deletions(-) diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c index 2d8d38ce9a40..95aa608d8c19 100644 --- a/drivers/usb/host/ohci-generic.c +++ b/drivers/usb/host/ohci-generic.c @@ -16,75 +16,41 @@ struct generic_ohci { ohci_t ohci; - struct clk *clocks; /* clock list */ - struct reset_ctl *resets; /* reset list */ + struct clk_bulk clocks; /* clock list */ + struct reset_ctl_bulk resets; /* reset list */ struct phy phy; - int clock_count; /* number of clock in clock list */ - int reset_count; /* number of reset in reset list */ }; static int ohci_usb_probe(struct udevice *dev) { struct ohci_regs *regs = dev_read_addr_ptr(dev); struct generic_ohci *priv = dev_get_priv(dev); - int i, err, ret, clock_nb, reset_nb; - - err = 0; - priv->clock_count = 0; - clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells", - 0); - if (clock_nb > 0) { - priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), - GFP_KERNEL); - if (!priv->clocks) - return -ENOMEM; - - for (i = 0; i < clock_nb; i++) { - err = clk_get_by_index(dev, i, &priv->clocks[i]); - if (err < 0) - break; - - err = clk_enable(&priv->clocks[i]); - if (err && err != -ENOSYS) { - dev_err(dev, "failed to enable clock %d\n", i); - clk_free(&priv->clocks[i]); - goto clk_err; - } - priv->clock_count++; - } - } else if (clock_nb != -ENOENT) { - dev_err(dev, "failed to get clock phandle(%d)\n", clock_nb); - return clock_nb; + int err, ret; + + ret = clk_get_bulk(dev, &priv->clocks); + if (ret && ret != -ENOENT) { + dev_err(dev, "Failed to get clocks (ret=%d)\n", ret); + return ret; + } + + err = clk_enable_bulk(&priv->clocks); + if (err) { + dev_err(dev, "Failed to enable clocks (err=%d)\n", err); + goto clk_err; } - priv->reset_count = 0; - reset_nb = dev_count_phandle_with_args(dev, "resets", "#reset-cells", - 0); - if (reset_nb > 0) { - priv->resets = devm_kcalloc(dev, reset_nb, - sizeof(struct reset_ctl), - GFP_KERNEL); - if (!priv->resets) - return -ENOMEM; - - for (i = 0; i < reset_nb; i++) { - err = reset_get_by_index(dev, i, &priv->resets[i]); - if (err < 0) - break; - - err = reset_deassert(&priv->resets[i]); - if (err) { - dev_err(dev, "failed to deassert reset %d\n", i); - reset_free(&priv->resets[i]); - goto reset_err; - } - priv->reset_count++; - } - } else if (reset_nb != -ENOENT) { - dev_err(dev, "failed to get reset phandle(%d)\n", reset_nb); + err = reset_get_bulk(dev, &priv->resets); + if (err && err != -ENOENT) { + dev_err(dev, "failed to get resets (err=%d)\n", err); goto clk_err; } + err = reset_deassert_bulk(&priv->resets); + if (err) { + dev_err(dev, "failed to get deassert resets (err=%d)\n", err); + goto reset_err; + } + err = generic_setup_phy(dev, &priv->phy, 0); if (err) goto reset_err; @@ -101,13 +67,13 @@ phy_err: dev_err(dev, "failed to shutdown usb phy\n"); reset_err: - ret = reset_release_all(priv->resets, priv->reset_count); + ret = reset_release_bulk(&priv->resets); if (ret) - dev_err(dev, "failed to assert all resets\n"); + dev_err(dev, "failed to release resets (ret=%d)\n", ret); clk_err: - ret = clk_release_all(priv->clocks, priv->clock_count); + ret = clk_release_bulk(&priv->clocks); if (ret) - dev_err(dev, "failed to disable all clocks\n"); + dev_err(dev, "failed to release clocks (ret=%d)\n", ret); return err; } @@ -125,11 +91,11 @@ static int ohci_usb_remove(struct udevice *dev) if (ret) return ret; - ret = reset_release_all(priv->resets, priv->reset_count); + ret = reset_release_bulk(&priv->resets); if (ret) return ret; - return clk_release_all(priv->clocks, priv->clock_count); + return clk_release_bulk(&priv->clocks); } static const struct udevice_id ohci_usb_ids[] = { -- 2.25.1

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[PATCH 0/2] risc-v: implement DBCN based debug console
by Heinrich Schuchardt 04 Sep '23

04 Sep '23

Currently we only offer an SBI based debug UART for SBI v0.1. With OpenSBI 1.3 the Debug Console Extension (DBCN) has become available. This allows us to implement a debug UART in a device independent manor. Heinrich Schuchardt (2): risc-v: implement DBCN write byte risc-v: implement DBCN based debug console arch/riscv/include/asm/sbi.h | 1 + arch/riscv/lib/sbi.c | 16 ++++++++++++++++ drivers/serial/Kconfig | 3 ++- drivers/serial/serial_sbi.c | 19 +++++++++++++++++++ 4 files changed, 38 insertions(+), 1 deletion(-) -- 2.40.1

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[PATCH 0/5] board: xilinx: zyqmp: add Beckhoff CX8200
by Steffen Dirkwinkel 04 Sep '23

04 Sep '23

From: Steffen Dirkwinkel <s.dirkwinkel(a)beckhoff.com> This adds support for the Beckhoff CX8200 series of industrial embedded PCs. There is some information about the device and features here: https://www.beckhoff.com/en-en/products/ipc/embedded-pcs/cx8200-arm-cortex-… We also add the rtc rv3032 driver from linux, as it is required for mac address loading, fix usb without reset gpios on zynqmp and move the fdt loadaddr to be compatible with less memory. Steffen Dirkwinkel (5): drivers: rtc: add rv3032 driver drivers/usb/dwc3: zynqmp: only free reset gpio if we have one xilinx: zynqmp: move fdt_addr so we can use devices with less memory xilinx: zynqmp: add Beckhoff CX8200 xilinx: zynqmp: beckhoff cx8200: setup inner cache broadcasting arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-beckhoff-cx8200.dts | 247 +++ .../zynqmp-beckhoff-cx8200/psu_init_gpl.c | 1960 +++++++++++++++++ .../zynqmp/zynqmp-beckhoff-cx8200/regs.init | 1 + configs/xilinx_zynqmp_virt_defconfig | 2 +- drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rv3032.c | 334 +++ drivers/usb/dwc3/dwc3-generic.c | 4 +- include/configs/xilinx_zynqmp.h | 2 +- 10 files changed, 2559 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/zynqmp-beckhoff-cx8200.dts create mode 100644 board/xilinx/zynqmp/zynqmp-beckhoff-cx8200/psu_init_gpl.c create mode 100644 board/xilinx/zynqmp/zynqmp-beckhoff-cx8200/regs.init create mode 100644 drivers/rtc/rv3032.c -- 2.42.0

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[PATCH] spl: add __noreturn attribute to spl_invoke_opensbi function
by Chanho Park 04 Sep '23

04 Sep '23

spl_invoke_opensbi function is not returned to SPL. Thus, we need to set __noreturn function attribute. Signed-off-by: Chanho Park <chanho61.park(a)samsung.com> --- common/spl/spl_opensbi.c | 7 ++++--- include/spl.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index b0f40076c345..e2aaa460468c 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -43,11 +43,12 @@ static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node) return -ENODEV; } -void spl_invoke_opensbi(struct spl_image_info *spl_image) +void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image) { int ret, uboot_node; ulong uboot_entry; - void (*opensbi_entry)(ulong hartid, ulong dtb, ulong info); + typedef void __noreturn (*opensbi_entry_t)(ulong hartid, ulong dtb, ulong info); + opensbi_entry_t opensbi_entry; if (!spl_image->fdt_addr) { pr_err("No device tree specified in SPL image\n"); @@ -74,7 +75,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) opensbi_info.options = CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS; opensbi_info.boot_hart = gd->arch.boot_hart; - opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point; + opensbi_entry = (opensbi_entry_t)spl_image->entry_point; invalidate_icache_all(); #ifdef CONFIG_SPL_SMP diff --git a/include/spl.h b/include/spl.h index 92bcaa90a4af..93e906431e7d 100644 --- a/include/spl.h +++ b/include/spl.h @@ -862,7 +862,7 @@ void __noreturn spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3); /** * spl_invoke_opensbi - boot using a RISC-V OpenSBI image */ -void spl_invoke_opensbi(struct spl_image_info *spl_image); +void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image); /** * board_return_to_bootrom - allow for boards to continue with the boot ROM -- 2.39.2

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[PATCH v6 4/4] configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default
by Shengyu Qu 04 Sep '23

04 Sep '23

SPL_SYS_MALLOC_CLEAR_ON_INIT would enable SYS_MALLOC_CLEAR_ON_INIT by default, but that's not need on JH7110, so disable that. Signed-off-by: Shengyu Qu <wiagn233(a)outlook.com> --- configs/starfive_visionfive2_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index e9b63e5b84..efe3c2205a 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -58,6 +58,8 @@ CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000 CONFIG_SYS_SPL_MALLOC_SIZE=0x400000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_SYS_MALLOC_CLEAR_ON_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2 CONFIG_SPL_I2C=y -- 2.42.0

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[PATCH v6 3/4] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT
by Shengyu Qu 04 Sep '23

04 Sep '23

Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error would be triggered. Currently, we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. Signed-off-by: Bo Gan <ganboing(a)gmail.com> Signed-off-by: Shengyu Qu <wiagn233(a)outlook.com> --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 8469ee7de5..e5549a01b8 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -28,3 +28,4 @@ config STARFIVE_JH7110 imply SPL_LOAD_FIT imply SPL_OPENSBI imply SPL_RISCV_ACLINT + imply SPL_SYS_MALLOC_CLEAR_ON_INIT -- 2.42.0

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[PATCH] eeprom: starfive: set eth0 mac address properly
by Seung-Woo Kim 04 Sep '23

04 Sep '23

fdt_fixup_ethernet() sets eth0 mac address from ethaddr. Set ethaddr to environment instead of eth0addr. Signed-off-by: Seung-Woo Kim <sw0312.kim(a)samsung.com> --- board/starfive/visionfive2/visionfive2-i2c-eeprom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index befe7888c400..c334d98cf6e5 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -504,7 +504,7 @@ int mac_read_from_eeprom(void) } // 1, setup ethaddr env - eth_env_set_enetaddr("eth0addr", pbuf.eeprom.atom4.data.mac0_addr); + eth_env_set_enetaddr("ethaddr", pbuf.eeprom.atom4.data.mac0_addr); eth_env_set_enetaddr("eth1addr", pbuf.eeprom.atom4.data.mac1_addr); /** -- 2.19.2

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[PATCH 0/2] riscv: jh7110: visionfive2: fix u-boot crash due to missing timer
by duwe＠lst.de 04 Sep '23

04 Sep '23

Hi all, Since commit 55171aedda8, U-Boot on the visionfive2 stops at | initcall sequence 00000000fffd76f8 failed at call 00000000402192c8 (err=-19) | ### ERROR ### Please RESET the board ### This is init_sequence_r[initr_dm_devices] calling dm_timer_init, which returns ENODEV, because the riscv architectural timer got initialised at the ROM stage, but then discarded at relocation, and never again to be re-registered. A workaround hack was to allow it to register again in drivers/core/root.c line 439: if (CONFIG_IS_ENABLED(DM_EVENT) /* && !(gd->flags & GD_FLG_RELOC) */ ) { but that would defeat the purpose of the commit 55171aedda8 cleanup. However, the timer has a defined device tree binding which, when used, IMHO makes things a lot clearer. AFAIU, the timer roughly corresponds to the x86 TSC, which is defined on many x86 platforms, compare yourself: grep -r tsc_timer.dtsi arch/x86/dts vs. grep -r '"riscv,timer"' arch/riscv/dts At first I tried to create a series that converts all riscv platforms to use the DT for the CPU timer and removes the calls from the CPU driver, but this takes too long. Release early, release often -- these two patches fix the visionfive2, for a start. Others may follow and the CPU driver calls can be removed later when they are not needed any longer. Torsten Fixes: 55171aedda8 ("dm: Emit the arch_cpu_init_dm() even only before relocation") --- Torsten Duwe (2): riscv: allow riscv timer to be instantiated via device tree riscv: jh7110: enable riscv,timer in the device tree arch/riscv/dts/jh7110.dtsi | 9 +++++++++ drivers/timer/riscv_timer.c | 28 ++++++++++++++++++++++++++-- 2 files changed, 35 insertions(+), 2 deletions(-) -- 2.35.3

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[PATCH v3 0/6] DTS Sync from v6.5-rc1 to u-boot
by Manorit Chawdhry 04 Sep '23

04 Sep '23

The sync tries to ensure that U-boot remains functional with the updated Linux DTS and all the fixes from Linux move to U-boot during the sync. The series tries to sync from Linux v6.5-rc1 along with addition of the documentation for J721S2 that had been previously missing. MCU Ringacc [0] and DMA fixes [1] are currently being upstreamed to Linux. They'll be fixed in U-boot post their merge in Linux hopefully during v6.6-rc1 timeframe. Test Logs are included in [2] [0]: https://lore.kernel.org/all/20230809175932.2553156-1-vigneshr@ti.com/ [1]: https://lore.kernel.org/all/20230810174356.3322583-1-vigneshr@ti.com/ [2]: https://gist.github.com/manorit2001/dbad09fd00e8b7c3872e85874c8e648c Signed-off-by: Manorit Chawdhry <m-chawdhry(a)ti.com> --- Changes in v3: - Move dm-tifs node to root node (Neha) - Change the documentation commit subject (Nishanth) - Remove stdout-path from U-boot (Nishanth) - Fix extra tab (Nishanth) - Fix documentation regarding comment of OPTEE Flavor (Nishanth) - Remove extra EOL (Nishanth) - Add AM68 documentation (Nishanth) - Add AM68 Maintainers entry (Nishanth) - Link to v2: https://lore.kernel.org/r/20230816-b4-upstream-j721s2-r5-pinmux-v2-0-a5f141… --- Manorit Chawdhry (5): arm: mach-k3: j721s2: Add mcu_timer0 id to the dev list k3-j721s2: Sync from Linux tag v6.5-rc1 k3-am68: Sync from Linux tag v6.5-rc1 docs: board: ti: Add j721s2_evm documentation board: ti: j721s2: MAINTAINERS: Update the MAINTAINERS File. Udit Kumar (1): configs: j721s2_evm_r5_defconfig: Increase malloc pool size in DRAM arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 69 +-- arch/arm/dts/k3-am68-sk-base-board.dts | 389 ++++++++------ arch/arm/dts/k3-am68-sk-r5-base-board.dts | 151 +----- arch/arm/dts/k3-am68-sk-som.dtsi | 112 +--- .../dts/k3-j721s2-common-proc-board-u-boot.dtsi | 60 +-- arch/arm/dts/k3-j721s2-common-proc-board.dts | 330 ++++++------ arch/arm/dts/k3-j721s2-main.dtsi | 585 ++++++++++++++++++++- arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 365 ++++++++++++- arch/arm/dts/k3-j721s2-r5-common-proc-board.dts | 158 +----- arch/arm/dts/k3-j721s2-som-p0.dtsi | 165 +++--- arch/arm/dts/k3-j721s2-thermal.dtsi | 101 ++++ arch/arm/dts/k3-j721s2.dtsi | 12 +- arch/arm/mach-k3/j721s2/dev-data.c | 1 + board/ti/j721s2/MAINTAINERS | 9 +- configs/j721s2_evm_r5_defconfig | 1 + doc/board/ti/j721s2_evm.rst | 298 +++++++++++ doc/board/ti/k3.rst | 1 + 17 files changed, 1953 insertions(+), 854 deletions(-) --- base-commit: 97841de680430e235f0954a188f245775cbbb962 change-id: 20230816-b4-upstream-j721s2-r5-pinmux-25c4cd61b258 Best regards, -- Manorit Chawdhry <m-chawdhry(a)ti.com>

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[PATCH v3 1/2] x86: coreboot: Update cbmem table
by Simon Glass 04 Sep '23

04 Sep '23

This changed a few years ago to include an overflow flag. Bring in the new structure. This comes from coreboot commit: 6f5ead14b4 ("mb/google/nissa/var/joxer: Update eMMC DLL settings") Note: There are several implementations of this in coreboot. I have chosen to follow the one in src/lib/cbmem_console.c Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Drop __packed as it does nothing useful arch/x86/include/asm/coreboot_tables.h | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 4de137fbab9d..0dfb64babb96 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -299,11 +299,24 @@ struct cb_vdat { #define CB_TAG_TIMESTAMPS 0x0016 #define CB_TAG_CBMEM_CONSOLE 0x0017 +#define CBMC_CURSOR_MASK ((1 << 28) - 1) +#define CBMC_OVERFLOW BIT(31) + +/* + * struct cbmem_console - In-memory console buffer for coreboot + * + * Structure describing console buffer. It is overlaid on a flat memory area, + * with body covering the extent of the memory. Once the buffer is full, + * output will wrap back around to the start of the buffer. The high bit of the + * cursor field gets set to indicate that this happened. If the underlying + * storage allows this, the buffer will persist across multiple boots and append + * to the previous log. + */ struct cbmem_console { u32 size; u32 cursor; - char body[0]; -} __packed; + u8 body[0]; +}; #define CB_TAG_MRC_CACHE 0x0018 -- 2.41.0.694.ge786442a9b-goog

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