September 2023 - U-Boot

[PATCH v1] drivers: spi: Add MT25U01G part number for SPI NOR Flash
by Jit Loon Lim 14 Dec '23

14 Dec '23

MT25QU01 OPN with 4B OPCODE support is currently not supported in source code and the driver reuses the definition for "n25q00a" which has the same silicon ID but is a slower part. Adding mt25u01g definition to the source code to support a faster read response for MT25QU01 QSPI NOR Flash device. Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3ca46330bb..1b2e88cd26 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -311,6 +311,8 @@ const struct flash_info spi_nor_ids[] = { { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { INFO6("mt25qu01g", 0x20bb21, 0x104400, 64 * 1024, 2048, SECT_4K | USE_FSR | +SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, -- 2.26.2

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[PATCH] drivers: mtd: Add MT25QU128AB params
by seanedmond＠linux.microsoft.com 14 Dec '23

14 Dec '23

From: Godfrey Mwangi <godmwan(a)microsoft.com> Add Micron MT25QU128AB flash. Signed-off-by: Godfrey Mwangi <godmwan(a)microsoft.com> --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4587215984..a99bb6125b 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -299,6 +299,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, + { INFO("mt25qu128ab", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, -- 2.40.0

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[PATCH v2] spi: cadence_qspi: Select flash subnode at runtime
by Udit Kumar 14 Dec '23

14 Dec '23

Currently spi driver gets flash parameter from first subnode. Few boards have more than one flash with different parameters and selection of flash is done by on board switch settings. In such case, uboot needs to be recompiled with updated device tree to align with board switch settings. This patch allows to select flash node at runtime. Boards those are supporting multiple flashes needs to implement cadence_qspi_get_subnode function and return correct flash node. Cc: Apurva Nandan <a-nandan(a)ti.com> Signed-off-by: Udit Kumar <u-kumar1(a)ti.com> Reviewed-by: Neha Malcom Francis <n-francis(a)ti.com> --- One of such platform is J721S2 EVM link https://www.ti.com/lit/pdf/spruj69 Fig 3.1, Page 18 has details of two flashes connected with one controller Change log: Changes in v2 - Corrected link in comment - removed extra space - Added Reviewed-by, after addressing v1 feedback - link to v1 https://lore.kernel.org/all/20230907092143.4110817-1-u-kumar1@ti.com/ drivers/spi/cadence_qspi.c | 7 ++++++- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index cc3a54f295..eb7fbf83d0 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -40,6 +40,11 @@ __weak int cadence_qspi_versal_flash_reset(struct udevice *dev) return 0; } +__weak ofnode cadence_qspi_get_subnode(struct udevice *dev) +{ + return dev_read_first_subnode(dev); +} + static int cadence_spi_write_speed(struct udevice *bus, uint hz) { struct cadence_spi_priv *priv = dev_get_priv(bus); @@ -401,7 +406,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); /* All other parameters are embedded in the child node */ - subnode = dev_read_first_subnode(bus); + subnode = cadence_qspi_get_subnode(bus); if (!ofnode_valid(subnode)) { printf("Error: subnode with SPI flash config missing!\n"); return -ENODEV; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 1c59d1a9d9..12825f8911 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -304,6 +304,7 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv); int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); int cadence_qspi_versal_flash_reset(struct udevice *dev); +ofnode cadence_qspi_get_subnode(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable); #endif /* __CADENCE_QSPI_H__ */ -- 2.34.1

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[PATCH v1] spi: spi-nor-ids: add flash model w25q01/02 support
by Jim Liu 14 Dec '23

14 Dec '23

add flash w25q01jv, w25q01jvfim and w25q02jv support Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/mtd/spi/spi-nor-ids.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4587215984..fd74efe609 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -512,6 +512,16 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q01jvfim", 0xef7021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q02jv", 0xef7022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -- 2.25.1

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[PATCH] imx7d-sdb: Sync devicetree with kernel 6.5-rc1
by Fabio Estevam 13 Dec '23

13 Dec '23

From: Fabio Estevam <festevam(a)denx.de> Commit 0aea5dda2928 ("ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operation") did a temporary workaround by addng the usdhc1 fix inside the -u-boot.dtsi file. The imx7d-sdb.dts from kernel 6.5-rc1 contains the proper UHS fix, so sync the devicetree tree and remove the previous fix from -u-boot.dtsi. Also, adjust the PMIC node name inside pmic_get() to match the devicetree update. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- arch/arm/dts/imx7d-sdb-u-boot.dtsi | 51 ---------------- arch/arm/dts/imx7d-sdb.dts | 73 +++++++++++++++++------ board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- 3 files changed, 56 insertions(+), 70 deletions(-) diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi index ac1d6e2e6480..b78358fa1397 100644 --- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi +++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi @@ -5,54 +5,3 @@ &usbotg1 { dr_mode = "peripheral"; }; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; -}; - -&pinctrl_usdhc1 { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; -}; - -&iomuxc { - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; -}; diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 78f4224a9bf4..75f1cd14bea1 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -24,14 +24,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -39,12 +39,12 @@ }; }; - spi4 { + spi-4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; - gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; @@ -60,6 +60,17 @@ }; }; + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <200000>; + off-on-delay-us = <20000>; + }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -205,13 +216,8 @@ pinctrl-0 = <&pinctrl_tsc2046_pendown>; interrupt-parent = <&gpio2>; interrupts = <29 0>; - pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <0>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <0>; - ti,pressure-max = /bits/ 16 <0>; - ti,x-plate-ohms = /bits/ 16 <400>; + pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; + touchscreen-max-pressure = <255>; wakeup-source; }; }; @@ -269,7 +275,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -478,10 +484,13 @@ }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&reg_sd1_vmmc>; wakeup-source; keep-power-in-suspend; status = "okay"; @@ -736,6 +745,15 @@ >; }; + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 @@ -744,9 +762,28 @@ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 2777ae13bce0..fbf85411910e 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -267,7 +267,7 @@ int power_init_board(void) struct udevice *dev; int ret, dev_id, rev_id; - ret = pmic_get("pfuze3000@8", &dev); + ret = pmic_get("pmic@8", &dev); if (ret == -ENODEV) return 0; if (ret != 0) -- 2.34.1

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[PATCH] imx8qm_dmsse20a1: Improve SPL memory configuration
by Fabio Estevam 13 Dec '23

13 Dec '23

From: Fabio Estevam <festevam(a)denx.de> Currently, building imx8qm_dmsse20a1_defconfig leads to the following warning: aarch64-linux-ld.bfd: invalid origin for memory region .sdram Fix it by using the same SPL memory layout as done in the imx8mq_evk. Reported-by: Tom Rini <trini(a)konsulko.com> Signed-off-by: Fabio Estevam <festevam(a)denx.de> Tested-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- configs/imx8qm_dmsse20a1_defconfig | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig index 3341b5e447fb..57a5007f9e5b 100644 --- a/configs/imx8qm_dmsse20a1_defconfig +++ b/configs/imx8qm_dmsse20a1_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SPL_STACK=0x13e000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_SYS_MEMTEST_START=0xA0000000 @@ -38,11 +39,17 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_BSS_START_ADDR=0x00128000 CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x3000 CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG_SUPPORT=y -- 2.34.1

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[PATCH v1 0/2] Fix host tools build without LIBCRYPTO support
by Paul-Erwan Rio 13 Dec '23

13 Dec '23

A target-independent configuration exists to enable/disable crypto feature when building the host tools. But the crypto-free build is broken. Paul-Erwan Rio (2): tools: kwbimage: disable secure boot build without LIBCRYPTO support tools: fix build without LIBCRYPTO support include/image.h | 2 +- tools/Kconfig | 1 + tools/fit_image.c | 2 +- tools/image-host.c | 2 ++ tools/kwbimage.c | 18 ++++++++++++++++++ tools/mkimage.c | 5 +++-- 6 files changed, 26 insertions(+), 4 deletions(-) -- 2.39.0

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[PATCH] mtd: spi-nor-core: Implement spi_nor_read_sfdp_dma_unsafe() for sfdp parse
by Vaishnav Achath 12 Dec '23

12 Dec '23

During SFDP header parse and BFPT parse, structures in stack are used to perform spi_nor_read_sfdp() which expects a dma-safe buffer. This commit introduces spi_nor_read_sfdp_dma_unsafe() to wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer which is the same implementation in Linux (drivers/mtd/spi-nor/sfdp.c). Signed-off-by: Vaishnav Achath <vaishnav.a(a)ti.com> --- drivers/mtd/spi/spi-nor-core.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 3b7c817c02..90d05da1d8 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2022,6 +2022,36 @@ read_err: return ret; } +/** + * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters. + * @nor: pointer to a 'struct spi_nor' + * @addr: offset in the SFDP area to start reading data from + * @len: number of bytes to read + * @buf: buffer where the SFDP data are copied into + * + * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not + * guaranteed to be dma-safe. + * + * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp() + * otherwise. + */ +static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr, + size_t len, void *buf) +{ + void *dma_safe_buf; + int ret; + + dma_safe_buf = kmalloc(len, GFP_KERNEL); + if (!dma_safe_buf) + return -ENOMEM; + + ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf); + memcpy(buf, dma_safe_buf, len); + kfree(dma_safe_buf); + + return ret; +} + /* Fast Read settings. */ static void @@ -2195,7 +2225,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, bfpt_header->length * sizeof(u32)); addr = SFDP_PARAM_HEADER_PTP(bfpt_header); memset(&bfpt, 0, sizeof(bfpt)); - err = spi_nor_read_sfdp(nor, addr, len, &bfpt); + err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt); if (err < 0) return err; @@ -2480,7 +2510,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, int i, err; /* Get the SFDP header. */ - err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); + err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header); if (err < 0) return err; -- 2.17.1

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[PATCH 0/7] spi-nor: Add parallel and stacked memories support
by Ashok Reddy Soma 12 Dec '23

12 Dec '23

This series adds support for Xilinx qspi parallel and stacked memeories. In parallel mode, the current implementation assumes that a maximum of two flashes are connected. The QSPI controller splits the data evenly between both the flashes so, both the flashes that are connected in parallel mode should be identical. During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in nor->flags. In stacked mode the current implementation assumes that a maximum of two flashes are connected and both the flashes are of same make but can differ in sizes. So, except the sizes all other flash parameters of both the flashes are identical Spi-nor will pass on the appropriate flash select flag to low level driver, and it will select pass all the data to that particular flash. Write operation in parallel mode are performed in page size * 2 chunks as each write operation results in writing both the flashes. For doubling the address space each operation is performed at addr/2 flash offset, where addr is the address specified by the user. Similarly for read and erase operations it will read from both flashes, so size and offset are divided by 2 and send to flash. Ashok Reddy Soma (7): dm: core: support reading a single indexed u64 value mtd: spi-nor: Add parallel and stacked memories support mtd: spi-nor: Add parallel memories support for read_sr and read_fsr mtd: spi-nor: Add parallel and stacked memories support in read_bar and write_bar spi: spi-uclass: Read chipselect and restrict capabilities spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver spi: zynq_qspi: Add parallel memories support in QSPI driver drivers/core/of_access.c | 22 ++ drivers/core/ofnode.c | 30 +++ drivers/mtd/spi/spi-nor-core.c | 385 ++++++++++++++++++++++++++++----- drivers/spi/spi-uclass.c | 21 +- drivers/spi/xilinx_spi.c | 4 +- drivers/spi/zynq_qspi.c | 145 +++++++++++-- drivers/spi/zynq_spi.c | 6 +- drivers/spi/zynqmp_gqspi.c | 146 +++++++++++-- include/dm/of_access.h | 19 ++ include/dm/ofnode.h | 12 + include/linux/mtd/spi-nor.h | 13 ++ include/spi.h | 29 ++- 12 files changed, 737 insertions(+), 95 deletions(-) -- 2.17.1

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[PATCH v1 1/1] Makefile.lib: Always rebuild DSDT
by Andy Shevchenko 09 Dec '23

09 Dec '23

The dsdt.asl is usually combined out of several files that are included in the main one. Whenever we change the content of any of such files, build system is not able to recognize them. Hence the easiest way is to force DSDT rebuild each time we run make. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- scripts/Makefile.lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 07696e86bb54..8c3c893b398a 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -441,7 +441,7 @@ cmd_acpi_c_asl= \ iasl -p $@ -tc $(ASL_TMP) $(if $(KBUILD_VERBOSE:1=), >/dev/null) && \ mv $(patsubst %.c,%.hex,$@) $@ -$(obj)/dsdt.c: $(src)/dsdt.asl +$(obj)/dsdt.c: $(src)/dsdt.asl FORCE $(call cmd,acpi_c_asl) $(Q)sed -i -e "s,dsdt_aml_code,AmlCode," $@ -- 2.33.0

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