September 2023 - U-Boot

[PATCH v7 1/2] schemas: memory: Add ECC properties
by Simon Glass 16 Jan '24

16 Jan '24

Some memories provide ECC detection and/or correction. For software which wants to check memory, it is helpful to see which regions provide this feature. Add this as a property of the /memory nodes, since it presumably follows the hardware-level memory system. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v7: - Drop unnecessary | - Add a blank line between properties Changes in v6: - Use a number of bits instead of a string property - Fix inidcates typo Changes in v5: - Redo to make this property specific to ECC - Provide properties both for detection and correction Changes in v3: - Add new patch to update the /memory nodes dtschema/schemas/memory.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/dtschema/schemas/memory.yaml b/dtschema/schemas/memory.yaml index 1d74410..b3bf3c9 100644 --- a/dtschema/schemas/memory.yaml +++ b/dtschema/schemas/memory.yaml @@ -35,6 +35,19 @@ patternProperties: For the purpose of identification, each NUMA node is associated with a unique token known as a node id. + ecc-detection-bits: + default: 0 + description: | + If present, this indicates the number of bits of memory error which + can be detected and reported by the Error-Correction Code (ECC) memory + subsystem (typically 0, 1 or 2). + + ecc-correction-bits: + default: 0 + description: | + If present, this indicates the number of bits of memory error which + can be corrected by the Error-Correction Code (ECC) memory subsystem + (typically 0, 1 or 2). required: - device_type -- 2.42.0.515.g380fc7ccd1-goog

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[PATCH V6 00/10] Update SPL splashscreen framework for AM62x
by Nikhil M Jain 12 Jan '24

12 Jan '24

This patch series aims at updating SPL splashscreen framework for AM62x. This patch series depends on https://lore.kernel.org/u-boot/20230504225829.2537050-1-sjg@chromium.org/ This series: - Fixes compilation issues in case splash related configs are not defined in SPL. - Does page table setup, dram initialisation and dcache enabling in one function call spl_enable_dcache. - Allows passing of framebuffer from spl to u-boot, eliminating flicker. V6: - Add patch [1] from Samuel Dionne-Riel fixing CMD_BMP/BMP dependecy. V5: - Change A53 SPL DDR layout from ASCII table to tabular format. V4: - Fix commit message. - Introduce patch defining DDR layout in A53 SPL. - Add Reviewed-by tags. V3: - Fix spacing issues. - Add Reviewed-by tag. - Replace #if with if in patch common: spl: spl: Remove video driver - Add link to updated memory map. V2: - Update cover letter. - Fix commit message. [1]: https://patchwork.ozlabs.org/project/uboot/patch/20230709231810.633044-1-sa… Nikhil M Jain (9): common: spl: spl: Update stack pointer address arch: arm: mach-k3: common: Return a pointer after setting page table board: ti: am62x: evm: Update function calls for splash screen include: video: Reserve video using blob common: board_f: Pass frame buffer info from SPL to u-boot drivers: video: Kconfig: Add config remove video common: spl: spl: Remove video driver configs: am62x_evm_a53: Add bloblist address doc: board: ti: am62x_sk: Add A53 SPL DDR layout Samuel Dionne-Riel (1): common: Kconfig: Fix CMD_BMP/BMP dependency arch/arm/mach-k3/am625_init.c | 1 + arch/arm/mach-k3/common.c | 2 ++ board/ti/am62x/evm.c | 41 +++++++++--------------- cmd/Kconfig | 1 + common/Kconfig | 1 - common/board_f.c | 11 ++++++- common/spl/spl.c | 23 ++++++------- configs/am62x_evm_a53_defconfig | 1 + doc/board/ti/am62x_sk.rst | 57 +++++++++++++++++++++++++++++++++ drivers/video/Kconfig | 12 +++++++ drivers/video/video-uclass.c | 23 +++++++++++++ include/video.h | 9 ++++++ 12 files changed, 143 insertions(+), 39 deletions(-) -- 2.34.1

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[RFC PATCH 0/2] board: ti: Use Extension framework
by Roger Quadros 11 Jan '24

11 Jan '24

Hi, RFC as only build tested. Need to get early feedback before I spend more time on this. Newer TI boards (AM6/J7) are using a custom logic to detect expansion cards and set a 'name_overlays' environment variable. Then DT overlays are applied by again custom environment scripts during boot. Instead of that migrate to using the Extension framework. This allows the user to call 'extension scan' and 'extension apply' commands to detect extension cards and apply the DT overlays respectively. For Booting, I expect distro boot scripts to already support the extension framework via following environment 'extension_overlay_cmd' and 'extension_overlay_addr'. i.e. include/config_distro_bootcmd.h cheers, -roger Roger Quadros (2): board: ti: common: Add CONFIG_TI_CAPE_DETECT for cape detection board: ti: am65x: Move to using Extension framework board/ti/am335x/board.c | 8 + board/ti/am65x/evm.c | 264 ++++++++--------------------- board/ti/common/Kconfig | 16 ++ board/ti/common/Makefile | 3 +- board/ti/common/cape_detect.c | 2 +- board/ti/common/cape_detect.h | 2 +- board/ti/common/ti_card_detect.c | 155 +++++++++++++++++ board/ti/common/ti_card_detect.h | 43 +++++ configs/am65x_evm_a53_defconfig | 2 + configs/am65x_hs_evm_a53_defconfig | 2 + 10 files changed, 299 insertions(+), 198 deletions(-) create mode 100644 board/ti/common/ti_card_detect.c create mode 100644 board/ti/common/ti_card_detect.h -- 2.34.1

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[PATCH 0/6] board: ti: Add support for BeaglePlay
by Nishanth Menon 07 Jan '24

07 Jan '24

Add support for BeaglePlay Boot log: https://gist.github.com/nmenon/e82fa95cff98942bdfc5c692a610c824 Full series can be found in: https://github.com/nmenon/fix-k3-dt-u-boot/commits/beagleplay-v1 Depends on: https://lore.kernel.org/all/20230725125856.1807742-1-nm@ti.com/ Caveats: * I have kept networking out of picture for now as it is still evolving. Nishanth Menon (5): doc: board: ti: k3: Sort the boards in alphabetical order arm: dts: k3-am625-sk-binman: Add labels for unsigned binary board: ti: am62x: Add basic initialization for usb voltage, 32k crystal, debounce configs: Add am62x_beagleplay_* defconfigs doc: board: ti: Add beagleplay documentation Robert Nelson (1): arm: dts: Add k3-am625-beagleplay arch/arm/dts/Makefile | 4 +- .../dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi | 2195 +++++++++++++++++ arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 172 ++ arch/arm/dts/k3-am625-beagleplay.dts | 758 ++++++ arch/arm/dts/k3-am625-r5-beagleplay.dts | 87 + arch/arm/dts/k3-am625-sk-binman.dtsi | 4 +- board/ti/am62x/evm.c | 46 + configs/am62x_beagleplay_a53_defconfig | 90 + configs/am62x_beagleplay_r5_defconfig | 110 + doc/board/ti/am62x_beagleplay.rst | 169 ++ doc/board/ti/k3.rst | 5 +- 11 files changed, 3635 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi create mode 100644 arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-beagleplay.dts create mode 100644 arch/arm/dts/k3-am625-r5-beagleplay.dts create mode 100644 configs/am62x_beagleplay_a53_defconfig create mode 100644 configs/am62x_beagleplay_r5_defconfig create mode 100644 doc/board/ti/am62x_beagleplay.rst -- 2.40.0

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CVE-2019-14194 patch bypass
by sploit em 26 Dec '23

26 Dec '23

Hello. I was analyzing CVE-2019-14194 and I think the patch can be bypassed. patch <https://source.denx.de/u-boot/u-boot/-/commit/aa207cf3a6d68f39d64cd29057a4f…> In nfs_read_reply, rlen is signed int. So we can make it less than zero. The value less than zero can bypass the check at line 756. This will lead to overflow due that assign has an unsigned int len parameter. For example -1 will become 0xffffffff. [image: nfs_read_reply_cve_2019_14194.png] I've constructed some code to prove this. [image: nfs_read_reply_cve_2019_14194_bypass.png] [image: nfs_read_reply_cve_2019_14194_3.png] Thanks.

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[PATCH] rsa: use pkcs11 uri as defined in rfc7512
by Ayoub Zaki 20 Dec '23

20 Dec '23

pkcs11 : change engine uri to use full pk11-URI as defined in: https://www.rfc-editor.org/rfc/rfc7512.html Signed-off-by: Ayoub Zaki <ayoub.zaki(a)embetrix.com> --- doc/uImage.FIT/signature.txt | 2 +- lib/rsa/rsa-sign.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt index c71280b63b..2ff0db3f98 100644 --- a/doc/uImage.FIT/signature.txt +++ b/doc/uImage.FIT/signature.txt @@ -681,7 +681,7 @@ $ ./tools/mkimage -f fit-image.its fitImage Sign the fitImage with the hardware key: $ ./tools/mkimage -F -k \ -"model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29" \ +"pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29" \ -K u-boot.dtb -N pkcs11 -r fitImage diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index d20bdb58a5..7ae163f264 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -116,15 +116,15 @@ static int rsa_engine_get_pub_key(const char *keydir, const char *name, if (keydir) if (strstr(keydir, "object=")) snprintf(key_id, sizeof(key_id), - "pkcs11:%s;type=public", + "%s;type=public", keydir); else snprintf(key_id, sizeof(key_id), - "pkcs11:%s;object=%s;type=public", + "%s;object=%s;type=public", keydir, name); else snprintf(key_id, sizeof(key_id), - "pkcs11:object=%s;type=public", + "object=%s;type=public", name); } else if (engine_id) { if (keydir) @@ -238,15 +238,15 @@ static int rsa_engine_get_priv_key(const char *keydir, const char *name, if (keydir) if (strstr(keydir, "object=")) snprintf(key_id, sizeof(key_id), - "pkcs11:%s;type=private", + "%s;type=private", keydir); else snprintf(key_id, sizeof(key_id), - "pkcs11:%s;object=%s;type=private", + "%s;object=%s;type=private", keydir, name); else snprintf(key_id, sizeof(key_id), - "pkcs11:object=%s;type=private", + "object=%s;type=private", name); } else if (engine_id) { if (keydir && name) -- 2.34.1

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[PATCH] imxtract: specify max gunzip size
by Nikita Shubin 20 Dec '23

20 Dec '23

From: Nikita Shubin <n.shubin(a)yadro.com> Specify max gunzip size from config to override SYS_XIMG_LEN default value wich is 0x800000. Signed-off-by: Nikita Shubin <n.shubin(a)yadro.com> --- cmd/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index d93731f2af6..06e200802d1 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -481,6 +481,13 @@ config CMD_XXD help Print file as hexdump to standard output +config SYS_XIMG_LEN + hex "imxtract max gunzip size" + default 0x800000 + depends on CMD_XIMG + help + Specify max gunzip size for imxtract tool. + config CMD_SPL bool "spl export - Export boot information for Falcon boot" depends on SPL -- 2.37.4

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[RFC PATCH] mxs: Don't enable 4P2 reg if mx28 is powered only from DCDC_BATT without 5V
by Alan Kay 19 Dec '23

19 Dec '23

mxs_power_enable_4p2() was added to mxs_batt_boot() in 'commit a0f97610757d ("ARM: mxs: Enable DCDC converter for battery boot")' to enable DCDC converter when board is powered from 5V and has detected sufficient battery voltage. This involves enabling 4P2 regulator and there is a code in mxs_power_enable_4p2() that disables VDDIO, VDDA, VDDD outputs of the DCDC converter and enables BO for each power rail e.g. setbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); In case the mx28 is powered by the 5V source and linear regulators are supplying power to the VDDIO, VDDA, VDDD rails there is no issue. However if the mx28 is powered by the DCDC_BATT source only without 5V, disabling the DCDC converter outputs causes brownout power down. The proposed solution is not to call mxs_power_enable_4p2() at all if the mx28 is powered by the DCDC_BATT source only. There is no reason to enable 4P2 regulator in this case and setup of all registers is done in mxs_batt_boot(). Also there is no need to enable 5V brownout in mxs_power_init() in this case. Please consider if this is acceptable and I will submit a proper patch. Signed-off-by: Alan Kay <alan(a)londelec.com> --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c33170f06d..c8feadce54 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -752,7 +752,9 @@ static void mxs_batt_boot(void) POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +#ifndef CONFIG_SPL_MXS_NO_VDD5V_SOURCE mxs_power_enable_4p2(); +#endif } /** @@ -1267,7 +1269,9 @@ void mxs_power_init(void) POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); +#ifndef CONFIG_SPL_MXS_NO_VDD5V_SOURCE writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); +#endif early_delay(1000); } -- 2.25.1

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[PATCH] arm: dts: imx8mm_evk: Fix PMIC definition
by Alexander Koch 15 Dec '23

15 Dec '23

Newer revisions of the i.MX8MM EVK are equipped with a different PMIC than the initial ones (PCA9540 instead of BD71847), which has already been reflected in 4c07a21e5. These changes have been reverted implicitly as part of the device tree re-sync with the Linux kernel done in 24a7a3c1c. This lead to an inconsistent state: while the device tree describes the old PMIC again the code in board/freescale/imx8mm_evk/spl.c tries to initialize the new PMIC: ret = pmic_get("pca9450@25", &dev); if (ret == -ENODEV) { puts("No pmic\n"); return 0; } This leads to the expected error message from SPL: U-Boot SPL 2023.07.02 (Sep 04 2023 - 15:57:57 +0200) -> No pmic SEC0: RNG instantiated WDT: Started watchdog@30280000 with servicing every 1000ms (60s timeout) Trying to boot from NOR NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.6-0-g15e8ff164 NOTICE: BL31: Built : 13:51:09, Sep 4 2023 Fix by re-applying the device tree changes from 4c07a21e5. Signed-off-by: Alexander Koch <akoch(a)initse.com> --- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +- arch/arm/dts/imx8mm-evk.dtsi | 126 ++++++++++++++-------------- 2 files changed, 67 insertions(+), 63 deletions(-) diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 13688ec0d0..1bc7e4a38b 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -121,11 +121,11 @@ bootph-pre-ram; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { bootph-pre-ram; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 7d6317d95b..f2c15bf0ff 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -183,114 +183,118 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450a"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; + regulator-ramp-delay = <3125>; }; - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; + regulator-ramp-delay = <3125>; }; - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; }; - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - ldo1_reg: LDO1 { - regulator-name = "ldo1"; + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo2_reg: LDO2 { - regulator-name = "ldo2"; + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; + regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; }; }; -- 2.42.0

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[PATCH v1] drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flash
by Jit Loon Lim 14 Dec '23

14 Dec '23

From: Teik Heng Chong <teik.heng.chong(a)intel.com> Add Support for GigaDevice GD55LB02GEBIR SPI NOR flash as QSPI configuration flash Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3f8b796789..3ca46330bb 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -200,6 +200,11 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + { + INFO("gd55lb02ge", 0xc8671c, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- 2.26.2

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