September 2023 - U-Boot

[PATCH v4 00/20] x86: efi: Fixes and improvements for coreboot
by Simon Glass 20 Sep '23

20 Sep '23

This little series fixes various bugs and annoyances in coreboot and coreboot64. With this both coreboot and coreboot64 start up and work reasonably well on Brya (x86 Chromebook) and U-Boot can boot common Linux distros. - Make coreboot64 debug UART start reliably - Avoid the long USB-init delay on startup - Correct the timer speed on coreboo64 - Fix a bootstd cros bug (will likely be squashed into another patch) - Fix the terribly slow console scrolling With v2 I have also brought in some lost x86 patches so they are all in one series. Changes in v4: - Fix arm and riscv - Rewrite this to use events instead Changes in v3: - Allow SMBIOS if EFI_LOADER is enabled - Reword the help - Use log_debug() to show the message - Squash in the next patch Changes in v2: - Update the malloc size too - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch Simon Glass (20): x86: coreboot: Add IDE and SATA x86: coreboot: Enable standard boot x86: coreboot: Rearrange arch_cpu_init() x86: Set the CPU vendor in SPL x86: Allow APCI in SPL x86: coreboot: Look for DBG2 UART in SPL too x86: coreboot: Enable CONFIG_SYS_NS16550_MEM32 x86: coreboot: Drop USB init on startup x86: coreboot: Align options between coreboot and coreboot64 x86: coreboot: Enable VIDEO_COPY efi: x86: Correct the condition for installing ACPI tables x86: smbios: Add a Kconfig indicating SMBIOS-table presence bootstd: Keep track of use of usb stop Record the position of the SMBIOS tables efi: Use the installed SMBIOS tables x86: coreboot: Record the position of the SMBIOS tables x86: doc: Move into its own directory x86: doc: Update summaries and add links x86: doc: Split out manual booting into its own file x86: doc: coreboot: Mention 64-bit Linux distros arch/arm/include/asm/global_data.h | 3 + arch/riscv/include/asm/global_data.h | 3 + arch/sandbox/include/asm/global_data.h | 1 + arch/x86/cpu/coreboot/coreboot.c | 16 +- arch/x86/cpu/x86_64/cpu.c | 7 + arch/x86/dts/coreboot.dts | 1 + arch/x86/include/asm/global_data.h | 1 + arch/x86/lib/coreboot/cb_sysinfo.c | 1 + arch/x86/lib/tables.c | 3 + board/Marvell/mvebu_armada-37xx/board.c | 2 + boot/bootdev-uclass.c | 27 +++ configs/coreboot64_defconfig | 25 +- configs/coreboot_defconfig | 21 +- doc/arch/index.rst | 2 +- doc/arch/x86/index.rst | 12 + doc/arch/x86/manual_boot.rst | 276 ++++++++++++++++++++++ doc/arch/{ => x86}/x86.rst | 295 ++---------------------- doc/board/coreboot/coreboot.rst | 38 ++- drivers/serial/Kconfig | 2 +- drivers/usb/host/usb-uclass.c | 8 + drivers/video/coreboot.c | 12 + include/asm-generic/global_data.h | 8 + include/bootdev.h | 9 + lib/Kconfig | 24 +- lib/efi_loader/Makefile | 4 +- lib/efi_loader/efi_setup.c | 20 +- lib/efi_loader/efi_smbios.c | 72 +++--- test/py/tests/test_event_dump.py | 1 + 28 files changed, 544 insertions(+), 350 deletions(-) create mode 100644 doc/arch/x86/index.rst create mode 100644 doc/arch/x86/manual_boot.rst rename doc/arch/{ => x86}/x86.rst (64%) -- 2.42.0.rc1.204.g551eb34607-goog

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[PATCH] mx8m: csf.sh: pad csf blob for u-boot.itb to CSF_SIZE minus IVT header
by Rasmus Villemoes 20 Sep '23

20 Sep '23

When built with CONFIG_IMX_HAB, the full FIT image, including stuff tacked on beyond the end of the fdt structure, is expected to be (fdt size rounded up to 0x1000 boundary)+CONFIG_CSF_SIZE. Now, when the FIT image is loaded from a storage device, it doesn't really matter that the flash.bin that gets written to target isn't quite that big - we will just load some garbage bytes that are never read or used for anything. But when flash.bin is uploaded via uuu, it's important that we actually serve at least as many bytes as the target expects, or we will hang in rom_api_download_image(). Extend the logic in the csf.sh script so that the csf blob is padded to CONFIG_CSF_SIZE minus the size of the IVT header. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- doc/imx/habv4/csf_examples/mx8m/csf.sh | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh index 65c143073c..80edc94aeb 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf.sh +++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh @@ -75,5 +75,13 @@ dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc # Generate CSF blob cst -i csf_fit.tmp -o csf_fit.bin + +# When loading flash.bin via USB, we must ensure that the file being +# served is as large as the target expects (see +# board_spl_fit_size_align()), otherwise the target will hang in +# rom_api_download_image() waiting for the remaining bytes. +CSF_SIZE=$(sed -n "/CONFIG_CSF_SIZE=/ s@.*=@@p" .config) +truncate -s $((CSF_SIZE - 0x20)) csf_fit.bin + # Patch CSF blob into flash.bin dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc -- 2.37.2

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[PATCH v5 00/21] Kconfig: Tidy up some options
by Simon Glass 19 Sep '23

19 Sep '23

The view from 'make menuconfig' is confusing in places. This series aims to improve the top-level menu and also the boot menu. It also groups FDT-fixup options tegether, at least the ones I could fine. Finally this series marks the distro scripts as deprecated, so people have a pointer to standard boot. Changes in v5: - Add back the Makefile condition, for efi-app builds Changes in v4: - Just move these options to driver/video for later consideration - Allow TIMESTAMP without FIT - Add new patch to drop SPL/TPL_RAM_SUPPORT option for SPL_LOAD_FIT_ADDRESS - Add new patch to make ARCH_FIXUP_FDT_MEMORY depend on OF_LIBFDT Changes in v3: - Drop comment about an update/ directory - Drop extra newline and quote - Add new patch to drop CMD_MTDPARTS condition for FDT_FIXUP_PARTITIONS - Drop patch 'Move SYS_RX_ETH_BUFFER into the network menu' - Drop patch 'video: Move BMP options and code to video directory' Changes in v2: - Add new patch to move bmp code to drivers/video - Fix FMU typo in the subject - Drop now-unnecessary depends on FWU_MULTI_BANK_UPDATE - Mention in the DISTRO_DEFAULTS option that it is script-based - Expand and rewrite the commit message - Use the word 'Mark' instead of 'Make' to improve the English Simon Glass (21): lib: rational: Move the Kconfigs into the correct place Kconfig: Move API into general setup video: Move bmp code to drivers/video video: Move the BMP options FWU: Avoid showing an unselectable menu option test: Move POST under a renamed Testing section boot: Move fdt_support to boot/ Move fdt_simplefb to boot/ boot: Move some other fdt-fixup options to the same menu boot: Rename Android-boot text Kconfig: Create a menu for FIT spl: Tidy up load address in spl_ram spl: Drop SPL/TPL_RAM_SUPPORT option for SPL_LOAD_FIT_ADDRESS Kconfig: Move SPL_FIT under FIT boot: Make standard boot a menu Kconfig: Move TEXT_BASE et al under general setup Mark DISTRO_DEFAULTS as deprecated Make ARCH_FIXUP_FDT_MEMORY depend on OF_LIBFDT boot: Join FDT_FIXUP_PARTITIONS with related options boot: Drop CMD_MTDPARTS condition for FDT_FIXUP_PARTITIONS boot: Join ARCH_FIXUP_FDT_MEMORY with related options Kconfig | 67 +++++++++- boot/Kconfig | 222 +++++++++++++------------------- boot/Makefile | 4 + {common => boot}/fdt_simplefb.c | 0 {common => boot}/fdt_support.c | 0 common/Kconfig | 20 --- common/Makefile | 4 - common/spl/spl_ram.c | 19 ++- doc/develop/bootstd.rst | 23 ++++ drivers/video/Kconfig | 16 +++ drivers/video/Makefile | 1 + {common => drivers/video}/bmp.c | 0 lib/Kconfig | 17 +-- lib/fwu_updates/Kconfig | 9 +- test/Kconfig | 12 +- 15 files changed, 225 insertions(+), 189 deletions(-) rename {common => boot}/fdt_simplefb.c (100%) rename {common => boot}/fdt_support.c (100%) rename {common => drivers/video}/bmp.c (100%) -- 2.42.0.459.ge4e396fd5e-goog

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[PATCH 1/2] Reland "x86: Move FACP table into separate functions""
by Simon Glass 19 Sep '23

19 Sep '23

Each board has its own way of creating this table. Rather than calling the acpi_create_fadt() function for each one from a common acpi_write_fadt() function, just move the writer into the board-specific code. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Make another attempt to land this. It apparently breaks Edison but I cannot test that board, nor can I work out what is wrong with the code. Previous test report is here: https://lore.kernel.org/all/Yga9Z7sBFAeV64FV@smile.fi.intel.com/ Looking at the image, the method is definitely present: $ nm /tmp/b/edison/u-boot |grep acpi_writer 0115fde0 D _u_boot_list_2_acpi_writer_2_0base 0115fdf0 D _u_boot_list_2_acpi_writer_2_1facs 0115fe00 D _u_boot_list_2_acpi_writer_2_3dsdt 0115fe10 D _u_boot_list_2_acpi_writer_2_4gnvs 0115fe20 D _u_boot_list_2_acpi_writer_2_5csrt 0115fe30 D _u_boot_list_2_acpi_writer_2_5fadt 0115fe40 D _u_boot_list_2_acpi_writer_2_5mcfg 0115fe50 D _u_boot_list_2_acpi_writer_2_5spcr 0115fe60 D _u_boot_list_2_acpi_writer_2_5tcpa 0115fe70 D _u_boot_list_2_acpi_writer_2_5tpm2 0115fe80 D _u_boot_list_2_acpi_writer_2_5x86 0115fe90 D _u_boot_list_2_acpi_writer_2_6ssdt 0115fea0 D _u_boot_list_2_acpi_writer_2_8dev I wonder if the code in quark_write_fadt() is not being called? 'acpi list' shows what tables are installed. On minnowmax there is no difference with or without this patch. Perhaps someone with sharper eyes than me can figure this out? The mechanism is that the functions to be called are put in a linker list, each element being declared using ACPI_WRITER(function_name). Then acpi_write_all() is called to write each one. Debugging could be added to that function, perhaps? arch/x86/cpu/apollolake/acpi.c | 17 +++++++++++++---- arch/x86/cpu/baytrail/acpi.c | 27 +++++++++++++++++++-------- arch/x86/cpu/quark/acpi.c | 27 +++++++++++++++++++-------- arch/x86/cpu/tangier/acpi.c | 25 +++++++++++++++++-------- arch/x86/include/asm/acpi_table.h | 2 -- arch/x86/lib/acpi_table.c | 15 --------------- 6 files changed, 68 insertions(+), 45 deletions(-) diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c index fd21c0b49684..16aaed7238ab 100644 --- a/arch/x86/cpu/apollolake/acpi.c +++ b/arch/x86/cpu/apollolake/acpi.c @@ -146,16 +146,25 @@ void fill_fadt(struct acpi_fadt *fadt) fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR; } -void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, - void *dsdt) +static int apl_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry) { - struct acpi_table_header *header = &fadt->header; + struct acpi_table_header *header; + struct acpi_fadt *fadt; - acpi_fadt_common(fadt, facs, dsdt); + fadt = ctx->current; + acpi_fadt_common(fadt, ctx->facs, ctx->dsdt); intel_acpi_fill_fadt(fadt); fill_fadt(fadt); + header = &fadt->header; header->checksum = table_compute_checksum(fadt, header->length); + + acpi_add_table(ctx, fadt); + + acpi_inc(ctx, sizeof(struct acpi_fadt)); + + return 0; } +ACPI_WRITER(5fadt, "FADT", apl_write_fadt, 0); int apl_acpi_fill_dmar(struct acpi_ctx *ctx) { diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 07757b88a305..4c526ff27310 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -15,20 +15,24 @@ #include <asm/arch/iomap.h> #include <dm/uclass-internal.h> -void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, - void *dsdt) +static int baytrail_write_fadt(struct acpi_ctx *ctx, + const struct acpi_writer *entry) { - struct acpi_table_header *header = &(fadt->header); + struct acpi_table_header *header; + struct acpi_fadt *fadt; + + fadt = ctx->current; + header = &fadt->header; u16 pmbase = ACPI_BASE_ADDRESS; - memset((void *)fadt, 0, sizeof(struct acpi_fadt)); + memset(fadt, '\0', sizeof(struct acpi_fadt)); acpi_fill_header(header, "FACP"); header->length = sizeof(struct acpi_fadt); header->revision = 4; - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; + fadt->firmware_ctrl = (u32)ctx->facs; + fadt->dsdt = (u32)ctx->dsdt; fadt->preferred_pm_profile = ACPI_PM_MOBILE; fadt->sci_int = 9; fadt->smi_cmd = 0; @@ -75,9 +79,9 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, fadt->reset_reg.addrh = 0; fadt->reset_value = SYS_RST | RST_CPU | FULL_RST; - fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_l = (u32)ctx->facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_l = (u32)ctx->dsdt; fadt->x_dsdt_h = 0; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; @@ -137,7 +141,14 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, fadt->x_gpe1_blk.addrh = 0x0; header->checksum = table_compute_checksum(fadt, header->length); + + acpi_add_table(ctx, fadt); + + acpi_inc(ctx, sizeof(struct acpi_fadt)); + + return 0; } +ACPI_WRITER(5fadt, "FADT", baytrail_write_fadt, 0); int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 82b776ff65f6..92fa5bc30c36 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -10,20 +10,24 @@ #include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> -void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, - void *dsdt) +static int quark_write_fadt(struct acpi_ctx *ctx, + const struct acpi_writer *entry) { - struct acpi_table_header *header = &(fadt->header); u16 pmbase = ACPI_PM1_BASE_ADDRESS; + struct acpi_table_header *header; + struct acpi_fadt *fadt; - memset((void *)fadt, 0, sizeof(struct acpi_fadt)); + fadt = ctx->current; + header = &fadt->header; + + memset(fadt, '\0', sizeof(struct acpi_fadt)); acpi_fill_header(header, "FACP"); header->length = sizeof(struct acpi_fadt); header->revision = 4; - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; + fadt->firmware_ctrl = (u32)ctx->facs; + fadt->dsdt = (u32)ctx->dsdt; fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED; fadt->sci_int = 9; fadt->smi_cmd = 0; @@ -70,9 +74,9 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, fadt->reset_reg.addrh = 0; fadt->reset_value = SYS_RST | RST_CPU | FULL_RST; - fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_l = (u32)ctx->facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_l = (u32)ctx->dsdt; fadt->x_dsdt_h = 0; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; @@ -132,7 +136,14 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, fadt->x_gpe1_blk.addrh = 0x0; header->checksum = table_compute_checksum(fadt, header->length); + + acpi_add_table(ctx, fadt); + + acpi_inc(ctx, sizeof(struct acpi_fadt)); + + return 0; } +ACPI_WRITER(5fadt, "FADT", quark_write_fadt, 0); int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 3ffba3897aad..01b30553818c 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -16,19 +16,23 @@ #include <asm/arch/iomap.h> #include <dm/uclass-internal.h> -void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, - void *dsdt) +static int tangier_write_fadt(struct acpi_ctx *ctx, + const struct acpi_writer *entry) { - struct acpi_table_header *header = &(fadt->header); + struct acpi_table_header *header; + struct acpi_fadt *fadt; - memset((void *)fadt, 0, sizeof(struct acpi_fadt)); + fadt = ctx->current; + header = &fadt->header; + + memset(fadt, '\0', sizeof(struct acpi_fadt)); acpi_fill_header(header, "FACP"); header->length = sizeof(struct acpi_fadt); header->revision = 6; - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; + fadt->firmware_ctrl = (u32)ctx->facs; + fadt->dsdt = (u32)ctx->dsdt; fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED; fadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT | @@ -41,13 +45,18 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, fadt->minor_revision = 2; - fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_l = (u32)ctx->facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_l = (u32)ctx->dsdt; fadt->x_dsdt_h = 0; header->checksum = table_compute_checksum(fadt, header->length); + + acpi_inc(ctx, sizeof(struct acpi_fadt)); + + return 0; } +ACPI_WRITER(5fadt, "FADT", tangier_write_fadt, 0); u32 acpi_fill_madt(u32 current) { diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 72e1873d15dc..226753b65d6a 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -24,8 +24,6 @@ struct acpi_table_header; /* These can be used by the target port */ -void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, - void *dsdt); int acpi_create_madt_lapics(u32 current); int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr, u32 gsi_base); diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index e3b7e9a4bbe8..c5b33dc65de4 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -458,21 +458,6 @@ int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry) } ACPI_WRITER(4gnvs, "GNVS", acpi_write_gnvs, 0); -static int acpi_write_fadt(struct acpi_ctx *ctx, - const struct acpi_writer *entry) -{ - struct acpi_fadt *fadt; - - fadt = ctx->current; - acpi_create_fadt(fadt, ctx->facs, ctx->dsdt); - acpi_add_table(ctx, fadt); - - acpi_inc(ctx, sizeof(struct acpi_fadt)); - - return 0; -} -ACPI_WRITER(5fact, "FADT", acpi_write_fadt, 0); - /** * acpi_write_hpet() - Write out a HPET table * -- 2.42.0.rc1.204.g551eb34607-goog

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[PATCH v2] clk: ti: Notify AVS driver upon setting clock rate
by Udit Kumar 19 Sep '23

19 Sep '23

AVS is enabled at R5 SPL stage, on few platforms like J721E and J7200 clk-k3 is used instead if clk-sci driver. Add support in clk-k3 driver as well to notify AVS driver upon setting clock rate so that voltage is changed accordingly. Cc: Keerthy <j-keerthy(a)ti.com> Signed-off-by: Udit Kumar <u-kumar1(a)ti.com> --- Change log: Changes in v2: - Kept clk-sci.c as is because this is used by AM64 and AM65 platforms - v1 link https://lore.kernel.org/all/20230919060649.2518147-1-u-kumar1@ti.com/ drivers/clk/ti/clk-k3.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index ba925fa3c4..8016c3784a 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -11,6 +11,7 @@ #include <errno.h> #include <soc.h> #include <clk-uclass.h> +#include <k3-avs.h> #include "k3-clk.h" #define PLL_MIN_FREQ 800000000 @@ -339,6 +340,10 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate) } } + if (IS_ENABLED(CONFIG_K3_AVS0)) + k3_avs_notify_freq(data->map[clk->id].dev_id, + data->map[clk->id].clk_id, rate); + return new_rate; } -- 2.34.1

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[PATCH 00/36] expo: Support editing lines of text
by Simon Glass 19 Sep '23

19 Sep '23

So far expo only supports menus. These are quite flexible for various kinds of settings, but cannot deal with free-form input, such as a serial number or a machine name. This series adds support for a textline object, which is a single line of text. It has a maximum length and its value is stored within the expo structure. U-Boot already has a command-line editor which provides most of the features needed by expo. But the code runs in its own loop and only returns when the line is finished. This is not suitable for expo, which must handle a keypress at a time, returning to its caller after each one. In order to use the CLI code, some significant refactoring is included here. This mostly involves moving the internal loop of the CLI to a separate function and recording its state in a struct, just as was done for single keypresses some time back. A minor addition is support for Ctrl-W to delete a word, since strangely this is currently only present in the simple version. The video-console system provides most of the features needed by testline, but a few things are missing. This series provides: - primitive cursor support so the user can see where he is typing - saving and restoring of the text-entry context, so that expo can allow the user to continue where he left off, including deleting previously entered characters correctly (for Truetype) - obtaining the nominal width of a string of n characters, so that a suitable width can be chosen for the textline object Note that no support is provided for clearing the cursor. This was addressed in a previous series[1] which could perhaps be rebased. For this implementation, the cursor is therefore not enabled for the normal command line, only for expo. Reading and writing textline objects is supported for FDT and environment, but not for CMOS RAM, since it would likely use too much RAM to store a string. In terms of code size, the overall size increase is 180 bytes for Thumb02 boards, 160 of whcih is the addition of Ctrl-W to delete a word. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=280178&state=* Simon Glass (36): cli: Move simple readline into a function cli: Add a command to show cmdline history cli: Drop some #ifdefs in cli_readline cli: Drop #ifdefs for CONFIG_AUTO_COMPLETE in cli_readline cli: Implement delete-word in cread_line() cli: Use unsigned int instead of unsigned long cli: Convert cread_line() to use a struct for the main vars cli: Unindent some code in cread_line() cli: Create a function to process characters cli: Terminate the string in cread_line_process_ch() cli: Allow history to be disabled cli: Allow command completion to be disabled cli: Add a function to set up a new cread video: Allow obtaining the nominal size of a string size video: Allow saving and restoring text-entry state video: Export vidconsole_entry_start() video: Support showing a cursor expo: Add better error reporting expo: Fix up comments for get_cur_menuitem_text() et al expo: Use switch statements more for object types expo: Correct some swallowed errors in scene expo: Correct the logic for duplicate-ID detection expo: Allow highlighting other scene-object types expo: Add a function to write a property to a devicetree expo: Make calculation of an object bounding box generic expo: Allow rendering the background of any object expo: Add some scene fields needed for text entry expo: Add basic support for textline objects expo: Support opening a textline expo: Plumb in textlines to a scene video: Mark truetype_measure() static expo: Support handling any key in cedit expo: Plumb in textline to cedit expo: Support building an expo with a textline expo: Update tests to include textline expo: Update documentation to include textline arch/sandbox/dts/cedit.dtsi | 8 + boot/Makefile | 3 +- boot/cedit.c | 196 ++++++++--- boot/expo_build.c | 103 +++++- boot/scene.c | 237 +++++++++++-- boot/scene_internal.h | 128 ++++++- boot/scene_menu.c | 68 +--- boot/scene_textline.c | 229 +++++++++++++ cmd/Kconfig | 7 + cmd/Makefile | 1 + cmd/history.c | 23 ++ common/cli_readline.c | 498 ++++++++++++++++------------ doc/develop/cedit.rst | 3 +- doc/develop/expo.rst | 48 ++- doc/usage/cmd/history.rst | 68 ++++ doc/usage/index.rst | 1 + drivers/video/console_core.c | 31 ++ drivers/video/console_normal.c | 29 ++ drivers/video/console_truetype.c | 191 ++++++++++- drivers/video/vidconsole-uclass.c | 71 +++- drivers/video/vidconsole_internal.h | 24 ++ include/cli.h | 51 +++ include/command.h | 6 + include/expo.h | 60 +++- include/menu.h | 7 +- include/test/cedit-test.h | 5 +- include/video_console.h | 123 +++++++ test/boot/cedit.c | 30 +- test/boot/expo.c | 2 +- test/boot/files/expo_ids.h | 3 + test/boot/files/expo_layout.dts | 8 + test/cmd/Makefile | 1 + test/cmd/history.c | 49 +++ 33 files changed, 1935 insertions(+), 377 deletions(-) create mode 100644 boot/scene_textline.c create mode 100644 cmd/history.c create mode 100644 doc/usage/cmd/history.rst create mode 100644 test/cmd/history.c -- 2.42.0.459.ge4e396fd5e-goog

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[PATCH 0/4] arm: dts: k3-am642: Sync with kernel v6.6-rc1
by Nishanth Menon 19 Sep '23

19 Sep '23

Sync with kernel v6.6-rc1 Bootlog: am642-sk: https://gist.github.com/nmenon/35f509e2f63b0ab0b434625e68e4f37d Nishanth Menon (4): arm: dts: Introduce k3-serdes.h from v6.6-rc1 arm: dts: k3*: Use local header for SERDES MUX idle-state values dt-bindings: ti-serdes: Deprecate header with constants with v6.6-rc1 arm: dts: k3-am642: Sync with kernel v6.6-rc1 arch/arm/dts/k3-am64-main.dtsi | 48 +++++----- arch/arm/dts/k3-am642-evm.dts | 4 +- arch/arm/dts/k3-am642-sk.dts | 8 +- arch/arm/dts/k3-j7200-common-proc-board.dts | 2 +- arch/arm/dts/k3-j721e-main.dtsi | 2 +- .../ti-serdes.h => arch/arm/dts/k3-serdes.h | 90 ++++++++++++++++++- include/dt-bindings/mux/ti-serdes.h | 70 +++++++++++++++ 7 files changed, 186 insertions(+), 38 deletions(-) copy include/dt-bindings/mux/ti-serdes.h => arch/arm/dts/k3-serdes.h (55%) -- 2.40.0

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[PATCH 0/2] arm: dts: k3-am625: Sync with kernel v6.6-rc1
by Nishanth Menon 19 Sep '23

19 Sep '23

Sync device tree with v6.6-rc1 Bootlog: beagleplay: https://gist.github.com/nmenon/b46863248e8cf0cdaaeca0d55c966af4 Nishanth Menon (2): arm: dts: k3-pinctrl: Sync with kernel v6.6-rc1 arm: dts: k3-am625: Sync with kernel v6.6-rc1 arch/arm/dts/k3-am62-main.dtsi | 52 ++++++++- arch/arm/dts/k3-am62-mcu.dtsi | 24 +++++ arch/arm/dts/k3-am62-verdin-dev.dtsi | 50 +++++++++ arch/arm/dts/k3-am62-verdin.dtsi | 45 +++++++- arch/arm/dts/k3-am62.dtsi | 8 ++ arch/arm/dts/k3-am625-beagleplay.dts | 154 ++++++++++++++++++++++++++- arch/arm/dts/k3-am625-sk.dts | 2 +- arch/arm/dts/k3-pinctrl.h | 12 +++ 8 files changed, 337 insertions(+), 10 deletions(-) -- 2.40.0

4 8

[PATCH] drivers: misc: k3_avs: Add Linux compatibles to maintain sync
by Reid Tonking 19 Sep '23

19 Sep '23

The ti,j7200-vtm and ti,j721e-vtm compatibles are used for voltage and thermal monitoring (VTM) by (drivers/thermal/k3_j72xx_bandgap.c) in Linux, but the same hardware is used for adaptive voltage scaling (AVS) in u-boot, This brings both drivers in line with the same compatibles. Since the j7200 uses the config as the j721e, the data is inherited from j721e vs creating a duplicate Signed-off-by: Neha Francis <n-francis(a)ti.com> Signed-off-by: Reid Tonking <reidt(a)ti.com> --- In preparation for syncing k3 socs j721e & j7200, a single patch is being submitted to avoid having dependency complications [0]. This patch will be a dependency for the following series [1] [2], each with another version to follow. [0] https://lore.kernel.org/u-boot/20230907150858.3l6q2yxyfgdx3jvn@mulled/T/#mf… [1] https://lore.kernel.org/u-boot/20230907150858.3l6q2yxyfgdx3jvn@mulled/T/#m8… [2] https://lore.kernel.org/u-boot/20230905181309.61666-1-reidt@ti.com/T/#m8d25… drivers/misc/k3_avs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 840148d090..acfc731845 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -382,6 +382,8 @@ static struct vd_config am654_vd_config = { static const struct udevice_id k3_avs_ids[] = { { .compatible = "ti,am654-avs", .data = (ulong)&am654_vd_config }, { .compatible = "ti,j721e-avs", .data = (ulong)&j721e_vd_config }, + { .compatible = "ti,j721e-vtm", .data = (ulong)&j721e_vd_config }, + { .compatible = "ti,j7200-vtm", .data = (ulong)&j721e_vd_config }, {} }; -- 2.34.1

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[PATCH v2] rockchip: include: asm: fix entering download mode rk3066
by Johan Jonker 19 Sep '23

19 Sep '23

Keep track of the re-entries with help of the lr register. This binary can be re-used and called from various BROM functions. Only when it's called from the part that handles SPI, NAND or EMMC hardware it needs to early return to BROM ones. In download mode when it handles data on USB OTG and UART0 this section must be skipped. Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in support to enter download mode on return to BROM. This binary must check the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set. It then returns to BROM to the end of the function that reads boot blocks. >From there the BROM code goes into a download mode and waits for data on USB OTG and UART0. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- Note: Normal boot flow is OK. In download mode this binary hangs after return to BROM for unknown reasons. Replace CODE471_OPTION with 30_LPDDR2_300MHz_DD.bin for now. Could Rockchip disclose what further conditions must be met in rk3066 download mode? Changed V2: Move file to rk3066 specific location Replace retry_counter by LR check Add DNL mode return address Restyle Reword --- arch/arm/include/asm/arch-rk3066/boot0.h | 77 +++++++++++++++++++++++- arch/arm/mach-rockchip/Kconfig | 17 +++++- arch/arm/mach-rockchip/rk3066/Kconfig | 6 ++ 3 files changed, 98 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h index 28c0fb9a4c6b..1af4b9c1d7ba 100644 --- a/arch/arm/include/asm/arch-rk3066/boot0.h +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -3,6 +3,81 @@ #ifndef __ASM_ARCH_BOOT0_H__ #define __ASM_ARCH_BOOT0_H__ -#include <asm/arch-rockchip/boot0.h> +#include <asm/arch-rockchip/boot_mode.h> +/* + * Execution starts on the instruction following this 4-byte header + * (containing the magic 'RK30'). This magic constant will be written into + * the final image by the rkimage tool, but we need to reserve space for it here. + */ +#ifdef CONFIG_SPL_BUILD + b 1f /* if overwritten, entry-address is at the next word */ +1: +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM) +/* + * Keep track of the re-entries with help of the lr register. + * This binary can be re-used and called from various BROM functions. + * Only when it's called from the part that handles SPI, NAND or EMMC + * hardware it needs to early return to BROM ones. + * In download mode when it handles data on USB OTG and UART0 + * this section must be skipped. + */ + ldr r3, =CONFIG_ROCKCHIP_BOOT_LR_REG + cmp lr, r3 /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG) */ + bne reset /* goto reset; */ +/* + * Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in + * support to enter download mode on return to BROM. This binary must check + * the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set. + * It then returns to BROM to the end of the function that reads boot blocks. + * From there the BROM code goes into a download mode and waits for data + * on USB OTG and UART0. + */ + ldr r2, =BOOT_BROM_DOWNLOAD + ldr r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG + ldr r0, [r3] /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != */ + cmp r0, r2 /* BOOT_BROM_DOWNLOAD) { */ + bne early_return /* goto early_return; */ + /* } else { */ + mov r0, #0 + str r0, [r3] /* writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); */ + + ldr r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG + bx r3 /* return to CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/ + +early_return: + bx lr /* return to LR in BROM */ + +SAVE_SP_ADDR: + .word 0 + + .globl save_boot_params +save_boot_params: + push {r1-r12, lr} + ldr r0, =SAVE_SP_ADDR + str sp, [r0] + b save_boot_params_ret + + .globl back_to_bootrom +back_to_bootrom: + ldr r0, =SAVE_SP_ADDR + ldr sp, [r0] + mov r0, #0 + pop {r1-r12, pc} +#endif + +#if (defined(CONFIG_SPL_BUILD)) +/* U-Boot proper of armv7 does not need this */ + b reset +#endif + +/* + * For armv7, the addr '_start' will be used as vector start address + * and is written to the VBAR register, which needs to aligned to 0x20. + */ + .align(5), 0x0 +_start: + ARM_VECTORS #endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 07b5595dac8c..84a2f0d5ff48 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -402,7 +402,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" default y - select ROCKCHIP_BROM_HELPER + select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066 select TPL_BOOTROM_SUPPORT depends on TPL help @@ -448,6 +448,21 @@ config ROCKCHIP_BOOT_MODE_REG The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. +config ROCKCHIP_BOOT_LR_REG + hex "Rockchip boot early return LR address" + depends on TPL_ROCKCHIP_EARLYRETURN_TO_BROM || SPL_ROCKCHIP_EARLYRETURN_TO_BROM + help + With ROCKCHIP_EARLYRETURN_TO_BROM enabled this LR address is + used to keep track of the re-entries. + +config ROCKCHIP_BOOT_RETURN_REG + hex "Rockchip download mode return address" + depends on TPL_ROCKCHIP_EARLYRETURN_TO_BROM || SPL_ROCKCHIP_EARLYRETURN_TO_BROM + help + Rockchip SoC models without built-in support to enter + download mode after early return to BROM code use a SoC + specific return address in BROM. + config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON bool "Disable device boot on power plug-in" depends on PMIC_RK8XX diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig index 95d7fc8a2917..3721f7469a9e 100644 --- a/arch/arm/mach-rockchip/rk3066/Kconfig +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -10,6 +10,12 @@ config TARGET_MK808 config ROCKCHIP_BOOT_MODE_REG default 0x20004040 +config ROCKCHIP_BOOT_LR_REG + default 0x00001058 + +config ROCKCHIP_BOOT_RETURN_REG + default 0x00001100 + config SYS_SOC default "rk3066" -- 2.39.2

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