August 2023 - U-Boot

[PATCH V2] doc: board: ti: k3: Add a guide to debugging with OpenOCD
by Nishanth Menon 01 Aug '23

01 Aug '23

From: Jason Kacines <j-kacines(a)ti.com> Bootloader debug usually tends to be a bit dicey prior to DDR and serial port getting active in the system. JTAG typically remains the only practical debug option during the initial bringup. OpenOCD is one of the most popular environment for providing debug capability via a gdb compatible interface for developers to work with. Debugging U-boot and bootloaders on K3 platform does have a bit of tribal knowledge that is better documented in our common platform documentation. Signed-off-by: Jason Kacines <j-kacines(a)ti.com> Signed-off-by: Nishanth Menon <nm(a)ti.com> --- Changes since V1: * Merged into k3.rst and added anchors for include, reference to other files * Added documentation for other board documentation. V1: https://lore.kernel.org/u-boot/20230721191934.1959003-1-j-kacines@ti.com/ doc/board/ti/am62x_sk.rst | 16 + doc/board/ti/am65x_evm.rst | 16 + doc/board/ti/img/openocd-overview.svg | 580 ++++++++++++++++++++++++++ doc/board/ti/j7200_evm.rst | 16 + doc/board/ti/j721e_evm.rst | 16 + doc/board/ti/k3.rst | 468 +++++++++++++++++++++ 6 files changed, 1112 insertions(+) create mode 100644 doc/board/ti/img/openocd-overview.svg diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index 637985cb096e..75aa1e827010 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -246,3 +246,19 @@ https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section. - 11001010 For SW2 and SW1, the switch state in the "ON" position = 1. + +Debugging U-boot +---------------- + +See :ref:`Common Debugging environment - openOCD<k3_rst_refer_openocd>`: for +detailed setup information. + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_xds110 + :end-before: .. k3_rst_include_end_openocd_connect_xds110 + +To start OpenOCD to connect to the board + +.. code-block:: bash + + openocd -f board/ti_am625evm.cfg diff --git a/doc/board/ti/am65x_evm.rst b/doc/board/ti/am65x_evm.rst index 0129235c2b29..daea943ebfbb 100644 --- a/doc/board/ti/am65x_evm.rst +++ b/doc/board/ti/am65x_evm.rst @@ -287,3 +287,19 @@ artifacts needed to the device: sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV sleep 1 sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV + +Debugging U-boot +---------------- + +See :ref:`Common Debugging environment - openOCD<k3_rst_refer_openocd>`: for +detailed setup information. + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_xds110 + :end-before: .. k3_rst_include_end_openocd_connect_xds110 + +To start OpenOCD to connect to the board + +.. code-block:: bash + + openocd -f board/ti_am654evm.cfg diff --git a/doc/board/ti/img/openocd-overview.svg b/doc/board/ti/img/openocd-overview.svg new file mode 100644 index 000000000000..a86a5d7939a8 --- /dev/null +++ b/doc/board/ti/img/openocd-overview.svg @@ -0,0 +1,580 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> + + + + +<svg + xmlns:xhtml="http://www.w3.org/1999/xhtml" + xmlns:dc="http://purl.org/dc/elements/1.1/" + xmlns:cc="http://creativecommons.org/ns#" + xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns="http://www.w3.org/2000/svg" + xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" + version="1.1" + width="281px" + height="671px" + viewBox="-0.5 -0.5 281 671" + id="svg128" + sodipodi:docname="openocd-overview.svg" + inkscape:version="0.92.3 (2405546, 2018-03-11)"> + <metadata + id="metadata132"> + <rdf:RDF> + <cc:Work + rdf:about=""> + <dc:format>image/svg+xml</dc:format> + <dc:type + rdf:resource="http://purl.org/dc/dcmitype/StillImage" /> + </cc:Work> + </rdf:RDF> + </metadata> + <sodipodi:namedview + pagecolor="#ffffff" + bordercolor="#666666" + borderopacity="1" + objecttolerance="10" + gridtolerance="10" + guidetolerance="10" + inkscape:pageopacity="0" + inkscape:pageshadow="2" + inkscape:window-width="3440" + inkscape:window-height="1391" + id="namedview130" + showgrid="false" + inkscape:zoom="1.4068554" + inkscape:cx="283.8637" + inkscape:cy="385.05999" + inkscape:window-x="0" + inkscape:window-y="25" + inkscape:window-maximized="1" + inkscape:current-layer="svg128" /> + <defs + id="defs2" /> + <g + id="g118"> + <path + d="M 0 510 L 0 510 L 280 510 L 280 510" + fill="rgb(255, 255, 255)" + stroke="#ff0a1b" + stroke-miterlimit="10" + pointer-events="all" + id="path4" /> + <path + d="M 0 510 L 0 670 L 280 670 L 280 510" + fill="none" + stroke="#ff0a1b" + stroke-miterlimit="10" + pointer-events="none" + id="path6" /> + <rect + x="10" + y="590" + width="100" + height="70" + fill="#f8cecc" + stroke="#b85450" + pointer-events="none" + id="rect8" /> + <path + d="M 20 590 L 20 660 M 100 590 L 100 660" + fill="none" + stroke="#b85450" + stroke-miterlimit="10" + pointer-events="none" + id="path10" /> + <g + transform="translate(-0.5 -0.5)" + id="g16"> + <switch + id="switch14"> + <foreignObject + style="overflow: visible; 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text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 28px; margin-left: 81px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">IDE debugging code</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="140" + y="32" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text112">IDE debugging code</text> + </switch> + </g> + </g> +</svg> diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst index 69abc55a93ce..021ff70d968f 100644 --- a/doc/board/ti/j7200_evm.rst +++ b/doc/board/ti/j7200_evm.rst @@ -201,3 +201,19 @@ fat formatted UDA FS as file. In case of booting from eMMC, write above images into raw or UDA FS. and set mmc partconf accordingly. + +Debugging U-boot +---------------- + +See :ref:`Common Debugging environment - openOCD<k3_rst_refer_openocd>`: for +detailed setup information. + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_xds110 + :end-before: .. k3_rst_include_end_openocd_connect_xds110 + +To start OpenOCD to connect to the board + +.. code-block:: bash + + openocd -f board/ti_j7200evm.cfg diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index f4b4c192d9da..f387a0e5139e 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -228,3 +228,19 @@ J721E common processor board can be attached to a Ethernet QSGMII card and the PHY in the card has to be reset before it can be used for data transfer. "do_main_cpsw0_qsgmii_phyinit" env variable has to be set for the U-BOOT to configure this PHY. + +Debugging U-boot +---------------- + +See :ref:`Common Debugging environment - openOCD<k3_rst_refer_openocd>`: for +detailed setup information. + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_xds110 + :end-before: .. k3_rst_include_end_openocd_connect_xds110 + +To start OpenOCD to connect to the board + +.. code-block:: bash + + openocd -f board/ti_j721eevm.cfg diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 9d40675b6007..825ce2aec90e 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -467,3 +467,471 @@ filesystem and then imported => fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile} => env import -t ${loadaddr} ${filesize} + +.. _k3_rst_refer_openocd: + +Common Debugging environment - OpenOCD +-------------------------------------- + +This section will show you how to connect a board to `OpenOCD +<https://openocd.org/>`_ and load the SPL symbols for debugging with +a K3 generation device. To follow this guide, you must build custom +u-boot binaries, start your board from an boot media such as SD card, +and use OpenOCD environment. This section uses generic examples, +though you can apply these instructions to any supported K3 generation +device. + +Overall structure of this setup is shown in the following figure. + +.. image:: img/openocd-overview.svg + +.. note:: + + If you find these instructions useful, please consider `donating + <https://openocd.org/pages/donations.html>`_ to OpenOCD. + +Step 1: Download and install OpenOCD +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To get started, it is more convenient if the distribution you +use supports OpenOCD by default. Follow the instructions in the +`getting OpenOCD <https://openocd.org/pages/getting-openocd.html>`_ +documentation to pick the installation steps appropriate to your +environment. Some references to OpenOCD documentations: + +* `OpenOCD User Guide <https://openocd.org/doc/html/index.html>`_ +* `OpenOCD Developer's Guide <https://openocd.org/doc/doxygen/html/index.html>`_ + +Refer to the release notes corresponding to the `OpenOCD version +<https://github.com/openocd-org/openocd/releases>`_ to ensure that: + +* Processor is supported: In general, the processor support + shouldn't present any difficulties since OpenOCD provides + solid support for both armv8 and armv7. +* SoC is supported: Support for System-on-a-Chip (SoC) usually + comes in the form of a tcl file that may be merged at various times. + One typically needs to ensure that the correct version of openOCD is + used OR use the tcl files from the mentioned or latest release. +* Board or the jtag adapter is supported: In most cases, board support + is a relatively easy problem to solve if the board has a jtag pin header. + All you need to do is ensure that the adapter you select is compatible + with OpenOCD. Some boards do come with onboard JTAG adapter that just + needs a USB cable to be plugged into the board, in which case, it is + important to ensure that the jtag adapter is supported. Fortunately, + almost all TI K3 SK/EVMs come with TI's xds110 which is supported out + of box with OpenOCD. The board specific documentation will cover the + details and any adapter recommendations. + +.. code-block:: bash + + openocd -v + +.. note:: + + OpenOCD version 0.12.0 is usually required to connect to most of K3 devices. + In case the support is on a newer version that is supported out of box + in your distribution, you may need to build it from source. + +Building OpenOCD from source +"""""""""""""""""""""""""""" + +Following dependency package installation instructions are based on +debian systems, but equivalent instructions should exist on systems +with other package managers. Please refer to `OpenOCD Documentation +<https://openocd.org/>`_ for more recent instructions. + +.. code-block:: bash + + $ sudo apt-get install libtool pkg-config texinfo libusb-dev \ + libusb-1.0.0-dev libftdi-dev libhidapi-dev autoconf automake + $ git clone https://github.com/openocd-org/openocd.git openocd + $ cd openocd + $ git submodule init + $ git submodule update + $ ./bootstrap + $ ./configure --prefix=/usr/local/ + $ make -j`nproc` + $ sudo make install + +.. note:: + + The example above uses the github mirror site. See + `git repo information <https://openocd.org/doc/html/Developers.html#OpenOCD-Git-Repository>`_ + information to pick the official git repo. + If a specific version is desired, select the version using `git checkout tag`. + +Installing OpenOCD udev rules +""""""""""""""""""""""""""""" + +The step is not necessary if the distribution supports the OpenOCD, but if +building from source, ensure that the udev rules are installed correctly to +ensure sane system. + +.. code-block:: bash + + # Go to the OpenOCD source directory + $ cd openocd + # Copy the udev rules to the correct system location + $ sudo cp ./contrib/60-openocd.rules \ + ./src/jtag/drivers/libjaylink/contrib/99-libjaylink.rules \ + /etc/udev/rules.d/ + # Get Udev to load the new rules up + $ sudo udevadm control --reload-rules + # Use the new rules on existing connected devices + $ sudo udevadm trigger + +Step 2: Setup gdb +^^^^^^^^^^^^^^^^^ + +Most systems come with gdb-multiarch package. + +.. code-block:: bash + + # Go to the OpenOCD source directory + $ sudo apt-get install gdb-multiarch + +Though using gdb natively is normal, developers with interest in using IDE +will find few of these interesting: + +* `gdb-dashboard <https://github.com/cyrus-and/gdb-dashboard>`_ +* `gef <https://github.com/hugsy/gef>`_ +* `peda <https://github.com/longld/peda>`_ +* `pwndbg <https://github.com/pwndbg/pwndbg>`_ +* `voltron <https://github.com/snare/voltron>`_ +* `ddd <https://www.gnu.org/software/ddd/>`_ +* `vscode <https://www.justinmklam.com/posts/2017/10/vscode-debugger-setup/>`_ +* `vim conque-gdb <https://github.com/vim-scripts/Conque-GDB>`_ +* `emacs realgud <https://github.com/realgud/realgud/wiki/gdb-notes>`_ +* `lauterbach IDE <https://www2.lauterbach.com/pdf/backend_gdb.pdf>`_ + +.. warning:: + lldb support for OpenOCD is still a work in progress as of this writing. + Using gdb is probably the safest option at this point in time. + +Step 3: Setup of board to PC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +There are few patterns of boards in the ecosystem + +.. k3_rst_include_start_openocd_connect_xds110 + +**Integrated JTAG adapter**: The board has a micro-USB connector labelled +XDS110 USB or JTAG. Connect a USB cable to the board to the mentioned port. + +.. note:: + + There are multiple USB ports on a typical board, So, ensure you have read + the user guide for the board and confirm the silk screen label to ensure + connecting to the correct port. + +.. k3_rst_include_end_openocd_connect_xds110 + +.. k3_rst_include_start_openocd_connect_cti20 + +**cTI20 connector**: The TI's `cTI20 +<https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_jtag_connec…>`_ connector +is probably the most prevelant on TI platforms. Though many +TI boards do have onboard xds110, cTI20 connector is usually +provided as an alternate scheme to connect alternatives such +as `Lauterbach <https://www.lauterbach.com/>`_ or `xds560 +<https://www.ti.com/tool/TMDSEMU560V2STM-U>`_. + +To debug on these boards, the following combinations is suggested: + +* `TUMPA <https://www.diygadget.com/jtag-cables-and-microcontroller-programmers/tiao-…>`_ + or equivalent supported by OpenOCD +* Cable such as `Tag-connect ribbon cable <https://www.tag-connect.com/product/20-pin-cortex-ribbon-cable-4-length-wit…>`_ +* Adapter to convert cTI20 to ARM20 such as those from + `Segger <https://www.segger.com/products/debug-probes/j-link/accessories/adapters/ti…>`_ + `Lauterbach LA-3780 <https://www.lauterbach.com/ad3780.html>`_ + Or optionally, if you have manufacturing capability then you could try + `beagle bone jtag adapter <https://github.com/mmorawiec/BeagleBone-Black-JTAG-Adapters>`_ + +.. warning:: + XDS560 and Lauterbach are proprietary solutions and is not supported by + OpenOCD. + When purchasing off the shelf adapters, you do want to be careful about the + signalling though. Please `read for additional info <https://software-dl.ti.com/ccs/esd/xdsdebugprobes/emu_jtag_connectors.html>`_ + +.. k3_rst_include_end_openocd_connect_cti20 + +.. k3_rst_include_start_openocd_connect_tag_connect + +**Tag-Connect**: `Tag-Connect <https://www.tag-connect.com/>`_ +pads on the boards which require special cable. Please check the documentation +to `identify <https://www.tag-connect.com/info/legs-or-no-legs>`_ if "legged" +or "no-leg" version of the cable is appropriate for the board. + +To debug on these boards, you will need: + +* `TUMPA <https://www.diygadget.com/jtag-cables-and-microcontroller-programmers/tiao-…>`_ + or equivalent supported by OpenOCD +* Tag-Connect cable appropriate to the board such as + `tc2050-idc-nl <https://www.tag-connect.com/product/tc2050-idc-nl-10-pin-no-legs-cable-with…>`_ +* In case of no-leg, version, a + `retaining clip <https://www.tag-connect.com/product/tc2050-clip-3pack-retaining-clip>`_ +* Tag-Connect to ARM20 + `adapter <https://www.tag-connect.com/product/tc2050-arm2010-arm-20-pin-to-tc2050-ada…>`_ + +.. note:: + You can optionally use a 3d printed solution such as + `Protective cap <https://www.thingiverse.com/thing:3025584>`_ or + `clip <https://www.thingiverse.com/thing:3035278>`_ to replace + the retaining clip. + +.. warning:: + With the Tag-Connect to ARM20 adapter, Please solder the "Trst" signal for + connection to work. + +.. k3_rst_include_end_openocd_connect_tag_connect + +Debugging with OpenOCD +^^^^^^^^^^^^^^^^^^^^^^ + +Debugging U-boot is different from debugging regular user space +applications. The bootloader initialization process involves many boot +media and hardware configuration operations. For K3 devices, there +are also interactions with security firmware. While reloading the +"elf" file works through gdb, developers must be mindful of cascading +initialization's potential consequences. + +Consider the following code change: + +.. code-block:: diff + + --- a/file.c 2023-07-29 10:55:29.647928811 -0500 + +++ b/file.c 2023-07-29 10:55:46.091856816 -0500 + @@ -1,3 +1,3 @@ + val = readl(reg); + -val |= 0x2; + +val |= 0x1; + writel(val, reg); + +Re-running the elf file with the above change will result in the +register setting 0x3 instead of the intended 0x1. There are other +hardware blocks which may not behave very well with re-initialization +sequence without proper shutdown. + +To help narrow the debug down, it is usually more simpler to use the +standard boot media to get to the booloader and debug only in the area +of interest. + +In general, to debug u-boot spl/u-boot with OpenOCD there are three steps: + +* Modify the code to put a loop to allow debugger to attach near the point + of interest. Boot up normally to stop at the loop. +* Connect with OpenOCD and step out of the loop +* Step through code to find the root of issue + +Typical debug involves a few iterations of the above sequence. Though +most bootloader developers like to use printf to debug, debug with +jtag tends to be most efficient since it is possible to investigate +code flow and inspect hardware registers without repeated iterations. + +Code modification +""""""""""""""""" + +* **start.S**: Adding an infinite while loop at the very entry of + U-Boot. For this, look for the corresponding start.S entry file. + This is usually only required when debugging some core SoC or + processor related function. For example: arch/arm/cpu/armv8/start.S or + arch/arm/cpu/armv7/start.S + +.. code-block:: diff + + diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S + index 69e281b086..744929e825 100644 + --- a/arch/arm/cpu/armv7/start.S + +++ b/arch/arm/cpu/armv7/start.S + @@ -37,6 +37,8 @@ + #endif + + reset: + +dead_loop: + + b dead_loop + /* Allow the board to save important registers */ + b save_boot_params + save_boot_params_ret: + +* **board_init_f**: Adding an infinite while loop at the board entry + function. In many cases, it is important to debug the boot process if + any changes are made for board-specific applications. Below is a step + by step process for debugging the boot SPL or Armv8 SPL: + + To debug the boot process in either domain, we will first + add a modification in the code we would like to debug. + In this example, we will debug ``board_init_f`` inside + ``arch/arm/mach-k3/{soc}_init.c``. Since some sections of U-Boot + will be executed multiple times during the bootup process of K3 + devices, we will need to include either ``CONFIG_CPU_ARM64`` or + ``CONFIG_CPU_V7R`` to catch the CPU at the desired place during the + bootup process (Main or Wakeup domains). For example, modify the + file as follows (depending on need): + +.. code-block:: c + + void board_init_f(ulong dummy) + { + . + . + /* Code to run on the R5F (Wakeup/Boot Domain) */ + if (IS_ENABLED(CONFIG_CPU_V7R)) { + volatile int x = 1; + while(x) {}; + } + ... + /* Code to run on the ARMV8 (Main Domain) */ + if (IS_ENABLED(CONFIG_CPU_ARM64)) { + volatile int x = 1; + while(x) {}; + } + . + . + } + +Connecting with OpenOCD for debug session +""""""""""""""""""""""""""""""""""""""""" + +Startup openocd to debug the platform as follows: + +* **integrated jtag interface**: If the evm has a debugger such as + xds110 inbuilt, there is typically an evm board support added and a + cfg file will be available. + +.. k3_rst_include_start_openocd_cfg_xds110 + +.. code-block:: bash + + openocd -f board/{board_of_choice}.cfg + +.. k3_rst_include_end_openocd_cfg_xds110 + +* **External jtag adapter/interface**: In other cases, where an + adapter is used, a simple cfg file can be created to integrate the SoC + and adapter information. See `supported TI K3 SoCs + <https://github.com/openocd-org/openocd/blob/master/tcl/target/ti_k3.cfg#L59>`_ + to decide if the SoC is supported or not. + + For example, with BeaglePlay (AM62X platform): + +.. code-block:: tcl + + # TUMPA example: + # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual + source [find interface/ftdi/tumpa.cfg] + + transport select jtag + + # default JTAG configuration has only SRST and no TRST + reset_config srst_only srst_push_pull + + # delay after SRST goes inactive + adapter srst delay 20 + + if { ![info exists SOC] } { + # Set the SoC of interest + set SOC am625 + } + + source [find target/ti_k3.cfg] + + ftdi tdo_sample_edge falling + + # Speeds for FT2232H are in multiples of 2, and 32MHz is tops + # max speed we seem to achieve is ~20MHz.. so we pick 16MHz + adapter speed 16000 + +Below is an example of what the output of this command will print. + +.. code-block:: console + + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + Info : XDS110: connected + Info : XDS110: vid/pid = 0451/bef3 + Info : XDS110: firmware version = 3.0.0.20 + Info : XDS110: hardware version = 0x002f + Info : XDS110: connected to target via JTAG + Info : XDS110: TCK set to 2500 kHz + Info : clock speed 2500 kHz + Info : JTAG tap: am625.cpu tap/device found: 0x0bb7e02f (mfg: 0x017 (Texas Instruments), part: 0xbb7e, ver: 0x0) + Info : starting gdb server for am625.cpu.sysctrl on 3333 + Info : Listening on port 3333 for gdb connections + Info : starting gdb server for am625.cpu.a53.0 on 3334 + Info : Listening on port 3334 for gdb connections + Info : starting gdb server for am625.cpu.a53.1 on 3335 + Info : Listening on port 3335 for gdb connections + Info : starting gdb server for am625.cpu.a53.2 on 3336 + Info : Listening on port 3336 for gdb connections + Info : starting gdb server for am625.cpu.a53.3 on 3337 + Info : Listening on port 3337 for gdb connections + Info : starting gdb server for am625.cpu.main0_r5.0 on 3338 + Info : Listening on port 3338 for gdb connections + Info : starting gdb server for am625.cpu.gp_mcu on 3339 + Info : Listening on port 3339 for gdb connections + +.. note:: + Notice the default configuration is non-SMP configuration allowing + for each of the core to be attached and debugged simultaneously. + armv8 SPL/U-boot starts up on cpu0 of a53/a72. + +To debug using this server, use gdb directly or your preferred +gdb-based IDE. To start up gdb in the terminal, run the following +command. + +.. code-block:: bash + + gdb-multiarch + +To connect to your desired core, run the following command within gdb +and load the symbols from the corresponding elf file. + +.. code-block:: bash + + target extended-remote localhost:{port for desired core} + symbol-file {path to elf file} + +In the above example of AM625, + +.. code-block:: bash + + target extended-remote localhost:3338 <- R5F (Wakeup Domain) + target extended-remote localhost:3334 <- A53 (Main Domain) + +The core can now be debugged directly within gdb using gdb commands or +if using IDE, as appropriate to the IDE. + +Stepping through the code +""""""""""""""""""""""""" + +Use the gdb command ``lay next`` after loading the symbols to see the +code and breakpoints. To exit the debug loop added above, add any +breakpoints needed and run the following gdb commands. + +.. code-block:: bash + + set x = 0 + continue + +The platform has now been successfully setup to debug with OpenOCD +using gdb commands or a gdb-based IDE. See `OpenOCD documentation for +gdb <https://openocd.org/doc/html/GDB-and-OpenOCD.html>`_ for further +information. + +.. warning:: + + On the K3 family of devices, a watchdog timer within the DMSC is + enabled by default by the ROM bootcode with a timeout of 3 minutes. + The watchdog timer is serviced by System Firmware (SYSFW) or TI + Foundational Security (TIFS) during normal operation. If debugging + the SPL before the SYSFW is loaded, the watchdog timer will not get + serviced automatically and the debug session will reset after 3 + minutes. It is recommended to start debugging SPL code only after + the startup of SYSFW to avoid running into the watchdog timer reset. + +Misc notes with openOCD +^^^^^^^^^^^^^^^^^^^^^^^ + +At the time of this writing openOCD does not support tracing for K3 +platforms. Tracing function could be very useful if the bug in code +occurs deep within nested function and can optionally save developers +major trouble of stepping through large quantity of code. -- 2.37.2

2 1

[PATCH] spl: spl_legacy: Fix spl_end address for non ARM target
by Shiji Yang 01 Aug '23

01 Aug '23

Only ARM target defines _image_binary_end symbol as char*, All other targets define it as an ulong type in include/asm-generic/sections.h. This patch fixes the boot failure on MIPS target. Error log: SPL: Image overlaps SPL Fixes: 1b8a1be1a1f1 ("spl: spl_legacy: Fix spl_end address") Signed-off-by: Shiji Yang <yangshiji66(a)outlook.com> --- common/spl/spl_legacy.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 095443c63d..0fef890384 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -18,9 +18,13 @@ static void spl_parse_legacy_validate(uintptr_t start, uintptr_t size) { + uintptr_t end = start + size; uintptr_t spl_start = (uintptr_t)_start; +#ifdef CONFIG_ARM uintptr_t spl_end = (uintptr_t)_image_binary_end; - uintptr_t end = start + size; +#else + uintptr_t spl_end = (uintptr_t)&_image_binary_end; +#endif /* CONFIG_ARM */ if ((start >= spl_start && start < spl_end) || (end > spl_start && end <= spl_end) || -- 2.39.2

3 5

Pull request: u-boot-rockchip-20230731
by Kever Yang 01 Aug '23

01 Aug '23

Hi Tom, Please pull the updates for rockchip platform: - Update dwc3 generic driver and update support for rk3568/rk3328; - Add boards: rk3566: Pine64 Quartz64-A/B, SOQuartz on Model A/Blade/CM4-IO rk3568: Radxa E25 Carrier Board rk3588: Radxa ROCK5A - Fixes and updates for chromebook veryon/jerry/speedy; - SPI support fixes for rk3399/rk3568/rk3588; - rk3588 usbdp phy support; - dts and config updates for different boards; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/17148 Thanks, - Kever The following changes since commit a36d59ba99a19c777d896d4c70e75975654e2831: Merge tag 'efi-2023-10-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2023-07-28 12:48:00 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20230731 for you to fetch changes up to 1f54f71b182e3515f72870a75ce2ba769b00b1f3: board: rockchip: Add Radxa E25 Carrier Board (2023-07-31 20:34:32 +0800) ---------------------------------------------------------------- Alper Nebi Yasak (7): rockchip: veyron: Enable RESET driver rockchip: veyron: Enable building SPI ROM images rockchip: veyron: Unify u-boot.dtsi bootph-all fragments rockchip: veyron: Add serial, logging, silent console support rockchip: veyron: Use TrueType fonts rockchip: chromebook_jerry: Re-enable MAX98090 codec driver rockchip: chromebook_speedy: Enable sound Eugen Hristev (2): ARM: dts: rockchip: rk3588: Move bootph-all props to common file board: rockchip: add Radxa ROCK5A Rk3588 board Jagan Teki (7): arm64: dts: rockchip: Drop unused rk3328-xhci node configs: Drop unused XHCI_DWC3 for RK3328 boards usb: dwc3-generic: Restrict single ctrl node for RK3328 configs: Enable DWC3 USB 3.0 on RK3328 boards phy: rockchip-inno-usb2: Add USB2 PHY for RK3328 clk: rockchip: rk3328: Handle usb480m phy clock configs: rockchip: Enable USB2PHY for RK3328 boards Jonas Karlman (24): Revert "arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb" usb: dwc3-generic: Return early when there is no child node usb: dwc3-generic: Relax unsupported dr_mode check usb: dwc3-generic: Add rk3568 support rockchip: rk3568: Use dwc3-generic driver board: rockchip: Add Pine64 Quartz64-A Board board: rockchip: Add Pine64 Quartz64-B Board board: rockchip: Add Pine64 SOQuartz on Model A board: rockchip: Add Pine64 SOQuartz on Blade board: rockchip: Add Pine64 SOQuartz on CM4-IO rockchip: rk356x: Sync dtsi from linux v6.4 rockchip: rk3566-radxa-cm3-io: Sync dts from linux v6.4 rockchip: rk356x-u-boot: Add bootph-all to common pinctrl nodes rockchip: rk356x-u-boot: Use relaxed u-boot,spl-boot-order rockchip: rk3399-rockpro64: Fix SPL max size and SPI flash payload offset rockchip: rk3399-pinebook-pro: Fix SPL max size and SPI flash payload offset rockchip: rk3399-pinephone-pro: Fix SPL max size and SPI flash payload offset rockchip: rk3399-roc-pc: Fix SPL max size and SPI flash payload offset doc: rockchip: Update SPI flashing instruction rockchip: rk3568-rock-3a: Fix SPI Flash alias rockchip: rk3588-rock-5b: Fix SPI Flash alias rockchip: rk3568-rock-3a: Fix pcie2x1 and pcie3x2 pinctrl override power: regulator: rk8xx: Add 500us delay after LDO regulator is enabled board: rockchip: Add Radxa E25 Carrier Board Pegorer Massimo (5): rockchip: rk3308: fix board_debug_uart_init rockchip: rk3308: no DEBUG_UART_BOARD_INIT for ROCK Pi S rockchip: rk3308: add support for sdmmc boot rockchip: rk3308: fix same-as-spl boot order configs: rockchip: drop useless DEBUG_UART_SKIP_INIT arch/arm/dts/Makefile | 10 +- arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 30 +- arch/arm/dts/rk3288-veyron-u-boot.dtsi | 4 + arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 2 +- arch/arm/dts/rk3308-u-boot.dtsi | 5 + arch/arm/dts/rk3308.dtsi | 6 +- arch/arm/dts/rk3328-evb-u-boot.dtsi | 5 - arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 14 - arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 5 - arch/arm/dts/rk3328-rock64-u-boot.dtsi | 15 - arch/arm/dts/rk3328-u-boot.dtsi | 11 - arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4 - arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 4 - arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 4 - arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 - arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 51 ++ arch/arm/dts/rk3566-quartz64-a.dts | 839 +++++++++++++++++++++++ arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 43 ++ arch/arm/dts/rk3566-quartz64-b.dts | 739 ++++++++++++++++++++ arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 60 -- arch/arm/dts/rk3566-radxa-cm3-io.dts | 8 + arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-blade.dts | 194 ++++++ arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-cm4.dts | 192 ++++++ arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-model-a.dts | 232 +++++++ arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 26 + arch/arm/dts/rk3566-soquartz.dtsi | 688 +++++++++++++++++++ arch/arm/dts/rk3568-pinctrl.dtsi | 94 +++ arch/arm/dts/rk3568-radxa-cm3i.dtsi | 415 +++++++++++ arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 32 + arch/arm/dts/rk3568-radxa-e25.dts | 236 +++++++ arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 80 +-- arch/arm/dts/rk356x-u-boot.dtsi | 67 +- arch/arm/dts/rk356x.dtsi | 14 +- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 55 -- arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 34 + arch/arm/dts/rk3588s-rock-5a.dts | 73 ++ arch/arm/dts/rk3588s-u-boot.dtsi | 65 ++ arch/arm/mach-rockchip/Kconfig | 1 - arch/arm/mach-rockchip/rk3288/Kconfig | 6 + arch/arm/mach-rockchip/rk3308/rk3308.c | 2 +- arch/arm/mach-rockchip/rk3568/Kconfig | 6 + arch/arm/mach-rockchip/rk3588/Kconfig | 29 +- board/pine64/quartz64_rk3566/Kconfig | 15 + board/pine64/quartz64_rk3566/MAINTAINERS | 23 + board/pine64/quartz64_rk3566/Makefile | 3 + board/pine64/quartz64_rk3566/quartz64-rk3566.c | 1 + board/radxa/rock5a-rk3588s/Kconfig | 15 + board/radxa/rock5a-rk3588s/MAINTAINERS | 6 + board/radxa/rock5a-rk3588s/Makefile | 6 + board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 ++ board/rockchip/evb_rk3568/MAINTAINERS | 8 + configs/chromebit_mickey_defconfig | 6 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_minnie_defconfig | 6 +- configs/chromebook_speedy_defconfig | 7 + configs/evb-px30_defconfig | 1 - configs/evb-px5_defconfig | 1 - configs/evb-rk3308_defconfig | 1 - configs/evb-rk3328_defconfig | 5 +- configs/firefly-px30_defconfig | 1 - configs/geekbox_defconfig | 1 - configs/lion-rk3368_defconfig | 1 - configs/nanopi-r2c-rk3328_defconfig | 4 +- configs/nanopi-r2s-rk3328_defconfig | 4 +- configs/nanopi-r5c-rk3568_defconfig | 3 +- configs/nanopi-r5s-rk3568_defconfig | 3 +- configs/odroid-go2_defconfig | 1 - configs/pinebook-pro-rk3399_defconfig | 4 +- configs/pinephone-pro-rk3399_defconfig | 4 +- configs/px30-core-ctouch2-of10-px30_defconfig | 1 - configs/px30-core-ctouch2-px30_defconfig | 1 - configs/px30-core-edimm2.2-px30_defconfig | 1 - configs/quartz64-a-rk3566_defconfig | 110 +++ configs/quartz64-b-rk3566_defconfig | 106 +++ configs/radxa-cm3-io-rk3566_defconfig | 2 +- configs/radxa-e25-rk3568_defconfig | 94 +++ configs/ringneck-px30_defconfig | 1 - configs/roc-cc-rk3308_defconfig | 1 - configs/roc-cc-rk3328_defconfig | 4 +- configs/roc-pc-mezzanine-rk3399_defconfig | 4 +- configs/roc-pc-rk3399_defconfig | 4 +- configs/rock-3a-rk3568_defconfig | 5 +- configs/rock-pi-e-rk3328_defconfig | 5 +- configs/rock-pi-s-rk3308_defconfig | 2 +- configs/rock5a-rk3588s_defconfig | 72 ++ configs/rock5b-rk3588_defconfig | 3 + configs/rock64-rk3328_defconfig | 4 +- configs/rockpro64-rk3399_defconfig | 5 +- configs/sheep-rk3368_defconfig | 1 - configs/soquartz-blade-rk3566_defconfig | 90 +++ configs/soquartz-cm4-rk3566_defconfig | 90 +++ configs/soquartz-model-a-rk3566_defconfig | 90 +++ doc/board/rockchip/rockchip.rst | 33 +- drivers/clk/rockchip/clk_rk3328.c | 2 + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 34 + drivers/power/regulator/rk8xx.c | 4 + drivers/usb/dwc3/dwc3-generic.c | 49 +- include/configs/quartz64_rk3566.h | 10 + include/configs/rock5a-rk3588s.h | 15 + 102 files changed, 5055 insertions(+), 371 deletions(-) create mode 100644 arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-a.dts create mode 100644 arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-b.dts create mode 100644 arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-blade.dts create mode 100644 arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-cm4.dts create mode 100644 arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-model-a.dts create mode 100644 arch/arm/dts/rk3566-soquartz-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-cm3i.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25.dts create mode 100644 arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588s-rock-5a.dts create mode 100644 board/pine64/quartz64_rk3566/Kconfig create mode 100644 board/pine64/quartz64_rk3566/MAINTAINERS create mode 100644 board/pine64/quartz64_rk3566/Makefile create mode 100644 board/pine64/quartz64_rk3566/quartz64-rk3566.c create mode 100644 board/radxa/rock5a-rk3588s/Kconfig create mode 100644 board/radxa/rock5a-rk3588s/MAINTAINERS create mode 100644 board/radxa/rock5a-rk3588s/Makefile create mode 100644 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c create mode 100644 configs/quartz64-a-rk3566_defconfig create mode 100644 configs/quartz64-b-rk3566_defconfig create mode 100644 configs/radxa-e25-rk3568_defconfig create mode 100644 configs/rock5a-rk3588s_defconfig create mode 100644 configs/soquartz-blade-rk3566_defconfig create mode 100644 configs/soquartz-cm4-rk3566_defconfig create mode 100644 configs/soquartz-model-a-rk3566_defconfig create mode 100644 include/configs/quartz64_rk3566.h create mode 100644 include/configs/rock5a-rk3588s.h

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[PATCH] x86: Add a little more info to cbsysinfo
by Simon Glass 01 Aug '23

01 Aug '23

Show the number of records in the table and the total table size in bytes. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/x86/include/asm/cb_sysinfo.h | 4 ++++ arch/x86/lib/coreboot/cb_sysinfo.c | 4 ++++ cmd/x86/cbsysinfo.c | 5 +++-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h index 2c78b22d0d2..12fa395ffd2 100644 --- a/arch/x86/include/asm/cb_sysinfo.h +++ b/arch/x86/include/asm/cb_sysinfo.h @@ -138,6 +138,8 @@ * @rsdp: Pointer to ACPI RSDP table * @unimpl_count: Number of entries in unimpl_map[] * @unimpl: List of unimplemented IDs (bottom 8 bits only) + * @table_size: Number of bytes taken up by the sysinfo table + * @rec_count: Number of records in the sysinfo table */ struct sysinfo_t { unsigned int cpu_khz; @@ -219,6 +221,8 @@ struct sysinfo_t { void *rsdp; u32 unimpl_count; u8 unimpl[SYSINFO_MAX_UNIMPL]; + uint table_size; + uint rec_count; }; extern struct sysinfo_t lib_sysinfo; diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c index 42cc3a128d9..dfbc80c430e 100644 --- a/arch/x86/lib/coreboot/cb_sysinfo.c +++ b/arch/x86/lib/coreboot/cb_sysinfo.c @@ -447,6 +447,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) ptr += rec->size; } + info->table_size += (void *)ptr - (void *)header; + info->rec_count += header->table_entries; return 1; } @@ -462,6 +464,8 @@ int get_coreboot_info(struct sysinfo_t *info) addr = locate_coreboot_table(); if (addr < 0) return addr; + info->table_size = 0; + info->rec_count = 0; ret = cb_parse_header((void *)addr, 0x1000, info); if (!ret) return -ENOENT; diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c index 2b8d3b0a435..84822a3e321 100644 --- a/cmd/x86/cbsysinfo.c +++ b/cmd/x86/cbsysinfo.c @@ -190,8 +190,9 @@ static void show_table(struct sysinfo_t *info, bool verbose) struct cb_serial *ser = info->serial; int i; - printf("Coreboot table at %lx, decoded to %p", - gd->arch.coreboot_table, info); + printf("Coreboot table at %lx, size %x, records %x (dec %d), decoded to %p", + gd->arch.coreboot_table, info->table_size, info->rec_count, + info->rec_count, info); if (info->header) printf(", forwarded to %p\n", info->header); printf("\n"); -- 2.41.0.487.g6d72f3e995-goog

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[PATCH v3] x86: Change tesing logic of mtrr commit
by Simon Glass 01 Aug '23

01 Aug '23

From: Bin Meng <bmeng.cn(a)gmail.com> On Coral U-Boot SPL programs some MTRRs and FSPv2 in U-Boot proper needs to program MTRRs too. With current testing logic of mtrr commit in init_cache_f_r(), the mtrr commit is skipped which won't work as the queued mtrr requests include setup for DRAM regions. Change the logic to allow such configuration. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Tweak to put back CONFIG_FSP_VERSION2 at top: Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Allow committing MTRRs with FSP_VERSION2 Changes in v2: - new patch: "x86: Change tesing logic of mtrr commit" arch/x86/lib/init_helpers.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index f33194045f9e..60a2707dcf1b 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -21,8 +21,7 @@ int init_cache_f_r(void) /* * Supported configurations: * - * booting from slimbootloader - in that case the MTRRs are already set - * up + * booting from slimbootloader - MTRRs are already set up * booting with FSPv1 - MTRRs are already set up * booting with FSPv2 - MTRRs must be set here * booting from coreboot - in this case there is no SPL, so we set up @@ -30,8 +29,7 @@ int init_cache_f_r(void) * Note: if there is an SPL, then it has already set up MTRRs so we * don't need to do that here */ - do_mtrr &= !IS_ENABLED(CONFIG_SPL) && - !IS_ENABLED(CONFIG_FSP_VERSION1) && + do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) && !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER); if (do_mtrr) { -- 2.41.0.487.g6d72f3e995-goog

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[PATCH v2 1/6] x86: Change tesing logic of mtrr commit
by Bin Meng 01 Aug '23

01 Aug '23

From: Bin Meng <bmeng.cn(a)gmail.com> On Coral U-Boot SPL programs some MTRRs and FSPv2 in U-Boot proper needs to program MTRRs too. With current testing logic of mtrr commit in init_cache_f_r(), the mtrr commit is skipped which won't work as the queued mtrr requests include setup for DRAM regions. Change the logic to allow such configuration. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - new patch: "x86: Change tesing logic of mtrr commit" arch/x86/lib/init_helpers.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index f33194045f..a2535e4468 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -14,15 +14,13 @@ DECLARE_GLOBAL_DATA_PTR; int init_cache_f_r(void) { - bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) || - IS_ENABLED(CONFIG_FSP_VERSION2); + bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT); int ret; /* * Supported configurations: * - * booting from slimbootloader - in that case the MTRRs are already set - * up + * booting from slimbootloader - MTRRs are already set up * booting with FSPv1 - MTRRs are already set up * booting with FSPv2 - MTRRs must be set here * booting from coreboot - in this case there is no SPL, so we set up @@ -30,7 +28,7 @@ int init_cache_f_r(void) * Note: if there is an SPL, then it has already set up MTRRs so we * don't need to do that here */ - do_mtrr &= !IS_ENABLED(CONFIG_SPL) && + do_mtrr &= (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_FSP_VERSION2)) && !IS_ENABLED(CONFIG_FSP_VERSION1) && !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER); -- 2.25.1

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