August 2023 - U-Boot

[PATCH 0/6] rockchip: rk3568: Fix use of PCIe bifurcation
by Jonas Karlman 02 Aug '23

02 Aug '23

This series add support for use of PCIe bifurcation on RK3568, and as a bonus support for the RK3588 PHY is also included. With PCIe bifurcation supported it is possible to enable PCIe on more RK3568 boards, e.g. on NanoPi R5C and NanoPi R5S. This series only include fixing the mini PCIe slot on Radxa E25. Most parts of this series was imported almost 1:1 from mainline linux. Patch 1 fixes configuration of number of lanes in pcie_dw_rockchip. Patch 2-3 refactor the snps-pcie3 phy driver. Patch 4 add bifurcation support for RK3568. Patch 5 add support for RK3588. Patch 6 enables the mini PCIe slot on Radxa E25. The RK3588 PHY part was tested on a ROCK 5B together with device tree files picked from Sebastian Reichel's rk3588 branch at [1]. Patches in this series is also aviliable at [2]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-misc.git/tree/?h=… [2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-pcie-bifurcation-v1 Jonas Karlman (6): pci: pcie_dw_rockchip: Configure number of lanes and link width speed phy: rockchip: snps-pcie3: Refactor to use clk_bulk API phy: rockchip: snps-pcie3: Refactor to use a phy_init ops phy: rockchip: snps-pcie3: Add bifurcation support for RK3568 phy: rockchip: snps-pcie3: Add support for RK3588 rockchip: rk3568-radxa-e25: Enable pcie3x1 node arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 11 +- configs/radxa-e25-rk3568_defconfig | 1 - drivers/pci/pcie_dw_rockchip.c | 58 ++++- .../phy/rockchip/phy-rockchip-snps-pcie3.c | 230 ++++++++++++++---- 4 files changed, 235 insertions(+), 65 deletions(-) -- 2.41.0

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[PATCH 0/6] rockchip: rk3568: Fix use of PCIe bifurcation
by Jonas Karlman 02 Aug '23

02 Aug '23

This series add support for use of PCIe bifurcation on RK3568, and as a bonus support for the RK3588 PHY is also included. With PCIe bifurcation supported it is possible to enable PCIe on more RK3568 boards, e.g. on NanoPi R5C and NanoPi R5S. This series only include fixing the mini PCIe slot on Radxa E25. Most parts of this series was imported almost 1:1 from mainline linux. Patch 1 fixes configuration of number of lanes in pcie_dw_rockchip. Patch 2-3 refactor the snps-pcie3 phy driver. Patch 4 add bifurcation support for RK3568. Patch 5 add support for RK3588. Patch 6 enables the mini PCIe slot on Radxa E25. The RK3588 PHY part was tested on a ROCK 5B together with device tree files picked from Sebastian Reichel's rk3588 branch at [1]. Patches in this series is also aviliable at [2]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-misc.git/tree/?h=… [2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-pcie-bifurcation-v1 Jonas Karlman (6): pci: pcie_dw_rockchip: Configure number of lanes and link width speed phy: rockchip: snps-pcie3: Refactor to use clk_bulk API phy: rockchip: snps-pcie3: Refactor to use a phy_init ops phy: rockchip: snps-pcie3: Add bifurcation support for RK3568 phy: rockchip: snps-pcie3: Add support for RK3588 rockchip: rk3568-radxa-e25: Enable pcie3x1 node arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 11 +- configs/radxa-e25-rk3568_defconfig | 1 - drivers/pci/pcie_dw_rockchip.c | 58 ++++- .../phy/rockchip/phy-rockchip-snps-pcie3.c | 230 ++++++++++++++---- 4 files changed, 235 insertions(+), 65 deletions(-) -- 2.41.0

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[PATCH 0/2] Update remove method for DSS driver
by Nikhil M Jain 01 Aug '23

01 Aug '23

This patch series aims at updating the remove method for DSS video driver. Nikhil M Jain (2): drivers: video: tidss: tidss_drv: Change remove method drivers: video: tidss: tidss_drv: Use kconfig VIDEO_REMOVE to remove video drivers/video/tidss/tidss_drv.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) -- 2.34.1

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Please pull u-boot-x86
by Bin Meng 01 Aug '23

01 Aug '23

Hi Tom, CI: https://source.denx.de/u-boot/custodians/u-boot-x86/-/pipelines/17161 The following changes since commit 4e619e8d4fd68095bc665a78f2651d8e478a4534: Merge tag 'u-boot-rockchip-20230731' of https://source.denx.de/u-boot/custodians/u-boot-rockchip (2023-07-31 11:33:51 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-x86.git tags/x86-pull-20230801 for you to fetch changes up to db971a7587d04b3f1cf2e6d452f9e37f50c5b3ed: x86: Add a little more info to cbsysinfo (2023-08-01 10:08:49 +0800) ---------------------------------------------------------------- - MTRR fixes for x86 boards - Add a little more info to 'cbsysinfo' command ---------------------------------------------------------------- Bin Meng (5): x86: Change testing logic of mtrr commit x86: fsp: Use mtrr_set_next_var() for graphics memory video: broadwell: Use mtrr_set_next_var() for graphics memory video: ivybridge: Use mtrr_set_next_var() for graphics memory video: vesa: Use mtrr_set_next_var() for graphics memory Simon Glass (2): x86: Return mtrr_add_request() to its old purpose x86: Add a little more info to cbsysinfo arch/x86/cpu/mtrr.c | 6 +++++- arch/x86/include/asm/cb_sysinfo.h | 4 ++++ arch/x86/lib/coreboot/cb_sysinfo.c | 4 ++++ arch/x86/lib/fsp/fsp_graphics.c | 3 +-- arch/x86/lib/init_helpers.c | 6 ++---- cmd/x86/cbsysinfo.c | 5 +++-- drivers/video/broadwell_igd.c | 10 +++------- drivers/video/ivybridge_igd.c | 3 +-- drivers/video/vesa.c | 3 +-- 9 files changed, 24 insertions(+), 20 deletions(-) Regards, Bin

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Please pull u-boot-video
by Anatolij Gustschin 01 Aug '23

01 Aug '23

Hi Tom, please pull new video patches for v2023.10. CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/17167 Thanks, Anatolij The following changes since commit 4e619e8d4fd68095bc665a78f2651d8e478a4534: Merge tag 'u-boot-rockchip-20230731' of https://source.denx.de/u-boot/custodians/u-boot-rockchip (2023-07-31 11:33:51 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-video.git tags/video-20230801 for you to fetch changes up to b8d3a6c7d12fc6101f99cde0acedb4a799fdb5f3: drivers: video: tidss: tidss_drv: Use kconfig VIDEO_REMOVE to remove video (2023-08-01 13:41:02 +0200) ---------------------------------------------------------------- - dm video cosmetic style fix - bochs: remove the x86 limitation - correct kconfig text for PCI default FB size - kconfig: drop the superfluous PCI dependency - set up default FB size for Bochs ---------------------------------------------------------------- Bin Meng (9): dm: video: Cosmetic style fix video: bochs: Drop inclusion of <asm/mtrr.h> video: bochs: Drop the useless argument of bochs_vga_write() video: bochs: Avoid using IO instructions to access VGA IO port video: bochs: Remove the x86 dependency video: kconfig: Fix wrong text for the PCI default FB size video: kconfig: Drop the superfluous dependency video: kconfig: Set default FB size for Bochs video: bochs: Set the frame buffer size per configuration Nikhil M Jain (2): drivers: video: tidss: tidss_drv: Change remove method drivers: video: tidss: tidss_drv: Use kconfig VIDEO_REMOVE to remove video drivers/video/Kconfig | 15 ++++++++------- drivers/video/bochs.c | 12 ++++++------ drivers/video/bochs.h | 7 ++++--- drivers/video/tidss/tidss_drv.c | 18 +++++++----------- drivers/video/video-uclass.c | 6 ++++-- 5 files changed, 29 insertions(+), 29 deletions(-)

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Please pull u-boot-marvell/master
by Stefan Roese 01 Aug '23

01 Aug '23

Hi Tom, please pull the following, partly Marvell MVEBU related patches into master: ---------------------------------------------------------------- - i2c-gpio: Correctly handle new {sda, scl}-gpios bindings (Chris) - mvebu: x240: Use i2c-gpio instead of built in controller (Chris) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=307&view=results Thanks, Stefan The following changes since commit a36d59ba99a19c777d896d4c70e75975654e2831: Merge tag 'efi-2023-10-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2023-07-28 12:48:00 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to 5c1c6b7306f2b4c0fd50c7cb5d757e245b93606e: arm: mvebu: x240: Use i2c-gpio instead of built in controller (2023-07-31 13:50:57 +0200) ---------------------------------------------------------------- Chris Packham (2): i2c: i2c-gpio: Correctly handle new {sda, scl}-gpios bindings arm: mvebu: x240: Use i2c-gpio instead of built in controller arch/arm/dts/ac5-98dx35xx-atl-x240.dts | 30 +++++++++++++++++++++++------- configs/x240_defconfig | 1 + drivers/i2c/i2c-gpio.c | 2 +- 3 files changed, 25 insertions(+), 8 deletions(-)

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[PATCH 00/18] video: bochs: Remove the x86 limitation
by Bin Meng 01 Aug '23

01 Aug '23

The Bochs VGA card emulated by QEMU does not enforce any architecture. It was first introduced on x86 and indeed the x86 IO instruction is used to access the legacy VGA IO ports, but that does not mean it has to be done like this. The first half of this series enhances the bochs video driver to remove the x86 limitation. The second half of this series enables bochs video as the output console for QEMU RISC-V, to prove that the bochs video driver can indeed work on a non-x86 architecture. To make it actually useful, enable a usb keyboard as well, otherwise we can't just type anything :-) This series is available at u-boot-x86/bochs for testing. Bin Meng (17): dm: video: Cosmetic style fix video: bochs: Drop inclusion of <asm/mtrr.h> video: bochs: Drop the useless argument of bochs_vga_write() video: bochs: Avoid using IO instructions to access VGA IO port video: bochs: Remove the x86 dependency video: kconfig: Fix wrong text for the PCI default FB size video: kconfig: Drop the superfluous dependency video: kconfig: Set default FB size for Bochs video: bochs: Set the frame buffer size per configuration riscv: qemu: Enable Bochs video support console: kconfig: Drop the redundant VIDEO dependency console: Make stdio_print_current_devices() static console: Refactor stdio_print_current_devices() a little bit console: Print out complete stdio device list riscv: qemu: Enable PRE_CONSOLE_BUFFER riscv: qemu: Remove out-of-date "riscv,kernel-start" handling riscv: qemu: Enable usb keyboard as an input device Heinrich Schuchardt (1): riscv: define a cache line size for the generic CPU arch/riscv/cpu/generic/Kconfig | 1 + board/emulation/qemu-riscv/Kconfig | 13 ++++++++ board/emulation/qemu-riscv/qemu-riscv.c | 27 +++------------ common/Kconfig | 2 +- common/console.c | 44 ++++++++++++++++--------- doc/board/emulation/qemu-riscv.rst | 10 ++++++ drivers/video/Kconfig | 15 +++++---- drivers/video/bochs.c | 12 +++---- drivers/video/bochs.h | 7 ++-- drivers/video/video-uclass.c | 6 ++-- include/configs/qemu-riscv.h | 15 +++------ include/stdio_dev.h | 2 -- 12 files changed, 84 insertions(+), 70 deletions(-) -- 2.34.1

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[PATCH v4 00/12] Integrate EFI capsule tasks into u-boot's build flow
by Sughosh Ganu 01 Aug '23

01 Aug '23

This patchset aims to bring two capsule related tasks under the u-boot build flow. One is the embedding of the public key into the platform's dtb. The public key is in the form of an EFI Signature List(ESL) file and is used for capsule authentication. This is being achieved by adding the signature node containing the capsule public key in the architecture's u-boot.dtsi file. Currently, the u-boot.dtsi file has been added for the sandbox and arm architectures. The path to the ESL file is being provided through a Kconfig symbol(CONFIG_EFI_CAPSULE_ESL_FILE). Changes have also been made to the test flow so that the keys used for signing the capsule, and the ESL file, are generated prior to invoking the u-boot's build, which enables embedding the ESL file into the dtb as part of the u-boot build. The other task is related to generation of capsules. Support is being added to generate capsules by specifying the capsule parameters in a config file. Calling the mkeficapsule tool then results in generation of the corresponding capsule files. The capsules can be generated as part of u-boot build, and this is being achieved through binman, by adding a capsule entry type. The capsules can be generated either by specifying the capsule parameters in a config file, or through specifying them as properties under the capsule entry node. If using the config file, the path to the config file is to be specified through a Kconfig symbol(CONFIG_EFI_CAPSULE_CFG_FILE). Changes have also been made to the efi capsule update feature testing setup on the sandbox variants. Currently, the capsule files and the public key ESL file are generated after u-boot has been built. This logic has been changed so that the capsule input files along with the keys needed for capsule signing and authentication are generated prior to initiation of the u-boot build. The placement of all the files needed for generation of capsules, along with the generated capsule files is under the /tmp/capsules/ directory. Currently, the capsule update feature is tested on the sandbox and sandbox_flattree variants in CI. The capsule generation through config file is enabled for the sandbox variant, with the sandbox_flattree variant generating capsules through the command-line parameters. The document has been updated to reflect the above changes. Changes since V3: * New patch to support passing multiple commands to the build_from_git * Put the two ifdef statements together in arm architecture's u-boot.dtsi file. * Remove the extra blank line in the Kconfig. function to build the tool. * Add support for firmware versioning, needed after rebasing on current master. * Add test cases for covering the various capsule generation scenarios. * Add function comments in the mkeficapsule bintool. * Fix the fetch method of the mkeficapsule bintool to enable building the tool. * Add more details about the capsule parameters in the documentation as well as the code. * Fix order of module imports, and addition of blank lines in the capsule.py file. * Use SetContents in the ObtainContents method. * Move the paragraph on version support under a separate subsection. * Move the description on generating capsules through config file under the section to describe capsule generation. * Add a subsection highlighting generation of capsules through binman. * Remove whitespace in the command to generate capsule keys. * Use fstrings for format specifiers. * Rebase on top of current master to work with test configuration for version support in capsule updates. * Use fstrings for format specifiers. * Add entries for generating capsules with version parameter. * Use blob nodes instead of incbin for including the binaries in FIT image. * Enable generation of capsules with versioning support. Sughosh Ganu (12): binman: bintool: Build a tool from a list of commands nuvoton: npcm845-evb: Add a newline at the end of file capsule: authenticate: Add capsule public key in platform's dtb doc: capsule: Document the new mechanism to embed ESL file into dtb tools: mkeficapsule: Add support for parsing capsule params from config file binman: capsule: Add support for generating capsules doc: Add documentation to highlight capsule generation related updates CI: capsule: Setup the files needed for capsule update testing test: py: Setup capsule files for testing test: capsule: Remove public key embed logic from capsule update test sandbox: capsule: Add a config file for generating capsules sandbox: capsule: Generate capsule related files through binman .azure-pipelines.yml | 26 ++ .gitlab-ci.yml | 24 ++ arch/arm/dts/nuvoton-npcm845-evb.dts | 2 +- arch/arm/dts/u-boot.dtsi | 17 + arch/sandbox/dts/u-boot.dtsi | 282 ++++++++++++++ configs/sandbox_defconfig | 3 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + doc/develop/uefi/uefi.rst | 106 +++++- lib/efi_loader/Kconfig | 10 + lib/efi_loader/Makefile | 7 + test/py/conftest.py | 89 +++++ test/py/tests/test_efi_capsule/conftest.py | 164 +------- .../test_efi_capsule/sandbox_capsule_cfg.txt | 162 ++++++++ test/py/tests/test_efi_capsule/signature.dts | 10 - .../tests/test_efi_capsule/uboot_bin_env.its | 36 -- tools/Kconfig | 16 + tools/Makefile | 1 + tools/binman/bintool.py | 19 +- tools/binman/btool/_testing.py | 3 +- tools/binman/btool/fiptool.py | 4 +- tools/binman/btool/futility.py | 4 +- tools/binman/btool/mkeficapsule.py | 158 ++++++++ tools/binman/entries.rst | 37 ++ tools/binman/etype/capsule.py | 132 +++++++ tools/binman/ftest.py | 127 +++++++ tools/binman/test/282_capsule.dts | 18 + tools/binman/test/283_capsule_signed.dts | 20 + tools/binman/test/284_capsule_conf.dts | 14 + tools/binman/test/285_capsule_missing_key.dts | 19 + .../binman/test/286_capsule_missing_index.dts | 17 + .../binman/test/287_capsule_missing_guid.dts | 17 + .../test/288_capsule_missing_payload.dts | 17 + tools/binman/test/289_capsule_missing.dts | 17 + tools/binman/test/290_capsule_version.dts | 19 + tools/binman/test/capsule_cfg.txt | 6 + tools/eficapsule.h | 115 ++++++ tools/mkeficapsule.c | 87 +++-- tools/mkeficapsule_parse.c | 352 ++++++++++++++++++ 39 files changed, 1900 insertions(+), 259 deletions(-) create mode 100644 arch/arm/dts/u-boot.dtsi create mode 100644 arch/sandbox/dts/u-boot.dtsi create mode 100644 test/py/tests/test_efi_capsule/sandbox_capsule_cfg.txt delete mode 100644 test/py/tests/test_efi_capsule/signature.dts delete mode 100644 test/py/tests/test_efi_capsule/uboot_bin_env.its create mode 100644 tools/binman/btool/mkeficapsule.py create mode 100644 tools/binman/etype/capsule.py create mode 100644 tools/binman/test/282_capsule.dts create mode 100644 tools/binman/test/283_capsule_signed.dts create mode 100644 tools/binman/test/284_capsule_conf.dts create mode 100644 tools/binman/test/285_capsule_missing_key.dts create mode 100644 tools/binman/test/286_capsule_missing_index.dts create mode 100644 tools/binman/test/287_capsule_missing_guid.dts create mode 100644 tools/binman/test/288_capsule_missing_payload.dts create mode 100644 tools/binman/test/289_capsule_missing.dts create mode 100644 tools/binman/test/290_capsule_version.dts create mode 100644 tools/binman/test/capsule_cfg.txt create mode 100644 tools/mkeficapsule_parse.c -- 2.34.1

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[PATCH v3] board: rockchip: Add Radxa E25 Carrier Board
by Jonas Karlman 01 Aug '23

01 Aug '23

Radxa E25 is a network application carrier board for the Radxa CM3I SoM with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key, USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header. Features tested on a Radxa E25 v1.4: - SD-card boot - eMMC boot - USB host - PCIe/Ethernet adapters is detected - SATA Device tree is imported from linux next-20230728. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v3: - Rebased on master and "board: rockchip: Add Pine64 Quartz64 and SOQuartz boards" v2 series - Sync device tree from linux next-20230728 to include sata1, combphy1 and regulator fixes merged into linux maintainer tree since v2 - Drop u-boot.dtsi pcie pinctrl change that caused pinmux issue in linux when using EFI boot flow - Collect r-b tag Changes in v2: - Remove the unneeded always-on/boot-on prop of vcc3v3_pi6c_05 - Drop PCI_INIT_R=y and add MMC_HS200_SUPPORT=y to speed up boot - Enable sata1 node and set correct regulator to combphy1 node, can be dropped in a future DT sync once linux patch [1] lands This patch depends on the series "board: rockchip: Add Pine64 Quartz64 and SOQuartz boards" v2 [2] and all its depends. A copy of this patch and all its depends can be found at [3]. [1] https://lore.kernel.org/linux-rockchip/20230724145213.3833099-1-jonas@kwibo… [2] https://patchwork.ozlabs.org/project/uboot/list/?series=366399 [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-radxa-e25-v3 arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-radxa-cm3i.dtsi | 415 ++++++++++++++++++++++ arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 32 ++ arch/arm/dts/rk3568-radxa-e25.dts | 236 ++++++++++++ board/rockchip/evb_rk3568/MAINTAINERS | 8 + configs/radxa-e25-rk3568_defconfig | 94 +++++ doc/board/rockchip/rockchip.rst | 1 + 7 files changed, 787 insertions(+) create mode 100644 arch/arm/dts/rk3568-radxa-cm3i.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25.dts create mode 100644 configs/radxa-e25-rk3568_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bf8c568260a6..01aba388994e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -180,6 +180,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ rk3568-odroid-m1.dtb \ + rk3568-radxa-e25.dtb \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi b/arch/arm/dts/rk3568-radxa-cm3i.dtsi new file mode 100644 index 000000000000..c50fbdd48680 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-cm3i.dtsi @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3568.dtsi" + +/ { + compatible = "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v_input>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_input>; + }; + + /* labeled +5v_input in schematic */ + vcc5v_input: vcc5v-input-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_input"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&display_subsystem { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v_input>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; +}; diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi new file mode 100644 index 000000000000..572bdc5665b1 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +/* PCIe PHY driver in U-Boot does not support bifurcation */ +&pcie3x1 { + status = "disabled"; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/rk3568-radxa-e25.dts b/arch/arm/dts/rk3568-radxa-e25.dts new file mode 100644 index 000000000000..72ad74c38a2b --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3568-radxa-cm3i.dtsi" + +/ { + model = "Radxa E25 Carrier Board"; + compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc1 = &sdmmc0; + }; + + pwm-leds { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + max-brightness = <255>; + + led-red { + color = <LED_COLOR_ID_RED>; + pwms = <&pwm1 0 1000000 0>; + }; + + led-green { + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm2 0 1000000 0>; + }; + + led-blue { + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm12 0 1000000 0>; + }; + }; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus_typec_en>; + regulator-name = "vbus_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc5v0_sys, dependent + * on pi6c clock generator + */ + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_enable_h>; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ngffpcie_enable_h>; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1_enable_h>; + regulator-name = "vcc3v3_pcie30x1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1 { + phy-supply = <&vcc3v3_pcie30x1>; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2_reset_h>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pinctrl { + pcie { + pcie20_reset_h: pcie20-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x1_enable_h: pcie30x1-enable-h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x2_reset_h: pcie30x2-reset-h { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + minipcie_enable_h: minipcie-enable-h { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ngffpcie_enable_h: ngffpcie-enable-h { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vbus_typec_en: vbus_typec_en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm12 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + /* Also used in pcie30x1_clkreqnm0 */ + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vbus_typec>; + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc3v3_ngff>; + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index a8ed2508a162..82a92b89fa64 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -27,6 +27,14 @@ M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained F: configs/radxa-cm3-io-rk3566_defconfig +RADXA-E25 +M: Jonas Karlman <jonas(a)kwiboo.se> +S: Maintained +F: configs/radxa-e25-rk3568_defconfig +F: arch/arm/dts/rk3568-radxa-cm3i.dtsi +F: arch/arm/dts/rk3568-radxa-e25.dts +F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi + ROCK-3A M: Akash Gajjar <gajjar04akash(a)gmail.com> S: Maintained diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig new file mode 100644 index 000000000000..a905100a794d --- /dev/null +++ b/configs/radxa-e25-rk3568_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index e23237e453f3..10fffb56f13d 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -101,6 +101,7 @@ List of mainline supported Rockchip boards: - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig) + - Radxa E25 Carrier Board (radxa-e25-rk3568_defconfig) * rk3588 - Rockchip EVB (evb-rk3588) -- 2.41.0

2 2

[PATCH v3] rockchip: rk3568: Add EmbedFire Lubancat 2 support
by Andy Yan 01 Aug '23

01 Aug '23

LubanCat2 is a rk3568 based SBC from EmbedFire. Specification: - Rockchip rk3568 - LPDDR4/4X 1/2/4/8 GB - TF scard slot - eMMC 8/32/64/128 GB - Gigabit ethernet x 2 - HDMI out - USB 2.0 Host x 1 - USB 2.0 Type-C OTG x 1 - USB 3.0 Host x 1 - Mini PCIE interface for WIFI/BT module - M.2 key for 2280 NVME - 40 pin header The dts file is sync from linux mainline. There are some dts bootph-all and USB3 update according to Jonas suggestion[0], so this patch based on Jonas patch [1] [2]. Signed-off-by: Andy Yan <andyshrk(a)163.com> [0]:http://patchwork.ozlabs.org/project/uboot/patch/20230708102556.25472-1-a… [1]:http://patchwork.ozlabs.org/project/uboot/cover/20230728115302.1735429-1… [2]:http://patchwork.ozlabs.org/project/uboot/cover/20230728124011.1747408-1… --- Changes in v3: - some alphabetical order update - disable all SPI flash related options. - remove bootph-all for pinctrl - add emmc_datastrobe pinconfig for hs200/hs400 in u-boot.dtsi - use USB_DWC3_GENERIC driver as Jonas suggested. - add CONFIG_SPL_DM_SEQ_ALIAS Changes in v2: - enable SPL_FIT_SIGNATURE arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi | 28 + arch/arm/dts/rk3568-lubancat-2.dts | 734 +++++++++++++++++++++ configs/lubancat-2-rk3568_defconfig | 87 +++ 4 files changed, 850 insertions(+) create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts create mode 100644 configs/lubancat-2-rk3568_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bd5887bf75..fb139a14fe 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -172,6 +172,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ + rk3568-lubancat-2.dtb \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ rk3568-odroid-m1.dtb \ diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi new file mode 100644 index 0000000000..52bd757bd0 --- /dev/null +++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Rockchip Electronics Co., Ltd + * (C) Copyright 2023 Andy Yan <andyshrk(a)163.com> + */ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-lubancat-2.dts b/arch/arm/dts/rk3568-lubancat-2.dts new file mode 100644 index 0000000000..da257b0591 --- /dev/null +++ b/arch/arm/dts/rk3568-lubancat-2.dts @@ -0,0 +1,734 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 EmbedFire <embedfire(a)embedfire.com> + * Copyright (c) 2023 Andy Yan <andyshrk(a)163.com> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "EmbedFire LubanCat 2"; + compatible = "embedfire,lubancat-2", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + user_led: user-led { + label = "user_led"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_pin>; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + dc_5v: dc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_5v>; + }; + + vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "m2_pcie_3v3"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc3v3_m2_pcie_en>; + pinctrl-names = "default"; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "minipcie_3v3"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc3v3_mini_pcie_en>; + pinctrl-names = "default"; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb20_host: vcc5v0-usb20-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb20_host"; + enable-active-high; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_usb20_host_en>; + pinctrl-names = "default"; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_usb30_host_en>; + pinctrl-names = "default"; + }; + + vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg_vbus"; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_otg_vbus_en>; + pinctrl-names = "default"; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x22>; + rx_delay = <0x0e>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x21>; + rx_delay = <0x0e>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gic { + mbi-ranges = <94 31>, <229 31>, <289 31>; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_m2_pcie>; + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_mini_pcie>; + status = "okay"; +}; + +&pmu_io_domains { + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm8 { + status = "okay"; +}; + +&pwm9 { + status = "disabled"; +}; + +&pwm10 { + status = "disabled"; +}; + +&pwm14 { + status = "disabled"; +}; + +&spi3 { + pinctrl-0 = <&spi3m1_pins>; + status = "disabled"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; + status = "disabled"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&sdhci { + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + supports-emmc; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +/* USB OTG/USB Host_1 USB 2.0 Comb */ +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_otg_vbus>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Host_2/USB Host_3 USB 2.0 Comb */ +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */ +&usb_host0_xhci { + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + dr_mode = "host"; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +/* USB3.0 Host */ +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&pinctrl { + leds { + user_led_pin: user-status-led-pin { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb30_host_en: vcc5v0-usb30-host-en { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig new file mode 100644 index 0000000000..278ee8dc70 --- /dev/null +++ b/configs/lubancat-2-rk3568_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +# CONFIG_SPI_FLASH is not set +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y +CONFIG_EFI_VAR_BUF_SIZE=16384 -- 2.34.1

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