July 2023 - U-Boot

[PATCH] spl: Add function called after fpga image upload
by christian.taedcke-oss＠weidmueller.com 11 Jul '23

11 Jul '23

From: Christian Taedcke <christian.taedcke(a)weidmueller.com> This way custom logic can be implemented per board after the fpga image is uploaded. Signed-off-by: Christian Taedcke <christian.taedcke(a)weidmueller.com> --- common/spl/spl_fit.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 730639f756..3a1e3382ba 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -560,6 +560,16 @@ __weak void *spl_load_simple_fit_fix_load(const void *fit) return (void *)fit; } +/* + * Weak default function to allow implementing logic after fpga image is + * uploaded. + */ +__weak void board_spl_fit_post_upload_fpga(const void *fit, int node, + struct spl_image_info *fpga_image, + int ret) +{ +} + static void warn_deprecated(const char *msg) { printf("DEPRECATED: %s\n", msg); @@ -590,6 +600,9 @@ static int spl_fit_upload_fpga(struct spl_fit_info *ctx, int node, ret = fpga_load(devnum, (void *)fpga_image->load_addr, fpga_image->size, BIT_FULL, flags); + + board_spl_fit_post_upload_fpga(ctx->fit, node, fpga_image, ret); + if (ret) { printf("%s: Cannot load the image to the FPGA\n", __func__); return ret; -- 2.34.1

5 11

[PATCH v5 00/23] Migration to using binman for bootloader
by Neha Malcom Francis 11 Jul '23

11 Jul '23

This series aims to eliminate the use of additional custom repositories such as k3-image-gen (K3 Image Generation) repo and core-secdev-k3 (K3 Security Development Tools) that was plumbed into the U-Boot build flow to generate boot images for TI K3 platform devices. And instead, we move towards using binman that aligns better with the community standard build flow. This series uses binman for all K3 platforms supported on U-Boot currently; both HS (High Security, both SE and FS) and GP (General Purpose) devices. Background on using k3-image-gen: * TI K3 devices require a SYSFW (System Firmware) image consisting of a signed system firmware image and board configuration binaries, this is needed to bring up system firmware during U-Boot R5 SPL startup. * Board configuration data contain board-specific information such as resource management, power management and security. Background on using core-secdev-k3: * Contains resources to sign x509 certificates for HS devices Series intends to use binman to take over the packaging and signing for the R5 bootloader images tiboot3.bin (and sysfw.itb, for non-combined boot flow) instead of k3-image-gen. Series also packages the A72/A53 bootloader images (tispl.bin and u-boot.img) using ATF, OPTEE and DM (Device Manager) Changes in v5: - updated all board configurations to latest - changed output binary filenames - fixed multiple certificate generation leading to packaging inconsistency in ti-secure*.py - added patch to overwrite symlink if exists, patch 21/23 ("binman: Overwrite symlink if it already exists") Changes in v4: - added support for iot2050 - documentation fixes - move to using self.Raise in ti-board-config etype - introduced common k3-binman.dtsi (further reduction in code duplication can be targeted, this as first step) Changes in v3: - added support for HS-FS devices - added support for AM68-sk - added back dropped documentation patch - changed prefix for SYSFW and DM files to expected directory name - extended test coverage to 100% - documentation fixes - corrected formatting changes Changes in v2: - removed all external scripts - created ti-board-config etype to support generation of board config binaries - created ti-secure and ti-secure-rom etypes to handle signing instead of using external TI_SECURE_DEV_PKG - updated openssl btool to support x509 certificate generation - dropped Makefile changes to obtain external binary components, moving to using BINMAN_INDIRS to achieve the same CI/CD passes 100% (with series rebased on -master, current series based on -next) [1] v1: https://patchwork.ozlabs.org/project/uboot/cover/20230120101903.179959-1-n-… v2: https://patchwork.ozlabs.org/project/uboot/cover/20230404121342.446935-1-n-… v3: https://patchwork.ozlabs.org/project/uboot/cover/20230421123203.1315330-1-n… v4: https://patchwork.ozlabs.org/project/uboot/cover/20230518142713.184164-1-n-… [1] https://github.com/u-boot/u-boot/pull/341 Andrew Davis (1): binman: Overwrite symlink if it already exists Neha Malcom Francis (20): binman: ti-board-config: Add support for TI board config binaries binman: ti-secure: Add support for TI signing arm: dts: k3: Add support for packaging sysfw.itb and tiboot3.bin j721e: schema: yaml: Add general schema and J721E board config files j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img j7200: yaml: Add J7200 board config files j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img am65x: yaml: Add AM65x board config files am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img am64x: yaml: Add board configs for AM64x am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.img j721s2: yaml: Add board configs for J721S2 j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img am62: yaml: Add board configs for AM62 am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img am62a: yaml: Add board configs for AM62ax am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img arm: k3-am65x-iot2050: Use binman for tispl.bin for iot2050 k3: tools: config.mk: Update makefile and remove scripts doc: board: ti: Update documentation for binman flow Tom Rini (2): buildman: Create a requirements.txt file CI: Make use of buildman requirements.txt .azure-pipelines.yml | 4 + .gitlab-ci.yml | 4 + arch/arm/dts/k3-am625-r5-sk.dts | 1 + arch/arm/dts/k3-am625-sk-binman.dtsi | 463 +++ arch/arm/dts/k3-am625-sk-u-boot.dtsi | 2 + arch/arm/dts/k3-am62a-sk-binman.dtsi | 466 +++ arch/arm/dts/k3-am62a7-r5-sk.dts | 1 + arch/arm/dts/k3-am62a7-sk.dts | 1 + arch/arm/dts/k3-am642-evm-u-boot.dtsi | 2 + arch/arm/dts/k3-am642-r5-evm.dts | 1 + arch/arm/dts/k3-am642-sk-u-boot.dtsi | 2 + arch/arm/dts/k3-am64x-binman.dtsi | 515 +++ arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 76 +- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 1 + .../dts/k3-am654-r5-base-board-u-boot.dtsi | 1 + arch/arm/dts/k3-am65x-binman.dtsi | 518 +++ .../arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 2 + arch/arm/dts/k3-binman.dtsi | 116 + arch/arm/dts/k3-j7200-binman.dtsi | 502 +++ .../k3-j7200-common-proc-board-u-boot.dtsi | 2 + arch/arm/dts/k3-j721e-binman.dtsi | 701 ++++ .../k3-j721e-common-proc-board-u-boot.dtsi | 1 + .../arm/dts/k3-j721e-r5-common-proc-board.dts | 1 + arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 1 + arch/arm/dts/k3-j721s2-binman.dtsi | 546 +++ .../k3-j721s2-common-proc-board-u-boot.dtsi | 2 + .../dts/k3-j721s2-r5-common-proc-board.dts | 1 + arch/arm/mach-k3/config.mk | 103 - board/ti/am62ax/Kconfig | 2 + board/ti/am62ax/board-cfg.yaml | 36 + board/ti/am62ax/pm-cfg.yaml | 12 + board/ti/am62ax/rm-cfg.yaml | 1151 ++++++ board/ti/am62ax/sec-cfg.yaml | 379 ++ board/ti/am62ax/tifs-rm-cfg.yaml | 1011 ++++++ board/ti/am62x/Kconfig | 2 + board/ti/am62x/board-cfg.yaml | 36 + board/ti/am62x/pm-cfg.yaml | 12 + board/ti/am62x/rm-cfg.yaml | 1088 ++++++ board/ti/am62x/sec-cfg.yaml | 379 ++ board/ti/am64x/Kconfig | 2 + board/ti/am64x/board-cfg.yaml | 37 + board/ti/am64x/pm-cfg.yaml | 12 + board/ti/am64x/rm-cfg.yaml | 1400 ++++++++ board/ti/am64x/sec-cfg.yaml | 380 ++ board/ti/am65x/Kconfig | 2 + board/ti/am65x/board-cfg.yaml | 36 + board/ti/am65x/pm-cfg.yaml | 12 + board/ti/am65x/rm-cfg.yaml | 2068 +++++++++++ board/ti/am65x/sec-cfg.yaml | 379 ++ board/ti/common/schema.yaml | 436 +++ board/ti/j721e/Kconfig | 4 + board/ti/j721e/board-cfg.yaml | 37 + board/ti/j721e/board-cfg_j7200.yaml | 36 + board/ti/j721e/pm-cfg.yaml | 13 + board/ti/j721e/pm-cfg_j7200.yaml | 12 + board/ti/j721e/rm-cfg.yaml | 3174 +++++++++++++++++ board/ti/j721e/rm-cfg_j7200.yaml | 2065 +++++++++++ board/ti/j721e/sec-cfg.yaml | 381 ++ board/ti/j721e/sec-cfg_j7200.yaml | 380 ++ board/ti/j721s2/Kconfig | 2 + board/ti/j721s2/board-cfg.yaml | 37 + board/ti/j721s2/pm-cfg.yaml | 12 + board/ti/j721s2/rm-cfg.yaml | 2901 +++++++++++++++ board/ti/j721s2/sec-cfg.yaml | 379 ++ board/ti/keys/custMpk.pem | 51 + board/ti/keys/ti-degenerate-key.pem | 10 + doc/board/ti/am62x_sk.rst | 42 +- doc/board/ti/j721e_evm.rst | 50 +- doc/board/ti/k3.rst | 95 +- tools/binman/btool/openssl.py | 244 ++ tools/binman/entries.rst | 113 + tools/binman/etype/ti_board_config.py | 259 ++ tools/binman/etype/ti_secure.py | 78 + tools/binman/etype/ti_secure_rom.py | 249 ++ tools/binman/etype/x509_cert.py | 87 +- tools/binman/ftest.py | 72 + tools/binman/image.py | 2 + tools/binman/test/277_ti_board_cfg.dts | 14 + .../binman/test/278_ti_board_cfg_combined.dts | 25 + .../binman/test/279_ti_board_cfg_no_type.dts | 11 + tools/binman/test/279_ti_secure.dts | 17 + tools/binman/test/280_ti_secure_rom.dts | 17 + .../test/281_ti_secure_rom_combined.dts | 25 + tools/binman/test/288_ti_secure_rom_a.dts | 19 + tools/binman/test/289_ti_secure_rom_b.dts | 18 + tools/binman/test/yaml/config.yaml | 19 + tools/binman/test/yaml/schema.yaml | 51 + tools/binman/test/yaml/schema_notype.yaml | 40 + tools/buildman/requirements.txt | 2 + tools/k3_fit_atf.sh | 123 - tools/k3_gen_x509_cert.sh | 262 -- 91 files changed, 23724 insertions(+), 612 deletions(-) create mode 100644 arch/arm/dts/k3-am625-sk-binman.dtsi create mode 100644 arch/arm/dts/k3-am62a-sk-binman.dtsi create mode 100644 arch/arm/dts/k3-am64x-binman.dtsi create mode 100644 arch/arm/dts/k3-am65x-binman.dtsi create mode 100644 arch/arm/dts/k3-binman.dtsi create mode 100644 arch/arm/dts/k3-j7200-binman.dtsi create mode 100644 arch/arm/dts/k3-j721e-binman.dtsi create mode 100644 arch/arm/dts/k3-j721s2-binman.dtsi delete mode 100644 arch/arm/mach-k3/config.mk create mode 100644 board/ti/am62ax/board-cfg.yaml create mode 100644 board/ti/am62ax/pm-cfg.yaml create mode 100644 board/ti/am62ax/rm-cfg.yaml create mode 100644 board/ti/am62ax/sec-cfg.yaml create mode 100644 board/ti/am62ax/tifs-rm-cfg.yaml create mode 100644 board/ti/am62x/board-cfg.yaml create mode 100644 board/ti/am62x/pm-cfg.yaml create mode 100644 board/ti/am62x/rm-cfg.yaml create mode 100644 board/ti/am62x/sec-cfg.yaml create mode 100644 board/ti/am64x/board-cfg.yaml create mode 100644 board/ti/am64x/pm-cfg.yaml create mode 100644 board/ti/am64x/rm-cfg.yaml create mode 100644 board/ti/am64x/sec-cfg.yaml create mode 100644 board/ti/am65x/board-cfg.yaml create mode 100644 board/ti/am65x/pm-cfg.yaml create mode 100644 board/ti/am65x/rm-cfg.yaml create mode 100644 board/ti/am65x/sec-cfg.yaml create mode 100644 board/ti/common/schema.yaml create mode 100644 board/ti/j721e/board-cfg.yaml create mode 100644 board/ti/j721e/board-cfg_j7200.yaml create mode 100644 board/ti/j721e/pm-cfg.yaml create mode 100644 board/ti/j721e/pm-cfg_j7200.yaml create mode 100644 board/ti/j721e/rm-cfg.yaml create mode 100644 board/ti/j721e/rm-cfg_j7200.yaml create mode 100644 board/ti/j721e/sec-cfg.yaml create mode 100644 board/ti/j721e/sec-cfg_j7200.yaml create mode 100644 board/ti/j721s2/board-cfg.yaml create mode 100644 board/ti/j721s2/pm-cfg.yaml create mode 100644 board/ti/j721s2/rm-cfg.yaml create mode 100644 board/ti/j721s2/sec-cfg.yaml create mode 100644 board/ti/keys/custMpk.pem create mode 100644 board/ti/keys/ti-degenerate-key.pem create mode 100644 tools/binman/etype/ti_board_config.py create mode 100644 tools/binman/etype/ti_secure.py create mode 100644 tools/binman/etype/ti_secure_rom.py create mode 100644 tools/binman/test/277_ti_board_cfg.dts create mode 100644 tools/binman/test/278_ti_board_cfg_combined.dts create mode 100644 tools/binman/test/279_ti_board_cfg_no_type.dts create mode 100644 tools/binman/test/279_ti_secure.dts create mode 100644 tools/binman/test/280_ti_secure_rom.dts create mode 100644 tools/binman/test/281_ti_secure_rom_combined.dts create mode 100644 tools/binman/test/288_ti_secure_rom_a.dts create mode 100644 tools/binman/test/289_ti_secure_rom_b.dts create mode 100644 tools/binman/test/yaml/config.yaml create mode 100644 tools/binman/test/yaml/schema.yaml create mode 100644 tools/binman/test/yaml/schema_notype.yaml create mode 100644 tools/buildman/requirements.txt delete mode 100755 tools/k3_fit_atf.sh delete mode 100755 tools/k3_gen_x509_cert.sh -- 2.34.1

6 41

[PATCH 00/10] firmware: scmi: add SCMI base protocol support
by AKASHI Takahiro 11 Jul '23

11 Jul '23

This patch series allows users to access SCMI base protocol provided by SCMI server (platform). It will also be utilized in separate patches in the future to add sanity/validity checks for other protocols. See SCMI specification document v3.2 beta[1] for more details about SCMI base protocol. What is currently not implemented is - SCMI_BASE_NOTIFY_ERRORS command and notification callback mechanism This feature won't be very useful in the current U-Boot environment. [1] https://developer.arm.com/documentation/den0056/e/?lang=en Test ==== The patch series was tested on the following platforms: * sandbox * qemu-arm64 with OPTEE as SCMI server Prerequisite: ============= * This patch series is based on v2023.07-rc and relies on the following patch: [2] https://lists.denx.de/pipermail/u-boot/2023-June/520083.html Patches: ======== Patch#1-#4: Add SCMI base protocol driver Patch#5-#7: Add SCMI base protocol device unit test Patch#8-#10: Add scmi command Change history: =============== v1 (Jun, 28, 2023) * initial release AKASHI Takahiro (10): firmware: scmi: implement SCMI base protocol firmware: scmi: framework for installing additional protocols firmware: scmi: install base protocol to SCMI agent sandbox: remove SCMI base node definition from test.dts firmware: scmi: fake base protocol commands on sandbox test: dm: simplify SCMI unit test on sandbox test: dm: add SCMI base protocol test cmd: add scmi command for SCMI firmware doc: cmd: add documentation for scmi test: dm: add scmi command test arch/sandbox/dts/test.dts | 4 - arch/sandbox/include/asm/scmi_test.h | 7 +- cmd/Kconfig | 8 + cmd/Makefile | 1 + cmd/scmi.c | 373 +++++++++++++++ doc/usage/cmd/scmi.rst | 98 ++++ drivers/firmware/scmi/Makefile | 1 + drivers/firmware/scmi/base.c | 523 +++++++++++++++++++++ drivers/firmware/scmi/sandbox-scmi_agent.c | 379 ++++++++++++++- drivers/firmware/scmi/scmi_agent-uclass.c | 195 +++++++- include/dm/uclass-id.h | 1 + include/scmi_agent-uclass.h | 84 ++++ include/scmi_agent.h | 24 + include/scmi_protocols.h | 201 +++++++- test/dm/scmi.c | 233 +++++++-- 15 files changed, 2057 insertions(+), 75 deletions(-) create mode 100644 cmd/scmi.c create mode 100644 doc/usage/cmd/scmi.rst create mode 100644 drivers/firmware/scmi/base.c -- 2.41.0

2 35

[PATCH v2 00/11] Sign Xilinx ZynqMP SPL/FSBL boot images using binman
by lukas.funke-oss＠weidmueller.com 10 Jul '23

10 Jul '23

From: Lukas Funke <lukas.funke(a)weidmueller.com> This series adds two etypes to create a verified boot chain for Xilinx ZynqMP devices. The first etype 'xilinx_fsbl_auth' is used to create a bootable, signed image for ZynqMP boards using the Xilinx Bootgen tool. The second etype 'u_boot_spl_pubkey_dtb' is used to add a '/signature' node to the SPL. The public key in the signature is read from a certificate file and added using the 'fdt_add_pubkey' tool. The series also contains the corresponding btool for calling 'bootgen' and 'fdt_add_pubkey' The following block shows an example on how to use this functionality: spl { filename = "boot.signed.bin"; xilinx_fsbl_auth { psk-filename = "psk0.pem"; ssk-filename = "ssk0.pem"; auth-params = "ppk_select=0", "spk_id=0x00000000"; u_boot_spl_nodtb { }; u_boot_spl_pubkey_dtb { algo = "sha384,rsa4096"; required = "conf"; key-name = "dev"; }; }; }; Changes in v2: - Changed u_boot_spl_pubkey_dtb to u-boot-spl-pubkey-dtb - Improved rst/python documentation - Changed u_boot_spl_pubkey_dtb to u-boot-spl-pubkey-dtb in example - Pass additional 'keysrc_enc' parameter to Bootgen - Added more information and terms to documentation - Fixed typo in dts name - Add 'keysrc-enc' property to pass down to Bootgen - Improved documentation - Use predictable output names for intermediated results Lukas Funke (11): binman: elf: Check for ELF_TOOLS availability and remove extra semicolon binman: Don't decompress data while signing binman: blob_dtb: Add fake_size argument to ObtainContents() binman: doc: Add documentation for fdt_add_pubkey bintool binman: ftest: Add test for u_boot_spl_pubkey_dtb binman: btool: Add fdt_add_pubkey as btool binman: etype: Add u_boot_spl_pubkey_dtb etype binman: doc: Add documentation for Xilinx Bootgen bintool binman: btool: Add Xilinx Bootgen btool binman: ftest: Add test for xilinx_fsbl_auth etype binman: etype: Add xilinx_fsbl_auth etype tools/binman/bintools.rst | 22 ++ tools/binman/btool/bootgen.py | 136 +++++++++++++ tools/binman/btool/fdt_add_pubkey.py | 67 ++++++ tools/binman/control.py | 2 +- tools/binman/elf.py | 10 +- tools/binman/entries.rst | 92 +++++++++ tools/binman/etype/blob_dtb.py | 2 +- tools/binman/etype/u_boot_spl_pubkey_dtb.py | 109 ++++++++++ tools/binman/etype/xilinx_fsbl_auth.py | 213 ++++++++++++++++++++ tools/binman/ftest.py | 42 +++- tools/binman/test/280_xilinx_fsbl_auth.dts | 23 +++ tools/binman/test/281_spl_pubkey_dtb.dts | 16 ++ 12 files changed, 727 insertions(+), 7 deletions(-) create mode 100644 tools/binman/btool/bootgen.py create mode 100644 tools/binman/btool/fdt_add_pubkey.py create mode 100644 tools/binman/etype/u_boot_spl_pubkey_dtb.py create mode 100644 tools/binman/etype/xilinx_fsbl_auth.py create mode 100644 tools/binman/test/280_xilinx_fsbl_auth.dts create mode 100644 tools/binman/test/281_spl_pubkey_dtb.dts -- 2.30.2

3 18

[PATCH] powerpc: Add support for CZ.NIC Turris 1.x routers
by Pali Rohár 10 Jul '23

10 Jul '23

CZ.NIC Turris 1.0 and 1.1 are open source routers, they have dual-core PowerPC Freescale P2020 CPU and are based on Freescale P2020RDB-PC-A board. Hardware design is fully open source, all firmware and hardware design files are available at Turris project website: https://docs.turris.cz/hw/turris-1x/turris-1x/ https://project.turris.cz/en/hardware.html This patch adds full U-Boot support for CZ.NIC Turris 1.x routers. P2020 BootROM can load U-Boot either from NOR flash or from SD card. So there is defconfig file turris_1x_nor_defconfig which builds NOR version and defconfig file turris_1x_sdcard_defconfig which builds SD card version. Design of CZ.NIC Turris 1.x routers is based on Freescale P2020RDB-PC-A board, so common board code from boards/freescale/p1_p2_rdb_pc directory is shared and linked also into Turris 1.x U-Boot board code. Turris 1.x code in this patch uses modern distroboot and can boot Linux kernel from various locations, including NAND, SD card, USB flash disks, NVMe disks or SATA disks (connected to extra SATA/SCSI PCIe controllers). Signed-off-by: Pali Rohár <pali(a)kernel.org> --- This patch depends on other powerpc patches: https://patchwork.ozlabs.org/bundle/pali/powerpc/ --- arch/powerpc/cpu/mpc85xx/Kconfig | 6 + arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/turris1x-u-boot.dtsi | 13 + arch/powerpc/dts/turris1x.dts | 475 ++++++++++++++++++++++++++ board/CZ.NIC/turris_1x/Kconfig | 177 ++++++++++ board/CZ.NIC/turris_1x/MAINTAINERS | 11 + board/CZ.NIC/turris_1x/Makefile | 15 + board/CZ.NIC/turris_1x/ddr.c | 27 ++ board/CZ.NIC/turris_1x/law.c | 13 + board/CZ.NIC/turris_1x/lbc.c | 26 ++ board/CZ.NIC/turris_1x/tlb.c | 142 ++++++++ board/CZ.NIC/turris_1x/turris_1x.c | 106 ++++++ configs/turris_1x_nor_defconfig | 50 +++ configs/turris_1x_sdcard_defconfig | 66 ++++ include/configs/turris_1x.h | 381 +++++++++++++++++++++ 15 files changed, 1509 insertions(+) create mode 100644 arch/powerpc/dts/turris1x-u-boot.dtsi create mode 100644 arch/powerpc/dts/turris1x.dts create mode 100644 board/CZ.NIC/turris_1x/Kconfig create mode 100644 board/CZ.NIC/turris_1x/MAINTAINERS create mode 100644 board/CZ.NIC/turris_1x/Makefile create mode 100644 board/CZ.NIC/turris_1x/ddr.c create mode 100644 board/CZ.NIC/turris_1x/law.c create mode 100644 board/CZ.NIC/turris_1x/lbc.c create mode 100644 board/CZ.NIC/turris_1x/tlb.c create mode 100644 board/CZ.NIC/turris_1x/turris_1x.c create mode 100644 configs/turris_1x_nor_defconfig create mode 100644 configs/turris_1x_sdcard_defconfig create mode 100644 include/configs/turris_1x.h diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 6f8b7593d250..28f69e7c73d2 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -150,6 +150,11 @@ config TARGET_P2020RDB imply CMD_SATA imply SATA_SIL +config TARGET_TURRIS_1X + bool "Support Turris 1.x" + select SUPPORT_SPL + select ARCH_P2020 + config TARGET_P2041RDB bool "Support P2041RDB" select ARCH_P2041 @@ -1201,6 +1206,7 @@ config SYS_FSL_LBC_CLK_DIV config FSL_VIA bool +source "board/CZ.NIC/turris_1x/Kconfig" source "board/emulation/qemu-ppce500/Kconfig" source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8548cds/Kconfig" diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index a4b0d7ddc4ff..d6462101211e 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -26,6 +26,7 @@ dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb +dtb-$(CONFIG_TARGET_TURRIS_1X) += turris1x.dtb dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb diff --git a/arch/powerpc/dts/turris1x-u-boot.dtsi b/arch/powerpc/dts/turris1x-u-boot.dtsi new file mode 100644 index 000000000000..aa758818d564 --- /dev/null +++ b/arch/powerpc/dts/turris1x-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&soc { + i2c@3000 { + u-boot,dm-pre-reloc; + + crypto@64 { + u-boot,dm-pre-reloc; + }; + }; +}; + +#include "u-boot.dtsi" diff --git a/arch/powerpc/dts/turris1x.dts b/arch/powerpc/dts/turris1x.dts new file mode 100644 index 000000000000..1b27c1b0bba6 --- /dev/null +++ b/arch/powerpc/dts/turris1x.dts @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Turris 1.x Device Tree Source + * + * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/) + * + * Pinout, Schematics and Altium hardware design files are open source + * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +/include/ "fsl/p2020si-pre.dtsi" + +/ { + model = "Turris 1.x"; + compatible = "cznic,turris1x", "fsl,P2020RDB-PC"; /* fsl,P2020RDB-PC is required for booting Linux */ + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + }; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x00100000>; + + i2c@3000 { + /* PCA9557PW GPIO controller for boot config */ + gpio-controller@18 { + compatible = "nxp,pca9557"; + label = "bootcfg"; + reg = <0x18>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + /* STM32F030R8T6 MCU for power control */ + power-control@2a { + /* + * Turris Power Control firmware runs on STM32F0 MCU. + * This firmware is open source and available at: + * https://gitlab.nic.cz/turris/hw/turris_power_control + */ + reg = <0x2a>; + }; + + /* DDR3 SPD/EEPROM PSWP instruction */ + eeprom@32 { + reg = <0x32>; + }; + + /* SA56004ED temperature control */ + temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>, /* GPIO12 - ALERT pin */ + <13 IRQ_TYPE_LEVEL_LOW>; /* GPIO13 - CRIT pin */ + }; + + /* DDR3 SPD/EEPROM */ + eeprom@52 { + compatible = "atmel,spd"; + reg = <0x52>; + }; + + /* MCP79402-I/ST Protected EEPROM */ + eeprom@57 { + reg = <0x57>; + }; + + /* ATSHA204-TH-DA-T crypto module */ + crypto@64 { + compatible = "atmel,atsha204"; + reg = <0x64>; + }; + + /* IDT6V49205BNLGI clock generator */ + clock-generator@69 { + compatible = "idt,6v49205b"; + reg = <0x69>; + }; + + /* MCP79402-I/ST RTC */ + rtc@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + interrupt-parent = <&gpio>; + interrupts = <14 0>; /* GPIO14 - MFP pin */ + }; + }; + + /* SPI on connector P1 */ + spi0: spi@7000 { + }; + + gpio: gpio-controller@fc00 { + #interrupt-cells = <2>; + interrupt-controller; + }; + + /* Connected to SMSC USB2412-DZK 2-Port USB 2.0 Hub Controller */ + usb@22000 { + phy_type = "ulpi"; + dr_mode = "host"; + }; + + enet0: ethernet@24000 { + /* Connected to port 6 of QCA8337N-AL3C switch */ + phy-connection-type = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + mdio@24520 { + /* QCA8337N-AL3C switch with integrated ethernet PHYs for LAN ports */ + switch@10 { + compatible = "qca,qca8337"; + interrupts = <2 1 0 0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu1"; + ethernet = <&enet1>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan5"; + }; + + port@2 { + reg = <2>; + label = "lan4"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan2"; + }; + + port@5 { + reg = <5>; + label = "lan1"; + }; + + port@6 { + reg = <6>; + label = "cpu0"; + ethernet = <&enet0>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + /* KSZ9031RNXCA ethernet phy for WAN port */ + phy: ethernet-phy@7 { + interrupts = <3 1 0 0>; + reg = <0x7>; + }; + }; + + ptp_clock@24e00 { + fsl,tclk-period = <5>; + fsl,tmr-prsc = <200>; + fsl,tmr-add = <0xcccccccd>; + fsl,tmr-fiper1 = <0x3b9ac9fb>; + fsl,tmr-fiper2 = <0x0001869b>; + fsl,max-adj = <249999999>; + }; + + enet1: ethernet@25000 { + /* Connected to port 0 of QCA8337N-AL3C switch */ + phy-connection-type = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + mdio@25520 { + status = "disabled"; + }; + + enet2: ethernet@26000 { + /* Connected to KSZ9031RNXCA ethernet phy (WAN port) */ + label = "wan"; + phy-handle = <&phy>; + phy-connection-type = "rgmii-id"; + }; + + mdio@26520 { + status = "disabled"; + }; + + sdhc@2e000 { + bus-width = <4>; + cd-gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + }; + + lbc: localbus@ffe05000 { + reg = <0 0xffe05000 0 0x1000>; + + ranges = <0x0 0x0 0x0 0xef000000 0x01000000>, /* NOR */ + <0x1 0x0 0x0 0xff800000 0x00040000>, /* NAND */ + <0x3 0x0 0x0 0xffa00000 0x00020000>; /* CPLD */ + + /* S29GL128P90TFIR10 NOR */ + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x0 0x0 0x01000000>; + bank-width = <2>; + device-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + /* 128 kB for Device Tree Blob */ + reg = <0x00000000 0x00020000>; + label = "dtb"; + }; + + partition@20000 { + /* 1.7 MB for Rescue Linux Kernel Image */ + reg = <0x00020000 0x001a0000>; + label = "rescue-kernel"; + }; + + partition@1c0000 { + /* 1.5 MB for Rescue JFFS2 Root File System */ + reg = <0x001c0000 0x00180000>; + label = "rescue-rootfs"; + }; + + partition@340000 { + /* 11 MB for TAR.XZ Backup with content of NAND Root File System */ + reg = <0x00340000 0x00b00000>; + label = "backup-rootfs"; + }; + + partition@e40000 { + /* 768 kB for Certificates JFFS2 File System */ + reg = <0x00e40000 0x000c0000>; + label = "certificates"; + }; + + /* free unused space 0x00f00000-0x00f20000 */ + + partition@f20000 { + /* 128 kB for U-Boot Environment Variables */ + reg = <0x00f20000 0x00020000>; + label = "u-boot-env"; + }; + + partition@f40000 { + /* 768 kB for U-Boot Bootloader Image */ + reg = <0x00f40000 0x000c0000>; + label = "u-boot"; + }; + }; + }; + + /* MT29F2G08ABAEAWP:E NAND */ + nand@1,0 { + compatible = "fsl,p2020-fcm-nand", "fsl,elbc-fcm-nand"; + reg = <0x1 0x0 0x00040000>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "bch"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + /* 256 MB for UBI with one volume: UBIFS Root File System */ + reg = <0x00000000 0x10000000>; + label = "rootfs"; + }; + }; + }; + + /* LCMXO1200C-3FTN256C FPGA */ + cpld@3,0 { + /* + * Turris CPLD firmware which runs on this Lattice FPGA, + * is extended version of P1021RDB-PC CPLD v4.1 firmware. + * It is backward compatible with its original version + * and the only extension is support for Turris LEDs. + * Turris CPLD firmware is open source and available at: + * https://gitlab.nic.cz/turris/hw/turris_cpld/-/blob/master/CZ_NIC_Router_CPL… + */ + compatible = "cznic,turris1x-cpld", "fsl,p1021rdb-pc-cpld", "simple-bus"; + reg = <0x3 0x0 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3 0x0 0x00020000>; + + /* MAX6370KA+T watchdog */ + watchdog@2 { + /* + * CPLD firmware maps SET0, SET1 and SET2 + * input logic of MAX6370KA+T chip to CPLD + * memory space at byte offset 0x2. WDI + * input logic is outside of the CPLD and + * connected via external GPIO. + */ + compatible = "maxim,max6370"; + reg = <0x02 0x01>; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + + led-controller@13 { + /* + * LEDs are controlled by CPLD firmware. + * All five LAN LEDs share common RGB settings + * and so it is not possible to set different + * colors on different LAN ports. + */ + compatible = "cznic,turris1x-leds"; + reg = <0x13 0x1d>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + reg = <0x0>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_WAN; + }; + + multi-led@1 { + reg = <0x1>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_LAN; + function-enumerator = <5>; + }; + + multi-led@2 { + reg = <0x2>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_LAN; + function-enumerator = <4>; + }; + + multi-led@3 { + reg = <0x3>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + }; + + multi-led@4 { + reg = <0x4>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + }; + + multi-led@5 { + reg = <0x5>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + }; + + multi-led@6 { + reg = <0x6>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_WLAN; + }; + + multi-led@7 { + reg = <0x7>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_POWER; + }; + }; + }; + }; + + pci2: pcie@ffe08000 { + /* + * PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller. + * This xHCI controller is available only on Turris 1.1 boards. + * Turris 1.0 boards have nothing connected to this PCIe bus, + * so system would see only PCIe Root Port of this PCIe Root + * Complex. TUSB7340RKM xHCI controller has four SuperSpeed + * channels. Channel 0 is connected to the front USB 3.0 port, + * channel 1 (but only USB 2.0 subset) to USB 2.0 pins on mPCIe + * slot 1 (CN5), channels 2 and 3 to connector P600. + * + * P2020 PCIe Root Port uses 1MB of PCIe MEM and xHCI controller + * uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required. + * So allocate 2MB of PCIe MEM for this PCIe bus. + */ + reg = <0 0xffe08000 0 0x1000>; + ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00200000>, /* MEM */ + <0x01000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; /* IO */ + + pcie@0 { + ranges; + }; + }; + + pci1: pcie@ffe09000 { + /* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */ + reg = <0 0xffe09000 0 0x1000>; + ranges = <0x02000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000>, /* MEM */ + <0x01000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; /* IO */ + + pcie@0 { + ranges; + }; + }; + + pci0: pcie@ffe0a000 { + /* + * PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card. + * Turris 1.1 boards have in this mPCIe slot additional USB 2.0 + * pins via channel 1 of TUSB7340RKM xHCI controller and also + * additional SIM card slot, both for USB-based WWAN cards. + */ + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000>, /* MEM */ + <0x01000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; /* IO */ + + pcie@0 { + ranges; + }; + }; +}; + +/include/ "fsl/p2020si-post.dtsi" diff --git a/board/CZ.NIC/turris_1x/Kconfig b/board/CZ.NIC/turris_1x/Kconfig new file mode 100644 index 000000000000..103c00d585d7 --- /dev/null +++ b/board/CZ.NIC/turris_1x/Kconfig @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) 2022 Pali Rohár <pali(a)kernel.org> + +if TARGET_TURRIS_1X + +# Board identification +config SYS_BOARD + default "turris_1x" +config SYS_VENDOR + default "CZ.NIC" +config SYS_CONFIG_NAME + default "turris_1x" +config DEFAULT_DEVICE_TREE + default "turris1x" + +# Board functions +config ATSHA204A + default y +config BOARD_EARLY_INIT_F + default y +config BOARD_EARLY_INIT_R + default y +config LAST_STAGE_INIT + default y +config OF_BOARD_SETUP + default y +config MISC + default y + +# ENV +config ENV_SIZE + default 0x2000 +config ENV_SECT_SIZE + default 0x20000 +config ENV_OVERWRITE + default y +config ENV_IS_IN_FLASH + default y +config ENV_ADDR + default 0xeff20000 # in NOR +config SYS_RELOC_GD_ENV_ADDR + default y + +# DDR +config DDR_CLK_FREQ + default 66666666 + +# UART +config DEBUG_UART_BASE + default 0xffe04500 if DEBUG_UART +config DEBUG_UART_CLOCK + default 37500000 if DEBUG_UART +config SYS_NS16550 + default y + +# I2C +config I2C_SET_DEFAULT_BUS_NUM + default y +config SYS_FSL_I2C_OFFSET + default 0x3000 +config SYS_FSL_HAS_I2C2_OFFSET + default y +config SYS_FSL_I2C2_OFFSET + default 0x3100 +config SYS_I2C_FSL + default y + +# PCIe +config PCI_INIT_R + default y +config PCIE_FSL + default y + +# Ethernet +config MII + default y +config PHY_FIXED + default y +config TSEC_ENET + default y + +# USB +config USB_EHCI_FSL + default y +config USB_XHCI_HCD + default y +config USB_XHCI_PCI + default y + +# SDHC +config FSL_ESDHC + default y +config FSL_PREPBL_ESDHC_BOOT_SECTOR + default y if SYS_EXTRA_OPTIONS = SDCARD +config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH + default 4 + +# NOR (CS0) +config SYS_BR0_PRELIM_BOOL + default y +config SYS_BR0_PRELIM + default 0xef001001 # (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_MS_GPCM | BR_V) +config SYS_OR0_PRELIM + default 0xff000ff7 # (OR_AM_16MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +config MTD_NOR_FLASH + default y +config CFI_FLASH + default y +config FLASH_CFI_MTD + default y +config SYS_FLASH_USE_BUFFER_WRITE + default y + +# NAND (CS1) +config SYS_BR1_PRELIM_BOOL + default y +config SYS_BR1_PRELIM + default 0xff800821 # (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) | BR_PS_8 | BR_MS_FCM | BR_V) +config SYS_OR1_PRELIM + default 0xfffc0796 # (OR_AM_256KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) +config MTD_RAW_NAND + default y +config NAND_FSL_ELBC + default y +config NAND_FSL_ELBC_DT + default y +config BCH + default y +config SYS_FLASH_CFI + default y + +# CPLD (CS3) +config SYS_BR3_PRELIM_BOOL + default y +config SYS_BR3_PRELIM + default 0xffa00801 # (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | BR_PS_8 | BR_MS_GPCM | BR_V) +config SYS_OR3_PRELIM + default 0xfffe09f7 # (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +config MPC85XX_HAVE_RESET_VECTOR + default y if SYS_EXTRA_OPTIONS != SDCARD + +config SYS_TEXT_BASE + default 0x11000000 if SPL # in DDR + default 0xf8f80000 if SYS_EXTRA_OPTIONS = SDCARD # in SRAM + default 0xeff40000 # in NOR + +if SPL + +config SPL_TEXT_BASE + default 0xf8f80000 if SYS_EXTRA_OPTIONS = SDCARD # in SRAM + default 0xeff40000 # in NOR + +config SPL_ENV_SUPPORT + default y +config SPL_FRAMEWORK + default n +config SPL_I2C + default y +config SPL_LIBCOMMON_SUPPORT + default y +config SPL_LIBGENERIC_SUPPORT + default y +config SPL_MMC + default y if SYS_EXTRA_OPTIONS = SDCARD +config SPL_MMC_BOOT + default y if SYS_EXTRA_OPTIONS = SDCARD +config SPL_MPC8XXX_INIT_DDR + default y +config SPL_SERIAL + default y +config SPL_SYS_I2C_LEGACY + default y + +endif + +endif diff --git a/board/CZ.NIC/turris_1x/MAINTAINERS b/board/CZ.NIC/turris_1x/MAINTAINERS new file mode 100644 index 000000000000..04f4915f7d7d --- /dev/null +++ b/board/CZ.NIC/turris_1x/MAINTAINERS @@ -0,0 +1,11 @@ +TURRIS 1.X BOARD +M: Pali Rohár <pali(a)kernel.org> +S: Maintained +F: arch/powerpc/dts/turris1x-u-boot.dtsi +F: arch/powerpc/dts/turris1x.dts +F: board/CZ.NIC/turris_1x/ +F: board/CZ.NIC/turris_atsha_otp.c +F: board/CZ.NIC/turris_atsha_otp.h +F: configs/turris_1x_nor_defconfig +F: configs/turris_1x_sdcard_defconfig +F: include/configs/turris_1x.h diff --git a/board/CZ.NIC/turris_1x/Makefile b/board/CZ.NIC/turris_1x/Makefile new file mode 100644 index 000000000000..d935456d27c9 --- /dev/null +++ b/board/CZ.NIC/turris_1x/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) 2022 Pali Rohár <pali(a)kernel.org> + +ifdef CONFIG_SPL_BUILD +obj-y += ../../freescale/p1_p2_rdb_pc/spl.o +endif + +obj-y += ../../freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.o +obj-y += ../turris_atsha_otp.o + +obj-y += turris_1x.o +obj-y += ddr.o +obj-y += law.o +obj-y += lbc.o +obj-y += tlb.o diff --git a/board/CZ.NIC/turris_1x/ddr.c b/board/CZ.NIC/turris_1x/ddr.c new file mode 100644 index 000000000000..ced4e97bfa30 --- /dev/null +++ b/board/CZ.NIC/turris_1x/ddr.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <pali(a)kernel.org> + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) +{ + int i; + + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} diff --git a/board/CZ.NIC/turris_1x/law.c b/board/CZ.NIC/turris_1x/law.c new file mode 100644 index 000000000000..1502ceecf823 --- /dev/null +++ b/board/CZ.NIC/turris_1x/law.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <pali(a)kernel.org> + +#include <common.h> +#include <asm/fsl_law.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_256K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/CZ.NIC/turris_1x/lbc.c b/board/CZ.NIC/turris_1x/lbc.c new file mode 100644 index 000000000000..de2f5d25da6d --- /dev/null +++ b/board/CZ.NIC/turris_1x/lbc.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <pali(a)kernel.org> + +#include <common.h> +#include <asm/fsl_lbc.h> +#include <linux/build_bug.h> + +/* + * Check if preliminary base/options config options have correct values. + * Due to broken build system, it is not possible to define these options + * in config.h file nor in other sane place. So do compile time checks here. + */ + +#define LBC_BR_NOR (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_MS_GPCM | BR_V) +#define LBC_OR_NOR (OR_AM_16MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define LBC_BR_NAND (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) | BR_PS_8 | BR_MS_FCM | BR_V) +#define LBC_OR_NAND (OR_AM_256KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) +#define LBC_BR_CPLD (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | BR_PS_8 | BR_MS_GPCM | BR_V) +#define LBC_OR_CPLD (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +static_assert(CONFIG_SYS_BR0_PRELIM == LBC_BR_NOR); +static_assert(CONFIG_SYS_OR0_PRELIM == LBC_OR_NOR); +static_assert(CONFIG_SYS_BR1_PRELIM == LBC_BR_NAND); +static_assert(CONFIG_SYS_BR1_PRELIM == LBC_BR_NAND); +static_assert(CONFIG_SYS_BR3_PRELIM == LBC_BR_CPLD); +static_assert(CONFIG_SYS_BR3_PRELIM == LBC_BR_CPLD); diff --git a/board/CZ.NIC/turris_1x/tlb.c b/board/CZ.NIC/turris_1x/tlb.c new file mode 100644 index 000000000000..e7113b0cd4c8 --- /dev/null +++ b/board/CZ.NIC/turris_1x/tlb.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <pali(a)kernel.org> + +#include <common.h> +#include <asm/mmu.h> +#include <linux/sizes.h> +#include <linux/build_bug.h> + +/* + * NOTE: e500v2 supports only following Book-E page sizes: + * + * TLB0: + * BOOKE_PAGESZ_4K + * + * TLB1: + * BOOKE_PAGESZ_4K + * BOOKE_PAGESZ_16K + * BOOKE_PAGESZ_64K + * BOOKE_PAGESZ_256K + * BOOKE_PAGESZ_1M + * BOOKE_PAGESZ_4M + * BOOKE_PAGESZ_16M + * BOOKE_PAGESZ_64M + * BOOKE_PAGESZ_256M + * BOOKE_PAGESZ_1G + * BOOKE_PAGESZ_4G + */ + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 */ + + /* ***** - Initial stack in L1 cache 16K */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * SZ_4K, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 0 * SZ_4K, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 1 * SZ_4K , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 1 * SZ_4K, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 2 * SZ_4K , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 2 * SZ_4K, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 3 * SZ_4K , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 3 * SZ_4K, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + + /* *I*** - Boot page 4K */ + SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, + 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSR 1M */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, + CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - NOR 16M */ + /* This will be changed to *I*G* after relocation to RAM in board_early_init_r() */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - CPLD 256K (effective 128K) */ + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, + CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256K, 1), + + /* *I*G* - NAND 1M */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, + CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* *I*G* - PCIe MEM (bus 1 and 2) 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, + CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCIe MEM (bus 3) 4M (effective 2M) */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, + CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_4M, 1), + + /* *I*G* - PCIe I/O (all 3 buses) 256K (effective 192K) */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, + CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* ***G* - Initial SRAM in L2 cache 512K */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, + CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 8, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + SZ_256K, + CONFIG_SYS_INIT_L2_ADDR_PHYS + SZ_256K, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 9, BOOKE_PAGESZ_256K, 1), +#endif + +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + /* **M** - SDRAM 2G */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 10, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + SZ_1G, + CONFIG_SYS_DDR_SDRAM_BASE + SZ_1G, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 11, BOOKE_PAGESZ_1G, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); + +/* + * PCIe MEM TLB entry expects that second PCIe MEM window is mapped after the + * first PCIe MEM window. Check for this requirement. + */ +static_assert(CONFIG_SYS_PCIE2_MEM_VIRT == CONFIG_SYS_PCIE1_MEM_VIRT + SZ_512M); +static_assert(CONFIG_SYS_PCIE2_MEM_PHYS == CONFIG_SYS_PCIE1_MEM_PHYS + SZ_512M); + +/* + * PCIe I/O TLB entry expects that all 3 PCIe I/O windows are mapped one after + * another. Check for this requirement. + */ +static_assert(CONFIG_SYS_PCIE2_IO_VIRT == CONFIG_SYS_PCIE1_IO_VIRT + SZ_64K); +static_assert(CONFIG_SYS_PCIE2_IO_PHYS == CONFIG_SYS_PCIE1_IO_PHYS + SZ_64K); +static_assert(CONFIG_SYS_PCIE3_IO_VIRT == CONFIG_SYS_PCIE2_IO_VIRT + SZ_64K); +static_assert(CONFIG_SYS_PCIE3_IO_PHYS == CONFIG_SYS_PCIE2_IO_PHYS + SZ_64K); diff --git a/board/CZ.NIC/turris_1x/turris_1x.c b/board/CZ.NIC/turris_1x/turris_1x.c new file mode 100644 index 000000000000..8f2400f79e05 --- /dev/null +++ b/board/CZ.NIC/turris_1x/turris_1x.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <pali(a)kernel.org> + +#include <common.h> +#include <init.h> +#include <env.h> + +#include "../turris_atsha_otp.h" + +/* + * Reset time cycle register provided by Turris CPLD firmware. + * Turris CPLD firmware is open source and available at: + * https://gitlab.nic.cz/turris/hw/turris_cpld/-/blob/master/CZ_NIC_Router_CPL… + */ +#define TURRIS_CPLD_RESET_TIME_CYCLE_REG ((void *)CONFIG_SYS_CPLD_BASE + 0x1f) +#define TURRIS_CPLD_RESET_TIME_CYCLE_300MS BIT(0) +#define TURRIS_CPLD_RESET_TIME_CYCLE_1S BIT(1) +#define TURRIS_CPLD_RESET_TIME_CYCLE_2S BIT(2) +#define TURRIS_CPLD_RESET_TIME_CYCLE_3S BIT(3) +#define TURRIS_CPLD_RESET_TIME_CYCLE_4S BIT(4) +#define TURRIS_CPLD_RESET_TIME_CYCLE_5S BIT(5) +#define TURRIS_CPLD_RESET_TIME_CYCLE_6S BIT(6) + +int misc_init_r(void) +{ + turris_atsha_otp_init_mac_addresses(0); + return 0; +} + +int show_board_info(void) +{ + u32 version_num, serial_num; + int err; + + err = turris_atsha_otp_get_serial_number(&version_num, &serial_num); + + /* + * Turris 1.0 boards have version_num 0x5. + * Turris 1.1 boards have version_num 0x6, 0x7, 0x8 and 0x9. + */ + printf("Model: Turris 1.%c\n", err ? 'x' : + (be32_to_cpu(version_num) >= 0x6) ? '1' : '0'); + + if (err) + printf("Serial Number: unknown\n"); + else + printf("Serial Number: %08X%08X\n", be32_to_cpu(version_num), + be32_to_cpu(serial_num)); + + err = checkboard(); + if (err) + return err; + + return 0; +} + +static void handle_reset_button(void) +{ + const char * const vars[1] = { "bootcmd_rescue", }; + + /* + * Ensure that bootcmd_rescue has always stock value, so that running + * run bootcmd_rescue + * always works correctly. + */ + env_set_default_vars(1, (char * const *)vars, 0); + + /* Check if red reset button was hold for at least six seconds. */ + if (in_8(TURRIS_CPLD_RESET_TIME_CYCLE_REG) & TURRIS_CPLD_RESET_TIME_CYCLE_6S) { + const char * const vars[2] = { + "bootcmd", + "distro_bootcmd", + }; + + /* + * Set the above envs to their default values, in case the user + * managed to break them. + */ + env_set_default_vars(2, (char * const *)vars, 0); + + /* Ensure bootcmd_rescue is used by distroboot */ + env_set("boot_targets", "rescue"); + + printf("RESET button was pressed, overwriting boot_targets!\n"); + } else { + /* + * In case the user somehow managed to save environment with + * boot_targets=rescue, reset boot_targets to default value. + * This could happen in subsequent commands if bootcmd_rescue + * failed. + */ + if (!strcmp(env_get("boot_targets"), "rescue")) { + const char * const vars[1] = { + "boot_targets", + }; + + env_set_default_vars(1, (char * const *)vars, 0); + } + } +} + +int last_stage_init(void) +{ + handle_reset_button(); + return 0; +} diff --git a/configs/turris_1x_nor_defconfig b/configs/turris_1x_nor_defconfig new file mode 100644 index 000000000000..ada6789dd6cd --- /dev/null +++ b/configs/turris_1x_nor_defconfig @@ -0,0 +1,50 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set +CONFIG_TARGET_TURRIS_1X=y +CONFIG_AHCI=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_MP=y +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run distro_bootcmd" +CONFIG_USE_PREBOOT=y +CONFIG_HUSH_PARSER=y +# CONFIG_AUTO_COMPLETE is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_EEPROM is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_I2C=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_NVME_PCI=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y diff --git a/configs/turris_1x_sdcard_defconfig b/configs/turris_1x_sdcard_defconfig new file mode 100644 index 000000000000..fcceb12cbcd1 --- /dev/null +++ b/configs/turris_1x_sdcard_defconfig @@ -0,0 +1,66 @@ +CONFIG_PPC=y +CONFIG_SPL=y +CONFIG_MPC85xx=y +CONFIG_TARGET_TURRIS_1X=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_MP=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_LZMADEC=y +CONFIG_CMD_UNLZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BTRFS=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SQUASHFS=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_PCA953X=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_NVME_PCI=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_ESPI=y +CONFIG_USB=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_MAX6370=y +CONFIG_FAT_WRITE=y diff --git a/include/configs/turris_1x.h b/include/configs/turris_1x.h new file mode 100644 index 000000000000..576767a6cbec --- /dev/null +++ b/include/configs/turris_1x.h @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <pali(a)kernel.org> + +#ifndef _CONFIG_TURRIS_1X_H +#define _CONFIG_TURRIS_1X_H + +#include <linux/sizes.h> + +/* + * Turris 1.x memory map: + * + * 0x0000_0000 - 0x7fff_ffff 2 GB DDR cacheable + * 0x8000_0000 - 0xbfff_ffff 1 GB PCIe MEM (bus 1-2) non-cacheable + * 0xc000_0000 - 0xc01f_ffff 2 MB PCIe MEM (bus 3) non-cacheable + * 0xc020_0000 - 0xeeff_ffff 750 MB unused + * 0xef00_0000 - 0xefff_ffff 16 MB NOR (CS0) non-cacheable + * 0xf000_0000 - 0xf8f7_ffff 143 MB unused + * 0xf8f8_0000 - 0xf8ff_ffff 512 kB L2 SRAM cacheable (early boot, SD card only) + * 0xf900_0000 - 0xff6f_ffff 103 MB unused + * 0xff70_0000 - 0xff7f_ffff 1 MB CCSR non-cacheable (SPL only) + * 0xff80_0000 - 0xff80_7fff 32 kB NAND (CS1) non-cacheable + * 0xffa0_0000 - 0xffa1_ffff 128 kB CPLD (CS3) non-cacheable + * 0xffc0_0000 - 0xffc2_ffff 192 kB PCIe IO non-cacheable + * 0xffd0_0000 - 0xffd0_3fff 16 kB L1 stack cacheable (early boot) + * 0xffe0_0000 - 0xffef_ffff 1 MB CCSR non-cacheable (not in SPL) + * 0xffff_f000 - 0xffff_ffff 4 kB Boot page non-cacheable + */ + +/* + * Global settings + */ + +/* + * CONFIG_ENABLE_36BIT_PHYS needs to be always defined when processor supports + * 36-bit addressing (which is case for P2020), also when only 32-bit addressing + * mode is used. Name of this config option is misleading and should have been + * called SUPPORT instead of ENABLE. + * When CONFIG_PHYS_64BIT is set then 36-bit addressing is used, when unset then + * 32-bit addressing is used. Name of this config option is misleading too and + * should have been called 36BIT and ENABLED, not 64BIT. + * Due to performance reasons (see document AN4064), Turris 1.x boards use only + * 32-bit addressing. Also all config options are currently defined only for + * 32-bit addressing, so compiling U-Boot for 36-bit addressing is not possible + * yet. + */ +#define CONFIG_ENABLE_36BIT_PHYS +#ifdef CONFIG_PHYS_64BIT +#error "36-bit addressing is not implemented for this board" +#endif + +#define CONFIG_HWCONFIG +#define CONFIG_L2_CACHE +#define CONFIG_SYS_L2_SIZE SZ_512K +#define CONFIG_BTB /* Enable Branch Prediction */ + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#define CONFIG_SYS_MONITOR_LEN CONFIG_BOARD_SIZE_LIMIT + +/* + * Boot settings + */ + +#ifdef CONFIG_SDCARD + +/* + * Booting from SD card + * BootROM configures L2 cache as SRAM, loads image from SD card into L2 SRAM + * and starts executing directly _start entry point in L2 SRAM. Therefore reset + * vector is not used and maximal size of the image is L2 cache size. For builds + * with SPL there is no limit of U-Boot proper as BootROM loads SPL which then + * loads U-Boot proper directly into DDR. + */ + +#define CONFIG_SYS_MPC85XX_NO_RESETVEC + +/* For SD card builds without SPL it is needed to set CONFIG_SYS_RAMBOOT */ +#ifndef CONFIG_SPL +#define CONFIG_SYS_RAMBOOT +#endif + +#ifdef CONFIG_SPL +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_PAD_TO 0 +#endif + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR +#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_L2_SIZE + CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * SZ_512) +#else +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_L2_SIZE +#endif +#define CONFIG_SYS_MMC_U_BOOT_SIZE CONFIG_BOARD_SIZE_LIMIT +#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_SYS_TEXT_BASE +#endif + +#else + +/* + * Booting from NOR + * Last 4kB page of the NOR is mapped into CPU address space and CPU starts + * executing last instruction of that page, which is reset vector address. + * We have 16 MB large NOR memory, so define correct reset vector address. + */ + +#define CONFIG_RESET_VECTOR_ADDRESS (CONFIG_SYS_FLASH_BASE + SZ_16M - 4) + +#endif + +/* + * CONFIG_BOARD_SIZE_LIMIT must be hex number because it is used in Makefile. + * For NOR build, size of the U-Boot binary must always be 768 kB. + * For SD card build with SPL, there is no limit, just broken build system which + * cannot fill CONFIG_SYS_MMC_U_BOOT_SIZE and CONFIG_SYS_MONITOR_LEN values + * automatically. So choose it as lowest value as possible with which build + * process does not fail, to minimize final binary size. + * For SD card build without SPL, there is upper limit of L2 cache size. + */ +#ifndef CONFIG_SDCARD +#define CONFIG_BOARD_SIZE_LIMIT 0x000c0000 /* 768 kB */ +#elif defined(CONFIG_SPL) +#define CONFIG_BOARD_SIZE_LIMIT 0x00100000 /* 1 MB */ +#else +#define CONFIG_BOARD_SIZE_LIMIT 0x00080000 /* 512 kB - must be same as CONFIG_SYS_L2_SIZE */ +#endif + +/* + * Initial stack in L1 cache + */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CONFIG_SYS_INIT_RAM_SIZE SZ_16K +#define CONFIG_SYS_INIT_RAM_LOCK + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Initial SRAM in L2 cache + */ + +/* Initial SRAM is used only for SD card boot in first stage image */ +#ifdef CONFIG_SDCARD +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SPL_RELOC_TEXT_BASE CONFIG_SYS_MONITOR_BASE +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * SZ_1K) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * SZ_1K) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * SZ_1K) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 * SZ_1K) +#endif +#endif + +/* + * CCSR + */ + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* + * U-Boot _start code expects that if CCSRBAR is configured to its default + * location and automatically relocate it to the new CONFIG_SYS_CCSRBAR_PHYS + * location. Relocation to the new location can be skipped by defining macro + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. + * + * All addresses in device tree are set to according the new relocated CCSRBAR. + * So device tree code cannot be used when CONFIG_SYS_CCSR_DO_NOT_RELOCATE is + * set. + * + * If CCSRBAR is is not configured to its default location then _start code + * hangs or crashes. + * + * So relocation of CCSRBAR must be disabled in every code which runs before + * U-Boot proper (e.g. SPL), otherwise U-Boot proper's _start code crashes. + */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +/* + * DDR + */ + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 +#define SPD_EEPROM_ADDRESS 0x52 + +/* + * NOR + */ + +#define CONFIG_SYS_FLASH_BASE 0xef000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16 MB */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_QUIET_TEST + +/* + * NAND + */ + +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM +#define CONFIG_NAND_ECC_BCH + +/* + * CPLD + */ + +#define CONFIG_SYS_CPLD_BASE 0xffa00000 +#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE + +/* + * Serial Port + */ + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) + +#define CONFIG_SYS_BAUDRATE_TABLE { 600, 1200, 1800, 2400, 4800, 9600, \ + 19200, 38400, 57600, 115200, 230400, \ + 460800, 500000, 576000, 921600, \ + 1000000, 1500000, 2000000, 3000000 } + +/* + * PCIe + */ + +/* PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card */ +#define CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_VIRT + +/* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */ +#define CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_VIRT +#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_VIRT + +/* PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller */ +#define CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_VIRT +#define CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT + +#define CONFIG_PCI_SCAN_SHOW /* Show pci devices on startup */ + +/* + * Ethernet + */ + +#define CONFIG_ETHPRIME "ethernet@26000" /* Primary ethernet device */ + +/* + * USB + */ + +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +/* + * eSDHC + */ + +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define SDHC_WP_IS_GPIO /* SDHC_WP pin is not connected to SD card slot, it is GPIO pin */ + +/* + * ATA/SCSI + */ + +#define CONFIG_LBA48 /* Enable support for 137+ GB disks */ +#define CONFIG_SYS_64BIT_LBA /* Enable support for 2.1+ TB disks */ + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* Allow baudrate change argument for loads */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ SZ_64M /* Initial Memory for Linux */ +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +/* + * Environment Configuration + */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(NVME, nvme, 0) \ + func(SCSI, scsi, 0) \ + func(USB, usb, 0) \ + func(USB, usb, 1) \ + func(USB, usb, 2) \ + func(USB, usb, 3) \ + func(USB, usb, 4) \ + func(UBIFS, ubifs, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +/* These boot source switches macros must be constant numbers as they are stringified */ +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0xc8 +#define __SW_BOOT_SPI 0x28 +#define __SW_BOOT_SD 0x68 +#define __SW_BOOT_SD2 0x18 +#define __SW_BOOT_NAND 0xe8 +#define __SW_BOOT_PCIE 0xa8 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ + +#include "p1_p2_bootsrc.h" + +#define REBOOT_ENV_SETTINGS \ + RST_NOR_UP_CMD(reboot_to_nor, echo Rebooting to NOR bootloader;) \ + RST_SD_CMD(reboot_to_sd, echo Rebooting to SD bootloader;) \ + RST_DEF_CMD(reboot_to_def, echo Rebooting to default bootloader;) \ + "" + +#define BOOTCMD_RESCUE \ + "setenv bootargs root=mtd2 rw rootfstype=jffs2 console=ttyS0,115200; " \ + "bootm 0xef020000 - 0xef000000" \ + "" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x2000000\0" \ + "kernel_addr_r=0x2100000\0" \ + "scriptaddr=0x3000000\0" \ + "pxefile_addr_r=0x3100000\0" \ + "ramdisk_addr_r=0x4000000\0" \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "fdt_addr=0xef000000\0" \ + "bootubipart=rootfs\0" \ + "bootubivol=rootfs\0" \ + "bootcmd_rescue=" BOOTCMD_RESCUE "\0" \ + REBOOT_ENV_SETTINGS \ + BOOTENV + +#endif /* _CONFIG_TURRIS_1X_H */ -- 2.20.1

4 14

[PATCH v3] phy: phy-imx8mq-usb: add vbus regulator support
by Tim Harvey 10 Jul '23

10 Jul '23

Add support for enabling and disabling vbus-supply regulator found on several imx8mp boards in the usb3_phy0 and usb3_phy1 nodes. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> Reviewed-by: Adam Ford <aford173(a)gmail.com> --- v3: - change pr_err to dev_err - add #if CONFIG_IS_ENABLED around vbus_supply in struct - add fail path to disable clock if regulator enable failed v2: - protect ret with __maybe_unused in case CONFIG_CLK and CONFIG_DM_REGULATOR not defined - add error prints on failures - add Adam's rb tag --- drivers/phy/phy-imx8mq-usb.c | 39 ++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c index 69f01de55538..cbd96a0bd4df 100644 --- a/drivers/phy/phy-imx8mq-usb.c +++ b/drivers/phy/phy-imx8mq-usb.c @@ -14,6 +14,8 @@ #include <linux/delay.h> #include <linux/err.h> #include <clk.h> +#include <dm/device_compat.h> +#include <power/regulator.h> #define PHY_CTRL0 0x0 #define PHY_CTRL0_REF_SSP_EN BIT(2) @@ -81,6 +83,9 @@ struct imx8mq_usb_phy { #endif void __iomem *base; enum imx8mpq_phy_type type; +#if CONFIG_IS_ENABLED(DM_REGULATOR) + struct udevice *vbus_supply; +#endif }; static const struct udevice_id imx8mq_usb_phy_of_match[] = { @@ -172,10 +177,10 @@ static int imx8mq_usb_phy_power_on(struct phy *usb_phy) { struct udevice *dev = usb_phy->dev; struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + __maybe_unused int ret; u32 value; #if CONFIG_IS_ENABLED(CLK) - int ret; ret = clk_enable(&imx_phy->phy_clk); if (ret) { printf("Failed to enable usb phy clock\n"); @@ -183,18 +188,31 @@ static int imx8mq_usb_phy_power_on(struct phy *usb_phy) } #endif + if (CONFIG_IS_ENABLED(DM_REGULATOR) && imx_phy->vbus_supply) { + ret = regulator_set_enable(imx_phy->vbus_supply, true); + if (ret) { + dev_err(dev, "Failed to enable VBUS regulator: %d\n", ret); + goto err; + } + } + /* Disable rx term override */ value = readl(imx_phy->base + PHY_CTRL6); value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL; writel(value, imx_phy->base + PHY_CTRL6); return 0; + +err: + clk_disable(&imx_phy->phy_clk); + return ret; } static int imx8mq_usb_phy_power_off(struct phy *usb_phy) { struct udevice *dev = usb_phy->dev; struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + __maybe_unused int ret; u32 value; /* Override rx term to be 0 */ @@ -206,6 +224,14 @@ static int imx8mq_usb_phy_power_off(struct phy *usb_phy) clk_disable(&imx_phy->phy_clk); #endif + if (CONFIG_IS_ENABLED(DM_REGULATOR) && imx_phy->vbus_supply) { + ret = regulator_set_enable(imx_phy->vbus_supply, false); + if (ret) { + dev_err(dev, "Failed to disable VBUS regulator: %d\n", ret); + return ret; + } + } + return 0; } @@ -224,6 +250,7 @@ struct phy_ops imx8mq_usb_phy_ops = { int imx8mq_usb_phy_probe(struct udevice *dev) { struct imx8mq_usb_phy *priv = dev_get_priv(dev); + __maybe_unused int ret; priv->type = dev_get_driver_data(dev); priv->base = dev_read_addr_ptr(dev); @@ -232,7 +259,6 @@ int imx8mq_usb_phy_probe(struct udevice *dev) return -EINVAL; #if CONFIG_IS_ENABLED(CLK) - int ret; /* Assigned clock already set clock */ ret = clk_get_by_name(dev, "phy", &priv->phy_clk); @@ -242,6 +268,15 @@ int imx8mq_usb_phy_probe(struct udevice *dev) } #endif + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + ret = device_get_supply_regulator(dev, "vbus-supply", + &priv->vbus_supply); + if (ret && ret != -ENOENT) { + dev_err(dev, "Failed to get VBUS regulator: %d\n", ret); + return ret; + } + } + return 0; } -- 2.25.1

3 2

[PATCH 0/2] Add initial support for PINE64 PineTab2
by David Hewitt 10 Jul '23

10 Jul '23

This is my first contribution to U-Boot and my first attempt at an email-patch submission workflow. So please go easy on me! This series of patches adds the basics required to get the PINE64 PineTab2 booting with U-Boot. This has only been tested thus far with eMMC and SD card booting, but I intend to do further work to get the display and USB tested and working in the future too. Some minor modifications were required to the mmc tree due to a bug in the implementation of the Designware MMC controller where pulling PWREN high causes it not to work. David Hewitt (2): rockchip: Add initial support for the PineTab2 from PINE64 mmc: Add quirk to disable PWREN for dw_mmc arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-pinetab2.dts | 422 ++++++++++++++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 9 + board/pine64/pinetab2-rk3566/Kconfig | 15 + board/pine64/pinetab2-rk3566/MAINTAINERS | 7 + board/pine64/pinetab2-rk3566/Makefile | 5 + .../pine64/pinetab2-rk3566/pinetab2-rk3566.c | 1 + configs/pinetab2_defconfig | 83 ++++ drivers/mmc/dw_mmc.c | 3 +- drivers/mmc/rockchip_dw_mmc.c | 3 + include/configs/pinetab2-rk3566.h | 13 + include/configs/rk3568_common.h | 4 +- include/dwmmc.h | 1 + 13 files changed, 564 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3566-pinetab2.dts create mode 100644 board/pine64/pinetab2-rk3566/Kconfig create mode 100644 board/pine64/pinetab2-rk3566/MAINTAINERS create mode 100644 board/pine64/pinetab2-rk3566/Makefile create mode 100644 board/pine64/pinetab2-rk3566/pinetab2-rk3566.c create mode 100644 configs/pinetab2_defconfig create mode 100644 include/configs/pinetab2-rk3566.h Signed-off-by: David Hewitt <davidmhewitt(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Philipp Tomsich <philipp.tomsich(a)vrull.eu> Cc: Kever Yang <kever.yang(a)rock-chips.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> -- 2.34.1

2 5

[PATCH v2 00/11] Remove unnecessary USBx dr_mode configuration.
by Julien Panis 10 Jul '23

10 Jul '23

For all TI platforms handled in this series, USBx dr_mode was configured as peripheral in '<board>-u-boot.dtsi'. This series removes these fragments, since USBx dual-role feature is already handled as peripheral only in 'dwc3_glue_bind_common()' function of 'dwc3-generic.c' driver: static int dwc3_glue_bind_common(struct udevice *parent, ofnode node) { [...] switch (dr_mode) { case USB_DR_MODE_PERIPHERAL: case USB_DR_MODE_OTG: debug("%s: dr_mode: OTG or Peripheral\n", __func__); driver = "dwc3-generic-peripheral"; break; [...] } This follows a discussion about a similar topic for am3 boards: https://lore.kernel.org/u-boot/20230621-fix_usb_ether_init-v4-0-5f4977bb767… Signed-off-by: Julien Panis <jpanis(a)baylibre.com> --- Changes in v2: - Handle 'unknown' mode as 'otg' in dwc3 usb driver. - Link to v1: https://lore.kernel.org/r/20230706-handle-otg-as-periph-v1-0-bd85d15ffd50@b… --- Julien Panis (11): usb: dwc3: Handle unknown mode as otg arm: dts: dra7-evm-u-boot: Remove usb1 mode configuration arm: dts: dra71-evm-u-boot: Remove usb1 mode configuration arm: dts: dra72-evm-revc-u-boot: Remove usb1 mode configuration arm: dts: dra72-evm-u-boot: Remove usb1 mode configuration arm: dts: dra76-evm-u-boot: Remove usb1 mode configuration arm: dts: k3-am642-evm-u-boot: Remove usb0 mode configuration arm: dts: k3-am654-r5-base-board-u-boot: Remove usb mode configuration arm: dts: k3-j7200-common-proc-board-u-boot: Remove usb0 mode configuration arm: dts: k3-j721e-common-proc-board-u-boot: Remove usb0 mode configuration arm: dts: keystone-k2e-evm-u-boot: Remove usb1 mode configuration arch/arm/dts/dra7-evm-u-boot.dtsi | 1 - arch/arm/dts/dra71-evm-u-boot.dtsi | 1 - arch/arm/dts/dra72-evm-revc-u-boot.dtsi | 1 - arch/arm/dts/dra72-evm-u-boot.dtsi | 1 - arch/arm/dts/dra76-evm-u-boot.dtsi | 1 - arch/arm/dts/k3-am642-evm-u-boot.dtsi | 1 - arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi | 5 ----- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 1 - arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 1 - arch/arm/dts/keystone-k2e-evm-u-boot.dtsi | 1 - drivers/usb/dwc3/dwc3-generic.c | 4 ++-- 11 files changed, 2 insertions(+), 16 deletions(-) --- base-commit: 19b77d3d23966a0d6dbb3c86187765f11100fb6f change-id: 20230706-handle-otg-as-periph-4546e874cd15 Best regards, -- Julien Panis <jpanis(a)baylibre.com>

2 12

[PATCH 00/10] Remove unnecessary USBx dr_mode configuration.
by Julien Panis 10 Jul '23

10 Jul '23

For all TI platforms handled in this series, USBx dr_mode was configured as peripheral in '<board>-u-boot.dtsi'. This series removes these fragments, since USBx dual-role feature is already handled as peripheral only in 'dwc3_glue_bind_common()' function of 'dwc3-generic.c' driver: static int dwc3_glue_bind_common(struct udevice *parent, ofnode node) { [...] switch (dr_mode) { case USB_DR_MODE_PERIPHERAL: case USB_DR_MODE_OTG: debug("%s: dr_mode: OTG or Peripheral\n", __func__); driver = "dwc3-generic-peripheral"; break; [...] } This follows a discussion about a similar topic for am3 boards: https://lore.kernel.org/u-boot/20230621-fix_usb_ether_init-v4-0-5f4977bb767… Signed-off-by: Julien Panis <jpanis(a)baylibre.com> --- Julien Panis (10): arm: dts: dra7-evm-u-boot: Remove usb1 mode configuration arm: dts: dra71-evm-u-boot: Remove usb1 mode configuration arm: dts: dra72-evm-revc-u-boot: Remove usb1 mode configuration arm: dts: dra72-evm-u-boot: Remove usb1 mode configuration arm: dts: dra76-evm-u-boot: Remove usb1 mode configuration arm: dts: k3-am642-evm-u-boot: Remove usb0 mode configuration arm: dts: k3-am654-r5-base-board-u-boot: Remove usb mode configuration arm: dts: k3-j7200-common-proc-board-u-boot: Remove usb0 mode configuration arm: dts: k3-j721e-common-proc-board-u-boot: Remove usb0 mode configuration arm: dts: keystone-k2e-evm-u-boot: Remove usb1 mode configuration arch/arm/dts/dra7-evm-u-boot.dtsi | 1 - arch/arm/dts/dra71-evm-u-boot.dtsi | 1 - arch/arm/dts/dra72-evm-revc-u-boot.dtsi | 1 - arch/arm/dts/dra72-evm-u-boot.dtsi | 1 - arch/arm/dts/dra76-evm-u-boot.dtsi | 1 - arch/arm/dts/k3-am642-evm-u-boot.dtsi | 1 - arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi | 5 ----- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 1 - arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 1 - arch/arm/dts/keystone-k2e-evm-u-boot.dtsi | 1 - 10 files changed, 14 deletions(-) --- base-commit: 19b77d3d23966a0d6dbb3c86187765f11100fb6f change-id: 20230706-handle-otg-as-periph-4546e874cd15 Best regards, -- Julien Panis <jpanis(a)baylibre.com>

3 16

[PATCH 0/6] nokia_nx51: Attempts to debug keyboard
by Simon Glass 10 Jul '23

10 Jul '23

This series is an attempt to get the keyboard working properly with bootmenu. It fixes the board's tstc() function, which should be in drivers/input It also adjusts stopping of the menu autodelay - it should only stop when a whole escape sequence is received, not when the first escape character is received. That is pretty minor, so we could drop that patch. This series also adds some debugging output. This seems to make things work correctly, suggesting that there is some other problem. I also see this message fairly often: cyclic function rx51_watchdog took too long: 10000us vs 1000us max Simon Glass (6): menu: Re-enable the ANSI codes nokia_rx51: Correct tstc() implementation bootmenu: Cancel delay only when a real key is pressed boobtmenu: Add debugging getch: debugging menu: Add debugging board/nokia/rx51/rx51.c | 3 +++ cmd/bootmenu.c | 19 ++++++++++++------- common/cli_getch.c | 23 ++++++++++++++++++++--- common/menu.c | 7 ++++++- 4 files changed, 41 insertions(+), 11 deletions(-) -- 2.41.0.162.gfafddb0af9-goog

3 14