June 2023 - U-Boot

Re: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator
by Conor Dooley 12 Jun '23

12 Jun '23

On Tue, May 23, 2023 at 01:10:06PM +0200, Torsten Duwe wrote: > On Tue, 23 May 2023 09:28:39 +0100 > Conor Dooley <conor.dooley(a)microchip.com> wrote: > > > On Tue, May 23, 2023 at 10:56:43AM +0800, Xingyu Wu wrote: > > > On 2023/5/19 22:16, Conor Dooley wrote: > > > > On Fri, May 19, 2023 at 03:57:33PM +0200, Torsten Duwe wrote: > > > >> On Fri, May 12, 2023 at 10:20:30AM +0800, Xingyu Wu wrote: > > > >> [...] > > > > >> > +/* PLL clocks */ > > > >> > +#define JH7110_CLK_PLL0_OUT 0 > > > >> > +#define JH7110_CLK_PLL1_OUT 1 > > > >> > +#define JH7110_CLK_PLL2_OUT 2 > > > >> > > > >> In U-Boot commit 58c9c60b Yanhong Wang added: > > > >> > > > >> + > > > >> +#define JH7110_SYSCLK_PLL0_OUT 190 > > > >> +#define JH7110_SYSCLK_PLL1_OUT 191 > > > >> +#define JH7110_SYSCLK_PLL2_OUT 192 > > > >> + > > > >> +#define JH7110_SYSCLK_END 193 > [...] > > > > Ohh, that's not good.. If you pass the U-Boot dtb to Linux it > > > > won't understand the numbering. The headers are part of the > > > > dt-binding :/ > > In fact, the clock index >= 190 makes linux hang on boot, waiting with > EPROBE_DEFER for every device's clock, because the sysclk driver errors > out with EINVAL (jh7110_sysclk_get()). Yup, that's about what I expected to happen. > > > Because PLL driver is separated from SYSCRG drivers in Linux, the > > > numbering starts from 0. But in Uboot, the PLL driver is included > > > in the SYSCRG driver, and the number follows the SYSCRG. > > > > Unfortunately, how you choose to construct your drivers has nothing to > > do with this. > > These defines/numbers appear in the dts and are part of the DT ABI. > > The same dts is supposed to work for Linux & U-Boot. > > The JH7110 has 6 blocks of 64k iomem in that functional area: > {SYS,STG,AON} x {CRG,SYSCON}. None of these has 190 clocks. > The good news: the current DTS, as proposed here and in U-Boot master, > provides nodes for all 6 entities. The bad news is that the clock > assignments to those nodes and their numbering is messed up. > > AFAICT PLL{0,1,2} _are_ generated in SYS_SYSCON and thus U-Boot gets it > wrong, in addition to the erroneous DTS. The numbers are kinda hocus-pocus anyway, they are just made up since the clock numbering usually isn't something with a nice TRM to go and reference (unlike interrupts which usually are documented in that way). It is very helpful to make them aligned some register/bit positions or, but that is not required. IOW U-Boot is not wrong per se to use 190 instead of 0, but it is wrong to have different numbers in both places. It sounds like you're saying that (and I have not looked) the U-Boot dts actually has structural difference w.r.t. what provides which clock? If so, that'll need to be fixed independently of the numbering problem. Otherwise Xingyu & Yanhong should coordinate on which is the "correct" way of doing things & do it in both places. Thanks, Conor.

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Re: [RESEND PATCH v1] arch: riscv: jh7110: Correctly zero L2 LIM
by Rick Chen 12 Jun '23

12 Jun '23

> From: Bo Gan <ganboing(a)gmail.com> > Sent: Monday, June 12, 2023 7:59 AM > To: u-boot(a)lists.denx.de > Cc: Bo Gan <ganboing(a)gmail.com>; samin . guo <samin.guo(a)starfivetech.com>; Yanhong Wang <yanhong.wang(a)starfivetech.com>; Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; Sean Anderson <seanga2(a)gmail.com>; Lukasz Majewski <lukma(a)denx.de> > Subject: [RESEND PATCH v1] arch: riscv: jh7110: Correctly zero L2 LIM > > Background information: > JH7110 SPL runs in L2 LIM (2M in size mapped at 0x8000000). It consists of 16 0x20000 sized regions, each one can be used as either L2 cache way or SRAM (not both). From top to bottom, there're ways 0-15. The way 0 is always enabled, at most 0x1e0000 can be used. > > In SPL, we don't enable any cache ways, thus all 15 (except way 0) ways can be used. However, due to HW requirement, we must zero the LIM before use. This is because ECC is applied to LIM, and if not cleared first, the ECC part is invalid, which can trigger ECC errors when reading/writing data. > > There are several issues currently. We clear L2 LIM from __bss_end to 0x81FFFFF in `harts_early_init`. This is wrong because: > > a. Each hart (in the middle of a function call) overwriting its own > stack and other harts' stacks. > (data-race and data-corruption) > b. Lottery winner hart can be doing `board_init_f_init_reserve`, > while other harts're in the middle of zeroing L2 LIM. > (data-race) > > To fix this, we split the job, such that there's one and only one owner of zeroing a specific region (No data-race). A new SPL config option `SPL_ZERO_MEM_BEFORE_USE` is introduced. Allowing The zeroing to happen in the same code path. (much easier to reason about). > > Another option `SPL_SYS_MALLOC_CLEAR_ON_INIT` also gets introduced. > It allows us to also zero late malloc (dlmalloc) area, in case it gets configured to be inside L2 LIM (via `CUSTOM_SYS_SPL_MALLOC_ADDR`) We by default enable it to be on the safe side. > > `CONFIG_SPL_STACK` is adjusted to reduce the waste of L2 LIM space. > When setting > > CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8100000 > CONFIG_SYS_SPL_MALLOC_SIZE=0xe0000 > > A 0.875M late malloc arena is available in L2 LIM. It's sufficient for loading JH7110 FIT Image (gzip compressed OpenSBI+UBOOT+DTB). > The advantage of this config is allowing OpenSBI/UBOOT to be loaded at any DDR memory address. By default the malloc arena is configured in DDR memory, so OpenSBI/UBOOT loading address must not collide with it. > > CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000 (DDR +1GB) > CONFIG_SYS_SPL_MALLOC_SIZE=0x400000 > > JH7110 SPL memory map (based on the following defconfig): > > CONFIG_NR_CPUS=8 > CONFIG_STACK_SIZE_SHIFT=14 > CONFIG_SPL_STACK=0x8100000 > CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 > CONFIG_SPL_BSS_START_ADDR=0x8040000 > > +----------------+ 0x81e0000 > | Free | > | | > +----------------+ 0x8100000 > | hart 0 stack | <--- cleared by each hart (start.S) > +----------------+ 0x80fc000 > | hart 1 stack | . > +----------------+ 0x80f8000 . > | ...... | . > +----------------+ > | hart N-1 stack| <--- cleared by each hart (start.S) > +----------------+ 0x80e0000 > | ...... | <--- cleared by lottery winner hart > | malloc_base | board_init_f_init_reserve() > +----------------+ 0x80d0000 > | GD | <--- cleared by lottery winner hart > +----------------+ board_init_f_init_reserve() > | | > | hole | > | | > +----------------+ > | BSS | <--- cleared by lottery winner hart > +----------------+ 0x8040000 spl_clear_bss (start.S) > | hole | > +----------------+ > | Image+DTB | <--- Assuming cleared/loaded by ROM > +----------------+ 0x8000000 > > Signed-off-by: Bo Gan <ganboing(a)gmail.com> > Cc: samin . guo <samin.guo(a)starfivetech.com> > Cc: Yanhong Wang <yanhong.wang(a)starfivetech.com> > Cc: Rick Chen <rick(a)andestech.com> > Cc: Leo <ycliang(a)andestech.com> > Cc: Sean Anderson <seanga2(a)gmail.com> > Cc: Lukasz Majewski <lukma(a)denx.de> > --- > > v1: > - patch is on top of https://patchwork.ozlabs.org/project/uboot/patch/1684650044-313122-1-git-se… > - Tested on VisionFive 2 board (4G) > --- > Kconfig | 11 +++++++++++ > arch/riscv/Kconfig | 7 +++++++ > arch/riscv/cpu/jh7110/Kconfig | 2 ++ > arch/riscv/cpu/jh7110/spl.c | 25 ------------------------- > arch/riscv/cpu/start.S | 12 ++++++++++++ > common/dlmalloc.c | 6 +++--- > common/init/board_init.c | 3 +++ > configs/starfive_visionfive2_defconfig | 3 ++- > 8 files changed, 40 insertions(+), 29 deletions(-) Please separate as several PATCHs, but not mix them as one PATCH Thanks, Rick

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Re: [RESEND PATCH v2] riscv: setup per-hart stack earlier
by Rick Chen 12 Jun '23

12 Jun '23

> From: Bo Gan <ganboing(a)gmail.com> > Sent: Monday, June 12, 2023 7:54 AM > To: u-boot(a)lists.denx.de > Cc: Bo Gan <ganboing(a)gmail.com>; Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; Sean Anderson <seanga2(a)gmail.com>; Bin Meng <bmeng.cn(a)gmail.com>; Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > Subject: [RESEND PATCH v2] riscv: setup per-hart stack earlier > > Harts need to use per-hart stack before any function call, even if that function is a simple one. When the callee uses stack for register save/ restore, especially RA, if nested call, concurrent access by multiple harts on the same stack will cause data-race. > > This patch sets up SP before `board_init_f_alloc_reserve`. A side effect of this is that the memory layout has changed as the following: > > +----------------+ +----------------+ <----- SPL_STACK/ > | ...... | | hart 0 stack | SYS_INIT_SP_ADDR > | malloc_base | +----------------+ > +----------------+ | hart 1 stack | > | GD | +----------------+ If not SMP, N=1 > +----------------+ | ...... | > | hart 0 stack | +----------------+ > +----------------+ ==> | hart N-1 stack| > | hart 1 stack | +----------------+ > +----------------+ | ...... | > | ...... | | malloc_base | > +----------------+ +----------------+ > | hart N-1 stack| | GD | > +----------------+ +----------------+ > | | | | > > Signed-off-by: Bo Gan <ganboing(a)gmail.com> > Cc: Rick Chen <rick(a)andestech.com> > Cc: Leo <ycliang(a)andestech.com> > Cc: Sean Anderson <seanga2(a)gmail.com> > Cc: Bin Meng <bmeng.cn(a)gmail.com> > Cc: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > --- > > v2: > - Fixed macro CONFIG_SYS_INIT_SP_ADDR -> SYS_INIT_SP_ADDR > - Tested SPL with VisionFive 2 board > --- > arch/riscv/cpu/start.S | 37 ++++++++++++++++++++++++------------- > 1 file changed, 24 insertions(+), 13 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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[RESEND PATCH v1] arch: riscv: jh7110: Correctly zero L2 LIM
by Bo Gan 12 Jun '23

12 Jun '23

Background information: JH7110 SPL runs in L2 LIM (2M in size mapped at 0x8000000). It consists of 16 0x20000 sized regions, each one can be used as either L2 cache way or SRAM (not both). From top to bottom, there're ways 0-15. The way 0 is always enabled, at most 0x1e0000 can be used. In SPL, we don't enable any cache ways, thus all 15 (except way 0) ways can be used. However, due to HW requirement, we must zero the LIM before use. This is because ECC is applied to LIM, and if not cleared first, the ECC part is invalid, which can trigger ECC errors when reading/writing data. There are several issues currently. We clear L2 LIM from __bss_end to 0x81FFFFF in `harts_early_init`. This is wrong because: a. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) b. Lottery winner hart can be doing `board_init_f_init_reserve`, while other harts're in the middle of zeroing L2 LIM. (data-race) To fix this, we split the job, such that there's one and only one owner of zeroing a specific region (No data-race). A new SPL config option `SPL_ZERO_MEM_BEFORE_USE` is introduced. Allowing The zeroing to happen in the same code path. (much easier to reason about). Another option `SPL_SYS_MALLOC_CLEAR_ON_INIT` also gets introduced. It allows us to also zero late malloc (dlmalloc) area, in case it gets configured to be inside L2 LIM (via `CUSTOM_SYS_SPL_MALLOC_ADDR`) We by default enable it to be on the safe side. `CONFIG_SPL_STACK` is adjusted to reduce the waste of L2 LIM space. When setting CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8100000 CONFIG_SYS_SPL_MALLOC_SIZE=0xe0000 A 0.875M late malloc arena is available in L2 LIM. It's sufficient for loading JH7110 FIT Image (gzip compressed OpenSBI+UBOOT+DTB). The advantage of this config is allowing OpenSBI/UBOOT to be loaded at any DDR memory address. By default the malloc arena is configured in DDR memory, so OpenSBI/UBOOT loading address must not collide with it. CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000 (DDR +1GB) CONFIG_SYS_SPL_MALLOC_SIZE=0x400000 JH7110 SPL memory map (based on the following defconfig): CONFIG_NR_CPUS=8 CONFIG_STACK_SIZE_SHIFT=14 CONFIG_SPL_STACK=0x8100000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_BSS_START_ADDR=0x8040000 +----------------+ 0x81e0000 | Free | | | +----------------+ 0x8100000 | hart 0 stack | <--- cleared by each hart (start.S) +----------------+ 0x80fc000 | hart 1 stack | . +----------------+ 0x80f8000 . | ...... | . +----------------+ | hart N-1 stack| <--- cleared by each hart (start.S) +----------------+ 0x80e0000 | ...... | <--- cleared by lottery winner hart | malloc_base | board_init_f_init_reserve() +----------------+ 0x80d0000 | GD | <--- cleared by lottery winner hart +----------------+ board_init_f_init_reserve() | | | hole | | | +----------------+ | BSS | <--- cleared by lottery winner hart +----------------+ 0x8040000 spl_clear_bss (start.S) | hole | +----------------+ | Image+DTB | <--- Assuming cleared/loaded by ROM +----------------+ 0x8000000 Signed-off-by: Bo Gan <ganboing(a)gmail.com> Cc: samin . guo <samin.guo(a)starfivetech.com> Cc: Yanhong Wang <yanhong.wang(a)starfivetech.com> Cc: Rick Chen <rick(a)andestech.com> Cc: Leo <ycliang(a)andestech.com> Cc: Sean Anderson <seanga2(a)gmail.com> Cc: Lukasz Majewski <lukma(a)denx.de> --- v1: - patch is on top of https://patchwork.ozlabs.org/project/uboot/patch/1684650044-313122-1-git-se… - Tested on VisionFive 2 board (4G) --- Kconfig | 11 +++++++++++ arch/riscv/Kconfig | 7 +++++++ arch/riscv/cpu/jh7110/Kconfig | 2 ++ arch/riscv/cpu/jh7110/spl.c | 25 ------------------------- arch/riscv/cpu/start.S | 12 ++++++++++++ common/dlmalloc.c | 6 +++--- common/init/board_init.c | 3 +++ configs/starfive_visionfive2_defconfig | 3 ++- 8 files changed, 40 insertions(+), 29 deletions(-) diff --git a/Kconfig b/Kconfig index 70efb41..e5eec1b 100644 --- a/Kconfig +++ b/Kconfig @@ -372,6 +372,17 @@ if EXPERT When disabling this, please check if malloc calls, maybe should be replaced by calloc - if one expects zeroed memory. + config SPL_SYS_MALLOC_CLEAR_ON_INIT + bool "Init with zeros the memory reserved for malloc (slow) in SPL" + depends on SPL + default SYS_MALLOC_CLEAR_ON_INIT + help + Same as SYS_MALLOC_CLEAR_ON_INIT, but for SPL. It's possible to + Enable it without SYS_MALLOC_CLEAR_ON_INIT. It's useful for boards + that must have particular memory regions zero'ed before first use. + If SYS_SPL_MALLOC_START is configured to be in such region, this + option should be enabled. + config SYS_MALLOC_DEFAULT_TO_INIT bool "Default malloc to init while reserving the memory for it" help diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f6ed059..5d942a8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -60,6 +60,13 @@ config SPL_SYS_DCACHE_OFF help Do not enable data cache in SPL. +config SPL_ZERO_MEM_BEFORE_USE + bool "Zero memory before use" + depends on SPL + default n + help + Zero stack/GD/malloc area in SPL. + # board-specific options below source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 3f14541..de1507d 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -13,6 +13,7 @@ config STARFIVE_JH7110 select SUPPORT_SPL select SPL_RAM if SPL select SPL_STARFIVE_DDR + select SPL_ZERO_MEM_BEFORE_USE select PINCTRL_STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD @@ -26,3 +27,4 @@ config STARFIVE_JH7110 imply SPL_LOAD_FIT imply SPL_OPENSBI imply SPL_SIFIVE_CLINT + imply SPL_SYS_MALLOC_CLEAR_ON_INIT diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 104f0fe..72c5b25 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -10,7 +10,6 @@ #include <log.h> #define CSR_U74_FEATURE_DISABLE 0x7c1 -#define L2_LIM_MEM_END 0x81FFFFFUL int spl_soc_init(void) { @@ -29,9 +28,6 @@ int spl_soc_init(void) void harts_early_init(void) { - ulong *ptr; - u8 *tmp; - ulong len, remain; /* * Feature Disable CSR * @@ -40,25 +36,4 @@ void harts_early_init(void) */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) csr_write(CSR_U74_FEATURE_DISABLE, 0); - - /* clear L2 LIM memory - * set __bss_end to 0x81FFFFF region to zero - * The L2 Cache Controller supports ECC. ECC is applied to SRAM. - * If it is not cleared, the ECC part is invalid, and an ECC error - * will be reported when reading data. - */ - ptr = (ulong *)&__bss_end; - len = L2_LIM_MEM_END - (ulong)&__bss_end; - remain = len % sizeof(ulong); - len /= sizeof(ulong); - - while (len--) - *ptr++ = 0; - - /* clear the remain bytes */ - if (remain) { - tmp = (u8 *)ptr; - while (remain--) - *tmp++ = 0; - } } diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 59d58a5..1a0b01e 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,6 +111,18 @@ call_board_init_f: * It's essential before any function call, otherwise, we get data-race. */ + /* clear stack if necessary */ +#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE) +clear_stack: + li t1, 1 + slli t1, t1, CONFIG_STACK_SIZE_SHIFT + sub t1, sp, t1 +clear_stack_loop: + SREG zero, 0(t1) /* t1 is always 16 byte aligned */ + addi t1, t1, REGBYTES + blt t1, sp, clear_stack_loop +#endif + call_board_init_f_0: /* find top of reserve space */ #if CONFIG_IS_ENABLED(SMP) diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 0f9b726..dcecdb8 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -631,7 +631,7 @@ void mem_malloc_init(ulong start, ulong size) debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start, mem_malloc_end); -#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT +#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT) memset((void *)mem_malloc_start, 0x0, size); #endif malloc_bin_reloc(); @@ -2153,7 +2153,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; /* check if expand_top called, in which case don't need to clear */ -#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT +#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT) #if MORECORE_CLEARS mchunkptr oldtop = top; INTERNAL_SIZE_T oldtopsize = chunksize(top); @@ -2184,7 +2184,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; csz = chunksize(p); -#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT +#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT) #if MORECORE_CLEARS if (p == oldtop && csz > oldtopsize) { diff --git a/common/init/board_init.c b/common/init/board_init.c index 96ffb79..ab8c508 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -162,6 +162,9 @@ void board_init_f_init_reserve(ulong base) #if CONFIG_VAL(SYS_MALLOC_F_LEN) /* go down one 'early malloc arena' */ gd->malloc_base = base; +#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE) + memset((void *)base, '\0', CONFIG_VAL(SYS_MALLOC_F_LEN)); +#endif #endif if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index ffbc4b9..4ce0f45 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -1,6 +1,7 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_SYS_MALLOC_F_LEN=0x10000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -13,7 +14,7 @@ CONFIG_SYS_PROMPT="StarFive #" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y -CONFIG_SPL_STACK=0x8180000 +CONFIG_SPL_STACK=0x8100000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -- 2.7.4

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[PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
by Pali Rohár 12 Jun '23

12 Jun '23

Boot configuration stored in EXT_CSC register is completely ignored by BootROM: https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F… Reflect this eMMC booting in documentation and in the code. Martin, can you test this patch series if SPL and main U-Boot is loaded from the same eMMC HW partition? When bootloader is stored on Boot 0, then SPL should take care of loading and executing main U-Boot. When it is stored on Boot 1 or User Data then SPL should return back to BootROM and let BootROM to load and execute main U-Boot. Pali Rohár (2): tools: kwboot: Fix MMC HW boot partitions info arm: mvebu: spl: Load proper U-Boot from eMMC Boot 0 partition arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/spl.c | 13 +++++++------ tools/kwboot.c | 6 +++--- 3 files changed, 11 insertions(+), 9 deletions(-) -- 2.20.1

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[RFC PATCH 0/5] LWIP stack integration
by Maxim Uvarov 11 Jun '23

11 Jun '23

Greetings, This RFC patchset is an attempt to try to use an already existing IP network stack inside U-boot. U-Boot recently got basic TCP/IP support, implementing wget, but in order to get a full IP stack with new features (e.g ipv6), it would be preferable to use an established embedded ip library, instead of rewriting the code from scratch. For this experiment LWIP network stack was selected: https://savannah.nongnu.org/git/?group=lwip LWIP main features include: - Protocols: IP, IPv6, ICMP, ND, MLD, UDP, TCP, IGMP, ARP, PPPoS, PPPoE - DHCP client, DNS client (incl. mDNS hostname resolver), AutoIP/APIPA (Zeroconf), SNMP agent (v1, v2c, v3, private MIB support & MIB compiler) - APIs: specialized APIs for enhanced performance, optional Berkeley-alike socket API - Extended features: IP forwarding over multiple network interfaces, TCP congestion control, RTT estimation and fast recovery/fast retransmit - Addon applications: HTTP(S) server, SNTP client, SMTP(S) client, ping, NetBIOS nameserver, mDNS responder, MQTT client, TFTP server. This RFC work is a demo to enable lwIP (lightweight IP) which is a widely used open-source TCP/IP stack designed for embedded systems for U-boot. That will allow using already written network applications for microcontrollers. lwIP is licensed under a BSD-style license: http://lwip.wikia.com/wiki/License. Which should be compatible with u-boot. In the current RFC I tried to use minimal changes to better see how LWIP code can be embedded into U-boot. Patches implement ping and wget commands work. Both commands are currently copy pasting and reusing lwIP examples. Whether we want to add the final application in U-Boot or lwIP is up to discussion, but the current approach was the easiest one for an RFC. Looking for your comments, Best regards, Maxim. Maxim Uvarov (5): add lwip-external submodule lib/lwip: compile-in core files add doc/README.lwip add doc/README.lwip.size lwip: implement wget command from http_client.c example .gitignore | 5 + .gitmodules | 3 + doc/README.lwip | 90 +++++ doc/README.lwip.size | 291 +++++++++++++++ include/net.h | 2 +- lib/Kconfig | 2 + lib/Makefile | 2 + lib/lwip/Kconfig | 12 + lib/lwip/Makefile | 86 +++++ lib/lwip/apps/http/lwip-wget.c | 67 ++++ lib/lwip/apps/http/rmstatic.patch | 47 +++ lib/lwip/apps/ping/lwip_ping.c | 33 ++ lib/lwip/apps/ping/lwip_ping.h | 19 + lib/lwip/apps/ping/ping.h | 0 lib/lwip/apps/ping/rmstatic.patch | 32 ++ lib/lwip/cmd-lwip.c | 129 +++++++ lib/lwip/lwip-external | 1 + lib/lwip/lwipopts.h | 484 +++++++++++++++++++++++++ lib/lwip/port/if.c | 256 +++++++++++++ lib/lwip/port/include/arch/cc.h | 41 +++ lib/lwip/port/include/arch/sys_arch.h | 78 ++++ lib/lwip/port/include/arch/u-sockets.h | 26 ++ lib/lwip/port/include/limits.h | 0 lib/lwip/port/sys-arch.c | 7 + net/eth-uclass.c | 4 +- net/net.c | 14 + 26 files changed, 1729 insertions(+), 2 deletions(-) create mode 100644 .gitmodules create mode 100644 doc/README.lwip create mode 100644 doc/README.lwip.size create mode 100644 lib/lwip/Kconfig create mode 100644 lib/lwip/Makefile create mode 100644 lib/lwip/apps/http/lwip-wget.c create mode 100644 lib/lwip/apps/http/rmstatic.patch create mode 100644 lib/lwip/apps/ping/lwip_ping.c create mode 100644 lib/lwip/apps/ping/lwip_ping.h create mode 100644 lib/lwip/apps/ping/ping.h create mode 100644 lib/lwip/apps/ping/rmstatic.patch create mode 100644 lib/lwip/cmd-lwip.c create mode 160000 lib/lwip/lwip-external create mode 100644 lib/lwip/lwipopts.h create mode 100644 lib/lwip/port/if.c create mode 100644 lib/lwip/port/include/arch/cc.h create mode 100644 lib/lwip/port/include/arch/sys_arch.h create mode 100644 lib/lwip/port/include/arch/u-sockets.h create mode 100644 lib/lwip/port/include/limits.h create mode 100644 lib/lwip/port/sys-arch.c -- 2.30.2

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[PATCH] pinephone-pro: Fix I/O port voltage (GPIO3D4A is 1.8V)
by Ondřej Jirman 11 Jun '23

11 Jun '23

From: Ondrej Jirman <megi(a)xff.cz> This fixes access to camera sensor over I2C during probe time in the kernel. (Kernel will fix I/0 port voltage by itself, but the timing depends on probe order of the drivers, so the fix can come after the camera sensor driver already failed to probe.) Signed-off-by: Ondrej Jirman <megi(a)xff.cz> Cc: Kever Yang <kever.yang(a)rock-chips.com> --- board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c index eb639cd0d070..b6ccbb9c1c4b 100644 --- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c +++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c @@ -15,7 +15,8 @@ #include <asm/arch-rockchip/misc.h> #include <power/regulator.h> -#define GRF_IO_VSEL_BT565_SHIFT 0 +#define GRF_IO_VSEL_BT565_GPIO2AB 1 +#define GRF_IO_VSEL_AUDIO_GPIO3D4A 2 #define PMUGRF_CON0_VSEL_SHIFT 8 #ifndef CONFIG_SPL_BUILD @@ -48,7 +49,8 @@ static void setup_iodomain(void) syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); /* BT565 is in 1.8v domain */ - rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); + rk_setreg(&grf->io_vsel, + GRF_IO_VSEL_BT565_GPIO2AB | GRF_IO_VSEL_AUDIO_GPIO3D4A); /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); -- 2.40.1

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[PATCH 1/2] spi: soft_spi: Support the recommended soft spi properties
by Fabio Estevam 11 Jun '23

11 Jun '23

From: Fabio Estevam <festevam(a)denx.de> According to Documentation/devicetree/bindings/spi/spi-gpio.yaml from Linux, the recommended spio-gpio properties are: sck-gpios, miso-gpios and mosi-gpios. gpio-sck, gpio-mosi and gpio-miso are considered deprecated. Currently, U-Boot only supports the deprecated properties. Allow the soft_spi driver to support both the new and old properties. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- drivers/spi/soft_spi.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index f3602a25ba30..0fa14339bdcd 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -248,19 +248,32 @@ static int soft_spi_probe(struct udevice *dev) cs_flags = (slave && slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW; clk_flags = (slave && slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0; - if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs, - GPIOD_IS_OUT | cs_flags) || - gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, - GPIOD_IS_OUT | clk_flags)) + ret = gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs, + GPIOD_IS_OUT | cs_flags); + if (ret) + return -EINVAL; + + ret = gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, + GPIOD_IS_OUT | clk_flags); + if (ret) + ret = gpio_request_by_name(dev, "sck-gpios", 0, &plat->sclk, + GPIOD_IS_OUT | clk_flags); + if (ret) return -EINVAL; ret = gpio_request_by_name(dev, "gpio-mosi", 0, &plat->mosi, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) + ret = gpio_request_by_name(dev, "mosi-gpios", 0, &plat->mosi, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); if (ret) plat->flags |= SPI_MASTER_NO_TX; ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso, GPIOD_IS_IN); + if (ret) + ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso, + GPIOD_IS_IN); if (ret) plat->flags |= SPI_MASTER_NO_RX; -- 2.34.1

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[PATCH] spi: synquacer: remove SPI_TX_BYTE handling
by Masahisa Kojima 11 Jun '23

11 Jun '23

Current code expects that SPI_TX_BYTE is single bit mode but it is wrong. It indicates byte program mode, not single bit mode. If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set, the default transfer bus width is single bit. Signed-off-by: Masahisa Kojima <masahisa.kojima(a)linaro.org> --- drivers/spi/spi-synquacer.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index 0f5d0a30c3..553f9687e3 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -186,7 +186,7 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) struct udevice *bus = dev->parent; struct synquacer_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 val, div, bus_width = 1; + u32 val, div, bus_width; int rwflag; rwflag = (rx ? 1 : 0) | (tx ? 2 : 0); @@ -203,16 +203,14 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) priv->mode = slave_plat->mode; priv->speed = slave_plat->max_hz; - if (priv->mode & SPI_TX_BYTE) - bus_width = 1; - else if (priv->mode & SPI_TX_DUAL) + if (priv->mode & SPI_TX_DUAL) bus_width = 2; else if (priv->mode & SPI_TX_QUAD) bus_width = 4; else if (priv->mode & SPI_TX_OCTAL) bus_width = 8; else - log_warning("SPI mode not configured, setting to byte mode\n"); + bus_width = 1; /* default is single bit mode */ div = DIV_ROUND_UP(125000000, priv->speed); -- 2.34.1

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[PULL] u-boot-sh/next_net/phy_connect_dev
by Marek Vasut 11 Jun '23

11 Jun '23

The following changes since commit 5f41ef792c307dedc12647cdde2ade273aa11805: Merge branch '2023-06-09-fwu-updates' into next (2023-06-09 20:35:02 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-sh.git next_net/phy_connect_dev for you to fetch changes up to 32d2461e0467b50abeb5662fce41fdd686e88b61: ARM: renesas: Enable DM_ETH_PHY and SMSC PHY driver (2023-06-10 13:34:06 +0200) ---------------------------------------------------------------- Geert Uytterhoeven (1): ARM: dts: renesas: Add compatible properties to LAN8710A Ethernet PHYs Marek Vasut (13): net: eth-phy: staticize eth_phy_reset() net: altera_tsa: Switch to new U-Boot PHY API net: ave: Switch to new U-Boot PHY API net: ethoc: Switch to new U-Boot PHY API net: pch_gbe: Switch to new U-Boot PHY API net: sh_eth: Switch to new U-Boot PHY API net: sunxi_emac: Switch to new U-Boot PHY API net: phy: Unpublish phy_connect_dev() net: phy: Bind ETH_PHY uclass driver to each new PHY net: phy: Handle reset-delay-us/reset-post-delay-us properties net: ravb: Drop reset GPIO handling in favor of common code net: sh_eth: Drop reset GPIO handling in favor of common code ARM: renesas: Enable DM_ETH_PHY and SMSC PHY driver Valentine Barshak (2): net: sh_eth: Workaround cache issues net: sh_eth: Fix RX error handling arch/arm/dts/r7s72100-gr-peach.dts | 2 ++ configs/grpeach_defconfig | 3 +++ drivers/net/Kconfig | 2 ++ drivers/net/altera_tse.c | 8 +------ drivers/net/eth-phy-uclass.c | 10 +++++++- drivers/net/ethoc.c | 8 +++---- drivers/net/pch_gbe.c | 5 +--- drivers/net/phy/ethernet_id.c | 17 ++++++++++++++ drivers/net/phy/phy.c | 4 ++-- drivers/net/ravb.c | 22 ----------------- drivers/net/sh_eth.c | 48 +++++++++++--------------------------- drivers/net/sni_ave.c | 6 ++--- drivers/net/sunxi_emac.c | 7 +++--- include/phy.h | 9 ------- 14 files changed, 59 insertions(+), 92 deletions(-)

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